Multi-mode oscillator circuit system with step control

Abstract

A device for implementing a multi-mode oscillating circuit system with step control is disclosed. In one exemplary aspect, the multi-mode oscillating circuit system includes a resonator coupled to a first oscillator and a second oscillator. The multi-mode oscillating circuit system is configured to selectively be in a first configuration or a second configuration, in which the first oscillator is in an active state and the second oscillator is in an inactive state, and in which the first oscillator is in an inactive state and the second oscillator is in an active state. The device also includes a step control circuit coupled to the multi-mode oscillating circuit system. The step control circuit is configured to cause the first oscillator to switch from an inactive state to an active state, and to increase a first gain of the first oscillator in increments based on the first oscillator being in an active state, so that the multi-mode oscillating circuit system can transition from the second configuration to the first configuration.

Description

[0001] Priority claim under 35 USC § 119

[0002] This patent application claims priority to non-provisional application No. 16 / 420,723, filed on May 23, 2019, entitled “Multi-mode Oscillator Circuit System with Step Control,” which application has been assigned to its assignee and is expressly incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to clock generation and, more particularly, to a multi-mode oscillator circuit system with step control for smooth transitions between different configurations utilizing different oscillators. Background Art

[0004] Electronic devices use radio frequency (RF) signals to communicate information. These RF signals enable users to talk with friends, download information, share pictures, remotely control home devices, receive global positioning information, use radar for detection and tracking, or listen to radio stations. In order to generate these RF signals, electronic devices may include a clock generator that generates a clock signal. The clock signal provides a stable frequency reference that is used to perform wireless communications. For example, the clock signal can be provided to a mixer for frequency conversion (e.g., up-converting or down-converting a communication signal) or a phase-locked loop for generating another signal with a different stable frequency reference.

[0005] Due to the reliance on clock signals, any frequency error or noise in the clock signal will directly affect the quality and performance of communications. In some cases, the operations performed using the clock signal may also increase the amplitude of the frequency error or noise of the clock signal. As such, the noise in the clock signal is important within a certain predetermined threshold. One specific type of noise is phase noise, which represents random fluctuations in the phase of the clock signal. High levels of phase noise may increase the overall noise floor of the receiver, thereby reducing the sensitivity or dynamic range of the electronic device. This makes it more challenging for electronic devices to detect weaker signals or signals originating from greater distances.

[0006] The phase noise performance of a clock generator may depend on many factors including power consumption and component type. Better phase noise performance is usually achieved through higher power consumption or by utilizing larger size components. The former is expensive in terms of battery usage, while the latter is expensive in terms of device cost. Furthermore, different communication standards may be associated with different phase noise thresholds. If an electronic device supports multiple communication standards (e.g., cellular, global positioning system (GPS), Wi-Fi TM or Bluetooth TM), the design of the clock generator may have to support more than one phase noise threshold. Overall, it becomes challenging to design a clock generator that supports multiple communication standards, saves power, and physically fits within a specified space. Summary of the invention

[0007] An apparatus for implementing a multi-mode oscillation circuit system with step control is disclosed. A clock generator generates a clock signal using the multi-mode oscillation circuit system, which includes two or more oscillators individually coupled to a resonator. In a first configuration, the multi-mode oscillation circuit system operates with the first oscillator in an active state and the second oscillator in an inactive state. In a second configuration, the multi-mode oscillation circuit system operates with the first oscillator in an inactive state and the second oscillator in an active state.

[0008] In some cases, the oscillators are designed to have different performance characteristics. For example, a first oscillator may generate a lower amount of phase noise relative to a second oscillator. However, relative to the first oscillator, the second oscillator may consume less power. Thus, the configuration of the multi-mode oscillator circuit system may be appropriately selected based on the operating mode of the wireless transceiver. However, a sudden switch between two or more configurations may adversely affect the clock signal generated using the multi-mode oscillator circuit system.

[0009] Instead of abruptly switching between different configurations as the operating mode of the wireless transceiver changes, the stepper control circuit enables a multi-mode oscillator circuit system to smoothly transition between different configurations. As described herein, the stepper control circuit incrementally adjusts the corresponding gain of the oscillator to continuously provide a clock signal while mitigating glitches or other interference with the clock signal. This enables sensitive systems to reliably use the clock signal, such as digital systems that operate to provide wireless communications. In these ways, a single resonator can be used with multiple oscillators to provide multiple clock signals with different characteristics at a lower cost and occupying a smaller area.

[0010] In one example aspect, a device is disclosed. The device includes a multi-mode oscillation circuit system, which is configured to be selectively in a first configuration or a second configuration. The multi-mode oscillation circuit system includes a resonator, a first oscillator coupled to the resonator, and a second oscillator coupled to the resonator. The first oscillator is configured to be selectively in an active state based on the first configuration and an inactive state based on the second configuration. The second oscillator is configured to be selectively in an inactive state based on the first configuration and an active state based on the second configuration. The device also includes a step control circuit coupled to the multi-mode oscillation circuit system. The step control circuit is configured to switch the first oscillator from the inactive state to the active state. The step control circuit is also configured to incrementally increase a first gain of the first oscillator based on the first oscillator being in the active state, so that the multi-mode oscillation circuit system can transition from the second configuration to the first configuration.

[0011] In one example aspect, a device is disclosed. The device includes a multi-mode oscillating circuit system, which is configured to be selectively in a first configuration or a second configuration. The multi-mode oscillating circuit system includes a resonator, a first oscillator coupled to the resonator, and a second oscillator coupled to the resonator. The first oscillator is configured to be selectively in an active state based on the first configuration and an inactive state based on the second configuration. The second oscillator is configured to be selectively in an inactive state based on the first configuration and an active state based on the second configuration. The device also includes a stepping component for switching the first oscillator from the inactive state to the active state and incrementally increasing a first gain of the first oscillator so that the multi-mode oscillating circuit system can transition from the second configuration to the first configuration.

[0012] In one example aspect, a method for operating a multi-mode oscillating circuit system with step control is disclosed. The method includes: generating a clock signal using a resonator of the multi-mode oscillating circuit system. The multi-mode oscillating circuit system includes a first oscillator and a second oscillator coupled to the resonator. The method also includes: operating the multi-mode oscillating circuit system in a first configuration so that the resonator can generate the clock signal, the first configuration including the first oscillator in an active state and the second oscillator in an inactive state. The method also includes: operating the multi-mode oscillating circuit system in a second configuration so that the resonator can generate the clock signal, the second configuration including the first oscillator in an inactive state and the second oscillator in an active state. Additionally, the method includes: transitioning from operating the multi-mode oscillating circuit system in the second configuration to operating the multi-mode oscillating circuit system in the first configuration by incrementally increasing a first gain of the first oscillator while the second oscillator is in an active state.

[0013] In one example aspect, an apparatus is disclosed. The apparatus includes a clock generator including a multi-mode oscillating circuit system and a step control circuit. The multi-mode oscillating circuit system includes a resonator, a first oscillator coupled to the resonator, and a second oscillator coupled to the resonator. The first oscillator and the second oscillator are individually configured to be selectively in an active state or an inactive state. The step control circuit includes a first step driver coupled to the first oscillator and configured to incrementally adjust a first gain of the first oscillator while the second oscillator is in an active state. The step control circuit also includes a second step driver coupled to the second oscillator and configured to incrementally adjust a second gain of the second oscillator while the first oscillator is in an active state. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 An example operating environment for implementing a multi-mode oscillator circuit system with step control is illustrated.

[0015] Figure 2 An example implementation of a clock generator implementing a multi-mode oscillation circuit system with step control is illustrated.

[0016] Figure 3 An example sequence flow chart for operating a multi-mode oscillator circuit system with step control is illustrated.

[0017] Figure 4-1 Example signals for operating a multi-mode oscillator circuit system with step control are illustrated.

[0018] Figure 4-2 Other example signals for operating a multi-mode oscillator circuit system with step control are illustrated.

[0019] Figure 5 An example voltage mode oscillator for implementing a multi-mode oscillation circuit system with step control is illustrated.

[0020] Figure 6 An example current mode oscillator for implementing a multi-mode oscillation circuit system with step control is illustrated.

[0021] Figure 7 is a flow chart illustrating an example process for operating a multi-mode oscillator circuit system with step control. DETAILED DESCRIPTION

[0022] Electronic devices use clock generators to support radio frequency communications. The clock generator generates a reference clock signal with a predetermined frequency. The clock signal can be referenced by other components in the electronic device, including mixers, signal generators, phase-locked loops (PLLs), delay-locked loops (DLLs), etc. Due to the reliance on the clock signal, any frequency error or phase noise in the clock signal may propagate to downstream circuit components, thereby affecting processing or communication quality and performance. Additionally, different communication standards may be associated with different phase noise thresholds. If an electronic device supports multiple communication standards (e.g., cellular, global positioning system (GPS), Wi-Fi TM or Bluetooth TM ), the clock generator design may have to support more than one phase noise threshold.

[0023] In order to support different communication standards, some technologies use different oscillating circuit systems, which use different resonators. The performance of each oscillating circuit system can be adjusted for the corresponding communication standard. However, implementing multiple oscillating circuit systems adds additional complexity and increases costs to electronic devices. Further, multiple oscillating circuit systems will take up additional space in the electronic device and involve additional wiring.

[0024] In contrast, an example method for a multi-mode oscillating circuit system with step control is described herein. A clock generator generates a clock signal using a multi-mode oscillating circuit system that includes two or more oscillators that are individually coupled to a resonator. In a first configuration, the multi-mode oscillating circuit system operates with a first oscillator in an active state and a second oscillator in an inactive state. In a second configuration, the multi-mode oscillating circuit system operates with the first oscillator in an inactive state and the second oscillator in an active state.

[0025] In some cases, the oscillators are designed to have different performance characteristics. For example, a first oscillator may generate a lower amount of phase noise relative to a second oscillator. However, relative to the first oscillator, the second oscillator may consume less power. Thus, the configuration of the multi-mode oscillating circuit system may be appropriately selected based on the operating mode of the wireless transceiver. However, a sudden switch between two or more configurations may adversely affect the clock signal generated using the multi-mode oscillating circuit system.

[0026] Instead of abruptly switching between different configurations as the operating mode of the wireless transceiver changes, the stepper control circuit enables a multi-mode oscillator circuit system to smoothly transition between different configurations. As described herein, the stepper control circuit incrementally adjusts the corresponding gain of the oscillator to continuously provide a clock signal while mitigating glitches or other interference with the clock signal. This enables sensitive systems to reliably use the clock signal, such as digital systems that operate to provide wireless communications. In these ways, a single resonator can be used with multiple oscillators to provide multiple clock signals with different characteristics at a lower cost and occupying a smaller area.

[0027] Figure 1 An example environment 100 for implementing a multi-mode oscillator circuit system with step control is illustrated. In the environment 100, a computing device 102 communicates with a base station 104 via a wireless communication link 106 (wireless link 106). In this example, the computing device 102 is depicted as a smart phone. However, the computing device 102 can be implemented as any suitable computing or electronic device, such as a modem, a cellular base station, a broadband router, an access point, a cellular phone, a gaming device, a navigation device, a media device, a laptop computer, a desktop computer, a tablet computer, a wearable computer, a server, a network attached storage (NAS) device, a smart device or other Internet of Things (IoT) device, a medical device, a vehicle communication system, a radar, a radio device, etc.

[0028] Base station 104 communicates with computing device 102 via wireless link 106, which may be implemented as any suitable type of wireless link. Although depicted as a tower of a cellular network, base station 104 may represent or be implemented as another device, such as a satellite, a server device, a terrestrial television broadcast tower, an access point, a peer device, a mesh network node, a fiber optic line, etc. Thus, computing device 102 may communicate with base station 104 or another device via a wired connection, a wireless connection, or a combination thereof.

[0029] Wireless link 106 may include a downlink of data or control information communicated from base station 104 to computing device 102 or an uplink of other data or control information communicated from computing device 102 to base station 104. Wireless link 106 may be implemented using any suitable communication protocol or standard, such as second generation (2G), third generation (3G), fourth generation (4G), or fifth generation (5G) cellular; IEEE 802.11 (e.g., Wi-Fi TM ); IEEE 802.15 (e.g., Bluetooth TM ); IEEE 802.16 (e.g., WiMAX TM ), etc. In some implementations, the wireless link 106 may provide power wirelessly and the base station 104 may include a power source.

[0030] As shown, computing device 102 includes an application processor 108 and a computer-readable storage medium 110 (CRM 110). Application processor 108 may include any type of processor, such as a multi-core processor, that executes processor-executable code stored by CRM 110. CRM 110 may include any suitable type of data storage medium, such as volatile memory (e.g., random access memory (RAM)), non-volatile memory (e.g., flash memory), optical media, magnetic media (e.g., disk), etc. In the context of the present disclosure, CRM 110 is implemented to store instructions 112, data 114, and other information of computing device 102, and therefore does not include transient propagating signals or carrier waves.

[0031] The computing device 102 may also include an input / output port 116 (I / O port 116) and a display 118. The I / O port 116 enables data exchange or interaction with other devices, networks, or users. The I / O port 116 may include a serial port (e.g., a universal serial bus (USB) port), a parallel port, an audio port, an infrared (IR) port, a user interface port such as a touch screen, etc. The display 118 presents graphics of the computing device 102, such as a user interface associated with an operating system, program, or application. Alternatively or additionally, the display 118 may be implemented as a display port or a virtual interface through which the graphical content of the computing device 102 is presented.

[0032] The wireless transceiver 120 of the computing device 102 provides connectivity with the corresponding network and other electronic devices connected thereto. Alternatively or additionally, the computing device 102 may include a wired transceiver, such as an Ethernet or fiber optic interface, for communicating through a local network, an intranet, or the Internet. The wireless transceiver 120 can facilitate communication through any suitable type of wireless network, such as a wireless local area network (WLAN), a peer-to-peer (P2P) network, a mesh network, a cellular network, a wireless wide area network (WWAN), and / or a wireless personal area network (WPAN). In the context of the example environment 100, the wireless transceiver 120 enables the computing device 102 to communicate with the base station 104 and the network connected thereto. However, the wireless transceiver 120 can also enable the computing device 102 to communicate "directly" with other devices or networks.

[0033] The wireless transceiver 120 includes circuitry and logic for transmitting and receiving communication signals via the antenna 122. The components of the wireless transceiver 120 may include mixers, phase-locked loops, delay-locked loops, amplifiers, switches, analog-to-digital converters, filters, etc. for conditioning communication signals (e.g., for generating or processing signals). The wireless transceiver 120 may also include logic for performing in-phase / quadrature (I / Q) operations, such as synthesis, encoding, modulation, decoding, demodulation, etc. In some cases, the components of the wireless transceiver 120 are implemented as separate receiver and transmitter entities. Additionally or alternatively, the wireless transceiver 120 may be implemented using multiple or different parts to implement corresponding receive and transmit operations (e.g., separate transmit and receive chains). In general, the wireless transceiver 120 processes data and / or signals associated with data communicated to the computing device 102 via the antenna 122.

[0034] As shown, the wireless transceiver 120 also includes at least one clock generator 124 and at least one processor 126. Alternatively, the clock generator 124 can be implemented separately from the wireless transceiver 120 and coupled thereto. In some implementations, the clock generator 124 and the processor 126 are implemented on separate integrated circuits. Generally speaking, the clock generator 124 uses a resonator to generate a clock signal rather than referencing another clock signal. This is different from other signal generating components (such as PLLs) that use the clock signal from the clock generator to generate other versions of the clock signal with different frequencies. Generally speaking, the clock signal generated by the clock generator 124 is a reference clock signal provided to other components of the wireless transceiver 120. The clock signal can additionally or alternatively be used to synchronize the timing operations of the logic. The clock generator 124 includes a multi-mode oscillation circuit system 128, at least one step control circuit 130, and at least one synchronizer 132, which are related to Figure 2 Further description is given.

[0035] The processor 126, which may include a modem, may be implemented within the wireless transceiver 120 or separately from the wireless transceiver 120. As an example, the processor 126 is implemented as a system on a chip (SoC) that provides a digital communication interface for data, voice, messaging, and other applications of the computing device 102. The processor 126 may also include baseband circuitry to perform high-speed sampling processing, which may include analog-to-digital conversion, digital-to-analog conversion, gain correction, skew correction, frequency conversion, etc. Although not explicitly shown, the processor 126 may include a portion of the CRM 110 or may access the CRM 110 to obtain computer-readable instructions.

[0036] The processor 126 controls the wireless transceiver 120 and enables wireless communications. The processor 126 can provide communication data to the wireless transceiver 120 for transmission. The processor 126 can also process a baseband version of the signal received from the wireless transceiver 120 to generate data, which can be provided to other parts of the computing device 102 via a communication interface for wireless communication or proximity detection. In general, the processor 126 controls the operating mode of the wireless transceiver 120 or understands the operating mode. Different types of operating modes can include different transceiver modes (e.g., transmit mode or receive mode), different power modes (e.g., low power mode or high power mode), different resource control states (e.g., connected mode, inactive mode, or idle mode), different communication modes (e.g., 3G mode, 4G mode, 5G mode, Wi-Fi TM mode, GPS mode), different modulation modes (e.g., lower order modulation modes such as quadrature phase shift keying (QPSK) mode or higher order modulation modes such as 64 quadrature amplitude modulation (QAM) or 256QAM), etc. The processor 126 changes the configuration of the multi-mode oscillator circuit system 128 based on the operating mode of the wireless transceiver 120, such as regarding Figure 2 as further described.

[0037] Figure 2 An example implementation of a clock generator 124 that implements a multi-mode oscillator circuit system 128 with step control is illustrated. In the depicted configuration, the clock generator 124 includes the multi-mode oscillator circuit system 128, the step control circuit 130, and the synchronizer 132. The clock generator 124 also includes an output node 202, which can be coupled to other circuit components within the wireless transceiver 120, such as a PLL or a mixer. The multi-mode oscillator circuit system 128 is coupled between the step control circuit 130 and the output node 202. The synchronizer is coupled between the output node 202 and the step control circuit 130.

[0038] The multi-mode oscillator circuit system 128 includes at least two oscillators 204-1 and 204-2 and at least one resonator 206 (e.g., as few as one resonator). In some implementations, the oscillators 204-1 and 204-2 are implemented on an integrated circuit and the resonator 206 is implemented on a printed circuit board (PCB). The resonator 206 is coupled between the resonator nodes 208-1 and 208-2. Figure 22, resonator node 208-2 is shown coupled to output node 202. As such, resonator node 208-1 represents an input node of resonator 206, while resonator node 208-2 represents an output node of resonator 206. Each oscillator 204-1 and 204-2 is coupled to both resonator node 208-1 and resonator node 208-2.

[0039] In some implementations, the designs of oscillators 204-1 and 204-2 have different performance characteristics. As an example, oscillator 204-1 may generate a lower amount of phase noise relative to oscillator 204-2, but oscillator 204-2 may consume less power relative to oscillator 204-1. Oscillators 204-1 and 204-2 may be implemented as voltage mode oscillators, current mode oscillators, or a combination thereof. Example voltage mode oscillators and example current mode oscillators are respectively about Figure 5 and Figure 6 Further description is given below. Generally speaking, the oscillators 204-1 and 204-2 include a power circuit and an amplification circuit.

[0040] Oscillators 204-1 and 204-2 can be independently configured to be in an active state or an inactive state. In the active state, oscillator 204-1 or 204-2 consumes power and operates at a specific gain. Additionally, oscillator 204-1 or 204-2 generates an oscillation signal 210 having a peak-to-peak voltage based on the gain. Oscillating signal 210 enables resonator 206 to resonate. In Figure 2 In the example, oscillator 204-1 generates oscillation signal 210-1 and oscillator 204-2 generates oscillation signal 210-2. When in an active state, the gain of oscillator 204-1 or 204-2 can be changed. Different gains can cause oscillator 204-1 or 204-2 to consume different amounts of power or generate different amounts of phase noise.

[0041] In the inactive state, the oscillator 204-1 or 204-2 does not generate the oscillation signal 210 or generates the oscillation signal 210 with a peak-to-peak voltage that does not resonate the resonator 206. Generally speaking, based on the inactive state, the oscillation signal 210 has a lower peak-to-peak voltage relative to any of the peak-to-peak voltages associated with the active state based on the gain.

[0042] The resonator 206 may include, for example, a quartz crystal, as shown by the quartz crystal 212. In other implementations, the resonator 206 may include an inductor capacitor (LC) resonator, a resonator transistor (e.g., a bipolar junction transistor (BJT), a junction gate field effect transistor (JFET), a metal oxide semiconductor field effect transistor (MOSFET), or a gallium arsenide field effect transistor (GaAsFET)), a transmission line, a diode, a piezoelectric oscillator, a plurality of quartz crystals 212, a plurality of resonators, etc. The resonator 206 resonates at a particular frequency.

[0043] The multi-mode oscillator circuitry 128 also includes an amplifier 214 coupled between the resonator node 208-2 and the output node 202. Although not shown, the multi-mode oscillator circuitry 128 may include other types of components, such as resistors and capacitors.

[0044] The step control circuit 130 is coupled between the processor 126 and the multi-mode oscillation circuit system 128, and it includes at least two step drivers 216-1 and 216-2. The step drivers 216-1 and 216-2 are coupled to the oscillators 204-1 and 204-2, respectively, and generate step control signals 218-1 and 218-2, respectively. The step control signals 218-1 and 218-2 control whether the oscillators 204-1 and 204-2 are in an active state or an inactive state, respectively. Additionally, if the oscillators 204-1 and 204-2 are in an active state, the step control signals 218-1 and 218-2 control the corresponding gains of the oscillators 204-1 and 204-2. The stepper drivers 216 - 1 and 216 - 2 may be implemented as digital voltage generators that generate control voltages or discrete voltages that are provided to components within the oscillators 204 - 1 and 204 - 2 via stepper control signals 218 - 1 and 218 - 2 , respectively.

[0045] The synchronizer 132 provides feedback information to the stepper control circuit 130 based on the clock signal 220, which is generated by the resonator 206 at the resonator node 208-2. Specifically, the synchronizer 132 generates a timing signal 222, which includes a trigger to cause the stepper driver 216-1 to adjust the gain of the oscillator 204-1 or the stepper driver 216-2 to adjust the gain of the oscillator 204-2 at a specific time. In this way, the synchronizer 132 can cause the gain of the oscillators 204-1 and 204-2 to change during the time when the clock signal 220 is not near the zero crossing. By changing the gain near the peak of the clock signal 220, burr errors in the clock signal 220 can be avoided.

[0046] During operation, the processor 126 determines the operating mode of the wireless transceiver 120. Based on the operating mode, the processor 126 generates oscillator state signals 224-1 and 224-2, which control whether the oscillators 204-1 and 204-2 are in an active state or an inactive state, respectively. The processor 126 also generates target gain signals 226-1 and 226-2, which specify target gains for the oscillating signals 210-1 and 210-2, respectively.

[0047] The stepper drivers 216-1 and 216-2 appropriately configure the oscillators 204-1 and 204-2 by generating stepper control signals 218-1 and 218-2 based on the oscillator state signals 224-1 and 224-2 and the target gain signals 226-1 and 226-2. Based on the stepper control signals 218-1 and 218-2, the oscillators 204-1 and 204-2 generate oscillation signals 210-1 and 210-2, respectively. Due to the oscillation signals 210-1 and / or 210-2, the resonator 206 resonates and generates a clock signal 220, which is amplified by the amplifier 214. Using the oscillator state signals 224-1 and 224-2 and the target gain reference signals 226-1 to 226-2, the processor 126 can cause the multi-mode oscillation circuit system 128 to be in a particular configuration and switch between different configurations over time, such as with respect to Figure 3 as further described.

[0048] Figure 3 An example sequence flow chart 300 for operating the multi-mode oscillating circuit system 128 with step control is illustrated, where time passes in a downward direction. In the depicted example, the multi-mode oscillating circuit system 128 can be in a first configuration 302 or a second configuration 304 at different times. In the first configuration 302, the oscillator 204-1 is in an active state 306 and the oscillator 204-2 is in an inactive state 308. Additionally, for the first configuration 302, the gain of the oscillator 204-1 is at a first target gain. The oscillator 204-1 generates a first amount of phase noise and consumes a first amount of power at the first target gain.

[0049] In the second configuration 304, oscillator 204-1 is in an inactive state 308 and oscillator 204-2 is in an active state 306. Additionally, the gain of oscillator 204-2 is at a second target gain for the second configuration 304. Oscillator 204-2 generates a second amount of phase noise and consumes a second amount of power at the second target gain.

[0050] For example, consider that a first amount of phase noise generated under the first configuration 302 is lower than a second amount of phase noise generated under the second configuration 304. However, the second amount of power consumed under the second configuration 304 is lower than the first amount of power consumed under the first configuration 302. Therefore, the first configuration 302 produces better phase noise performance while the second configuration 304 produces reduced power consumption.

[0051] At 310, the wireless transceiver 120 is in a second operating mode 312 with a specific target phase noise level. As an example, the second operating mode 312 may represent a connected mode for 4G or an idle mode for 5G. In this case, the target phase noise level of the second operating mode 312 may be achieved using the first configuration 302 or the second configuration 304. However, because the second configuration 304 saves power, the processor 126 causes the multi-mode oscillation circuit system 128 to operate in the second configuration 304.

[0052] At 314, the wireless transceiver 120 is in a first operating mode 316 having a lower target phase noise level relative to the second operating mode 312. As an example, the first operating mode 316 may represent a connection mode for 5G. In this case, the target phase noise level of the first operating mode 316 may be achieved using the first configuration 302 but not the second configuration 304. In this way, the processor 126 causes the multi-mode oscillator circuit system 128 to operate in the first configuration 302 so that the wireless transceiver 120 can meet the target phase noise level of the first operating mode 316.

[0053] At 318, the wireless transceiver 120 is in the second operating mode 312. Thus, the processor 126 causes the multi-mode oscillating circuitry 128 to operate in the second configuration 304 to save power.

[0054] As the wireless transceiver 120 switches between the second operating mode 312 and the first operating mode 316, rather than abruptly switching between the second configuration 304 and the first configuration 302, the step control circuit 130 causes the multi-mode oscillator circuit system 128 to incrementally transition between the second configuration 304 and the first configuration 302. Specifically, as described with respect to Figure 4-1 and Figure 4-2 As further described, the step control circuit 130 incrementally adjusts the gain of the oscillator 204 - 1 and the oscillator 204 - 2 to enable the multi-mode oscillator circuitry 128 to transition between the second configuration 304 and the first configuration 302 without introducing glitch errors or stopping the clock signal 220 .

[0055] Figure 4-1 and Figure 4-2Example signals for operating the multi-mode oscillator circuit system 128 with step control are illustrated. Specifically, Figure 4-1 and Figure 4-2 The signals shown illustrate the incremental transition that occurs from operating the multi-mode oscillating circuitry 128 in the second configuration 304 to operating the multi-mode oscillating circuitry 128 in the first configuration 302. Graphs 400, 402, 404, 406 illustrate changes in the step control signal 218-2, the step control signal 218-1, the oscillation signal 210-1, and the oscillation signal 210-2, respectively, that may occur during the transition.

[0056] In a first example, the multi-mode oscillator circuit system 128 transitions from the second configuration 304 to the first configuration 302, which may occur in Figure 3 310 and 314 in. Assume that the target gain 412 of the first configuration 302 is gain 410-4. However, other operating modes may cause the target gain to be associated with a different gain such as one of gains 410-1, 410-2, or 410-3. Oscillators 204-1 and 204-2 may operate in an active state 306 with different gains. For example, oscillator 204-1 may operate with gains 408-1, 408-2, 408-3, and 408-4 that are ordered from the lowest gain to the highest gain. Additionally, oscillator 204-2 may operate with gains 410-1, 410-2, 410-3, and 410-4 that are also ordered from the lowest gain to the highest gain. Gains 408-1 to 408-4 and gains 410-1 to 410-4 may represent different gains (e.g., gains 408-1 to 408-4 are not necessarily equal to gains 410-1 to 410-4). In this example, oscillator 204-1 may operate at four different gains 408-1 through 408-4, while oscillator 204-2 may operate at four different gains 410-1 through 410-4. In other examples, oscillator 204-1 may operate at a different number of gains relative to oscillator 204-2.

[0057] At time T0, the multi-mode oscillator circuit system 128 operates in the second configuration 304. In the graph 400, the step control signal 218-2 is at a level that causes the oscillator 204-2 to be in the active state 306 and have a gain 408-4. In the graph 402, the step control signal 218-1 is at a level that causes the oscillator 204-1 to be in the inactive state 308. In the inactive state 308, the oscillator 204-1 does not generate the oscillation signal 210-1, as shown in the graph 404.

[0058] At time T1, the multi-mode oscillation circuit system 128 begins to transition to the first configuration 302 as the stepper driver 216-1 causes the oscillator 204-1 to switch from the inactive state 308 to the active state 306. To this end, the stepper control signal 218-1 rises to another level at T1, which causes the oscillator 204-1 to be in the active state 306 with a gain 410-1. As a result, the oscillator 204-1 generates an oscillation signal 210-1 having a first peak-to-peak voltage, as shown in the graph 404.

[0059] From time T2 to time T3 to time T4, the multi-mode oscillation circuit system 128 continues to transition to the first configuration 302 as the stepper driver 216-1 incrementally increases the gain of the oscillator 204-1 until the target gain 412 is achieved. To do so, the stepper driver 216-1 incrementally increases the level of the stepper control signal 218-1, which causes the gain of the oscillator 204-1 to change stepwise (e.g., from gain 410-1 to gain 410-2 to gain 410-3 to gain 410-4). By incrementally changing the gain, the oscillator 204-1 incrementally increases the peak-to-peak voltage of the oscillation signal 210-1, as shown in the graph 404. To mitigate glitch errors, the synchronizer 132 causes the level of the stepper control signal 218-1 to change at times T2, T3, and T4, which occur at times such as the peak-to-peak voltage of the oscillation signal 210-1. Figure 4-1 The peaks shown (the valleys in an alternative implementation not shown) are near and away from the zero crossings of the oscillating signal 210-1. During this time, the oscillator 204-2 continues to be in the active state 306 with a gain 408-4.

[0060] At time T4, oscillator 204-1 is at target gain 412 (e.g., gain 410-4). However, because oscillator 204-2 is in active state 306, multi-mode oscillator circuit system 128 is still in the transition configuration at time T4. In other words, multi-mode oscillator circuit system 128 is not in first configuration 302 and is not in second configuration 304 at time T4. To address this issue, step control signal 218-2 is adjusted, as described with respect to FIG. Figure 4-2 as further described.

[0061] exist Figure 4-24. In FIG. 4, the multi-mode oscillation circuit system 128 continues to transition to the first configuration 302 from time T5 to time T6 to time T7 to time T8 because the stepper driver 216-2 incrementally reduces the gain of the oscillator 204-2 before causing the oscillator 204-2 to switch from the active state 306 to the inactive state 308 at time T8. To do so, the stepper driver 216-2 incrementally reduces the level of the stepper control signal 218-2, which causes the gain of the oscillator 204-2 to change at intervals (e.g., from gain 408-4 to gain 408-3 to gain 408-2 to gain 408-1). By incrementally changing the gain, the oscillator 204-2 incrementally reduces the peak-to-peak voltage of the oscillation signal 210-2, as shown in the graph 406. To mitigate glitch errors, the synchronizer 132 causes the level of the stepper control signal 218-2 to change at times T5, T6, and T7, which occur at times such as Figure 4-2 The oscillator 204-2 is in the active state 306 with the lowest gain (e.g., gain 408-1) as shown in the graph 402. From time T5 to time T7, the oscillator 204-1 continues to be in the active state 306 with gain 410-4, as shown in the graph 402.

[0062] At time T8, in response to the stepper driver 216-2 causing the oscillator 204-2 to switch from the active state 306 to the inactive state 308 at time T8, the multi-mode oscillation circuit system 128 completes the transition to the first configuration 302. To this end, the stepper driver 216-2 reduces the stepper control signal 218-2 to another level at T8, which causes the oscillator 204-2 to be in the inactive state 308, as shown in the graph 400. Therefore, the oscillator 204-2 does not generate the oscillation signal 210-2, as shown in the graph 406.

[0063] From time T4 to T8 and beyond, oscillator 204-1 is in active state 306 and continues to generate oscillation signal 210-1 having gain 410-4 shown in graph 404 at time T4. Since multi-mode oscillation circuitry 128 is in first configuration 302 at time T8, resonator 206 generates clock signal 220 based on oscillation signal 210-1. This enables clock signal 220 to meet the target phase noise level of first operating mode 316 of wireless transceiver 120, as described above with respect to Figure 3 If the wireless transceiver 120 switches to the second operating mode 312, the multi-mode oscillator circuitry 128 may transition from the first configuration 302 to the second configuration 304 to save power.

[0064] like Figure 4-2As shown, incrementally reducing the gain of the oscillating signal 210-2 enables sensitive systems to reliably use the clock signal 220. For other types of less sensitive systems, the stepper driver 216-2 can cause the level of the stepper control signal 218-2 to change directly from T4 to T8. This causes the oscillator 204-2 to change directly from operating in the active state 306 with the gain 408-4 at time T4 to the inactive state 308 at time T8, thereby reducing the time it takes for the multi-mode oscillating circuit system 128 to transition from the first configuration 302 to the second configuration 304. Additionally, because the oscillator 204-1 is in the active state 306 before the oscillator 204-2 switches from the active state 306 to the inactive state 308, this change can occur without stopping the generation of the clock signal 220.

[0065] In a second example, the multi-mode oscillator circuit system 128 transitions from the first configuration 302 to the second configuration 304, which may occur at Figure 3 In this case, the operations described above are performed in reverse order (eg, performed from time T8 to time T1).

[0066] In general, the step rate or time period between T2, T3, T4, T5, T6, and T7 can be based on the period of the clock signal 220. As an example, the time period can be several periods of the clock signal 220 (e.g., ten or more periods of the clock signal 220). Additionally, the number of incremental steps that occur can vary based on the target gain 412, which can vary based on the operating mode of the wireless transceiver 120. As an example, the target gain 412 of the first configuration 302 can be the gain 410-2 for the GPS mode. Alternatively, the target gain 412 of the first configuration 302 can be the gain 410-4 for the 5G mode.

[0067] In other implementations, the multi-mode oscillator circuit system 128 may include more than two oscillators 204. As such, the multi-mode oscillator circuit system 128 may operate according to more than two configurations (e.g., more than two modes). The techniques described above with respect to transitioning between the first configuration 302 and the second configuration 304 may also be applied to transitioning between the first configuration 302 and the third configuration or between the second configuration 304 and the third configuration.

[0068] Figure 5An example voltage mode oscillator 500 for implementing the multi-mode oscillator circuit system 128 with step control is illustrated. In some implementations, the voltage mode oscillator 500 achieves better phase noise performance relative to the current mode oscillator. The voltage mode oscillator 500 includes an input node 502, a power circuit 504, an amplifier circuit 506, and an inverter 508. Consider that the voltage mode oscillator 500 implements the oscillator 204-1. In this case, the input node 502 is coupled to the stepper driver 216-1.

[0069] The power circuit 504 is coupled to the input node 502, the supply voltage 510, the ground 512, and the amplifier circuit 506. The power circuit 504 includes first switches 516-1 to 516-N, which are coupled to the supply voltage 510 and the amplifier circuit 506, where N represents a positive integer greater than 2. In the depicted configuration, the first switches 516-1 to 516-2 are implemented as p-channel metal oxide semiconductor field effect transistors (PMOSFETs). The power circuit 504 also includes second switches 518-1 to 518-N, which are coupled to the ground 512 and the amplifier circuit 506. The second switches 518-1 to 518-N are shown as Figure 5 An n-channel metal oxide semiconductor field effect transistor (NMOSFET) in.

[0070] The amplifier circuit 506 can implement a low noise variable gain amplifier. The amplifier circuit 506 includes a plurality of amplifier branches 514-1 to 514-N. The amplifier branches 514-1 to 514-N respectively include complementary metal oxide semiconductor (CMOS) inverters. Each amplifier branch 514-1 to 514-N is coupled to a first switch in a first switch 516-1 to 516-N and a second switch in a second switch 518-1 to 518-N. The gates of the NMOSFET and the PMOSFET in the CMOS inverter are coupled together to the resonator node 208-1. The drains of the NMOSFET and the PMOSFET in the CMOS inverter are coupled to the resonator node 208-2.

[0071] The step control signal 218-1 provides N discrete voltages to the second switches 518-1 to 518-N, respectively. These discrete voltages are also provided to the inverter 508. The inverter 508 provides inverted versions of the discrete voltages to the corresponding first switches 516-1 to 516-N. Based on the discrete voltages provided by the step control signal 218-1, different combinations of amplifier branches 514-1 to 514-N within the amplifier circuit 506 can be connected in parallel between the power supply voltage 510 and the ground 512 to achieve different gains, such as Figure 4-1To place the voltage mode oscillator 500 in the inactive state 308, the step control signal 218-1 causes the first switches 516-1 to 516-N to disconnect the amplifier branches 514-1 to 514-N from the supply voltage 510, respectively, and causes the second switches 518-1 to 518-N to disconnect the amplifier branches 514-1 to 514-N from the ground 512, respectively.

[0072] Figure 6 An example current mode oscillator 600 for implementing the multi-mode oscillator circuit system 128 with step control is shown. In some implementations, relative to Figure 5 Compared to the voltage mode oscillator 500, the current mode oscillator 600 consumes less power. The current mode oscillator 600 includes an input node 602, a power circuit 604, an amplifier circuit 606, a variable current source 608, and an automatic gain control circuit 610. Consider that the current mode oscillator 600 implements the oscillator 204-2. In this case, the input node 602 is coupled to the stepper driver 216-2.

[0073] The power circuit 604 is coupled to a variable current source 608, an amplifier circuit 606, and a ground 512. The power circuit 504 includes a PMOSFET coupled between the variable current source 608 and the amplifier circuit 606, and an NMOSFET coupled between the amplifier circuit 606 and the ground 512. The gates of the PMOSFET and the NMOSFET are coupled to a voltage generator (not shown) that provides voltages to bias the PMOSFET and the NMOSFET, respectively.

[0074] The amplifier circuit 606 can implement a low power amplifier. In this example, the amplifier circuit 606 includes a CMOS inverter. The gates of the NMOSFET and PMOSFET in the CMOS inverter are coupled together to the resonator node 208-1. The drains of the NMOSFET and PMOSFET in the CMOS inverter are coupled to the resonator node 208-2.

[0075] The variable current source 608 is coupled to the supply voltage 510, the input node 602, the automatic gain control circuit 610, and the PMOSFET of the power circuit 604. In the depicted example, the variable current source 608 includes pairs of switches 612-1 to 612-M and PMOSFETs 614-1 to 614-M that are coupled together in parallel between the supply voltage 510 and the source of the PMOSFET of the power circuit 604, where M represents a positive integer greater than two.

[0076] The automatic gain control circuit 610 is coupled between the resonator node 208-2 and the gates of the PMOSFETs 614-1 to 614-M. The automatic gain control circuit 610 generates a bias voltage 616 to bias the PMOSFETs 614-1 to 614-M based on the voltage at the resonator node 208-2.

[0077] The step control signal 218-2 provides M discrete voltages to the variable current source 608. These discrete voltages control the states of the switches 612-1 to 612-M. Based on the discrete voltages provided by the step control signal 218-2, different combinations of the PMOSFETs 614-1 to 614-M are connected to the supply voltage 510 to generate bias currents with different amplitudes. The different amplitudes of the bias currents enable the current mode oscillator 600 to achieve different gains, such as Figure 4-2 To place the current mode oscillator 600 in the inactive state 308 , the step control signal 218 - 2 causes the variable current source 608 to not generate a bias current.

[0078] Figure 7 700 is a flow chart illustrating an example process 700 for operating a multi-mode oscillator circuit system with step control. The process 700 is described in the form of a set of blocks 702 to 708, which specify operations that may be performed. However, the operations are not necessarily limited to Figure 7 The operations may be performed in an alternate order or in a fully or partially overlapping manner, rather than in the order shown or described herein. In addition, more, fewer, and / or different operations may be performed to perform process 700 or an alternative process. The operations represented by the illustrated blocks of process 700 may be performed by (e.g., Figure 1 or Figure 2 More specifically, the operations of process 700 may be performed by: Figure 2 The multi-mode oscillator circuit system 128 and the step control circuit 130 are shown to perform.

[0079] At block 702, a clock signal is generated using a resonator of a multi-mode oscillator circuit system. The multi-mode oscillator circuit system includes a first oscillator and a second oscillator, the first oscillator and the second oscillator being coupled to the resonator. For example, the resonator 206 of the multi-mode oscillator circuit system 128 generates the clock signal 220, such as Figure 2 The multi-mode oscillator circuit system 128 includes an oscillator 204 - 1 and an oscillator 204 - 2 , each of which is coupled to a resonator 206 .

[0080] At block 704, the multi-mode oscillator circuit system operates in a first configuration including a first oscillator in an active state and a second oscillator in an inactive state to enable the resonator to generate a clock signal. For example, the multi-mode oscillator circuit system 128 operates in a first configuration 302 including the oscillator 204-1 in an active state 306 and the second oscillator 204-2 in an inactive state 308, as shown in FIG. Figure 3 The first configuration 302 enables the resonator 206 to generate the clock signal 220 .

[0081] At block 706, the multi-mode oscillator circuit system operates in a second configuration including the first oscillator in an inactive state and the second oscillator in an active state to enable the resonator to generate a clock signal. For example, the multi-mode oscillator circuit system 128 operates in the second configuration 304 including the oscillator 204-1 in the inactive state 308 and the second oscillator 204-2 in the active state 306, as shown in FIG. Figure 3 The second configuration 304 enables the resonator 206 to generate the clock signal 220 .

[0082] At block 708, the multi-mode oscillator circuitry 128 transitions from operating in accordance with the second configuration 304 to operating in accordance with the first configuration 302 by incrementally increasing the first gain of the first oscillator while the second oscillator is in the active state. For example, the multi-mode oscillator circuitry 128 transitions from operating in accordance with the second configuration 304 to operating in accordance with the first configuration 302 based on the step control circuit 130 incrementally increasing the first gain of the first oscillator 204-1 while the second oscillator 204-2 is in the active state 306. Figure 4-1 shown.

[0083] Unless the context indicates otherwise, the word "or" used herein may be considered to be using an "inclusive or" or a term that permits the inclusion or application of one or more items linked by the word "or" (e.g., the phrase "A or B" may be interpreted as permitting only "A", only "B", or both "A" and "B"). Further, the items represented in the drawings and the terms discussed herein may indicate one or more items or terms, and thus reference may be made interchangeably to the items and terms in single or multiple forms in this written description. Finally, although the subject matter has been described in language specific to structural features or methodological operations, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or operations described above, including not necessarily to the organization of arranged features or the order in which operations are performed.

Claims

1. A device comprising: A multi-mode oscillator circuit system is configured to be selectively in a first configuration or a second configuration, the multi-mode oscillator circuit system comprising: Resonator; A first oscillator, coupled to the resonator, the first oscillator being configured to selectively: An activity state based on the first configuration; and An inactive state based on the second configuration; and A second oscillator, coupled to the resonator, the second oscillator being configured to selectively: the inactive state based on the first configuration; and the activity state based on the second configuration; and a step control circuit coupled to the multi-mode oscillator circuit system, the step control circuit being configured to: causing the first oscillator to switch from the inactive state to the active state; and A first gain of the first oscillator is incrementally increased based on the first oscillator being in the active state to enable the multi-mode oscillation circuitry to transition from the second configuration to the first configuration.

2. The device according to claim 1, wherein: The resonator is coupled between a first resonator node and a second resonator node; The first oscillator includes a first amplification circuit coupled to the first resonator node and the second resonator node; as well as The second oscillator includes a second amplification circuit coupled to the first resonator node and the second resonator node.

3. The device according to claim 1, wherein: The step control circuit is configured to incrementally increase the first gain of the first oscillator in two or more steps; and The second oscillator is configured to be in the active state while the step control circuit incrementally increases the first gain of the first oscillator.

4. The apparatus according to claim 1, wherein the step control circuit is configured to: incrementally increasing the first gain of the first oscillator to a target gain; and In response to the first gain of the first oscillator being at the target gain, the second oscillator is switched from the active state to the inactive state.

5. The device according to claim 4, wherein: The step control circuit is configured to incrementally decrease a second gain of the second oscillator before causing the second oscillator to switch from the active state to the inactive state.

6. The device according to claim 1, wherein: The stepper control circuit is configured as follows: causing the second oscillator to switch from the inactive state to the active state; and incrementally increasing a second gain of the second oscillator based on the second oscillator being in the active state to enable the multi-mode oscillation circuitry to transition from the first configuration to the second configuration; and The first oscillator is configured to be in the active state while the step control circuit incrementally increases the second gain of the second oscillator.

7. The device according to claim 6, wherein: the first oscillator being configured to generate a first oscillation signal in response to being in the active state; the step control circuit being configured to incrementally increase a first peak-to-peak voltage of the first oscillating signal to cause the multi-mode oscillating circuitry to transition from the second configuration to the first configuration; the second oscillator being configured to generate a second oscillating signal in response to being in the active state; as well as The step control circuit is configured to incrementally increase a second peak-to-peak voltage of the second oscillating signal to enable the multi-mode oscillating circuitry to transition from the first configuration to the second configuration.

8. The apparatus of claim 7, wherein the resonator is configured to selectively: generating a clock signal based on the first oscillation signal; generating the clock signal based on the second oscillation signal; or The clock signal is generated based on both the first oscillation signal and the second oscillation signal.

9. The device according to claim 6, wherein: The first oscillator comprises a voltage mode oscillator; and The second oscillator comprises a current mode oscillator.

10. The device according to claim 9, wherein: The voltage mode oscillator comprises: an amplifier circuit, comprising a plurality of amplifier branches; and A power circuit is coupled to the amplifying circuit, the power circuit comprising: first switches, respectively coupled between the plurality of amplifier branches and a power supply voltage; and second switches, respectively coupled between the plurality of amplifier branches and ground, The power circuit is configured to connect different numbers of the plurality of amplifier branches in parallel via the first switch and the second switch; and The step control circuit is configured to generate a step control signal that incrementally increases the number of the plurality of amplifier branches connected in parallel via the power circuit to incrementally increase the first gain of the voltage mode oscillator.

11. The device according to claim 9, wherein: The current mode oscillator comprises: a variable current source configured to generate a bias current; and an amplifier circuit coupled to the variable current source; and The step control circuit is configured to generate a step control signal that incrementally increases the magnitude of the bias current to incrementally increase the second gain of the current mode oscillator.

12. The apparatus according to claim 1, further comprising: Wireless transceiver; as well as A clock generator includes an output node, the multi-mode oscillation circuit system and the step control circuit, the output node is coupled to the wireless transceiver, and the clock generator is configured to generate a clock signal at the output node.

13. The device according to claim 12, wherein: The wireless transceiver is configured to selectively operate in a first operating mode or a second operating mode, the first operating mode having a first target phase noise level that is lower than a second target phase noise level of the second operating mode; The first oscillator is configured to consume a first amount of power to generate a first oscillating signal having a first amount of phase noise; The second oscillator is configured to consume a second amount of power to generate a second oscillating signal having a second amount of phase noise, the second amount of phase noise being greater than the first amount of phase noise, the second amount of power being lower than the first amount of power; The resonator is configured to selectively: generating the clock signal based on the first oscillation signal; or generating the clock signal based on the second oscillation signal; and The multi-mode oscillator circuit system is configured to selectively: based on the first configuration of the first operating mode; or The second configuration is based on the second operating mode.

14. The apparatus according to claim 12, further comprising: Display screen; as well as A processor is operably coupled to the display screen and the wireless transceiver, the processor being configured to present one or more graphical images on the display screen based on signals communicated by the wireless transceiver using the clock signal.

15. The device according to claim 12, wherein: The clock generator further includes a synchronizer coupled between the output node and the step control circuit, the synchronizer being configured to: A timing signal is generated at a time occurring between two zero crossings of the clock signal, the timing signal causing the step control circuit to increase the first gain of the first oscillator, the time being associated with a peak or a valley of the clock signal.

16. An apparatus comprising: A multi-mode oscillator circuit system is configured to be selectively in a first configuration or a second configuration, the multi-mode oscillator circuit system comprising: Resonator; A first oscillator, coupled to the resonator, the first oscillator being configured to selectively: An activity state based on the first configuration; and An inactive state based on the second configuration; and A second oscillator, coupled to the resonator, the second oscillator being configured to selectively: the inactive state based on the first configuration; and the activity state based on the second configuration; and A stepping component is configured to switch the first oscillator from the inactive state to the active state and incrementally increase a first gain of the first oscillator to enable the multi-mode oscillation circuitry to transition from the second configuration to the first configuration.

17. The device according to claim 16, wherein: The stepping component is configured to incrementally increase the first gain of the first oscillator in two or more steps; and The second oscillator is configured to be in the active state while the stepping component incrementally increases the first gain of the first oscillator.

18. The apparatus according to claim 16, wherein the stepping component is configured to: incrementally increasing the first gain of the first oscillator to a target gain; and In response to the first gain of the first oscillator being at the target gain, the second oscillator is switched from the active state to the inactive state.

19. The apparatus of claim 18, wherein: The stepping component is configured to incrementally decrease a second gain of the second oscillator before causing the second oscillator to switch from the active state to the inactive state.

20. The apparatus of claim 16, wherein: The stepping means comprises digital means for generating a stepping control signal, the stepping control signal controlling the first gain of the first oscillator.

21. The apparatus of claim 20, wherein: The first oscillator comprises: an amplifier circuit, comprising a plurality of amplifier branches; A power circuit is coupled to the amplifying circuit, the power circuit comprising: first switches, respectively coupled between the plurality of amplifier branches and a power supply voltage; and second switches, respectively coupled between the plurality of amplifier branches and ground, The power circuit is configured to connect different numbers of the plurality of amplifier branches in parallel via the first switch and the second switch; The step control signal includes discrete voltages, and the discrete voltages control the states of the first switch and the second switch respectively; and The digital component is configured to incrementally increase the number of the plurality of amplifier branches connected together in parallel via the step control signal to incrementally increase the first gain of the first oscillator.

22. The apparatus of claim 20, wherein: The first oscillator comprises: a variable current source configured to generate a bias current; and an amplifier circuit coupled to the variable current source; The stepping component controls the magnitude of the bias current; and The digital component is configured to incrementally increase the first gain of the first oscillator by incrementally increasing the magnitude of the bias current via the step control signal.

23. A method for operating a multi-mode oscillator circuit system with step control, the method comprising: generating a clock signal using a resonator of the multi-mode oscillator circuit system, the multi-mode oscillator circuit system including a first oscillator and a second oscillator, the first oscillator and the second oscillator being coupled to the resonator; operating the multi-mode oscillator circuitry in a first configuration to enable the resonator to generate the clock signal, the first configuration comprising the first oscillator in an active state and the second oscillator in an inactive state; operating the multi-mode oscillator circuitry in a second configuration to enable the resonator to generate the clock signal, the second configuration comprising the first oscillator in the inactive state and the second oscillator in the active state; as well as Transitioning from the multi-mode oscillatory circuitry operating in the second configuration to the multi-mode oscillatory circuitry operating in the first configuration is performed by incrementally increasing a first gain of the first oscillator while the second oscillator is in the active state.

24. The method of claim 23, wherein: The transitioning from the multi-mode oscillating circuit system operating in the second configuration to the multi-mode oscillating circuit system operating in the first configuration comprises: incrementally increasing the first gain of the first oscillator to a target gain in two or more steps; and In response to the first gain of the first oscillator being at the target gain, the second oscillator is switched from the active state to the inactive state.

25. The method of claim 24, wherein: The transitioning from the multi-mode oscillating circuit system operating in the second configuration to the multi-mode oscillating circuit system operating in the first configuration comprises: Prior to causing the second oscillator to switch from the active state to the inactive state, a second gain of the second oscillator is incrementally reduced.

26. The method of claim 23, further comprising: A transition is made from the multi-mode oscillatory circuitry operating in the first configuration to the multi-mode oscillatory circuitry operating in the second configuration by incrementally increasing a second gain of the second oscillator.

27. The method of claim 23, wherein: The operation of the multi-mode oscillator circuit system in the first configuration includes: generating a first oscillating signal via the first oscillator; and generating the clock signal based on the first oscillation signal; The operation of the multi-mode oscillator circuit system in the second configuration includes: generating a second oscillating signal via the second oscillator; and generating the clock signal based on the second oscillation signal; and The transitioning from the multi-mode oscillating circuit system operating in the second configuration to the multi-mode oscillating circuit system operating in the first configuration comprises: generating the first oscillating signal via the first oscillator; generating the second oscillating signal via the second oscillator; and The clock signal is generated based on both the first oscillation signal and the second oscillation signal.

28. An apparatus comprising: Clock generator, including: A multi-mode oscillation circuit system, comprising: Resonator; a first oscillator coupled to the resonator, the first oscillator being configured to be selectively in an active state or an inactive state; and a second oscillator coupled to the resonator, the second oscillator configured to be selectively in the active state or the inactive state; and Stepper control circuit, comprising: a first stepper driver coupled to the first oscillator and configured to incrementally adjust a first gain of the first oscillator while the second oscillator is in the active state; and A second stepper driver is coupled to the second oscillator and is configured to incrementally adjust a second gain of the second oscillator while the first oscillator is in the active state.

29. The apparatus of claim 28, wherein the clock generator comprises a synchronizer coupled between the multi-mode oscillation circuit system and the step control circuit, the synchronizer being configured to control a time when the first stepper driver adjusts the first gain and a time when the second stepper driver adjusts the second gain.

30. The apparatus of claim 28, wherein: The first oscillator comprises a voltage mode oscillator; and The second oscillator comprises a current mode oscillator.

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