Ratio gain error calibration scheme for delta-sigma adc with capacitive gain input stage

Abstract

An analog-to-digital converter (ADC) circuit includes a voltage input terminal, a reference input terminal, a sampling circuit, and a control logic component. The sampling circuit includes an input terminal, an output terminal, and capacitors in parallel disposed between the input terminal and the output terminal. The control logic component is configured to, during a calibration operation phase: cause a multiplexer to route the ADC reference input terminal to the sampling voltage input terminal; determine a given gain value; determine a set of multiple capacitors to be used to achieve the given gain value; successively enable subsets of the capacitors to sample a voltage of the reference input terminal while disabling the remaining capacitors until all of the capacitors have been enabled; determine a resulting output code; and determine, from the output code, a gain error for the given gain value of the ADC circuit.

Description

[0001] Related patent applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 852,544, filed May 24, 2019, the contents of which are hereby incorporated in their entirety. Technical Field

[0003] The present disclosure relates to analog-to-digital converters (ADCs), and more particularly to a ratiometric gain error calibration scheme for a Delta-Sigma (Δ-Σ) ADC having a capacitive gain input stage. Background Art

[0004] Analog-to-digital converters are used in electronic devices for consumer and industrial applications. Typically, an analog-to-digital converter includes circuitry for receiving an analog input signal and outputting a digital value proportional to the analog input signal. This digital output value is typically in the form of a parallel word or a serial digital bit string. There are many types of analog-to-digital conversion schemes, such as voltage-to-frequency conversion, charge redistribution, quadrature modulation, and others. Each of these conversion schemes typically has its own advantages and disadvantages. One type of analog-to-digital converter that is gaining popularity is the switched-capacitor delta-sigma converter.

[0005] The input stage of an ADC can be implemented using a switched capacitor sampling circuit for both the input voltage and the reference voltage. The gain of the input stage can then be determined by the ratio between the input sampling capacitor and the reference sampling capacitor, or the ratio between a pair of capacitors for a fully differential configuration. The gain of the ADC's input stage can be used to more closely match the ADC's input to the range within which the ADC is configured to convert analog signals into digital signals. For example, if the ADC's voltage range is 0 volts to 2 volts, but the expected ADC input is only in the range of 0 volts to 1 volt, the ADC can apply a gain of 2 to its input so that the possible values ​​of the ADC input match the ADC's range.

[0006] Using gain in the input stage of an ADC may introduce gain error. Gain error can be tested using a known, accurate reference voltage or source voltage. This accurate reference voltage or source voltage may be equal to the voltage of the ADC divided by the gain of the ADC. However, when the ADC is deployed in various electronic devices, such electronic devices may not include an accurate reference or source voltage or may not be able to obtain an accurate reference or source voltage. Therefore, self-testing of such ADCs may be impossible or impractical. Moreover, testing the ADC may require testing every gain arrangement or combination of capacitor gains in the input stage. Therefore, testing such ADCs may be very slow because each gain setting must be tested and its settling time may be long. The inventors of the embodiments of the present disclosure have discovered systems and methods for testing ADCs that address one or more of these challenges. Summary of the Invention

[0007] Embodiments of the present disclosure may include an analog-to-digital converter (ADC) circuit. The ADC circuit may include an ADC voltage input terminal, an ADC reference input terminal, and a sampling circuit. The sampling circuit may include a sampling voltage input terminal, a sampling voltage output terminal, and a capacitor connected in parallel and configured to selectively enable or disable. The capacitor may be provided between the sampling voltage input terminal and the sampling voltage output terminal. The ADC may include a multiplexer connected between the ADC voltage input terminal and the sampling voltage input terminal and between the ADC reference input terminal and the sampling voltage input terminal. The ADC may include a control logic component that is configured to, during a calibration operation phase: cause a multiplexer to route an ADC reference input terminal to a sampling voltage input terminal; determine a given gain value of the ADC circuit for which gain error is to be calibrated; determine a set of capacitors to be used to achieve the given gain value; successively enable a subset of capacitors in the set of multiple capacitors to sample a voltage at the ADC reference input terminal at the sampling voltage input terminal while disabling the remaining capacitors in the set of capacitors until all capacitors in the set of multiple capacitors have been enabled; determine an output code generated after all capacitors in the set of multiple capacitors have been enabled; determine a gain error for the given gain value of the ADC circuit from the output code; and take corrective action based on the gain error for the given gain value of the ADC circuit.

[0008] Embodiments of the present disclosure may include a system. The system may include a reference voltage source connected to an ADC reference input terminal of the ADC circuit and the ADC circuit of any of the above embodiments.

[0009] Embodiments of the present disclosure may include methods performed by any of the systems or ADCs of the above-described embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is an illustration of an example system for ADC gain error calibration according to some implementations.

[0011] Figure 2 is a diagram of an example system for ADC ratiometric gain error calibration according to an embodiment of the present disclosure.

[0012] Figure 3 An example implementation of an analog input multiplexer according to an embodiment of the present disclosure is shown.

[0013] Figure 4 is a diagram of an example implementation of a delta-sigma modulator circuit according to an embodiment of the present disclosure.

[0014] Figure 5 An example implementation of a sampling circuit according to an embodiment of the present disclosure is shown.

[0015] Figure 6 A timing diagram generated by a control circuit and applied to a sampling circuit according to an embodiment of the present disclosure is shown.

[0016] Figure 7 Another timing diagram to be applied to a sampling circuit according to an embodiment of the present disclosure is described.

[0017] Figure 8 is a diagram of an example method for determining ratiometric gain error for an ADC with a capacitive gain input stage, according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] Embodiments of the present disclosure include an ADC circuit. The ADC circuit can be included in any larger electronic device. The ADC circuit may include an ADC voltage input terminal. Utilizing the ADC voltage input terminal, the ADC circuit may be configured to receive a voltage for analog-to-digital conversion during normal operation. The ADC circuit may also include an ADC reference input terminal. Utilizing the ADC reference input terminal, the ADC circuit may be configured to receive a reference voltage that defines a range of voltages for analog-to-digital conversion. The ADC circuit may include a sampling circuit. The sampling circuit may be configured to sample inputs routed thereto. The sampling circuit may include a sampling voltage input terminal and a sampling voltage output terminal. Furthermore, the sampling circuit may include capacitors connected in parallel and configured to be selectively enabled or disabled. The number of enabled capacitors may define the gain of the sampling circuit, and thereby the gain of the ADC. The capacitors may be disposed between the sampling voltage input terminal and the sampling voltage output terminal. The ADC circuit may include a multiplexer connected between the ADC voltage input terminal and the sampling voltage input terminal, and between the ADC reference input terminal and the sampling voltage input terminal. The ADC circuit may include an integration circuit, such as a delta-sigma analog loop circuit, to accumulate values ​​sampled by the sampling circuit and generate an output code. The ADC circuit may include a control logic component. The control logic component may be configured to, during a calibration operation phase, cause a multiplexer to route the ADC reference input terminal to the sampling voltage input terminal and determine a given gain value for the ADC circuit for which gain error is to be calibrated. The control logic component may be configured to, during the calibration operation phase, determine a set of multiple capacitors in the sampling circuit to be used to achieve the given gain value; and successively enable a subset of capacitors in the set of capacitors to sample the voltage at the ADC reference input terminal at the sampling voltage input terminal, while disabling the remaining capacitors in the set of capacitors until all capacitors in the set of capacitors are enabled. The control logic component may be configured to, during the calibration operation phase, determine an output code generated after enabling all capacitors in the set of capacitors. The control logic component may be configured to determine, from the output code, a gain error for the given gain value of the ADC circuit during the calibration operation phase. The control logic component may also be configured to take corrective action based on the gain error for the given gain value of the ADC circuit. The corrective action may include, for example, alerting a user of the ADC circuit, adjusting the input range of the ADC circuit, or adjusting the output of the ADC circuit.

[0019] In conjunction with any of the above embodiments, each subset of the set of enabled capacitors may be configured to set the ADC circuit to perform at a gain of 1.

[0020] In combination with any of the above embodiments, a given gain value of the ADC circuit may be a multiple of 2.

[0021] In combination with any of the above embodiments, each subset of the set of capacitors can be enabled for the same number of samples.

[0022] In combination with any of the above embodiments, the control logic can be further configured to determine another gain value of the ADC circuit to calibrate for gain error during a calibration operation phase; determine another set of capacitors in the sampling circuit to implement the another gain value; successively enable subsets of capacitors in the another set of capacitors to sample the voltage of the ADC reference input terminal at the sampling voltage input terminal while disabling remaining capacitors in the another set of capacitors until all capacitors in the another set of capacitors have been enabled; determine an output code produced after all capacitors in the another set of capacitors have been enabled; and determine a gain error of the another gain value of the ADC circuit from the output code. This can be repeated for any suitable gain value of the ADC circuit.

[0023] In combination with any of the above embodiments, the control logic can be further configured to sample the voltage of the ADC reference input terminal at the sampling voltage input terminal for a given number of samples; and sample each subset of the set of capacitors for a subset of the given number of samples, where the subset of the given number of samples is equal to the given number of samples divided by the given gain value.

[0024] In combination with any of the above embodiments, the division of the given number of samples by the given gain value has no remainder.

[0025] Figure 1 is a diagram of an example system 100 for ADC gain error calibration according to some implementations. The system 100 can include an ADC 102. The ADC 102 can be a delta-sigma ADC. The system 100 can be configured to determine a gain error in the ADC 102.

[0026] The ADC 102 can be configured to convert an analog input signal into a digital output code. The analog input signal can be single-ended (not shown, in which case a voltage is received as input and the received voltage is compared to a ground voltage) or differential, as shown in Figure 1 The differential analog input can be a voltage difference between a VIN+ terminal and a VIN- terminal of the ADC 102, resulting in a sum VIN (VIN = VIN+ - VIN-). The ADC 102 can be configured to receive a reference voltage. The reference voltage can be single-ended (not shown, in which case a voltage is received as a reference and the received reference voltage is compared to a ground voltage) or differential, as shown in Figure 1The differential analog input may be the voltage difference between the VREF+ terminal and the VREF- terminal of the ADC 102, resulting in a total VREF, which is given by:

[0027] VREF=VREF+-VREF-

[0028] These differential voltages can be added to a common mode, not depicted in the figure. The output code can be a value proportional to VIN / VREF. The ADC code is given by:

[0029] ADC code = K*VIN / VREF

[0030] Where K is a constant.

[0031] ADC 102 may have an analog gain denoted as G. This analog gain G amplifies the input signal VIN inside ADC 102 so that the voltage converted by ADC 102 is actually G*VIN. In this case, the transfer function of ADC 102 becomes:

[0032] ADC code = G*K*VIN / VREF

[0033] VREF may define the range of voltage inputs that can be converted by ADC 102. For a single-ended converter, the input voltage range applicable to A / D conversion may be the range [0, VREF]. For a fully differential converter, the input voltage range applicable to A / D conversion may be the range [-VREF, +VREF]. When a gain of G is applied, the input voltage range of ADC 102 remains the same, but applies to G*VIN, so the input voltage range effectively becomes the range [0, VREF / G] for a single-ended converter and [-VREF / G, +VREF / G] for a fully differential converter. Outside this range, the A / D conversion may experience greater inaccuracies, the output codes may be clipped, and the overall linearity of the converter may no longer be guaranteed.

[0034] ADC 102 can be configured to achieve analog gain G through various methods, but due to physical implementation limitations (such as mismatches between analog components in ADC 102), the actual transfer function performance of ADC 102 may not exactly equal the expected or ideal transfer function performance. Therefore, system 100 can enable gain measurement and compensation to be performed within ADC 102 to more closely approximate the expected or ideal transfer function (G*K*VIN / VREF). The error in achieving the gain of the transfer function is referred to as the ADC's gain error. The ADC transfer function can then be equal to G*K'*VIN / VREF, where (K' / K-1) is the gain error of gain G. The inventors of the disclosed embodiments have discovered that gain error can vary and depend on gain G, in addition to other parameters such as temperature or supply voltage. Gain error is the error in the slope of the linear transfer function of ADC 102. Other errors may also occur and be characterized, including errors that occur in addition to gain error. Such other errors may include offset error, integral nonlinearity error, and differential nonlinearity error. These other errors are independent of the gain error and can be addressed independently.

[0035] In order to measure the gain of the ADC 102 (and thereby assess the gain error), two measurements are performed. From these two measurements, the equation of the straight line at the intersection of these data points can be extracted and the slope of the line determined. If the two points are farther apart, the inaccuracy introduced by the measurement becomes less important and can be ignored if the inaccuracy is small compared to the voltage being measured. Typically, these two measurements are made with a zero voltage input and a full-scale voltage range (FS) for a single-ended converter and with a negative full-scale (-FS) and a positive full-scale (+FS) for a fully differential converter. The full-scale signal may include the extremes of the input voltage range. To maximize the accuracy of the gain error measurement, the system typically measures as follows: for a single-ended converter, VIN is set to zero and VIN is set to FS, which is (REF / G); for a fully differential converter, VIN- is set to -FS, which is (-VREF / G), and VIN+ is set to FS, which is (VREF / G). This is Figure 1 The VIN input of ADC 102, depicted in FIG, is connected to a voltage source 101 that applies a -FS value, a 0 value, or a +FS value. Meanwhile, the VREF input of ADC 102 is connected to a voltage source 103, whose value is constant and equal to VREF.

[0036] A zero-value measurement measures the offset of ADC 102. To measure the offset, zero volts can be applied to the VIN input of ADC 102 and the output of ADC 102 observed. A zero-value measurement can be achieved by shorting the VIN+ and VIN- inputs together, resulting in VIN = 0 at the VIN input of ADC 102. This can be performed internally within ADC 102. However, this can make it more difficult to accurately generate the FS signal, where the entire input range of ADC 102 is used by the voltage input. When G = 1, VIN with the VREF voltage can be generated by an input switch that multiplexes the VREF input and the VIN input. However, if G is not equal to 1, the FS signal cannot be easily generated because it is not a simple copy of an existing voltage, such as by shorting VIN+ and VIN- to obtain 0 volts, or by connecting to VREF+ and VREF- to obtain VREF. The FS = VREF / G input voltage is typically generated from another voltage source or by using a DAC that uses a reference voltage as a reference element. However, the inventors of the present disclosure have discovered that such FS signals can be inaccurate due to the total unadjusted error of the DAC or inaccuracies in the reference voltage. Reference voltage inaccuracies can directly lead to additional error sources in the gain measurement of ADC 102 and, in some cases, can even become the dominant error source in ADC 102 performance. Furthermore, adding a DAC or voltage source to generate such a reference voltage can increase the overall system cost of system 100. Furthermore, during operation of system 100, the DAC or voltage source added to generate such a reference voltage may not be effectively applied to ADC 102 to measure gain error. Furthermore, because a given ADC can include many different gain settings, a different voltage must be generated for each new value of G to be tested. The settling time required to create each such reference voltage can delay ADC 102 evaluation.

[0037] Therefore, the inventors of the embodiments of the present disclosure have discovered that it is desirable to have a system that measures gain error without generating an FS signal by dividing a reference voltage by a gain (VREF / G). The inventors of the embodiments of the present disclosure have discovered a system that can have significant advantages, such as not requiring the use of an external voltage source or DAC and having a faster settling time. Such a system can measure gain error using only zero-value measurement (VIN=0) and VIN=VREF voltage instead of full-scale (VREF / G) voltage, thereby reducing inaccuracies caused by voltage measurement by using input voltages across all gains. However, when using a standard ADC, a gain greater than 1 does not allow the input voltage VIN to be greater than VREF / G (thus VIN*G is greater than VREF). The embodiments of the present disclosure address at least some of these issues and include an ADC that allows VIN=VREF to be input for any given gain G, while still allowing an accurate assessment of the gain error obtained when any given gain G is selected and applied to the ADC.

[0038] Figure 2 is a diagram of an example system 200 for ADC ratiometric gain error calibration according to an embodiment of the present disclosure.

[0039] System 200 can be adapted for or include any suitable ADC, such as ADC 203. ADC 203 can be included in a microcontroller, a processor, a mobile device, a computer, a smartphone, a tablet, a power converter, a controller, a power supply, a sensor, a vehicle, or any other suitable electronic device. ADC 203 can be a delta-sigma ADC. Furthermore, ADC 203 can include a capacitive gain input stage. System 200 can be configured to determine a gain error in ADC 203. Furthermore, system 200 can be configured to calibrate the operation of ADC 203 based on any determined gain error, or to take any other suitable corrective action.

[0040] ADC 203 may include ADC voltage input terminals, such as VIN+ and VIN-. ADC 203 may include ADC reference input terminals, such as VREF+ and VREF-.

[0041] The ADC 203 may be configured to convert an analog input signal into a digital output code. The analog input signal may be single-ended (not shown, in which case a voltage is received as an input and the received voltage is compared to ground) or differential, as shown in FIG. Figure 2The differential analog input may be the voltage difference between VIN+ and VIN-, resulting in a total VIN (VIN=VIN+-VIN-). The ADC 203 may be configured to receive a reference voltage. The reference voltage may be single-ended (not shown, in which case the received voltage is used as a reference and the received reference voltage is compared to ground) or differential, as shown in FIG. Figure 2 As shown in the figure, the differential analog input can be the voltage difference between VREF+ and VREF-, resulting in a total VREF (VREF = VREF+ - VREF-). These differential voltages can be added to a common mode, not depicted in the figure. The output code can then be a value proportional to VIN / VREF (ADC code = K*VIN / VREF, where K is a constant).

[0042] ADC 203 may have a variable, selectable gain, whose value is denoted as G. This analog gain G amplifies the input signal VIN inside ADC 203 so that the voltage converted by ADC 102 is actually G*VIN. In this case, the transfer function of ADC 203 becomes

[0043] ADC code = G*K*VIN / VREF

[0044] VREF may define the range of voltage inputs that can be converted by ADC 203. For a single-ended converter, the input voltage range applicable to A / D conversion may be [0, VREF]. For a fully differential converter, the input voltage range applicable to A / D conversion may be [VREF-, VREF+]. When a gain of G is applied, the input voltage range to ADC 203 remains the same, but applies to G*VIN, so the input voltage range effectively becomes [0, VREF / G] for a single-ended converter and [VREF- / G, VREF+ / G] for a fully differential converter. Outside this range, the A / D conversion may experience greater inaccuracies, the output codes may be clipped, and the overall linearity of the converter may no longer be guaranteed.

[0045] ADC 203 can be connected to voltage source 201. The voltage of voltage source 201 can be selected between + / - VREF or 0. Voltage source 201 can generate voltages external to system 200 (using an external voltage source or multiplexer) or internal to system 200. These voltages can be applied via analog input multiplexer 204. Analog input multiplexer 204 can be implemented in any suitable manner. Analog input multiplexer 204 can be configured to generate a VOUT signal (VOUT+-VOUT-) such that VOUT = + / - VREF or 0. The VOUT signal can be provided to delta-sigma modulator circuit 205.

[0046] ADC 203 may be a delta-sigma ADC and, therefore, include a delta-sigma modulator circuit 205. Delta-sigma modulator circuit 205 may be implemented in any suitable manner, such as by digital circuitry, analog circuitry, instructions executed by a processor (not shown), or any suitable combination thereof. Delta-sigma modulator circuit 205 may include a stage with an analog gain G to amplify the input received at the VI+ / VI- input terminals. Delta-sigma modulator circuit 205 may receive a reference voltage signal routed from the VREF+ / - input terminals of ADC 203 without any modification.

[0047] System 100 may include a voltage reference component 202. Voltage reference component 202 may be implemented in any suitable manner. Voltage reference component 202 may generate a reference voltage for system 200. Voltage reference component 202 may be internal to ADC 203 (not shown) in system 200 or external to ADC 203. Furthermore, voltage reference component 202 may be external to system 200.

[0048] The delta-sigma modulator circuit 205 can be configured to generate a bit stream based on its input. The voltage inputs to the delta-sigma modulator circuit 205 (to be amplified according to the gain G) can be represented as VI+ and VI-. The delta-sigma modulator circuit 205 can also include reference voltage inputs, represented as VREF+ and VREF-. The bit stream can be sent to the digital filter 206. The digital filter 206 can be implemented by digital circuitry, analog circuitry, instructions executed by a processor (not shown), or any suitable combination thereof. The digital filter 260 can be configured to generate a digital output code at the end of a conversion cycle, with a time increment represented as TCONV. TCONV can be long enough for the delta-sigma modulator circuit 205 to process its input to generate the bit stream.

[0049] In one embodiment, the system 200 can be configured to evaluate the gain error of the ADC 203 for any given gain G (G integer) setting without generating different reference signals, such as + / - VREF / G signals. In another embodiment, the system 200 can be configured to evaluate the gain error of the ADC 203 without generating any external voltage reference or DAC by using the analog input multiplexer 204 to switch the existing voltage at the input of the delta-sigma modulator circuit 205.

[0050] ADC 203 may include control logic 207. Control logic 207 may be implemented by digital circuitry, analog circuitry, instructions executed by a processor, or any suitable combination thereof. Control logic 207 may be configured to selectively operate ADC 203 during a calibration phase of operation or during a normal phase of operation. During the calibration phase, the inputs of delta-sigma modulator circuit 205 may be controlled to operate ADC 203 in a manner to assess whether ADC 203 has any gain error and, based on such determination, adjust the operation of ADC 203 to account for such gain error. During the normal phase, the inputs of delta-sigma modulator circuit 205 may be controlled to operate ADC 203 in a manner to generate a digital code output based on inputs from voltage source 201 and reference component 202, which reflect analog signals for which system 200 requests an associated digital value. Control logic 207 may be configured to selectively operate one or more of analog input multiplexer 204, delta-sigma modulator circuit 205, and digital filter 206.

[0051] During the calibration operation phase, the multiplexer 204 can be configured to route the ADC reference input terminals VREF+ / VREF- to the sampling voltage input terminals VI+ and VI- of the delta-sigma modulator circuit 205 and the sampling circuit therein. During the normal operation phase, the multiplexer 204 can be configured to route the ADC voltage input terminals VIN+ / VIN- to the sampling voltage input terminals VI+ and VI- of the delta-sigma modulator circuit 205 and the sampling circuit therein.

[0052] Figure 3 1 shows an example implementation of the analog input multiplexer 204 according to an embodiment of the present disclosure. The analog input multiplexer may include eight switches 301-308. Switch 301 can connect VIN+ to VOUT+. Switch 302 can connect VIN- to VOUT+. Switch 303 can connect VREF+ to VOUT+. Switch 304 can connect VREF- to VOUT+. Switch 305 can connect VIN+ to VOUT-. Switch 306 can connect VIN- to VOUT-. Switch 307 can connect VREF+ to VOUT-. Switch 308 can connect VREF- to VOUT-. At any given time, only one of switches 301, 302, 303, and 304 can be enabled; the others are disabled. Similarly, only one of switches 305, 306, 307, and 308 can be enabled; the others are disabled / off. Figure 3The enabling or disabling of the switches in the analog input multiplexer 104 can be performed at the direction of the control logic component 207 (not shown). This implementation allows the desired + / -VREF or zero differential voltage to be generated. For zero-value measurements, switches 301 and 305 can be enabled, or switches 302 and 306 can be enabled. For +VREF measurements, switches 303 and 308 can be enabled. For -VREF measurements, switches 304 and 307 can be enabled. In each of these examples, the remaining switches can be disabled. Although shown as a separate component, analog input multiplexer 104 can be implemented as a specific circuit within ADC 203, external to ADC 203, or within delta-sigma modulator circuit 205. Analog input multiplexer 204 can also include additional components and can be implemented as part of a larger multiplexer, as long as analog input multiplexer 204 can connect VOUT to + / -VREF or 0 throughout the A / D conversion period.

[0053] Figure 4 is a diagram of an example implementation of delta-sigma modulator circuit 205 according to an embodiment of the present disclosure.

[0054] Delta-sigma modulator circuit 205 may include sampling circuit 401, control circuit 402, and delta-sigma analog loop circuit 403. Sampling circuit 401, control circuit 402, and delta-sigma analog loop circuit 403 may be implemented by analog circuits, digital circuits, instructions executed by a processor (not shown), or any suitable combination thereof.

[0055] Sampling circuit 401 may include sampling voltage input terminals VI+ and VI-. Sampling circuit 401 may be configured to sample the input voltages at VI+ and VI-. Furthermore, sampling circuit 401 may be configured to apply a gain, G, to the input voltage signals and output these signals at sampling voltage output terminals, VO+ and VO-. Sampling circuit 401 may be configured to operate based on commands or signals from control circuit 402. Control circuit 402 may also receive commands or signals from control logic component 207 (not shown). Delta-sigma analog loop circuit 403 may be configured to generate an output bit stream that is fed to digital filter 206 in ADC 203. Reference input signals VREF+ and VREF- (also denoted as VREF+ and VREF-) may be routed unmodified to the delta-sigma analog loop input circuit 403 reference pins.

[0056] Figure 5 FIG. 4 shows an example implementation of a sampling circuit 401 according to an embodiment of the present disclosure. In one embodiment, as Figure 5 As shown, the sampling circuit 401 can be implemented in a fully differential manner or in a single-ended manner, where VI- is grounded.

[0057] Sampling circuit 401 may have two pairs of input switches 501 and 502. In an interleaved implementation, input switches 501 and 502 may be connected to inputs VI+ / −, with VI+ connected to switch 501A and switch 502B, and VI− connected to switch 502A and switch 501B. Switch 501 may be controlled by a first switch control signal S1. Switch 502 may be controlled by a second switch control signal S2. Switches 501A and 502A may be connected to capacitor array 507A. Switches 501B and 502B may be connected to capacitor array 507B. Capacitor array 507 may be implemented with capacitors connected in parallel and configured to be selectively enabled or disabled. Capacitor array 507 may be configured to be disposed between sampling input voltage terminal VI+ and sampling input voltage terminal VI−, and between sampling output voltage terminal VO+ and sampling output voltage terminal VO−.

[0058] Capacitor array 507A may include a series of input switches 505A and a series of output switches 506A, which are configured to select which capacitors of capacitor array 507A will be connected to input switch 501A and input switch 502A. Similarly, capacitor array 507B may include a series of input switches 505B and a series of output switches 506B, which are configured to select which capacitors of capacitor array 507B will be connected to input switch 501B and input switch 502B. Each capacitor array 507 may include up to n pairs of capacitors with the same and matched values, and the capacitors in capacitor array 507A are designated as CIN 1...n + and the capacitor in capacitor array 507B is named CIN 1...n -. Switch 505 and switch 506 can be controlled by a command SG applied to the two capacitor arrays 507 1...n Control, so that the given enable command SG k Enable capacitor CIN k + / - to sample the input signal routed by switch 501 and switch 502. Switch 501 and switch 502 may not be enabled at the same time. Switch commands S1 and S2 applied to switches 501 and 502, respectively, may be clocked on two different phases of the same clock in a non-overlapping manner. Switches 503A and 503B may be configured to connect each CIN 1...nEach plate of the + / - capacitors is connected to an internal common-mode voltage (VCM). This VCM can also be generated externally. If all capacitors are matched and only G pairs of capacitors are actually connected via switches 505 and 506, the gain of the system will be G times greater than if only one pair of capacitors were connected via switches 505 and 506. Thus, sampling circuit 401 effectively achieves an analog gain of G while sampling the input signal present at inputs VI+ / -. If G capacitors are selected, the sampled charge on capacitor array 507 will be G times greater than if only one capacitor is selected to sample the VI+ and VI- input signals. The VO+ / - output can then be sent to delta-sigma loop circuit 403, which can be configured to evaluate the amount of charge stored on the sampling circuits within capacitor array 507 and, therefore, generate a bit stream that will be filtered by digital filter 206 to produce the output code of ADC 203. Other sources of gain error can be inherent to delta-sigma analog loop circuit 403, delta-sigma modulator circuit 205, or digital filter 206. However, these errors may not depend on the gain G, and this may be ignored to simplify the description of this disclosure.

[0059] The gain G implemented by the sampling circuit 401 is subject to inaccuracies in its implementation, such as CIN 1...n The gain may also be affected by the parasitic capacitors used to implement switches 505 and 506. Therefore, such switches should be made small enough so that the additional capacitance is small relative to each CIN. 1...n The leakage current through the sampling circuit 401 is negligible compared to the unit capacitance of + / -. Switches 505 and 506 should also be implemented so that the leakage current through them is negligible when they are in the disabled state. Since ADC 203 is a delta-sigma converter, the delta-sigma analog loop circuit 403 may include an integrator circuit, so any leakage current from the sampling circuit 401 can be integrated into the loop, resulting in potentially large inaccuracies. This leakage current effect can be minimized through appropriate switch implementation technology and faster conversion times. These inaccuracies are taken into account in the gain error measurement system described herein. The maximum gain of the sampling circuit 401 is determined by the number of paired capacitors in each array 507. In this example, the maximum value is n. Due to capacitor mismatch and switch inaccuracies, the source of gain error of the ADC 203 at each gain is primarily in the sampling circuit 401.

[0060] During the calibration operation phase, control circuit 402 and control logic 207 can be configured to issue switching signals to switches 501, 502, 503, 505, and 506. Such switching signals are illustrated in greater detail in the timing diagram below. Control logic 207 can be configured to operate multiplexer 204 to route the reference voltage input (VREF) of ADC circuit 200 to the VI+ / - inputs of sampling circuit 401 during the calibration operation phase. Control circuit 402 and control logic 207 can be configured to determine which gain value to test. The gain value to test can be determined on any suitable basis, such as by a command to ADC circuit 200, a register value, a setting, or any other suitable input. Furthermore, possible gain values ​​of ADC circuit 200 can be tested continuously. Based on the gain value to be tested, control circuit 402 and control logic 207 can be configured to determine which subset of capacitors 507 are associated with the gain value. The subset can be defined based on capacitor pairs. The determination of which subsets of capacitors 507 are associated with a gain value can be made in any suitable manner, such as by reference to a user command, setting, or register value. Based on which subsets of capacitors 507 are associated with a gain value, each subset is sequentially enabled for a determined number of samples, while the other subsets and the remainder of capacitors 507 are disabled. This can be performed using control signals sent to switches 501, 502, 503, 505, and 506, as described in greater detail below. This process can be repeated for each subset of capacitors 507 associated with a gain value. During the period in which each subset of capacitors 507 is enabled, the ADC circuit 200 and sampling circuit 401 can have an effective gain of 1. Each subset of capacitors 507 can be enabled for the same number of samples. After all subsets of capacitors 507 associated with a gain value have been enabled, the values ​​stored in capacitors 507 can be integrated by delta-sigma analog loop circuit 403, which can generate an output code in the form of a bitstream. The control logic component 207 can be configured to take corrective action to correct the gain error based on the gain error determined from the output code. The control logic component 207 may determine another gain value for the ADC circuit 200 to be calibrated, determine another set of capacitors 507 for achieving the other gain value, successively enable a subset of the set of capacitors 507 while disabling the remaining capacitors 507, determine another output code resulting from enabling all capacitors 507 in the other set, and determine another gain error for the other gain value of the ADC circuit 200 from the other output code. The control logic component 207 may be configured to sample each subset of the set of capacitors 507 to obtain a subset of the total number of samples. All sampling may be performed across all subsets to obtain a given gain value. The total number of samples taken for a given gain value divided by the given gain value is the number of samples in each subset of the total number of samples.The quotient of the total number of samples divided by the gain value can have no remainder.

[0061] Figure 6 A timing diagram is shown that is generated by the control circuit 402 and applied to the sampling circuit 401 according to an embodiment of the present disclosure. Figure 6 The timing diagram describes the switch commands S1, S2 and SG during a standard conversion in normal phase for a given set value of the analog gain G of the ADC 203 1...n With this timing diagram, the voltage converted at the input VIN+ / - of the VIN terminal of the ADC 203 is amplified G times within the sampling circuit 401 when converted from voltage to charge by using the capacitor array 507.

[0062] In Figure 6 , the timing diagram shows one conversion period, which has a total time of TCONV. One conversion can be divided into a number of samplings. The necessary number of samplings can be an oversampling rate (OSR). Each sampling is timed with a constant sampling time taken at a sampling frequency fs. Thus,

[0063] TCONV = OSR / fs.

[0064] To achieve a gain G, the control circuit 402 can have to generate control signals for SG 1...n switches. In the n pairs of capacitors in the capacitor array 507, only the number G should be selected to achieve a gain G. The specific capacitors of the n capacitors can be chosen arbitrarily, but since the gain error depends to a large extent on the capacitor mismatch, the control circuit 402 should always select the same capacitor pair in order to produce a repeatable gain error at each conversion, which can be taken into account. Since the order in which the capacitors are selected is not important, the example shown in Figure 6 selects the first SG 1...G capacitor pair. These capacitor pairs are selected by enabling the respective switches in the switches 505 and 506. In Figure 6 , the SG 1...G timing diagram shows that the logic signal is high (where a logic high enables the switches in the convention selected in Figure 6 ) during the entire conversion period. The other switches SG G+1...n are disabled (logic low during the entire conversion period), so no charge is sampled on these capacitors during the conversion.

[0065] During each sampling period, the signals S1 and S2 that control switches 501, 502, and 503 represent two phases of the same clock running at a frequency of fs. To avoid any short circuits, these signals are not simultaneously logic high. During the S1 phase (when S2 is logic low and S1 is logic high), switches 501 and 503 are enabled, thus providing a voltage across capacitor CIN. 1...G The input voltages VI+ and VI- are sampled on the + / - pins. During this time, the input voltages are converted into charges that are stored in the capacitor array 507. If all capacitors are matched and their values ​​are equal to C, then the charge stored on capacitor CIN 1...G The total charge on the + will be equal to G*C*(VI+-VCM). Similarly, the charge stored on capacitor CIN 1...G The total charge difference between the capacitors is G*C*(VI - VCM).

[0066] Q = G*C*(VI+-VI-).

[0067] If each capacitor is equal to CIN k and is therefore equal to C*e k (Considering the error factor e of each capacitor k ), then the sum will be

[0068] Q=C*Σ{(e k )*(VI+-VI-)}.

[0069] Here, for simplicity, the capacitor has been defined as CIN k + and CIN k -, since their mismatch between positive and negative results in a common-mode variation that will be filtered out by the fully differential nature of the converter. The gain error will be

[0070] GERR=Σ{(e k ) / G-1}.

[0071] This gain error is caused by capacitor mismatch and includes the parasitic effects of each capacitor in switch 505 and switch 506. This gain error is the ADC gain error caused by sampling circuit 401. ADC 203 may have other sources of gain error, but these may not depend on the gain selection, but rather are inherent to other parts of system 200. Therefore, when the gain selection is changed, these other gain error sources should remain constant and can be ignored for the purpose of gain error measurement because they do not contribute to it.

[0072] During the S2 phase (when S2 is logic high and S1 is logic low), terminals VO+ and VO- are typically connected to a virtual ground (e.g., the input of an operational amplifier) ​​so that the charge stored on the capacitor can be transferred to the rest of the circuitry to be integrated into the delta-sigma analog loop circuit 403. In this example, switch 502 is enabled and switches 501 and 503 are disabled. By connecting switch 502 to the opposite input (compared to switch 501), another sampling of the VI+ / - inputs is performed, synchronized with the charge transfer achieved in the S2 phase. This additional sampling does not change the gain error, but has the effect of multiplying the gain of the sampling circuit by 2, thereby improving the signal-to-noise ratio of the sampling and transfer events for each sampling time. The total charge during the S1 and S2 phases is then given by:

[0073] Qtot=2*C*Σ(e k )*(VI+-VI-).

[0074] In one embodiment, sampling circuit 401 may be used in a configuration where the gain would be 1 instead of G, but where the gain error would be substantially equal to the gain error estimated when the gain was G, e.g. Figure 6 In one embodiment, it may not be necessary to modify sampling circuit 401 to achieve a gain of 1 with a gain error substantially equal to the gain error estimated when the gain is G. Instead, the control of switches 505 and 506 may be modified as described below.

[0075] Figure 7 Another timing diagram to be applied to the sampling circuit 401 according to an embodiment of the present disclosure is described. Figure 7 This timing diagram can be realized with Figure 6 The same gain error is achieved by this timing diagram, but when applied to sampling circuit 401, Figure 7 This timing diagram can be used to define this same gain error using a gain of 1.

[0076] exist Figure 7 In the example, signal S1 and signal S2 are Figure 6 The signal S1 and signal S2 in the same. The sampling event is timed at the same time. Signal SG G+1...n Also similar to Figure 6 , where the capacitor pair CIN G+1...n remains unselected during the conversion period. Since these signals are identical, they are not Figure 7 They are shown in .

[0077] Figure 7 The timing diagram of the gain error can be realized for different gain settings by using the signal SG 1...G to use only a gain of 1. Figure 7In each sampling, the SG is enabled at the same time 1...G If all capacitors are matched, the charge stored by the sampling circuit on each phase will be equal to Q = C*(VI+-VI-), resulting in a gain of 1. This is consistent with Figure 6 In contrast to the timing diagram of , the stored charge is Q = G*C*(VI+-VI-). k =C*e k The mismatch is defined as the time at which the capacitor to CIN k The + / - upsampled charge will be

[0078] Q k =2*e k *C*(VI+-VI-).

[0079] The factor of 2 comes from the double sampling implemented in the S1 and S2 stages.

[0080] During a certain number of OSR / G samples, the signal SG is enabled. 1…G This imposes conditions on G and OSR, where OSR should be a multiple of G. Control circuit 402 can be configured to limit OSR so that OSR is a multiple of G. Furthermore, digital filter 206 can be configured to generate the desired decimation using OSR samples, where OSR is a multiple of G.

[0081] The delta-sigma analog loop circuit 403 can be configured to perform integration to average each sample. Therefore, the conversion output code is proportional to the sum of the charges sampled during the conversion period. If each CIN is selected during the OSR / G sampling period k , and when choosing a given CIN k If no other capacitors are selected, the average charge can be evaluated. Figure 7 SG 1...G This is done with the timing signal of the input capacitor. This average charge can be expressed as Q = Σ{(total charge during each sampling period) / OSR}. If the total charge sampled on the input capacitor (Q ktot =2*C*e k *(VI+-VI-)) is replaced by OSR / G sample, the result may be

[0082] Q=2*C*(VI+-VI-)*Σ{(e k ) / G}

[0083] Given this resulting charge, use Figure 7 The gain error from the timing diagram compared to the ideal gain of 1 will be equal to

[0084] GERR=Σ{(ek ) / G-1},

[0085] It is equivalent to passing Figure 6 The timing diagram is applied to the sampling circuit 401 and the gain error is calculated, but Figure 7 The timing diagram uses a gain of 1 instead of Figure 6 The gain G used in the timing diagram.

[0086] therefore, Figure 7 The timing diagram can be used with a signal at the differential input that is as large as VREF. This can be performed without significant inaccuracies due to saturation of ADC 203, as the voltage is too large for the defined input voltage range. When the effective gain is 1, the converter range is [-VREF, +VREF]. Therefore, when +VREF is applied to the VIN input of ADC 203, and when a signal is applied to sampling circuit 401 by control circuit 402, the range of the converter is [-VREF, +VREF]. Figure 7 The timing diagram of the control signal is shown in Figure 2. The gain error is related to the applied Figure 6 The control signals in the timing diagram are basically the same. Figure 7 The converter code output obtained by the timing diagram is equivalent to the converter code output when the ADC gain is G and its input is +FS (which can be defined as +VREF / G). Figure 7 The timing diagram of Figure 1 performs gain error calibration for gain G without applying different input voltages, as long as the conversion includes OSR sampling and OSR is a multiple of G.

[0087] Since VREF can be applied at the input of ADC 203 for any given gain G (as long as G is a submultiple of OSR), and since Figure 7 The timing diagram of FIG1 results in a gain error for ADC 203 while achieving an effective gain of 1, so gain calibration can be performed for the gains G1 ... Gm in any given order without increasing the settling time at the input of ADC 203. As a result, the calibration process for all selected gains G1 ... Gm can be faster. Control logic 207 can be configured to iterate through all available selectable gain settings G1 ... Gm for ADC 203 to evaluate the gain error for each such gain setting.

[0088] exist Figure 7 In the timing diagram, SG can be enabled in any order 1...G signal. This may be caused by averaging the stored charge by the sampling circuit 401. Any such order may be used as long as for each given sample, SG 1...G Only one of the signals enables the switching of the corresponding capacitor, while all the signals disable the switching of the other capacitors. 1...GAny such order can be used as long as each of the signals enables the switching of the corresponding capacitor for the same number of samples (equal to OSR / G). The sampling order does not change the effective gain of the conversion, which remains equal to 1.

[0089] Embodiments of the present disclosure may not require any additional voltage source other than VREF to perform gain error calibration for different gain values. Embodiments of the present disclosure may not require VREF to be generated precisely. VREF is applied to both inputs of the delta-sigma analog loop circuit 403, so the solution for determining gain error can be said to be ratiometric. Moreover, embodiments of the present disclosure may not require a precision voltage source or device to measure gain error. Embodiments of the present disclosure can utilize any available DC voltage with sufficiently low noise as VREF. It may not be necessary to generate a precise VREF / G value as used in other solutions for testing gain error. Furthermore, since VREF is used as the VIN input during calibration, any noise or other non-ideal factors caused by the generation of VREF can be eliminated through ratiometric measurement. Furthermore, calibration can be performed without waiting for the input to settle between conversions.

[0090] Once the gain error for a given gain value is determined, ADC 203 may be configured to take any appropriate corrective action. For example, ADC 203 may be configured to selectively apply a compensation signal to future measurements taken at the given gain value during normal operation.

[0091] Figure 8 An example method 800 for determining the ratiometric gain error of an ADC having a capacitive gain input stage according to an embodiment of the present disclosure is shown. The method 800 may include comparing Figure 8 Furthermore, the steps of method 800 may be omitted, repeated, performed in parallel, performed in a different order, or performed recursively. Figures 2 to 5 Component usage Figure 7 Specifically, the method 800 may be executed directly or indirectly by the control logic component 207 .

[0092] At step 805 , it may be determined whether the ADC is to be operated in a normal phase or a calibration phase. If the ADC is to be operated in a normal phase, the method 800 may proceed to step 810 . Otherwise, the method 800 may proceed to step 815 .

[0093] At step 810, the gain to be used in the ADC can be determined. The gain can be applied to the input voltage to be converted to a digital value. After the gain is applied, the input voltage can be converted within the range defined by the ADC's reference voltage range. The ADC can output a digital code based on the input voltage. Method 800 can then proceed to step 850.

[0094] Different possible gain settings for the ADC may be determined at step 815. Additionally, a reference voltage for the ADC may be applied to the ADC voltage input.

[0095] An untested ADC gain setting may be selected for testing at step 820. A set of capacitor pairs to be used for the selected ADC gain setting may be determined.

[0096] At step 825, a subset of capacitor pairs, such as a single capacitor pair, may be enabled. The capacitor pair may be enabled long enough to capture a large number of samples, defined by the sampling period divided by the gain. While the capacitor pair is enabled, the other capacitors may be disabled. At the end of the sampling period, the results may be integrated.

[0097] At step 830, it may be determined whether there are additional unsampled capacitor pairs from the set of capacitor pairs determined in step 820. If so, method 800 may repeat, for example, at step 825. Otherwise, method 800 may proceed to step 835.

[0098] At step 835, a gain error may be determined based on the integration result of the selected gain setting.At step 840, a gain error correction value for the gain may be set for future operation in the normal phase.

[0099] At step 845 , it may be determined whether there are additional gain settings that have not been tested. If so, method 800 may repeat, for example, at step 820 . Otherwise, method 800 may proceed to step 850 .

[0100] At step 850, it may be determined whether method 800 should be repeated. Method 800 may be repeated based on any suitable criteria, such as whether the larger device or system in which the ADC is implemented has commanded the ADC to continue operating or stop. If method 800 is to be repeated, then method 800 may be repeated, for example, at step 805. Otherwise, method 800 may proceed to step 855.

[0101] The present disclosure has been described in terms of one or more embodiments, and it should be understood that many equivalents, alternatives, variations, and modifications are possible and within the scope of the present disclosure, in addition to those explicitly stated. Although the present disclosure is susceptible to various modifications and alternative forms, specific exemplary embodiments thereof have been shown in the drawings and described in detail herein. However, it should be understood that the description herein of specific exemplary embodiments is not intended to limit the present disclosure to the particular forms disclosed herein.

Claims

1. An analog-to-digital converter (ADC) circuit, comprising: ADC voltage input terminal; ADC reference input terminal; A sampling circuit, the sampling circuit comprising: Sampling voltage input terminal; sampling voltage output terminal; and a plurality of capacitors connected in parallel and configured to be selectively enabled or disabled, the plurality of capacitors being arranged between the sampling voltage input terminal and the sampling voltage output terminal; a multiplexer connected between the ADC voltage input terminal and the sampling voltage input terminal and between the ADC reference input terminal and the sampling voltage input terminal; and A control logic component configured to, during a calibration operation phase: causing the multiplexer to route the ADC reference input terminal to the sample voltage input terminal; determining a given gain value of the ADC circuit for which gain error is to be calibrated; determining, based on the given gain value, a set of the plurality of capacitors in the sampling circuit to be used to achieve the given gain value, the set of the plurality of capacitors comprising a plurality of capacitor subsets; successively enabling a subset of the capacitors in the set of the plurality of capacitors to sample a voltage of the ADC reference input terminal at the sample voltage input terminal while disabling remaining capacitors in the set of the plurality of capacitors until all capacitors in the set of the plurality of capacitors have been enabled; determining an output code produced after enabling all capacitors in the set of the plurality of capacitors; and A gain error for the given gain value of the ADC circuit is determined from the output code; wherein the control logic component is further configured to take corrective action based on the gain error for the given gain value of the ADC circuit. 2 . The analog-to-digital converter (ADC) circuit of claim 1 , wherein enabling each subset of the set of the plurality of capacitors is configured to set the ADC circuit to perform at a gain of 1. 3 . 3 . The analog-to-digital converter (ADC) circuit according to claim 1 , wherein each subset of the set of the plurality of capacitors is enabled for the same number of samples.

4. The analog-to-digital converter (ADC) circuit according to any one of claims 1 to 2, wherein the control logic component is further configured to, during the calibration operation phase: determining another gain value of the ADC circuit for which gain error is to be calibrated; determining another set of the plurality of capacitors in the sampling circuit to be used to achieve another gain value; successively enabling a subset of capacitors in the another set of the plurality of capacitors to sample a voltage of the ADC reference input terminal at the sample voltage input terminal while disabling remaining capacitors in the another set of the plurality of capacitors until all capacitors in the another set of the plurality of capacitors have been enabled; determining another output code produced after enabling all capacitors in the another set of the plurality of capacitors; as well as A gain error for the other gain value of the ADC circuit is determined from the other output code.

5. The analog-to-digital converter (ADC) circuit according to any one of claims 1 to 2, wherein the control logic component is further configured to: sampling the voltage of the ADC reference input terminal at the sampling voltage input terminal to obtain a given number of samples; and Each subset of the set of the plurality of capacitors is sampled to obtain the subset of the given number of samples, the subset of the given number of samples being equal to the given number of samples divided by the given gain value. 6 . The analog-to-digital converter (ADC) circuit according to claim 5 , wherein a result obtained by dividing the given number of samples by the given gain value has no remainder.

7. A system for calibrating gain error of an analog-to-digital converter (ADC) circuit, the system comprising: An ADC circuit, wherein the ADC circuit is any one of the ADC circuits according to claims 1 to 6; an input voltage connected to the ADC voltage input terminal of the ADC circuit, the ADC circuit being configured to convert the input voltage into the output code; as well as A reference voltage source is connected to the ADC reference input terminal of the ADC circuit, the ADC circuit being configured to convert the input voltage according to a range defined by the reference voltage source.

8. A method for gain error calibration of an analog-to-digital converter (ADC) circuit, the method comprising the operation of a system or an ADC circuit configured according to any one of claims 1 to 7.

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