Solid-state imaging element, imaging device, and control method of solid-state imaging element

Abstract

The object of the present invention is to improve the processing speed in a solid-state imaging element that performs signal processing on a part of image data. According to the present invention, a repeater is connected to a cluster and transmits a digital signal representing a time within a predetermined period, in which a predetermined number of pixels are arranged. A comparator compares an analog signal corresponding to an exposure amount with a reference signal that changes within a predetermined period, and outputs a comparison result. A latch circuit acquires a digital signal from the repeater and stores the digital signal. A latch control circuit controls the latch circuit so that the latch circuit stores the digital signal when the comparison result is inverted, and controls the latch circuit so that the latch circuit outputs the digital signal to the repeater at a moment indicated by an output timing signal. When the output of the digital signal is set to be valid according to a predetermined output enable signal, the enable control unit provides the output timing signal to the latch control circuit.

Description

Technical Field

[0001] The present technology relates to a solid-state imaging element, and more specifically, to a solid-state imaging element, an imaging device, and a control method of the solid-state imaging element that expose all pixels at the same time. Background Art

[0002] In order to capture an image of a fast-moving subject, for example, a global shutter method of simultaneously exposing all pixels is conventionally used in a solid-state imaging element, taking into account the advantage of not causing rolling shutter distortion. For example, a solid-state imaging element is proposed in which a pixel circuit and an analog-to-digital converter (ADC) are arranged for each pixel, and a driving circuit simultaneously exposes all pixels and outputs digital signals (for example, see Patent Document 1). In order to perform signal processing on only a portion of the image data in a solid-state imaging element, a repeater transmits a digital signal from a pixel to be processed to a signal processing unit in units of rows, and the signal processing unit extracts the digital signal to be processed in units of columns and performs signal processing.

[0003] Citation list

[0004] Patent Literature

[0005] Patent Document 1: WO 2016 / 136448 A Summary of the invention

[0006] Problems to be solved by the present invention

[0007] In the above-mentioned prior art, ADC is arranged for each pixel, so the speed of analog-to-digital (AD) conversion can be increased compared with the case where ADC is arranged for each column. However, in the above solid-state imaging element, since the repeater transmits the digital signal to be processed to the signal processing unit in units of rows, the amount of data transmitted to the signal processing unit increases as the number of pixels in the row (i.e., the number of columns) increases. Therefore, the following problem is caused: the throughput of the signal processing unit increases as the number of columns increases, thereby reducing the processing speed.

[0008] The present technology has been made in view of such circumstances, and an object of the present technology is to increase the processing speed in a solid-state imaging element for performing signal processing on a part of image data.

[0009] Technical solutions to the problem

[0010] The present technology is made to solve the above problems, and the first aspect of the present technology is a solid-state imaging element and a control method thereof, wherein the solid-state imaging element includes: a repeater connected to a cluster and transmitting a digital signal indicating a time within a predetermined period, in which a predetermined number of pixels are arranged; a vertical drive circuit, which provides an output timing signal indicating an output moment of each of the predetermined number of pixels and an output enable signal indicating whether the output of the digital signal is valid for each pixel; a comparator, which compares an analog signal corresponding to an exposure amount with a reference signal that changes within a predetermined period and outputs a comparison result; a latch circuit, which acquires a digital signal from the repeater and stores the digital signal; a latch control circuit, which controls the latch circuit when the comparison result is inverted so that the latch circuit stores the digital signal, and, at a moment indicated by the output timing signal, controls the latch circuit so that the latch circuit outputs the digital signal to the repeater; and an enable control unit, which provides the output timing signal to the latch control circuit when the output of the digital signal is set to be valid according to the output enable signal. Therefore, the output of the digital signal can be set to be effective in units of pixels.

[0011] In addition, in the first aspect, the repeater and a predetermined number of pixels can be arranged in each of a plurality of clusters, and the comparator, latch circuit, latch control circuit and enable control unit can be arranged in each of the predetermined number of pixels. Therefore, the pixels in the cluster can be driven sequentially.

[0012] In addition, in the first aspect, a signal processing unit may be further included, the signal processing unit performing predetermined signal processing on the digital signal transmitted by the repeater. Therefore, the signal processing can be performed on the digital signal output in units of pixels.

[0013] In addition, in the first aspect, the signal processing unit may include a first signal processing unit and a second signal processing unit, the first signal processing unit may perform signal processing on digital signals output from a portion of the plurality of clusters, and the second signal processing unit may perform signal processing on digital signals output from the remaining portion of the plurality of clusters. Therefore, the first signal processing unit and the second signal processing unit are capable of processing digital signals in parallel.

[0014] In addition, in the first aspect, the signal processing unit may include: a signal processing circuit that performs predetermined signal processing on the output digital signal and generates image data; and an area of ​​interest setting unit that sets an area in the image data where the digital signal is to be output as the area of ​​interest. Therefore, it is possible to perform signal processing on the area of ​​interest.

[0015] In addition, in the first aspect, the signal processing unit may further include: a motion vector detection unit that detects a motion vector indicating a motion direction of the subject for each subject in the image data; and an area of ​​interest prediction unit that predicts the position of the area of ​​interest in the image data to be generated next based on the motion vector. Therefore, the position of the area of ​​interest can be predicted based on the motion.

[0016] In addition, a second aspect of the present technology is an image pickup device including: a repeater connected to a cluster in which a predetermined number of pixels are arranged and transmitting a digital signal indicating a time within a predetermined period; a vertical drive circuit providing an output timing signal indicating an output moment of each of the predetermined number of pixels and an output enable signal indicating whether the output of the digital signal is valid for each pixel; a comparator comparing an analog signal corresponding to an exposure amount with a reference signal that varies within a predetermined period and outputting a comparison result; a latch circuit acquiring a digital signal from the repeater and storing the digital signal; a latch control circuit controlling the latch circuit when the comparison result is inverted so that the latch circuit stores the digital signal, and controlling the latch circuit at a moment indicated by the output timing signal so that the latch circuit outputs the digital signal to the repeater; an enable control unit providing the output timing signal to the latch control circuit when the output of the digital signal is set to be valid according to the output enable signal; and a storage unit storing image data in which the digital signal is arranged. Therefore, digital signals output in units of pixels can be stored. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 : is a block diagram showing a configuration example of an image pickup device in the first embodiment of the present technology.

[0018] Figure 2 An example of a stacked structure of the solid-state imaging element in the first embodiment of the present technology is shown.

[0019] Figure 3 : is a block diagram showing a configuration example of a solid-state image pickup element in the first embodiment of the present technology.

[0020] Figure 4 : is a plan view showing a configuration example of a pixel array unit in the first embodiment of the present technology.

[0021] Figure 5 is a block diagram showing a configuration example of a pixel in the first embodiment of the present technology.

[0022] Figure 6: is a circuit diagram showing a configuration example of a pixel circuit, a differential input circuit, a positive feedback circuit, and an inverter circuit in the first embodiment of the present technology.

[0023] Figure 7 : is a block diagram showing a configuration example of a latch unit in the first embodiment of the present technology.

[0024] Figure 8 : is a circuit diagram showing a configuration example of a latch control circuit and a latch circuit in the first embodiment of the present technology.

[0025] Fig. 9 An outline of the operation of the latch circuit in the first embodiment of the present technology is shown.

[0026] Fig.10 A configuration example of the repeater unit and the cluster in the first embodiment of the present technology is shown.

[0027] Fig.11 is a circuit diagram showing a configuration example of a repeater in the first embodiment of the present technology.

[0028] Fig.12 is a block diagram showing a configuration example of a signal processing unit in the first embodiment of the present technology.

[0029] Fig.13 : is a timing chart showing an operation example for switching the P phase in the first embodiment of the present technology.

[0030] Fig.14 : is a timing chart showing an operation example for switching the D phase in the first embodiment of the present technology.

[0031] Fig.15 : is a timing chart showing an operation example in which the 0th cluster in the 001th column outputs a digital signal in the first embodiment of the present technology.

[0032] Fig.16 : is a timing chart showing an operation example in which the 1st cluster in the 001th column outputs a digital signal in the first embodiment of the present technology.

[0033] Fig.17 is an explanatory diagram showing analog-to-digital conversion in the first embodiment of the present technology.

[0034] Fig.18 : is an explanatory diagram showing the operation of a pixel in which an output enable signal is set to be valid in the first embodiment of the present technology.

[0035] Fig.19 : is an explanatory diagram showing the operation of a pixel in which an output enable signal is set to be disabled in the first embodiment of the present technology.

[0036] Fig. 20 Examples of image data before and after setting a region of interest (ROI) in the first embodiment of the present technology are shown.

[0037] Fig.21 An example of ROI in the first embodiment of the present technology is shown.

[0038] Fig. 22 The image data in which the ROI is set and the image data transmitted to the signal processing unit in the comparative example are shown.

[0039] Fig.23 An example of ROI in the comparative example is shown.

[0040] Fig.24 is a flowchart showing an operation example of the solid-state imaging element in the first embodiment of the present technology.

[0041] Fig.25 : is a block diagram showing a configuration example of a solid-state image pickup element in a second embodiment of the present technology.

[0042] Fig.26 : is a plan view showing a configuration example of a pixel array unit in a second embodiment of the present technology.

[0043] Fig. 27 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0044] Fig.28 1 is an explanatory diagram showing an example of the installation positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0045] Hereinafter, a mode for implementing the present technology (hereinafter referred to as an "embodiment") will be described. The description will be made in the following order.

[0046] 1. First Embodiment (Example of Setting Output of Digital Signals to Be Valid in Pixel Units)

[0047] 2. Second Embodiment (Example in which output of digital signals is set to be effective in units of pixels and a plurality of signal processing units are provided)

[0048] 3. Application examples for mobile objects

[0049] <1. First Embodiment>

[0050] [Configuration Example of Image Pickup Device]

[0051] Figure 11 is a block diagram showing a configuration example of an image pickup device 100 in the first embodiment of the present technology. The image pickup device 100 is a device for acquiring image data, and includes an optical unit 110, a solid-state image pickup element 200, and a digital signal processing (DSP) circuit 120. The image pickup device 100 also includes a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a storage unit 170, and a power supply unit 180. For example, the image pickup device 100 is not only a digital camera such as a digital camera, but also a smartphone, a personal computer, or a car camera, etc. having an image pickup function.

[0052] The optical unit 110 collects light from the subject and guides the light to the solid-state imaging element 200. The solid-state imaging element 200 generates image data by photoelectric conversion in synchronization with the vertical synchronization signal VSYNC. Here, the vertical synchronization signal VSYNC is a periodic signal with a predetermined frequency indicating the timing of capturing an image. The solid-state imaging element 200 provides the generated image data to the DSP circuit 120 via the signal line 209.

[0053] The DSP circuit 120 performs predetermined signal processing on the image data supplied from the solid-state imaging element 200. The DSP circuit 120 outputs the processed image data to the frame memory 160 or the like via the bus 150.

[0054] The display unit 130 displays image data. The display unit 130 is, for example, a liquid crystal panel or an organic electroluminescent (EL) panel. The operation unit 140 generates an operation signal in response to a user operation.

[0055] The bus 150 is a common path through which the optical unit 110 , the solid-state imaging element 200 , the DSP circuit 120 , the display unit 130 , the operation unit 140 , the frame memory 160 , the storage unit 170 , and the power supply unit 180 exchange data with each other.

[0056] The frame memory 160 stores image data. The storage unit 170 stores various data such as image data. The power supply unit 180 supplies power to the solid-state imaging element 200, the DSP circuit 120, the display unit 130, and the like.

[0057] [Configuration Example of Solid-State Image Pickup Element]

[0058] Figure 2 An example of a stacked structure of a solid-state imaging element 200 in the first embodiment of the present technology is shown. The solid-state imaging element 200 includes a circuit chip 202 and a light receiving chip 201 stacked on the circuit chip 202. These chips are electrically connected via a connection portion such as a through hole. Note that these chips can be connected not only by a through hole, but also by Cu-Cu bonding or bump connection.

[0059] Figure 3 1 is a block diagram showing a configuration example of a solid-state imaging element 200 in the first embodiment of the present technology. The solid-state imaging element 200 includes a digital-to-analog converter (DAC) 211, a time code generating unit 212, a vertical drive circuit 213, a pixel array unit 214, a pixel driving circuit 215, a timing generating circuit 216, and a signal processing unit 250.

[0060] The DAC 211 generates an analog reference signal that changes within a predetermined AD conversion period through digital-to-analog (DA) conversion. For example, a sawtooth ramp signal is used as the reference signal. The DAC 211 provides the reference signal to the pixel array unit 214.

[0061] Each time code generating unit 212 generates a digital signal representing the time within the AD conversion period as a time code. The time code generating unit 212 is implemented by a counter, for example. The counter is, for example, a Gray code counter. The time code generating unit 212 provides the time code to the pixel array unit 214.

[0062] In the pixel array unit 214, a plurality of pixels are arranged in a two-dimensional grid. Each pixel generates an analog signal corresponding to the exposure amount and converts the analog signal into a digital signal. Then, the pixel provides the digital signal as pixel data to the signal processing unit 250.

[0063] The vertical driving circuit 213 drives the pixels so that the pixels perform AD conversion, and the pixel driving circuit 215 drives the pixels so that the pixels generate analog signals.

[0064] The timing generation circuit 216 controls the operation timing of the vertical driving circuit 213 , the pixel driving circuit 215 , and the signal processing unit 250 in synchronization with the vertical synchronization signal VSYNC.

[0065] The signal processing unit 250 performs predetermined signal processing on the pixel data provided from the pixel array unit 214. As the signal processing, for example, correlated double sampling (CDS) processing and image recognition processing are performed. The signal processing unit 250 provides the processed data to the DSP circuit 120. In addition, the signal processing unit 250 sets the ROI in response to the user operation, and provides the setting information about the ROI to the vertical driving circuit 213.

[0066] [Configuration Example of Pixel Array Unit]

[0067] Figure 4 1 is a plan view showing a configuration example of the pixel array unit 214 in the first embodiment of the present technology. In the pixel array unit 214, a plurality of pixels 300 and a plurality of repeater units 220 are arranged.

[0068] Furthermore, the pixel array unit 214 is divided into a plurality of clusters 217, each of which includes a predetermined number (eg, 128) of pixels. Furthermore, a repeater unit 220 is provided for each column of the cluster 217. A time code generation unit 212 is also provided for each column of the cluster 217.

[0069] The repeater unit 220 transmits the time code. The repeater unit 220 transmits the time code from the corresponding time code generation unit 212 to the pixels 300 in the corresponding cluster 217. In addition, the repeater unit 220 transmits the pixel data from the pixels in the corresponding cluster 217 to the signal processing unit 250.

[0070] [Pixel Structure Example]

[0071] Figure 5 300 is a block diagram showing a configuration example of a pixel 300 in the first embodiment of the present technology. The pixel 300 includes a pixel circuit 310 and an ADC 305 .

[0072] The pixel circuit 310 generates an analog signal corresponding to the exposure amount as a pixel signal SIG under the control of the pixel driving circuit 215. The pixel circuit 310 supplies the generated pixel signal SIG to the ADC 305.

[0073] The ADC 305 performs AD conversion on the analog pixel signal SIG. The ADC 305 includes a comparator 320 and a latch unit 400.

[0074] The comparator 320 compares the pixel signal SIG provided from the pixel circuit 310 with the reference signal REF provided from the DAC 211. The comparator 320 provides the comparison result VCO to the latch unit 400. In addition, the comparator 320 includes a differential input circuit 330, a positive feedback circuit 340, and an inversion circuit 350.

[0075] The differential input circuit 330 amplifies the difference between the pixel signal SIG and the reference signal REF. The positive feedback circuit 340 adds a part of the output to the input. The inversion circuit 350 inverts the output of the positive feedback circuit 340.

[0076] The latch unit 400 acquires the time code when the comparison result VCO is inverted from the repeater unit 220 and stores the time code. In addition, the latch unit 400 outputs the stored time code as pixel data to the repeater unit 220 under the control of the vertical drive circuit 213.

[0077] [Configuration Example of Pixel Circuit and Comparator]

[0078] Figure 6is a circuit diagram showing a configuration example of the pixel circuit 310 , the differential input circuit 330 , the positive feedback circuit 340 , and the inverter circuit 350 in the first embodiment of the present technology.

[0079] The pixel circuit 310 includes a reset transistor 311, a floating diffusion layer 312, an FDG transistor 313, a floating diffusion layer 314, a transfer transistor 315, a photoelectric conversion element 316, and a charge discharge transistor 317. The reset transistor 311, the FDG transistor 313, the transfer transistor 315, and the charge discharge transistor 317 are, for example, n-channel metal oxide semiconductor (nMOS) transistors.

[0080] The differential input circuit 330 includes p-channel MOS (pMOS) transistors 331 and 334 , differential transistors 332 and 335 , and a current source transistor 333 .

[0081] Furthermore, the positive feedback circuit 340 includes nMOS transistors 341, 342, 343, and 345, and a pMOS transistor 344. The inverter circuit 350 includes pMOS transistors 351 and 352, and nMOS transistors 353 and 354.

[0082] The reset transistor 311 in the pixel circuit 310 initializes the floating diffusion layers 312 and 314 in response to a reset signal RST supplied from the pixel driving circuit 215 .

[0083] The floating diffusion layers 312 and 314 store charges and generate a voltage corresponding to the amount of the charges.

[0084] The FDG transistor 313 opens and closes a path between the floating diffusion layers 312 and 314 in response to a control signal FDG supplied from the pixel driving circuit 215 , thereby controlling charge-voltage conversion efficiency.

[0085] The transfer transistor 315 transfers charges from the photoelectric conversion element 316 to the floating diffusion layer 314 in response to a transfer signal TX supplied from the pixel driving circuit 215. The photoelectric conversion element 316 generates charges by photoelectric conversion. The photoelectric conversion element 316 is, for example, a photodiode.

[0086] The charge discharge transistor 317 discharges the charge from the photoelectric conversion element 316 in response to the control signal OFG supplied from the pixel driving circuit 215 , thereby initializing the charge amount thereof.

[0087] The pMOS transistors 331 and 334 in the differential input circuit 330 are connected in parallel to the power supply voltage VDDH. The gate of the pMOS transistor 331 is connected to its own drain and the gate of the pMOS transistor 334. In addition, the drain of the pMOS transistor 334 is connected to the gate of the nMOS transistor 341 in the positive feedback circuit 340.

[0088] A differential transistor 332 is inserted between the pMOS transistor 331 and the current source transistor 333. In addition, a reference signal REF is input to the gate of the differential transistor 332. A differential transistor 335 is inserted between the pMOS transistor 334 and the current source transistor 333. In addition, a pixel signal SIG is input to the gate of the differential transistor 335. The current source transistor 333 is inserted between the differential transistors 332 and 335 and the ground terminal. A constant bias voltage Vb is applied to the gate of the current source transistor 333.

[0089] In addition, the pixel circuit 310, the differential transistors 332 and 335, and the current source transistor 333 are arranged on the light receiving chip 201. Similarly, the DAC 211 and the pixel driving circuit 215 are also arranged on the light receiving chip 201. Meanwhile, the pMOS transistors 331 and 334, the positive feedback circuit 340, and the inverter circuit 350 are arranged on the circuit chip 202. The time code generation unit 212, the vertical driving circuit 213, the latch unit 400, the repeater unit 220, and the signal processing unit 250 are also arranged on the circuit chip 202.

[0090] Note that the circuits arranged on the light receiving chip 201 and the circuit chip 202 are not limited to Figure 6 These are shown.

[0091] The nMOS transistors 341, 342 and 345 in the positive feedback circuit 340 are connected in series between the power supply terminal and the ground terminal. In addition, the gate of the nMOS transistor 342 is connected to a power supply voltage VDDL lower than the power supply voltage VDDH.

[0092] The nMOS transistor 343 and the pMOS transistor 344 are connected in series between the gate of the nMOS transistor 342 and the connection node between the nMOS transistors 342 and 345. In addition, the potential of the connection node is supplied to the inverter circuit 350 as an inversion signal xVCO.

[0093] Furthermore, the driving signal INI1 supplied from the vertical driving circuit 213 is input to the gate of the nMOS transistor 345. The driving signal INI2 supplied from the vertical driving circuit 213 is input to the gate of the nMOS transistor 343.

[0094] The pMOS transistors 351 and 352 in the inverter circuit 350 are connected in series to the power supply voltage VDDL. The nMOS transistors 353 and 354 are connected in parallel between the pMOS transistor 352 and the ground terminal.

[0095] Furthermore, the driving signal TESTVCO supplied from the vertical driving circuit 213 is input to the gates of the pMOS transistor 352 and the nMOS transistor 354. The gate of the pMOS transistor 344 is connected to a connection node between the pMOS transistor 352 and the nMOS transistor 354, and the potential of the connection node is supplied to the latch unit 400 as a comparison result VCO.

[0096] Note that the pixel circuit 310, the differential input circuit 330, the positive feedback circuit 340, and the inverter circuit 350 are not limited to Figure 6 The circuit configurations shown are sufficient as long as these circuits can achieve the reference Figure 5 The functions described are sufficient.

[0097] [Configuration Example of Latch Unit]

[0098] Figure 7 4 is a block diagram showing a configuration example of the latch unit 400 in the first embodiment of the present technology. The latch unit 400 includes a NAND (Not-AND) gate 410 , a latch control circuit 420 , and a plurality of latch circuits 430 .

[0099] NAND gate 410 outputs an enable signal EN_OUT_i <j>and output timing signal xWORD <m>The NAND is output to the latch control circuit 420. Output timing signal xWORD <m>It is through inverting the output timing signal WORD <m>The obtained signal, the output timing signal WORD <m>Indicates the output timing of the mth (m is an integer) pixel among the pixels in the cluster 217. In the case where the number of pixels in the cluster 217 is "128", "0" to "127" are set to m. Output timing signal xWORD <0> to xWORD <127> is provided to all clusters.

[0100] In addition, the output enable signal EN_OUT_i <j>The vertical drive circuit 213 outputs an output enable signal EN_OUT_i with a value of "1" when the output is set to be valid. <j>, and the output enable signal EN_OUT_i with a value of "0" is set to disable <j>.

[0101] The character i is a three-digit integer representing a column of the cluster 217. When the number of columns of the cluster 217 is, for example, "512", a value of "000" to "511" is set to i. In addition, the character j is an integer representing a pixel in a corresponding column. For example, when 3584 pixels are included in a column of the cluster 217, a value of "0" to "3583" is set to j. For example, the output enable signal EN_OUT_000 <0> Input is the 0th pixel in the 000th column.

[0102] When the number of columns of the cluster 217 is "512" and the number of pixels in each column is "3584", the total number of pixels is 512×3584. The output enable signal EN_OUT_i is set for each of these pixels. <j>In the initial state, the output enable signal EN_OUT_i of all pixels <j>is set to be valid.

[0103] The latch control circuit 420 controls each latch circuit 430 so that the latch circuit 430 holds the time code when the comparison result VCO provided from the comparator 320 is inverted. In addition, the latch control circuit 420 controls the latch circuit 430 in response to the signal provided from the NAND gate 410, and causes the latch circuit 430 to output the held time code as pixel data.

[0104] The latch circuit 430 holds the time code supplied from the repeater 230 according to the latch control circuit 420, and outputs the time code as pixel data to the repeater 230. The latch circuit 430 is provided corresponding to the bit length of the time code.

[0105] Figure 8 : is a circuit diagram showing a configuration example of the latch control circuit 420 and the latch circuit 430 in the first embodiment of the present technology.

[0106] The latch control circuit 420 includes a NOR (Not-OR) gate 421 and inverters 422 and 423. Each latch circuit 430 includes a switch 431 and inverters 432 and 433.

[0107] The NOR gate 421 outputs the NOR of the signal supplied from the NAND gate 410 and the comparison result VCO supplied from the comparator 320. The NOR is supplied to the inverter 422 and the switch 431 as the control signal xT. The inverter 422 inverts the control signal xT and supplies the inverted control signal as the control signal T to the switch 431. The inverter 423 inverts the comparison result VCO and supplies the inverted comparison result VCO as the control signal L to the inverter 432. In addition, the comparison result VCO is supplied to the inverter 432 as the control signal xL.

[0108] In each latch circuit 430, the inverter 432 outputs the inverted value of the output of the inverter 433 to the switch 431 and the input terminal of the inverter 433 according to the control signals L and xL. The inverter 432 outputs the inverted value when the control signal L is at a high level and the control signal xL is at a low level, and does not output the inverted value in other cases. The inverter 433 outputs the inverted value of the output of the inverter 432 to the input terminal of the inverter 432.

[0109] The switch 431 opens and closes the path between the repeater unit 220 and the output terminal of the inverter 432 according to the control signals T and xT. The inverter 432 turns to a closed state when the control signal T is at a high level and the control signal xT is at a low level, and turns to an open state in other cases.

[0110] use Figure 7 and Figure 8 In the structure shown in FIG. 1 , the latch control circuit 420 controls the latch circuit 430 so that the latch circuit 430 stores the digital time code when the comparison result VCO is inverted. Therefore, the analog pixel signal SIG is AD-converted into the digital time code. In addition, in the corresponding output timing signal WORD <m>and output enable signal EN_OUT_i <j>When the latch control circuit 420 is "1", the latch circuit 430 is controlled so that the latch circuit 430 outputs the stored time code as pixel data. Note that the circuit configuration of the latch unit 400 is not limited to Figure 7 and Figure 8 As long as the latch unit 400 can realize the reference Figure 7 and Figure 8 The functions described are sufficient.

[0111] Fig. 9 The operation outline of the latch circuit 430 in the first embodiment of the present technology is shown. <m>is "1" and the output enable signal EN_OUT_i <j>When the corresponding latch circuit 430 is "1" (valid), the corresponding latch circuit 430 outputs the stored time code as pixel data. <m>"0" or output enable signal EN_OUT_i <j>When "0" (disabled), no pixel data is output.

[0112] [Configuration Example of Repeater Unit]

[0113] Fig.10 The configuration example of the repeater unit 220 and the cluster 217 in the first embodiment of the present technology is shown. In each repeater unit 220, a plurality of repeaters 230 are arranged vertically. The cluster 217 and the repeater 230 are connected one to one. For example, when 28 clusters 217 are arranged vertically in each column, 28 repeaters 230 are arranged.

[0114] Each repeater 230 transmits time data. The repeater 230 is, for example, a shift register. Each repeater 230 is connected to all latch units 400 in the corresponding cluster 217 via a local bit line.

[0115] The repeater 230 transmits the time code to the corresponding latch unit 400. In addition, the repeater 230 transmits the pixel data from the corresponding latch unit 400 to the signal processing unit 250.

[0116] Fig.11 2 is a circuit diagram showing a configuration example of a repeater 230 in the first embodiment of the present technology. The repeater 230 includes a plurality of transmission circuits 240 and inverters 231 to 234. The transmission circuits 240 are provided corresponding to the bit length of the time code. Each transmission circuit 240 includes inverters 241 and 242 and a flip-flop 243.

[0117] The inverter 231 inverts a main clock signal MCK having a predetermined frequency and supplies the inverted main clock signal to the inverters 232 and 234. The inverter 232 inverts the signal supplied from the inverter 231 and supplies the inverted signal to the subsequent-stage repeater 230.

[0118] The inverter 234 inverts the signal supplied from the inverter 231, and supplies the inverted signal to the inverter 233. The inverter 233 inverts the signal supplied from the inverter 234, and supplies the inverted signal to each flip-flop 243.

[0119] The flip-flop 243 holds the corresponding bit of the time code in synchronization with the signal supplied from the inverter 233. The corresponding bit of the time code supplied from the time code generating unit 212 is input to the input terminal of the flip-flop 243 through the main bit line MBL. In addition, the flip-flop 243 supplies the held bit to the inverter 241 and the subsequent repeater 230.

[0120] The inverter 241 inverts the bits provided from the flip-flop 243 according to the control signal WEN, and provides the inverted bits to the corresponding latch units 400 through the local bit lines LBL, respectively.

[0121] The inverter 242 inverts a bit provided from the corresponding latch unit 400 according to the control signal REN, and provides the inverted bit to the repeater 230 at a subsequent stage.

[0122] [Configuration Example of Signal Processing Unit]

[0123] Fig.12 1 is a block diagram showing a configuration example of the signal processing unit 250 in the first embodiment of the present technology. The signal processing unit 250 includes a CDS processing unit 251, a frame memory 252, a motion vector detection unit 253, a ROI setting unit 254, a next frame ROI prediction unit 255, and a post-processing unit 256.

[0124] The CDS processing unit 251 performs CDS processing on each pixel data supplied from the pixel array unit 214. The CDS processing unit 251 supplies the processed pixel data to the frame memory 252, the motion vector detection unit 253, and the post-processing unit 256. The image data (frame) in which a plurality of pieces of processed pixel data are arranged is supplied as a current frame to the motion vector detection unit 253. Note that the CDS processing unit 251 is an example of a signal processing circuit described in the claims.

[0125] The frame memory 252 stores image data (frame) in which a plurality of pieces of pixel data supplied from the CDS processing unit 251 are arranged as a past frame.

[0126] Based on the current frame and the past frame stored in the frame memory 252, the motion vector detection unit 253 detects a vector indicating the moving direction and distance of the subject as a motion vector for each subject in the frame. For example, the motion vector detection unit 253 divides the current frame into a plurality of blocks, and performs block matching to find the best matching block from the past frame for each block. Then, the motion vector detection unit 253 detects a vector from a block in the past frame to a corresponding block in the current frame as a motion vector. The motion vector detection unit 253 provides the detected motion vector to the next frame ROI prediction unit 255.

[0127] In response to the operation signal from the operation unit 140, the ROI setting unit 254 sets a partial area in the image data as a region of interest (ROI) to be subjected to predetermined signal processing (e.g., image recognition processing). Here, the shape of the ROI is not limited, and the ROI setting unit 254 is capable of setting a rectangular, circular, or elliptical ROI. The ROI setting unit 254 provides setting information for specifying the periphery of the ROI to the next frame ROI prediction unit 255. In the case where the ROI is a rectangle, the setting information shows, for example, the coordinates of each of a pair of diagonal corners of the rectangle. In addition, in the case where the ROI is a circle, the setting information shows, for example, the center coordinates and radius of the circle. Note that the ROI setting unit 254 is an example of a region of interest setting unit described in the claims.

[0128] The next frame ROI prediction unit 255 predicts the position of the ROI in the next frame of the current frame. The next frame ROI prediction unit 255 predicts the position of the ROI in the next frame based on the setting information related to the ROI in the current frame and the motion vector provided from the motion vector detection unit 253. For example, the next frame ROI prediction unit 255 saves the setting information related to the ROI in the current frame, moves the ROI by the amount of the motion vector, and obtains the position of the moved ROI as the position of the ROI in the next frame. The next frame ROI prediction unit 255 provides the setting information about the predicted ROI to the vertical driving circuit 213. In the first prediction, the ROI set by the ROI setting unit 254 is used as the ROI in the current frame. In the second and subsequent predictions, the ROI in the current frame is updated based on the ROI predicted the previous time.

[0129] The vertical driving circuit 213 performs setting so that the output enable signal EN_OUT is valid for each pixel in the set ROI, and the output enable signal EN_OUT is disabled for other pixels.

[0130] The post-processing unit 256 performs various signal processing such as demosaic processing and image recognition processing on the frame that has been subjected to CDS processing. For example, in the case where ROI is set, the post-processing unit 256 performs image recognition processing on the ROI. The post-processing unit 256 supplies the processed data to the DSP circuit 120.

[0131] Note that part of the processing or all of the processing by the signal processing unit 250 may be performed by a circuit (eg, the DSP circuit 120 ) outside the solid-state imaging element 200 instead of the signal processing unit 250 .

[0132] Furthermore, the signal processing unit 250 detects a motion vector and predicts an ROI in a next frame, but in the case of setting an ROI within a range where no motion occurs, the signal processing unit 250 may not include the motion vector detection unit 253 or the next frame ROI prediction unit 255 .

[0133] [Operation example of solid-state imaging element]

[0134] Fig.13 1 is a timing chart showing an example of an operation for switching the P phase in the first embodiment of the present technology. Here, the P phase represents the level of the pixel signal SIG obtained when the pixel circuit 310 is initialized.

[0135] At time t0, a 1V period starts. Here, the 1V period is a period until AD conversion of all pixels is completed. The length of the 1V period is set to, for example, a cycle of a vertical synchronization signal VSYNC.

[0136] At time t1 after time t0, the pixel driving circuit 215 provides a reset signal RST to all pixels to initialize the floating diffusion layer. As a result, the P phase is generated in all pixels. At time t2 after time t1, the vertical driving circuit 213 changes the driving signal TESTVCO from a high level to a low level. In addition, the comparator 320 starts to output a high level comparison result VCO.

[0137] At time t3 after time t2, the vertical drive circuit 213 sequentially provides drive signals INI2 and INI1 to initialize the positive feedback circuit 340. In the period from time t4 to time t7 after time t3, the vertical drive circuit 213 provides the control signal WEN, and the DAC 211 changes the reference signal REF in a ramp shape. At t5 within this period, if the P phase exceeds the level of the reference signal REF, the comparator 320 inverts the comparison result VCO. The repeater unit 220 transmits the time data to the pixel according to the control signal WEN, and the latch unit 400 saves the time data obtained when the comparison result VCO is inverted. Therefore, the P phase is AD converted in all pixels.

[0138] In addition, at time t8 after time t7, the vertical drive circuit 213 provides the output timing signal WORD to the 0th pixel in the cluster 217 within a specific period. At time t9 within the transmission period of the output timing signal WORD, the vertical drive circuit 213 provides the control signal REN. According to the control signal REN, the repeater unit 220 transmits the 0th pixel data (time data) of each cluster to the signal processing unit 250.

[0139] Subsequently, the output timing signal WORD is sequentially transmitted to the 1st to 127th pixels in each cluster 217, and the control signal REN is provided during the transmission period of the output timing signal WORD. Therefore, pixel data in which the P phase has been converted is transmitted from all pixels to the signal processing unit 250.

[0140] Fig.14 1 is a timing chart showing an example of an operation for switching the D phase in the first embodiment of the present technology. Here, the D phase represents the level of the pixel signal SIG corresponding to the exposure amount.

[0141] At time t21 after the P phase conversion, the comparator 320 starts to output the comparison result VCO of the high level, and then the pixel driving circuit 215 provides the transmission signal TX. When the transmission signal TX is provided, the exposure of all pixels ends, and the D phase is generated in all pixels. In addition, immediately after the transmission signal TX is provided, the vertical driving circuit 213 sequentially provides the driving signals INI2 and INI1.

[0142] In the period from time t22 to time t24 after time t21, the vertical driving circuit 213 provides the control signal WEN, and the DAC 211 changes the reference signal REF in a ramp shape. At t23 in this period, when the D phase exceeds the level of the reference signal REF, the comparator 320 inverts the comparison result VCO. The latch unit 400 stores the time data obtained when the comparison result VCO is inverted. Therefore, the D phase is AD converted in all pixels.

[0143] At time t25 after time t24, the vertical driving circuit 213 provides the output timing signal WORD to the 0th pixel in the cluster 217 within a specific period. At time t26 within the transmission period of the output timing signal WORD, the vertical driving circuit 213 provides the control signal REN. In response to the control signal REN, the repeater unit 220 transmits the 0th pixel data (time data) of each cluster to the signal processing unit 250.

[0144] Subsequently, the output timing signal WORD is sequentially transmitted to the 1st to 127th pixels in each cluster 217, and the control signal REN is provided during the transmission period of the output timing signal WORD. Therefore, pixel data in which the D phase has been converted is transmitted from all pixels to the signal processing unit 250.

[0145] The subsequent signal processing unit 250 performs CDS processing to obtain the difference between the P phase and the D phase of all pixels.

[0146] Fig.15 : is a timing chart showing an example of an operation in which the 0th cluster 217 in the 001th column outputs a digital signal in the first embodiment of the present technology.

[0147] At time t30, the supply of the control signal WEN ends, and the AD conversion of the P phase is completed in all pixels. During the period from time t31 to time t35 after time t30, the vertical drive circuit 213 provides a high-level output timing signal WORD to the 0th pixel of each cluster. <0> During this period, the output timing signal WORD <1> To WORD <127> is set to low level.

[0148] During the pulse period from time t32 to time t33, the vertical driving circuit 213 provides the output enable signal EN_OUT_001 at a high level. <0> , time t32 is a time after a certain delay time from time t30. In addition, during the pulse period, the vertical drive circuit 213 provides a high-level control signal REN. <0> and output enable signal EN_OUT_001 <0> is at a high level, so pixel data of the P phase is output from the 0th pixel in the 001th column.

[0149] At time t34 after a gap period has elapsed from time t33, supply of the master clock signal MCK starts. The repeater unit 220 transmits pixel data of the P phase in synchronization with the master clock signal MCK.

[0150] In a predetermined period starting from time t35, the vertical driving circuit 213 provides a high-level output timing signal WORD to the first pixel of each cluster. <1> During this period, the output timing signal WORD m is not "1". <m>is set to low level.

[0151] At time t36 after time t35, the supply of the main clock signal MCK is stopped. At time t37 after the gap period has passed since time t36, the vertical drive circuit 213 supplies the control signal REN at a high level during the pulse period. During this period, the output enable signal EN_OUT_001 is <1> is set to low level. Since the output enable signal EN_OUT_001 <1> It is at a low level (disabled), and therefore, pixel data of the P phase is not output from the first pixel in the 001th column.

[0152] Subsequently, the output timing signal WORD, the output enable signal EN_OUT, and the control signal REN are sequentially provided to the 2nd pixel to the 127th pixel. Then, at time t38, the transmission of the P phase is completed in all pixels.

[0153] After the transmission of the P phase, the D phase is sequentially transmitted for the 0th pixel to the 127th pixel. Fig.15 In the figure, the transmission of phase D is omitted.

[0154] like Fig.15 As shown, pixel data is output from a pixel (eg, the 0th pixel) for which the output enable signal EN_OUT is valid. Meanwhile, pixel data is not output from a pixel (eg, the first pixel) for which the output enable signal EN_OUT is disabled.

[0155] Fig.16 : is a timing chart showing an example of an operation in which the first cluster 217 in the 001th column outputs a digital signal in the first embodiment of the present technology.

[0156] Output enable signal EN_OUT_001 <128> To EN_OUT_001 <255> is provided to the 0th pixel to the 127th pixel in the first cluster 217 .

[0157] At time t32, the vertical driving circuit 213 provides the control signal REN in the pulse period, and outputs the enable signal EN_OUT_001 <128> Therefore, pixel data of the P phase is not output from the 128th pixel in the 001th column (in other words, the 0th pixel in the first cluster).

[0158] In addition, at time t37, the vertical drive circuit 213 provides a high-level output enable signal EN_OUT_001 in the pulse period. <129> The pixel data of the P phase is output from the 129th pixel in the 001th column (in other words, the first pixel in the first cluster).

[0159] Subsequently, the output timing signal WORD, the output enable signal EN_OUT, and the control signal REN are sequentially provided to the 2nd pixel to the 127th pixel, and at time t38, the transmission of the P phase is completed in all the pixels.

[0160] like Fig.16 As shown, pixel data is output from a pixel (eg, the 1st pixel) for which the output enable signal EN_OUT is valid, while pixel data is not output from a pixel (eg, the 0th pixel) for which the output enable signal EN_OUT is disabled.

[0161] In addition, the output enable signal EN_OUT_001 <256> To EN_OUT_001 <383> is provided to the second cluster 217 in the 001th column. Subsequently, the 128-bit output enable signal is similarly provided to the third and subsequent clusters 217. The output enable signals EN_OUT_001<(k×128)> to EN_OUT_001<(k×128+127)> are provided to the kth (k is an integer) cluster 217. For example, the output enable signal EN_OUT_001 <3456> To EN_OUT_001 <3583> is provided to the 27th cluster 217. The same applies to columns other than the 001st column.

[0162] like Fig.15 and Fig.16 As shown, the output timing signal WORD <0> To WORD <127> Then, the corresponding output enable signal EN_OUT_i <j>When valid, pixel data is output from the corresponding pixel, and when the corresponding output enable signal EN_OUT_i <j>When the enable signal EN_OUT_i is disabled, pixel data is not output. As described above, the solid-state imaging element 200 can set whether digital pixel data can be output in units of pixels. Note that when the output enable signal EN_OUT_i is disabled for all pixels, the pixel data is not output. <j>When set to valid, according to the output timing signal WORD <m>Output the pixel data of the mth pixel in all clusters. Assuming the total number of pixels is N (N is an integer), since the number of clusters is N / 128, according to the output timing signal WORD <m>Output N / 128 pixel data at the same time.

[0163] Fig.17 2 is an explanatory diagram showing analog-to-digital conversion in the first embodiment of the present technology. A predetermined number (for example, 128) of pixels and repeaters 230 are arranged in each of the plurality of clusters 217 .

[0164] The repeater 230 is connected to the cluster 217 in which a predetermined number (for example, 128) of pixels are arranged. The repeater 230 transmits a time code.

[0165] In each pixel, a pixel circuit 310 and an ADC 305 are arranged. In the ADC 305, a NAND gate 410, a comparator 320, a latch control circuit 420, and a latch circuit 430 are arranged.

[0166] Note that Fig.17 In the figure, for convenience of explanation, the NAND gate 410 is represented by a switch symbol. In addition, the xWORD signal obtained by inverting the output timing signal WORD signal is input to the NAND gate 410, but for convenience of explanation, Fig.17 The signal is shown without inversion at the input.

[0167] The pixel driving circuit 215 drives the pixel circuits 310 of all pixels so that the pixel circuits 310 generate analog pixel signals SIG corresponding to the exposure amount.

[0168] The comparator 320 compares the pixel signal SIG with the reference signal REF that changes within a predetermined AD conversion period, and outputs a comparison result VCO. When the comparison result is inverted, the latch control circuit 420 controls each latch circuit 430 so that the latch circuit 430 holds (in other words, latches) a digital time code representing the time within the AD conversion period. The latch circuit 430 acquires the time code from the repeater 230 under the control of the latch control circuit 420 and latches the time code. Through the above control, in all pixels, the analog pixel signal SIG is converted into a digital time code.

[0169] Fig.18 : is an explanatory diagram showing the operation of a pixel in which the output enable signal EN_OUT is set to be active in the first embodiment of the present technology.

[0170] The vertical driving circuit 213 provides the output enable signal EN_OUT to the NAND gate 410. In addition, the vertical driving circuit 213 outputs the enable signal EN_OUT according to the output timing signal WORD <0> To WORD <127> The 128 pixels are sequentially driven so that the pixels output pixel data.

[0171] Here, it is assumed that the output of a certain pixel data in the ROI is set to be valid according to the output enable signal EN_OUT. In this case, the NAND gate 410 outputs the corresponding timing signal WORD <0> Provided to the latch control circuit 420. <0> At the time indicated, the latch control circuit 420 controls each latch circuit 430 so that the latch circuit 430 outputs the digital time code as pixel data to the repeater 230. The repeater 230 transmits the pixel data to the signal processing unit 250. The signal processing unit 250 performs signal processing such as image recognition processing on the transmitted pixel data.

[0172] Note that the NAND gate 410 is an example of an enable control unit described in the claims.

[0173] Fig.19 : is an explanatory diagram showing the operation of a pixel in which the output enable signal EN_OUT is set to disabled in the first embodiment of the present technology.

[0174] Here, it is assumed that the output of a certain pixel data outside the ROI is set to be disabled according to the output enable signal EN_OUT. In this case, the NAND gate 410 does not provide the corresponding output timing signal WORD to the latch control circuit 420. <1> . Since no output timing signal WORD is provided <1> Therefore, the latch control circuit 420 does not cause each latch circuit 430 to output pixel data.

[0175] like Fig.18 and Fig.19 As shown, the solid-state imaging element 200 can set whether to output pixel data to the repeater 230 in units of pixels according to the output enable signal EN_OUT.

[0176] Fig. 20 An example of image data before and after setting the ROI in the first embodiment of the present technology is shown. Fig. 20 In FIG. 1 , a shows an example of image data before setting ROI. Fig. 20 In FIG. 8 , b shows an example of image data after setting the ROI.

[0177] When ROI is not set, the solid-state imaging element 200 continuously acquires image data in synchronization with the vertical synchronization signal VSYNC, and Fig. 20 As shown in a, the display unit 130 displays image data 500.

[0178] The user refers to the displayed image data and sets the ROI by operating the touch screen or the like. For example, Fig. 20 As shown in b, a circular ROI 512 is set.

[0179] The motion vector detection unit 253 performs block matching and the like based on the past image data (frame) 500 and the current image data (frame) 501 and detects a motion vector 511 .

[0180] Fig.21 An example of ROI in the first embodiment of the present technology is shown. Fig.21 , the dotted line indicates the periphery of the image data before the ROI is set. When the motion vector 511 of the ROI is detected, the next frame ROI prediction unit 255 predicts the position of the ROI in the next image data 502 of the current image data based on the motion vector 511. Then, the next frame ROI prediction unit 255 provides the setting information about the predicted ROI to the vertical drive circuit 213.

[0181] The vertical drive circuit 213 sets the output enable signal EN_OUT for the pixels in the predicted ROI to be valid, and sets the output enable signal EN_OUT for the pixels outside the ROI to be disabled. Fig.21 As shown, only pixel data in ROI 520 in next image data 502 is output to repeater 230 and transmitted to signal processing unit 250. Therefore, signal processing (eg, CDS processing and image recognition processing) is performed on ROI 520, and the processed ROI 520 is displayed.

[0182] like Fig. 20 and Fig.21 As shown, the solid-state imaging element 200 predicts the ROI of the next frame, and therefore, even when the ROI is set within a range where motion occurs, the ROI can be moved to an appropriate position according to the motion.

[0183] Here, a comparative example in which the NAND gate 410 is not provided and the output enable signal EN_OUT is not supplied to each pixel will be described.

[0184] Fig. 22 2 shows image data in which ROI is set in a comparative example and image data transmitted to the signal processing unit 250. Fig. 22 In FIG. 1 , a shows an example of image data 550 in which ROI is set. Fig. 22 In FIG. 1 , b shows an example of image data 560 transmitted from the repeater 230 to the signal processing unit 250. Fig. 22 In b, the outer dotted line indicates the periphery of the image data before setting the ROI.

[0185] like Fig. 22 As shown in a, a rectangular ROI 551 is set in the image data 550. In this case, the vertical driving circuit 213 and the pixel driving circuit 215 of the comparative example drive the pixels so that the pixels output the pixel data in the ROI to the repeater 230 in units of rows. Fig. 22 As shown in b, the repeater 230 transmits the image data 560 including the ROI to the signal processing unit 250. Since the image data is output in units of lines, the columns of the image data 560 include not only the columns within the ROI but also the columns outside the ROI.

[0186] Fig.23 An example of ROI in the comparative example is shown. Fig.23 , the outer dotted line indicates the periphery of the image data before setting the ROI. The signal processing unit 250 of the comparative example stores the image data 560 output in line units in a frame memory or the like, and extracts pixel data in the ROI 570 from the image data 560 in column units. The signal processing unit 250 of the comparative example performs various signal processing such as image recognition processing on the extracted ROI 570.

[0187] like Fig. 22 and Fig.23 As shown, in the comparative example in which the NAND gate 410 is not provided, the vertical drive circuit 213 cannot output the pixel data to be processed in the ROI to the repeater 230 in units of pixels. Therefore, the vertical drive circuit 213 and the pixel drive circuit 215 drive the pixels so that the pixels output the pixel data to be processed to the repeater 230 in units of rows. Then, the repeater 230 must transmit the pixel data output in units of rows to the signal processing unit 250, and the signal processing unit 250 must extract the pixel data to be processed in units of columns. In this configuration, as the number of columns increases, the amount of data to be transmitted to the signal processing unit 250 increases, thereby reducing the processing speed of the signal processing unit 250. Therefore, the solid-state imaging element 200 of the comparative example can only achieve a frame rate of, for example, several hundred frames per second (fps).

[0188] At the same time, if Fig. 20 and Fig.21 As shown, in the solid-state imaging element 200 including the NAND gate 410, the vertical drive circuit 213 can output the pixel data to be processed to the repeater 230 in units of pixels according to the output enable signal EN_OUT. Therefore, it is not necessary to perform the following processing: in which the signal processing unit 250 stores the image data output in units of rows in a frame memory or the like, and extracts the pixel data to be processed in units of columns. Therefore, the processing speed of the signal processing unit 250 can be improved by the amount of processing. Through this improvement in processing speed, the solid-state imaging element 200 can capture and process frames at an extremely high frame rate of, for example, tens of thousands of frames per second (fps).

[0189] Fig.24 1 is a flowchart showing an example of the operation of the solid-state image pickup element 200 in the first embodiment of the present technology. For example, when a predetermined application for capturing image data is executed, the operation is started.

[0190] The pixel driving circuit 215 and the vertical driving circuit 213 drive each pixel to expose all pixels and perform AD conversion on the P phase (step S901). The vertical driving circuit 213 initializes m to "0" (step S902).

[0191] In each cluster 217, the m-th pixel determines whether the output enable signal EN_OUT corresponding to the pixel is "1" (i.e., valid) (step S903). When the corresponding output enable signal EN_OUT is "1" (step S903: Yes), the output timing signal WORD <m>When the m-th pixel becomes "1", the pixel data is output to the repeater 230 (step S904).

[0192] When the output enable signal EN_OUT is not "1" (step S903: No) or after step S904, the vertical drive circuit 213 determines whether m is "127" (step S905). When m is not "127" (step S905: No), the vertical drive circuit 213 increases m (step S906) and repeats step S903 and subsequent steps.

[0193] When m is "127" (step S905: Yes), the vertical drive circuit 213 determines whether the conversion of the D phase has been completed (step S907). When the conversion of the D phase has not been completed (step S907: No), the pixel drive circuit 215 and the vertical drive circuit 213 drive each pixel so that the pixel generates the D phase, performs AD conversion on the D phase, and sets m to "0" in the same manner as the P phase conversion (step S908). Then, the vertical drive circuit 213 repeats step S902 and subsequent steps.

[0194] If the conversion of the D phase has been completed (step S907: Yes), the signal processing unit 250 performs signal processing such as CDS processing and image recognition processing on the transmitted pixel data (step S908). After step S908, the solid-state imaging element 200 terminates the operation of acquiring and processing image data.

[0195] In the case where a plurality of pieces of image data are continuously acquired, the processes in steps S901 to S908 are performed overlappingly in synchronization with a vertical synchronization signal VSYNC.

[0196] As described above, according to the first embodiment of the present technology, when the output is set to be valid according to the output enable signal EN_OUT, the pixel 300 outputs the pixel data, so the vertical drive circuit 213 can output the pixel data to be processed in units of pixels. Therefore, compared with the case where the pixel data to be processed is output to the signal processing unit 250 in units of lines, the throughput of the signal processing unit 250 can be reduced and its processing speed can be increased.

[0197] <2. Second Embodiment>

[0198] In the first embodiment described above, the signal processing unit 250 processes the pixel data in the ROI. However, as the number of pixels in the ROI increases, the throughput of the signal processing unit 250 increases, which may reduce the processing speed. The solid-state imaging element 200 of the second embodiment is different from the solid-state imaging element of the first embodiment in that a plurality of signal processing units process pixel data in parallel.

[0199] Fig.25 1 is a block diagram showing a configuration example of a solid-state imaging element 200 in a second embodiment of the present technology. The solid-state imaging element 200 of the second embodiment is different from the solid-state imaging element of the first embodiment in that an upper signal processing unit 260 and a lower signal processing unit 270 are provided instead of the signal processing unit 250.

[0200] The upper signal processing unit 260 performs CDS processing on the pixel data output from a part of the plurality of clusters (e.g., clusters of even columns). The upper signal processing unit 260 provides the processed pixel data to the lower signal processing unit 270. Note that the upper signal processing unit 260 is an example of the first signal processing unit described in the claims.

[0201] The lower signal processing unit 270 performs CDS processing on the pixel data output from the rest of the plurality of clusters (e.g., clusters of odd columns). The lower signal processing unit 270 generates image data by arranging the pixel data subjected to CDS processing provided from the upper signal processing unit 260 and the pixel data subjected to CDS processing by the lower signal processing unit 270 itself. Then, the lower signal processing unit 270 further performs subsequent processing such as image recognition processing, and outputs the processed data. Note that the lower signal processing unit 270 is an example of a second signal processing unit described in the claims.

[0202] like Fig.25 As shown, the upper signal processing unit 260 and the lower signal processing unit 270 process pixel data in parallel. Therefore, compared with the first embodiment in which only the signal processing unit 250 processes pixel data, the processing speed can be increased.

[0203] Fig.26 2 is a plan view showing a configuration example of the pixel array unit 214 in the second embodiment of the present technology. The repeater unit 220 of the cluster 217 in the odd-numbered columns (e.g., the first column) transmits the pixel data to the lower signal processing unit 270. At the same time, the repeater unit 220 of the cluster 217 in the even-numbered columns (e.g., the second column) transmits the pixel data to the upper signal processing unit 260.

[0204] As described above, according to the second embodiment of the present technology, the upper signal processing unit 260 and the lower signal processing unit 270 process odd and even columns in parallel. Therefore, the processing speed can be increased compared to the case where only the signal processing unit 250 processes the columns.

[0205] <3. Application examples of mobile objects>

[0206] The technology according to the present disclosure (the present technology) is applicable to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile body, such as: a car, an electric car, a hybrid car, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a ship, and a robot.

[0207] Fig. 27 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the present disclosure is applied.

[0208] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig. 27 In the example of , the vehicle control system 12000 includes: a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, the integrated control unit 12050 includes a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F: Interface) 12053 as a functional structure.

[0209] The drive system control unit 12010 controls the operation of the devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device for the following devices: a drive force generator for generating the drive force of the vehicle, such as an internal combustion engine or a drive motor, etc.; a drive force transmission mechanism for transmitting the drive force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a brake device for generating the braking force of the vehicle, etc.

[0210] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for the following devices: a keyless entry system; a smart key system; a power window device; or various lights such as headlights, taillights, brake lights, turn signal lights, and fog lights. In this case, it is possible to input radio waves sent from a portable device that replaces the key or signals of various switches to the body system control unit 12020. The body system control unit 12020 receives input of these radio waves or signals, and controls the door lock device, power window device, and lights of the vehicle.

[0211] The vehicle exterior information detection unit 12030 detects information of the exterior of the vehicle on which the vehicle control system 12000 is installed. For example, the vehicle exterior information detection unit 12030 is connected to the camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the exterior of the vehicle and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform detection processing on objects such as pedestrians, vehicles, obstacles, traffic signs, or text on the road surface, or distance detection processing thereto.

[0212] The imaging unit 12031 is an optical sensor for receiving light and outputting an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, and can also output the electrical signal as distance measurement information. In addition, the light received by the imaging unit 12031 can be visible light or non-visible light such as infrared rays.

[0213] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting a driver state. For example, the driver state detection unit 12041 includes a camera for capturing an image of the driver, and based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the degree of fatigue or concentration of the driver, or can determine whether the driver has fallen asleep.

[0214] The microcomputer 12051 can calculate the control target value of the driving force generator, the steering mechanism or the braking device based on the information outside or inside the vehicle obtained by the vehicle outside information detection unit 12030 or the vehicle inside information detection unit 12040, and can output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control for the purpose of realizing the advanced driver assistance system (ADAS) function, and the advanced driver assistance function includes: collision avoidance or impact reduction of the vehicle, following driving based on the following distance, speed maintenance driving, collision warning of the vehicle, and lane departure warning of the vehicle.

[0215] In addition, the microcomputer 12051 is capable of controlling the driving force generator, steering mechanism or braking equipment, etc. based on the information about the vehicle surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040, thereby performing collaborative control for the purpose of automatic driving in which the vehicle can drive autonomously without relying on the driver's operation or for other purposes.

[0216] Furthermore, based on the information outside the vehicle acquired by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 can control the headlights and switch the high beam to the low beam, for example, according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, thereby performing cooperative control for the purpose of glare protection.

[0217] The sound / image output unit 12052 sends an output signal of at least one of sound or image to an output device that can visually or auditorily notify information to passengers on the vehicle or outside the vehicle. As an example of an output device, Fig. 27 The example of FIG. 1 shows an audio speaker 12061, a display unit 12062, and an instrument panel 12063. For example, the display unit 12062 may include at least one of an on-board display or a head-up display.

[0218] Fig.28 An example of the installation position of the camera unit 12031 is shown.

[0219] exist Fig.28 In the figure, the camera unit 12031 includes camera units 12101, 12102, 12103, 12104 and 12105.

[0220] For example, the camera units 12101, 12102, 12103, 12104 and 12105 are arranged at the following positions: for example, the front nose, rearview mirror, rear bumper and trunk door of the vehicle 12100 and the upper part of the windshield in the vehicle. The camera unit 12101 arranged on the front nose and the camera unit 12105 arranged on the upper part of the windshield in the vehicle mainly obtain the front view image of the vehicle 12100. The camera units 12102 and 12103 arranged on the rearview mirror mainly obtain the side view image of the vehicle 12100. The camera unit 12104 arranged on the rear bumper or the trunk door mainly obtains the rear view image of the vehicle 12100. The camera unit 12105 arranged on the upper part of the windshield in the vehicle is mainly used to detect the front vehicle, pedestrians, obstacles, traffic lights, traffic signs or lanes, etc.

[0221] Notice, Fig.28 Examples of the imaging ranges of the imaging units 12101 to 12104 are shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 disposed on the front nose. The imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 disposed on the rearview mirror. The imaging range 12114 indicates the imaging range of the imaging unit 12104 disposed on the rear bumper or the trunk door. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above is obtained.

[0222] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element including pixels for phase difference detection.

[0223] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 obtains the distance to each three-dimensional object within the camera range 12111 to 12114 and the change of the distance over time (relative speed relative to the vehicle 12100), so that the three-dimensional object that is closest to the vehicle 12000 on the road of travel and travels at a predetermined speed (for example, greater than or equal to 0 km / h) in the same direction as the vehicle 12100 can be extracted as the leading vehicle. In addition, the microcomputer 12051 can set the following distance to be maintained with the leading vehicle in advance, and can perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control) and the like. Therefore, cooperative control for the purpose of automatic driving in which the vehicle travels autonomously without relying on the driver's operation or for other purposes can be performed.

[0224] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 can classify the three-dimensional object data related to the three-dimensional object into two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, extract the three-dimensional object data, and use these three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that are easily noticed by the driver of the vehicle 12100 and obstacles that are difficult for the driver to perceive. In addition, the microcomputer 12051 determines the collision risk used to represent the risk of collision with each obstacle, and when the collision risk is greater than or equal to the set value, that is, in the case of a possible collision, the microcomputer 12051 can output a warning to the driver through the audio speaker 12061 or the display unit 12062, or perform forced deceleration or evasive steering through the drive system control unit 12010, thereby performing driving assistance for avoiding collision.

[0225] At least one of the camera units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can identify pedestrians by determining whether there are pedestrians in the images captured by the camera units 12101 to 12104. For example, such identification of pedestrians is achieved by performing the following processes: a process of extracting feature points in the images captured by the camera units 12101 to 12104 as infrared cameras; and a process of determining whether the object is a pedestrian by pattern matching a series of feature points representing the contour of the object. When the microcomputer 12051 determines that there are pedestrians in the images captured by the camera units 12101 to 12104 and identifies the pedestrians, the sound / image output unit 12052 controls the display unit 12062 so that a rectangular contour line for emphasis is superimposed on the identified pedestrian and displayed. In addition, the sound / image output unit 12052 may also control the display unit 12062 so that an icon for representing a pedestrian is displayed at a desired position.

[0226] In the above, an example of a vehicle control system to which the technology of the present disclosure is applicable has been described. The technology of the present disclosure is applicable to, for example, the camera unit 12031 in the above configuration. Specifically, Figure 1 The camera device 100 in the embodiment is applicable to the camera unit 12031. By applying the technology according to the present disclosure to the camera unit 12031, the frame rate can be increased. Therefore, the image quality of the moving image can be improved and the fatigue of the driver can be reduced.

[0227] Note that the above embodiments show examples for embodying the present technology, and the matters in the embodiments have a corresponding relationship with the matters specifying the present invention in the claims. Similarly, the matters specifying the present invention in the claims have a corresponding relationship with the matters represented by the same names as the names of the matters specifying the present invention in the claims in the embodiments of the present technology. However, the present technology is not limited to these embodiments, and the present technology can be implemented within its gist by applying various modifications to the embodiments.

[0228] Note that the effects described in this specification are merely examples and are not limiting, and other effects may be produced.

[0229] Note that the present technology may also have the following configurations.

[0230] (1) A solid-state imaging element comprising:

[0231] a repeater connected to a cluster in which a predetermined number of pixels are arranged, and transmitting a digital signal indicating a time within a predetermined period;

[0232] a vertical drive circuit that provides an output timing signal indicating an output timing of each of a predetermined number of pixels and an output enable signal indicating whether the output of the digital signal is valid for each pixel;

[0233] a comparator that compares an analog signal corresponding to the exposure amount with a reference signal that varies within a predetermined period of time and outputs a comparison result;

[0234] a latch circuit that acquires a digital signal from the repeater and stores the digital signal;

[0235] a latch control circuit that controls the latch circuit so that the latch circuit holds the digital signal when the comparison result is inverted, and controls the latch circuit so that the latch circuit outputs the digital signal to the repeater at a timing indicated by the output timing signal; and

[0236] The enable control unit provides an output timing signal to the latch control circuit when the output of the digital signal is set to be valid according to the output enable signal.

[0237] (2) The solid-state imaging device according to (1), further comprising:

[0238] a repeater connected to a predetermined number of pixels and transmitting a digital signal; and

[0239] A vertical driving circuit, the vertical driving circuit sequentially drives a predetermined number of pixels according to an output timing signal so that the predetermined number of pixels output digital signals, wherein:

[0240] A transponder and a predetermined number of pixels are arranged in each of the plurality of clusters; and

[0241] A comparator, a latch circuit, a latch control circuit, and an enable control unit are arranged in each of a predetermined number of pixels.

[0242] (3) The solid-state imaging device according to (1) or (2), further comprising:

[0243] A signal processing unit performs predetermined signal processing on the digital signal transmitted by the repeater.

[0244] (4) The solid-state imaging device according to (3), wherein:

[0245] The signal processing unit includes a first signal processing unit and a second signal processing unit;

[0246] A first signal processing unit performs signal processing on a digital signal output from a part of the plurality of clusters; and

[0247] The second signal processing unit performs signal processing on the digital signals output from the remaining ones of the plurality of clusters.

[0248] (5) The solid-state imaging device according to (3) or (4), wherein:

[0249] The signal processing unit includes:

[0250] a signal processing circuit that performs predetermined signal processing on the output digital signal and generates image data; and

[0251] The region of interest setting unit sets a region in the image data where a digital signal is to be output as a region of interest.

[0252] (6) The solid-state imaging device according to (5), wherein:

[0253] The signal processing unit also includes:

[0254] a motion vector detection unit that detects, for each object in the image data, a motion vector indicating a motion direction of the object; and

[0255] The region of interest prediction unit predicts the position of the region of interest in image data to be generated next based on the motion vector.

[0256] (7) A camera device comprising:

[0257] a repeater connected to a cluster in which a predetermined number of pixels are arranged, and transmitting a digital signal indicating a time within a predetermined period;

[0258] a vertical drive circuit that provides an output timing signal indicating an output timing of each of a predetermined number of pixels and an output enable signal indicating whether the output of the digital signal is valid for each pixel;

[0259] a comparator that compares an analog signal corresponding to the exposure amount with a reference signal that varies within a predetermined period of time and outputs a comparison result;

[0260] a latch circuit that acquires a digital signal from the repeater and stores the digital signal;

[0261] a latch control circuit that controls the latch circuit so that the latch circuit holds the digital signal when the comparison result is inverted, and controls the latch circuit so that the latch circuit outputs the digital signal to the repeater at a timing indicated by the output timing signal;

[0262] an enable control unit, which provides an output timing signal to the latch control circuit when the output of the digital signal is set to be valid according to the output enable signal; and

[0263] A storage unit stores image data in which digital signals are arranged.

[0264] (8) A method for controlling a solid-state imaging element, the method comprising:

[0265] A transmitting step of connecting to a cluster in which a predetermined number of pixels are arranged, and transmitting a digital signal representing a time within a predetermined period;

[0266] A vertical driving step of providing an output timing signal indicating an output timing of each of a predetermined number of pixels and an output enable signal indicating whether the output of the digital signal is valid for each pixel;

[0267] Comparison step: comparing the analog signal corresponding to the exposure amount with a reference signal that changes within a predetermined period of time, and outputting a comparison result;

[0268] Latching step: obtaining the digital signal from the repeater and saving the digital signal;

[0269] a latch control step of controlling the latch circuit so that the latch circuit holds the digital signal when the comparison result is inverted, and controlling the latch circuit so that the latch circuit outputs the digital signal to the repeater at a timing indicated by the output timing signal; and

[0270] Enable control step: when the output of the digital signal is set to be valid according to the output enable signal, the output timing signal is provided to the latch control circuit.

[0271] Reference numerals list

[0272] 100 Camera Device

[0273] 110 Optical unit

[0274] 120 DSP circuit

[0275] 130 Display unit

[0276] 140 Operating Units

[0277] 150 Bus

[0278] 160 frame memory

[0279] 170 storage units

[0280] 180 Power supply unit

[0281] 200 Solid-state imaging element

[0282] 201 Optical Receiver Chip

[0283] 202 Circuit Chip

[0284] 211 DAC

[0285] 212 Time code generation unit

[0286] 213 Vertical drive circuit

[0287] 214 pixel array unit

[0288] 215 pixel driving circuit

[0289] 216 Timing Generation Circuit

[0290] 217 Cluster

[0291] 220 Transponder Unit

[0292] 230 Forwarder

[0293] 231 to 234,241,242,422,423,432,433 Inverter

[0294] 240 Transmission Circuit

[0295] 243 Trigger

[0296] 250 signal processing units

[0297] 251 CDS processing unit

[0298] 252 frame memory

[0299] 253 Motion Vector Detection Unit

[0300] 254 ROI setting unit

[0301] 255 Next frame ROI prediction unit

[0302] 256 post-processing units

[0303] 260 Upper signal processing unit

[0304] 270 Lower signal processing unit

[0305] 300 pixels

[0306] 305 ADC

[0307] 310 pixel circuit

[0308] 311 Reset transistor

[0309] 312,314 Floating diffusion layer

[0310] 313 FDG ​​transistor

[0311] 315 Pass transistor

[0312] 316 Photoelectric conversion element

[0313] 317 Charge Drain Transistor

[0314] 320 Comparator

[0315] 330 Differential Input Circuit

[0316] 331,334,344,351,352 pMOS transistors

[0317] 332,335 Differential transistors

[0318] 333 Current Source Transistor

[0319] 340 Positive Feedback Circuit

[0320] 341 to 343, 345, 353, 354 nMOS transistors

[0321] 350 Inverter Circuit

[0322] 400 Latch Unit

[0323] 410 NAND gate

[0324] 420 Latch control circuit

[0325] 421 NOR Gate

[0326] 431 Switch

[0327] 430 Latch Circuit

[0328] 12031 Camera unit.< / m> < / m> < / m> < / j> < / j> < / j> < / m> < / j> < / m> < / j> < / m> < / j> < / m> < / j> < / j> < / j> < / j> < / j> < / m> < / m> < / m> < / m> < / j>

Claims

1. A solid-state imaging element, comprising: a repeater connected to a cluster in which a predetermined number of pixels are arranged, and transmitting a digital signal indicating a time within a predetermined period; a vertical driving circuit, the vertical driving circuit providing an output timing signal indicating an output timing of each of the predetermined number of pixels and an output enable signal indicating whether the output of the digital signal is valid for each of the pixels; a comparator that compares an analog signal corresponding to the exposure amount with a reference signal that varies within the predetermined period and outputs a comparison result; a latch circuit, the latch circuit acquiring the digital signal from the repeater and storing the digital signal; a latch control circuit that controls the latch circuit so that the latch circuit holds the digital signal when the comparison result is inverted, and controls the latch circuit so that the latch circuit outputs the digital signal to the repeater at a time indicated by the output timing signal; and An enable control unit, when the output of the digital signal is set to be valid according to the output enable signal, the enable control unit provides the output timing signal to the latch control circuit.

2. The solid-state imaging element according to claim 1, wherein The comparator, the latch circuit, the latch control circuit, and the enable control unit are arranged in each of the predetermined number of pixels.

3. The solid-state imaging element according to claim 1 or 2, further comprising: A signal processing unit performs predetermined signal processing on the digital signal transmitted by the repeater.

4. The solid-state imaging element according to claim 3, wherein: The signal processing unit includes a first signal processing unit and a second signal processing unit; The first signal processing unit performs the signal processing on the digital signal output from a part of the clusters; and The second signal processing unit performs the signal processing on the digital signals output from the remaining parts in the cluster.

5. The solid-state imaging element according to claim 3, wherein: The signal processing unit comprises: a signal processing circuit that performs predetermined signal processing on the output digital signal and generates image data; and A region of interest setting unit is configured to set a region of the image data where the digital signal is to be output as a region of interest.

6. The solid-state imaging element according to claim 5, wherein: The signal processing unit also includes: a motion vector detection unit configured to detect, for each object in the image data, a motion vector indicating a motion direction of the object; and A region of interest prediction unit predicts a position of the region of interest in image data to be generated next based on the motion vector.

7. A camera device, comprising: a repeater connected to a cluster in which a predetermined number of pixels are arranged, and transmitting a digital signal indicating a time within a predetermined period; a vertical driving circuit, the vertical driving circuit providing an output timing signal indicating an output timing of each of the predetermined number of pixels and an output enable signal indicating whether the output of the digital signal is valid for each of the pixels; a comparator that compares an analog signal corresponding to the exposure amount with a reference signal that varies within the predetermined period and outputs a comparison result; a latch circuit, the latch circuit acquiring the digital signal from the repeater and storing the digital signal; a latch control circuit that controls the latch circuit so that the latch circuit holds the digital signal when the comparison result is inverted, and controls the latch circuit so that the latch circuit outputs the digital signal to the repeater at a time indicated by the output timing signal; an enabling control unit, wherein when the output of the digital signal is set to be valid according to the output enabling signal, the enabling control unit provides the output timing signal to the latch control circuit; and A storage unit stores the image data in which the digital signal is arranged.

8. A method for controlling a solid-state imaging element, the method comprising: The transmitting step: the repeater is connected to a cluster in which a predetermined number of pixels are arranged, and transmits a digital signal indicating a time within a predetermined period; Vertical driving step: providing an output timing signal indicating an output timing of each of the predetermined number of pixels and an output enable signal indicating whether the output of the digital signal is valid for each of the pixels; Comparison step: comparing the analog signal corresponding to the exposure amount with the reference signal that changes within the predetermined period of time, and outputting the comparison result; Latching step: acquiring the digital signal from the repeater and storing the digital signal; A latch control step: when the comparison result is inverted, the latch circuit is controlled by the latch control circuit so that the latch circuit stores the digital signal, and at a time indicated by the output timing signal, the latch circuit is controlled by the latch control circuit so that the latch circuit outputs the digital signal to the repeater; and An enabling control step: providing the output timing signal to the latch control circuit when the output of the digital signal is set to be valid according to the output enabling signal.

Images