Current acquisition circuit, integrated device and battery management system

Abstract

The present disclosure provides a current collection circuit for detecting charging current and / or discharging current of a battery / battery pack, the charging and discharging of the battery / battery pack being controlled by a charging control transistor and a discharging control transistor connected in series with the battery / battery pack, wherein the drain of the charging control transistor and the drain of the discharging control transistor are connected, the current collection circuit comprising: a first transistor, a second transistor, a first voltage collection circuit, a second voltage collection circuit, and a constant current source. The present disclosure also provides an integrated device and a battery management system.

Description

TECHNICAL FIELD

[0001] The present disclosure provides a current collection circuit, an integrated device and a battery management system. BACKGROUND

[0002] With the development of technology of rechargeable batteries, the rechargeable batteries have been widely used in various fields such as electric tools, portable devices, electric vehicles and the like. The rechargeable batteries are charged and provided to the power consuming devices. However, the charging current and the discharging current need to be detected during the charging process and the discharging process of the rechargeable batteries to avoid overcharging and overdischarging and the like, so as to avoid the occurrence of safety accidents, the damage of the battery life and the like.

[0003] The detection of the charging current and the discharging current currently adopted can be realized by means of an external detection resistor. However, the external detection resistor will result in energy loss, and in the case of using a high-precision detection resistor, the cost will be greatly increased and the like.

[0004] There is also a way of detecting the discharging current and the charging current by means of the voltage on both sides of the charging control transistor and / or the discharging control transistor. However, in this detection method, the voltage generated by the on-resistance of the charging control transistor and / or the discharging control transistor needs to be detected to realize the detection of the discharging current and the charging current.

[0005] For example Figure 1 As shown, the discharging voltage detected by the analog-to-digital converter (ADC) is equal to (Ron(M1)+Ron(M2))*ILOAD, and the charging voltage detected by the ADC is equal to (Ron(M1)+Ron(M2))*ICHG, wherein Ron(M1) is the on-resistance of the discharging control transistor, Ron(M2) is the on-resistance of the charging control transistor, ILOAD is the discharging current, and ICHG is the charging current.

[0006] The on-resistance of the charging control transistor and the discharging control transistor is represented as wherein μ n is the channel electron mobility, Cox is the gate oxide layer capacitance per unit area, W is the channel width of the transistor, L is the channel width of the transistor, VGS is the gate-source voltage of the transistor, VTH is the on-threshold voltage of the transistor, Rcont is the contact resistance, and Rdrift is the drift region resistance. Accordingly, the detected charging current or discharging current is equal to the voltage detected by the ADC divided by the on-resistance.

[0007] However, it should be noted that the on-resistance of the transistor will change with the change of the ambient temperature during the use of the transistor, and the on-resistance of the transistor will change with the change of the process during the manufacture of the transistor, so that the on-resistance of the transistor used during the use of the transistor cannot be completely guaranteed to be constant. Thus, due to the uncertainty of the on-resistance of the transistor, the detected charging current or discharging current will be uncertain, so that more accurate detection cannot be achieved in this way. SUMMARY

[0008] To solve one of the above technical problems, the present disclosure provides a current acquisition circuit, an integrated device and a battery management system. Compared with the prior art, according to the technical solution of the present disclosure, the charging and discharging currents can be detected more accurately without being affected by the ambient temperature and the transistor manufacturing process.

[0009] According to one aspect of the present disclosure, a current acquisition circuit for detecting the charging current and / or the discharging current of a battery / battery pack, the charging and discharging of the battery / battery pack being controlled by a charging control transistor and a discharging control transistor connected in series with the battery / battery pack, wherein the drain of the charging control transistor and the drain of the discharging control transistor are connected, the current acquisition circuit comprising:

[0010] a first transistor and a second transistor for detecting the discharging current and / or the charging current, the drain of the first transistor being connected with the drain of the discharging control transistor and the drain of the charging control transistor, and the drain of the second transistor being connected with the drain of the discharging control transistor and the drain of the charging control transistor;

[0011] a first voltage acquisition circuit, the input end of the first voltage acquisition circuit being connected with the source of the first transistor;

[0012] a second voltage acquisition circuit, the input end of the second voltage acquisition circuit being connected with the source of the second transistor; and

[0013] a constant current source for providing a constant current, and the output end of the constant current source being connected with the source of the first transistor or the source of the second transistor.

[0014] Optionally, the channel length-width ratio / cell number of the first transistor and / or the second transistor is proportional to the channel length-width ratio / cell number of the discharging control transistor and / or the charging control transistor.

[0015] Optionally, the on-resistance of the first transistor and / or the second transistor is proportional to the on-resistance of the discharge control transistor and / or the charge control transistor.

[0016] Optionally, the on-resistance of the first transistor and / or the second transistor is greater than the on-resistance of the discharge control transistor and / or the charge control transistor.

[0017] Optionally, the on-resistance of the first transistor and the second transistor is the same as the on-resistance of the discharge control transistor and / or the charge control transistor.

[0018] Optionally, the first transistor, the second transistor, the discharge control transistor and the charge control transistor are integrated in one device.

[0019] Optionally, when detecting the discharge current and / or the charge current, the first transistor is turned on and the second transistor is turned off, or the second transistor is turned on and the first transistor is turned off.

[0020] Optionally, the first transistor, the second transistor, the discharge control transistor and the charge control transistor are NMOS transistors or PMOS transistors of the same type.

[0021] Optionally, the first voltage acquisition circuit includes a first switch and a first acquisition capacitor, and the second voltage acquisition circuit includes a second switch and a second acquisition capacitor, the first switch and the second switch are turned on or turned off at the same time, and the voltage of the source of the first transistor is transferred to the first acquisition capacitor and the voltage of the source of the second transistor is transferred to the second acquisition capacitor through the turning on of the first switch and the second switch.

[0022] Optionally, an analog-to-digital converter is further included, which is used to convert the voltage of the first acquisition capacitor and the voltage of the second acquisition capacitor into a digital signal.

[0023] Optionally, a reference voltage generation circuit is further included, which is used to provide a temperature-independent reference voltage to the analog-to-digital converter, and the analog-to-digital converter converts the voltage of the first acquisition capacitor and the voltage of the second acquisition capacitor into a digital signal based on the reference voltage.

[0024] Optionally, in the discharge detection process and / or the charge detection process, the discharge current and / or the charge current is determined based on the voltage of the source of the first transistor, the voltage of the source of the second transistor, the current value of the constant current, and the ratio of the channel length-width ratio / cell number of the first transistor to the discharge control transistor.

[0025] Optionally, in the discharging detection process and / or the charging detection process, the discharging current and / or the charging current is determined based on the voltage of the source of the second transistor, the voltage of the source of the first transistor, the current value of the constant current, and the ratio of the channel length-width ratio / cell number of the second transistor to the charging control transistor.

[0026] Optionally, the gate control signal of the second transistor is low, and in the discharging detection process, the gate control signal of the first transistor and the gate control signal of the discharging control transistor are the same control signal, and in the charging detection process, the gate control signal of the first transistor and the gate control signal of the charging control transistor are the same control signal.

[0027] Optionally, the gate control signal of the first transistor is low, and in the discharging detection process, the gate control signal of the second transistor and the gate control signal of the discharging control transistor are the same control signal, and in the charging detection process, the gate control signal of the second transistor and the gate control signal of the charging control transistor are the same control signal.

[0028] Optionally, in the discharging and / or charging detection process, the gate control signal of the second transistor is low, and the gate control signal of the first transistor is high, or in the discharging and / or charging detection process, the gate control signal of the second transistor is high, and the gate control signal of the first transistor is low.

[0029] Optionally, the number of the first transistor and the second transistor is one or more than two, and when the number of the first transistor and the second transistor is more than two, the more than two first transistors are connected in parallel between the drain of the discharging control transistor and the input terminal of the first voltage acquisition circuit, and one first transistor is selected by a gating switch, and the more than two second transistors are connected in parallel between the drain of the charging control transistor and the input terminal of the first voltage acquisition circuit, and one second transistor is selected by a gating switch.

[0030] Optionally, the on-resistance of the more than two first transistors is proportional, and / or the on-resistance of the more than two second transistors is proportional.

[0031] Optionally, the channel length-width ratio / cell number of the more than two first transistors is proportional, and / or the channel length-width ratio / cell number of the more than two second transistors is proportional.

[0032] Optionally, the constant current is a constant current independent of temperature.

[0033] A calibration resistor is also included, which is connected between the output terminal of the current source and the ground terminal, so as to calibrate the on-resistance of the discharge control transistor, the charge control transistor, the first transistor, and / or the second transistor, so as to be independent of temperature.

[0034] According to another aspect of the present disclosure, an integrated device at least integrates the discharge control transistor, the charge control transistor, the first transistor, and the second transistor in the current collection circuit according to any one of the above.

[0035] According to still another aspect of the present disclosure, a battery management system comprises:

[0036] the current collection circuit according to any one of the above or the integrated device according to the above claim; and

[0037] a logic control circuit for providing gate control signals to the discharge control transistor, the charge control transistor, the first transistor, and the second transistor, so as to control the on and off of the discharge control transistor, the charge control transistor, the first transistor, and the second transistor, and receiving the detected charging current and / or discharging current,

[0038] Optionally, the gate control signals are provided according to the received charging current and / or discharging current. BRIEF DESCRIPTION OF DRAWINGS

[0039] The accompanying drawings illustrate exemplary embodiments of the present disclosure and together with the general description of the disclosure given above, and the detailed description of the embodiments below, serve to explain the principles of the present disclosure. These drawings are included herewith and constitute a part of this specification.

[0040] Figure 1 A schematic diagram of a current collection circuit according to the prior art is shown.

[0041] Figure 2 A schematic diagram of a current collection circuit according to one embodiment of the present disclosure is shown.

[0042] Figure 3 A schematic diagram of a current collection circuit according to one embodiment of the present disclosure is shown.

[0043] Figure 4 A schematic diagram of a current collection circuit according to one embodiment of the present disclosure is shown.

[0044] Figure 5 A schematic diagram of a battery management system according to one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0045] The present disclosure will be described in further detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are merely exemplary and are not limiting to the present disclosure. In addition, it should also be understood that for the convenience and clarity of the description, only parts of the relevant are shown in the drawings.

[0046] It should be noted that the embodiments and features of the present disclosure can be combined with each other if there is no conflict. The technical solutions of the present disclosure will be described in detail below with reference to the drawings and in combination with the embodiments.

[0047] Unless otherwise specified, the exemplary embodiments / examples shown will be understood as providing exemplary features of various details that can implement the technical concepts of the present disclosure in practice. Therefore, unless otherwise specified, the features of various embodiments / examples can be additionally combined, separated, interchanged and / or rearranged without departing from the technical concepts of the present disclosure.

[0048] In the drawings, cross-hatching and / or shading are generally used for clarity of view of boundaries between adjacent parts. Thus, the presence or absence of cross-hatching or shading does not convey or imply any preference or requirement for specific material, material properties, dimensions, proportions, commonality of the illustrated parts between the parts, and / or any other characteristics, attributes, properties, etc. of the parts, unless stated. In addition, in the drawings, the size and relative sizes of parts can be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments can be implemented differently, a specific process sequence can be performed in a different order from that described. For example, two consecutively described processes can be performed substantially simultaneously or in an order opposite to that described. In addition, the same reference numerals represent the same parts.

[0049] When a part is referred to as "on" or "above" another part, "connected to" or "bonded to" another part, the part can be directly on, directly connected to or directly bonded to the other part, or there can be an intermediate part. However, when a part is referred to as "directly on" another part, "directly connected to" or "directly bonded to" another part, there is no intermediate part. For this reason, the term "connected" can refer to a physical connection, an electrical connection, etc., with or without an intermediate part.

[0050] For descriptive purposes, the disclosure can use spatially relative terms, such as "below," "lower," "under," "downward," "down," "upper" "over," "upward" and "on" (and derivatives thereof), to describe the relative position of one component to another (or another component) as illustrated in the figures. Unless otherwise stated as used herein, the spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "under" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. Moreover, the device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0051] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms "including," "includes," "having," "has," "with," or "contains," "containing," or variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprising." It is also noted that the terms "substantial," "approximately," and other similar terms, as used herein, are used in their normal, ordinary sense and are not used in an absolute sense.

[0052] According to one embodiment of the present disclosure, a charge-discharge current acquisition circuit is provided.

[0053] The charge-discharge current acquisition circuit can be used to detect the charge current and discharge current of a battery pack.

[0054] Figure 2 A charge-discharge current acquisition circuit according to one embodiment of the present disclosure is shown.

[0055] The charge-discharge current acquisition circuit can be used to detect the charge-discharge current of a battery or a battery pack. And more accurate detection of the charge-discharge current can be achieved by the charge-discharge current acquisition circuit of the present disclosure.

[0056] The charge-discharge current collection circuit can include a discharge control transistor MD and a charge control transistor MC, wherein the discharge control transistor MD and the charge control transistor MC can be NMOS transistors or PMOS transistors. Figure 2 In the embodiment, the discharge control transistor MD and the charge control transistor MC are arranged at the low-voltage side of the negative terminal of the battery, but those skilled in the art should understand that the discharge control transistor MD and the charge control transistor MC can also be arranged at the high-voltage side of the positive terminal of the battery. In the following, the arrangement at the low-voltage side will be taken as an example for description. The principle of the arrangement at the high-voltage side is the same, and will not be described herein again.

[0057] Figure 2 The discharge current detection is shown. As shown in FIG. 1, the source S1 of the discharge control transistor MD can be connected to the negative terminal of the battery pack BAT, and the drain D of the discharge control transistor MD can be connected to the drain D of the charge control transistor MC, and the source S2 of the charge control transistor MC can be connected to the load LOAD. In addition, the source S2 of the charge control transistor MC can also be connected to the negative terminal of the battery pack BAT, and the drain D of the charge control transistor MC can be connected to the drain D of the discharge control transistor MD, and the source S1 of the discharge control transistor MD can be connected to the load LOAD. Figure 2

[0058] In addition, a parasitic diode D1 connected in reverse between the source S1 and the drain D of the discharge control transistor MD, and a parasitic diode D2 connected in reverse between the source S2 and the drain D of the charge control transistor MC can exist.

[0059] The discharge control transistor MD is controlled to be turned on and turned off by providing a discharge control signal DSG to the gate of the discharge control transistor MD, so as to control the discharge of the battery pack BAT. The charge control transistor MC is controlled to be turned on and turned off by providing a charge control signal CHG to the gate of the charge control transistor MC, so as to control the charge of the battery pack BAT.

[0060] The charge-discharge current collection circuit can further include a first transistor MS1 and a second transistor MS2. The drain D of the first transistor MS1 can be connected to the drain D of the discharge control transistor MD, and the drain D of the second transistor MS2 can be connected to the drain of the charge control transistor MC.

[0061] In addition, a parasitic diode D3 connected in reverse between the source S3 and the drain D of the first transistor MS1, and a parasitic diode D4 connected in reverse between the source S4 and the drain D of the second transistor MS2 can exist.

[0062] ​The detection of the discharge current is controlled by providing a discharge current detection control signal DSG to the gate of the first transistor MS1 to control the on and off of the first transistor MS1. The detection of the charge current is controlled by providing a charge current detection control signal CHG to the gate of the second transistor MS2 to control the on and off of the second transistor MS2. It is noted that although the discharge control signal DSG and the discharge current detection control signal DSG are shown as the same signal in Figure 2 and the following drawings, they can be different control signals, although in Figure 2 and the following drawings, the charge control signal CHG and the charge current detection control signal CHG are shown as the same signal, they can be different control signals.

[0063] The charge and discharge current collection circuit can further include a constant current source, and the constant current source can generate a constant current IREF according to the voltage AVDD.

[0064] In detecting the discharge current, the source S3 of the first transistor MS1 can be connected to the constant current IREF provided by the constant current source, and the source terminal S3 of the first transistor MS1 is also connected to the first voltage collection circuit. The first voltage collection circuit can include a first switch SW1 and a first capacitor CS1. The first end of the first switch SW1 is connected to the source terminal S3 of the first transistor MS1, the second end of the first switch SW1 is connected to the first end of the first capacitor CS1, and the second end of the first capacitor CS1 is grounded. The source terminal S4 of the second transistor MS2 is also connected to the second voltage collection circuit, which can include a second switch SW2 and a second capacitor CS2. The first end of the second switch SW2 is connected to the source terminal S4 of the second transistor MS2, the second end of the second switch SW2 is connected to the first end of the second capacitor CS2, and the second end of the second capacitor CS2 is grounded. In this disclosure (including the following description), the ground terminal can be the negative terminal B- of the battery / battery pack, or the negative terminal P- of the load / charger. For example, the ground terminal is preferably the negative terminal B- of the battery / battery pack.

[0065] In addition, the first end of the first capacitor CS1 can be connected to the first analog-to-digital converter ADC1 for detecting the voltage of the first capacitor CS1, and the first end of the second capacitor CS2 can be connected to the second analog-to-digital converter ADC2 for detecting the voltage of the second capacitor CS2. Although two analog-to-digital converters are shown in Figure 2 , one analog-to-digital converter can also be used. The voltages of the first capacitor CS1 and the second capacitor CS2 are detected simultaneously by the one analog-to-digital converter.

[0066] In the present disclosure, two or more first transistors MS1 can be included, and each first transistor MS1 is connected in the same manner, and two or more second transistors MS2 can also be included, and each second transistor MS2 is connected in the same manner.

[0067] In the case of some types of transistors, the channel aspect ratio of the first transistor can be proportional to the channel aspect ratio of the discharge control transistor MD, and the proportional value can be 100, 1000, 10000, etc. The channel aspect ratio of the second transistor can be proportional to the channel aspect ratio of the charge control transistor MC, and the proportional value can be 100, 1000, 10000, etc. In this way, the on-resistance of the first transistor and the on-resistance of the discharge control transistor MD can also be the same proportion, and the on-resistance of the second transistor and the on-resistance of the charge control transistor MC can also be the same proportion.

[0068] In the case of some types of transistors, the cell number of the first transistor can be proportional to the cell number of the discharge control transistor MD, and the proportional value can be 100, 1000, or 10000, etc. The cell number of the second transistor can be proportional to the cell number of the charge control transistor MC, and the proportional value can be 100, 1000, or 10000, etc. In this way, the on-resistance of the first transistor and the on-resistance of the discharge control transistor MD can also be the same proportion, and the on-resistance of the second transistor and the on-resistance of the charge control transistor MC can also be the same proportion. In addition, the channel aspect ratio / cell number of the first transistor and the channel aspect ratio / cell number of the second transistor can be set to be the same and proportional to the channel aspect ratio / cell number of the same discharge control transistor MD and the channel aspect ratio / cell number of the charge control transistor MC.

[0069] In the present disclosure, the discharge control transistor MD, the first transistor, the second transistor, and the charge control transistor MC are integrated in one device, so that the four can ensure that the on-resistance of the discharge control transistor MD, the first transistor, the second transistor, and the charge control transistor MC changes correspondingly when the temperature or process conditions change.

[0070] When discharging the battery pack BAT, the discharge control signal DSG and the discharge current detection control signal DSG are high, and the charge control signal CHG and the charge current detection control signal CHG are low, so that the discharge control transistor MD is turned on, the first transistor MS1 is turned on, the charge control transistor MC is turned off, and the second transistor MS2 is turned off.

[0071] In this case, the discharge current ILOAD flows from the positive terminal of the battery pack BAT, through the load LOAD and to the negative terminal of the battery pack BAT. And the constant current IREF can flow to the discharge control transistor MD via the first transistor MS1.

[0072] Thus the voltage at the source S3 of the first transistor MS1 VS3 = IREF x Ron(MS1) + ILOAD x Ron(MD), where IREF is the current value of the constant current, Ron(MS1) is the resistance value of the on-resistance of the first transistor MS1, ILOAD is the current value of the discharge current, and Ron(MD) is the resistance value of the on-resistance of the discharge control transistor MD.

[0073] As mentioned above, since the on-resistance of the first transistor MS1 is significantly greater than the on-resistance of the discharge control transistor MD, the voltage value generated by the discharge control transistor MD will be significantly less than the voltage value generated by the first transistor MS1 for the same current value IREF of the constant current, and thus the voltage value generated by the discharge control transistor MD for the same current value IREF of the constant current can be omitted in the above equation.

[0074] In the process of detecting the voltage at the source S3 of the first transistor MS1, the first switch SW1 of the first voltage acquisition circuit can be turned on, so that the charge will be transferred to the first capacitor CS1, and the voltage across the first capacitor CS1 will be equal to the voltage at the source S3 of the first transistor MS1, and the voltage VS3 is detected by the first analog-to-digital converter ADC1.

[0075] In addition, the voltage at the source S4 of the second transistor MS2 VS4 is detected simultaneously by the second voltage acquisition circuit. In the detection process, the second switch SW2 of the second voltage acquisition circuit can be turned on, so that the charge will be transferred to the second capacitor CS2, and the second capacitor CS2 will be equal to VS4. The voltage VS4 is detected by the second analog-to-digital converter ADC2. It should be noted that in this disclosure, the voltages VS3 and VS4 need to be detected simultaneously. If they are not detected at the same time, the charging current and the discharging current will change over time, which will cause errors to occur, whether in the charging process or in the discharging process. Finally, the voltage at the source S4 of the second transistor MS2 VS4 = ILOAD x Ron(MD).

[0076] As shown above, the first analog-to-digital converter ADC1 and the second analog-to-digital converter ADC2 can be different analog-to-digital converters or the same analog-to-digital converter. The analog-to-digital converter can receive a reference voltage provided by the reference voltage generation circuit, where the reference voltage sets a zero-temperature-coefficient voltage, that is, the reference voltage will not change with temperature. The analog-to-digital converter can convert the voltages VS3 and VS4 through the reference voltage, so that the voltage VS3 will be converted into the first digital signal DVS3, and the voltage VS4 will be converted into the second digital signal DVS4.

[0077] where K is a proportional coefficient.

[0078] Formula 1 can also be transformed as: After transformation, we can get: where the coefficient M is the ratio of the on-resistance of the first transistor MS1 and the on-resistance of the discharge control transistor MD, since they are integrated in one integrated device, the on-resistance of the two will change accordingly with the change of the ambient temperature and the manufacturing process, so the coefficient M will not be affected by the change of the ambient temperature and the manufacturing process, the proportional coefficient K is the ratio between the first digital signal DVS3 and the second digital signal DVS4 detected by the analog-to-digital converter, the proportional coefficient K can be obtained by the output digital signal of the analog-to-digital converter, so it will not be affected by the change of the ambient temperature and the manufacturing process, IREF is the constant current provided by the constant current source, which will not be affected by the change of the ambient temperature and the manufacturing process.

[0079] Therefore, the discharge current will not be affected by the change of the ambient temperature and the manufacturing process, and through the way of the present disclosure, the detection value of the discharge current which is completely not affected by the change of the ambient temperature and the manufacturing process can be obtained.

[0080] In addition, the charge and discharge current collection circuit can also include an external resistance REXT (an external resistance separate from the integrated device), which can be used for calibration through the external resistance REXT. The calibration of the on-resistance of the first transistor MS1 can be realized by comparing the voltage generated by the external resistance REXT and the voltage generated by the on-resistance of the first transistor MS1 when the constant current flows through the external resistance REXT and the first transistor MS1, so as to realize the calibration of the discharge control transistor MD and the like.

[0081] In the present disclosure, the constant current IREF can be calibrated by the external resistor REXT, so as to make the constant current IREF completely irrelevant to temperature. For example, the external resistor REXT can be selected as a low temperature coefficient resistor or a zero temperature coefficient resistor, for example, the temperature coefficient can be 10 ppm / °C. In the calibration process of the constant current IREF, the voltage of the external resistor can be measured, for example, if the actual measured voltage of the external resistor is inconsistent with the reference voltage (pre-stored) at 27°C, it indicates that the constant current IREF is affected by temperature and changes. In order to eliminate this effect, the constant current IREF value can be adjusted according to the inconsistency, or the inconsistency can also be considered in the processing of the analog-to-digital converter or the logic control unit, for example, a corresponding coefficient is set according to the inconsistency, so that the inconsistency is eliminated.

[0082] According to the embodiments of the present disclosure, those skilled in the art should understand that the embodiments can perfectly realize the accurate detection of the discharge current without being affected by the changes of the ambient temperature and the manufacturing process.

[0083] In the optional embodiments of the present disclosure, the number of the first transistors and / or the second transistors can be more than two, for example, in Figure 3 The case including two first transistors MS1, MS3 and two second transistors MS2, MS4 is shown in FIG. 1. The on-resistance of each first transistor can be set in proportion and the on-resistance of each second transistor can also be set in proportion, for example, 100, 1000, etc., and be arranged in parallel. In this case, the appropriate first transistor and / or second transistor can be selected according to the size of the discharge current value. The on-resistance value of the first transistor is obviously larger than the on-resistance value of the discharge control transistor MD. In the case of small discharge current, if the first transistor with large on-resistance is selected, the voltage generated by the first transistor will drown the voltage generated by the discharge control transistor MD, so that the detection of the discharge current is not accurate. By switching the first transistors with different proportions, the detection of the discharge current can be more accurate.

[0084] In the above description, it is explained that the detection of the discharge current is carried out by Figure 2 the embodiments of FIG. 1, and the first transistor is used as the discharge current detection transistor. However, the detection of the charging current ICHG can also be carried out by the embodiments of FIG. 2, and the first transistor can be used as the charging current detection transistor when the charging current detection is carried out. The principle of the charging current detection and the discharge current detection is completely the same, for example, ILOAD in the above is replaced by ICHG, which will not be described here.

[0085] In the above embodiment, the first transistor is shown as the charging current or discharging current detection transistor. However, the second transistor can also be used as the charging current or discharging current detection transistor.

[0086] Figure 4 The charging current detection is shown as follows: Figure 4 As shown, the source S1 of the discharging control transistor MD can be connected to the negative terminal of the battery pack BAT, and the drain D of the discharging control transistor MD can be connected to the drain D of the charging control transistor MC, and the source S2 of the charging control transistor MC can be connected to the charger. In addition, the source S2 of the charging control transistor MC can also be connected to the negative terminal of the battery pack BAT, and the drain D of the charging control transistor MC can be connected to the drain D of the discharging control transistor MD, and the source S1 of the discharging control transistor MD can be connected to the load LOAD. It should be noted that, regardless of charging control or discharging control, similar circuits can be used, and for ease of illustration, different figures are used for illustration. In the circuits of the two controls, the main difference is the connection mode of the current source, external resistance, etc.

[0087] Moreover, in the present disclosure, the same current source and the same external resistance can be used in charging control or discharging control, and the same current source and / or the same external resistance can be switched by a switch to change the connection mode of the same current source and / or the same external resistance.

[0088] In addition, a reverse-connected parasitic diode D1 can exist between the source S1 and the drain D of the discharging control transistor MD, and a reverse-connected parasitic diode D2 can exist between the source S2 and the drain D of the charging control transistor MC.

[0089] The charging of the battery pack BAT is controlled by providing a charging control signal CHG to the gate of the charging control transistor MC to control the on and off of the charging control transistor MC, and the discharging of the battery pack BAT is controlled by providing a discharging control signal DSG to the gate of the discharging control transistor MD to control the on and off of the discharging control transistor MD.

[0090] The charging and discharging current collection circuit can further include a first transistor MS1 and a second transistor MS2. The drain D of the first transistor MS1 can be connected to the drain D of the discharging control transistor MD, and the drain D of the second transistor MS2 can be connected to the drain of the charging control transistor MC.

[0091] Further, a reverse-connected parasitic diode D3 can exist between the source S3 and the drain D of the first transistor MS1, and a reverse-connected parasitic diode D4 can exist between the source S4 and the drain D of the second transistor MS2.

[0092] The detection of the discharge current is controlled by providing the gate of the first transistor MS1 with a discharge current detection control signal DSG to control the on and off of the first transistor MS1. The detection of the charge current is controlled by providing the gate of the second transistor MS2 with a charge current detection control signal CHG to control the on and off of the second transistor MS2. Note that although the discharge control signal DSG and the discharge current detection control signal DSG are shown as the same signal in Figure 4 , they can be different control signals. Although the charge control signal CHG and the charge current detection control signal CHG are shown as the same signal in Figure 4 , they can be different control signals.

[0093] The charge and discharge current acquisition circuit can further include a constant current source, and the constant current source can generate a constant current IREF according to the voltage AVDD.

[0094] In the detection of the charge current, the source S4 of the second transistor MS2 can be connected with the constant current IREF provided by the constant current source, and the source terminal S4 of the second transistor MS2 is also connected with a second voltage acquisition circuit. The second voltage acquisition circuit can include a second switch SW2 and a second capacitor CS2. The first terminal of the second switch SW2 is connected with the source terminal S4 of the second transistor MS2, the second terminal of the second switch SW2 is connected with the first terminal of the second capacitor CS2, and the second terminal of the second capacitor CS2 is grounded. The source terminal S3 of the first transistor MS1 is also connected with a first voltage acquisition circuit, which can include a first switch SW1 and a first capacitor CS1. The first terminal of the first switch SW1 is connected with the source terminal S3 of the first transistor MS1, the second terminal of the first switch SW1 is connected with the first terminal of the first capacitor CS1, and the second terminal of the first capacitor CS1 is grounded.

[0095] In addition, the first terminal of the first capacitor CS1 can be connected with a first analog-to-digital converter ADC1 for detecting the voltage of the first capacitor CS1, and the first terminal of the second capacitor CS2 can be connected with a second analog-to-digital converter ADC2 for detecting the voltage of the second capacitor CS2. Although two analog-to-digital converters are shown in Figure 4 , one analog-to-digital converter can also be used. The voltages of the first capacitor CS1 and the second capacitor CS2 are detected simultaneously by the one analog-to-digital converter.

[0096] In the present disclosure, two or more first transistors can be included, and each first transistor can be connected in the same manner. Two or more second transistors can also be included, and each second transistor can be connected in the same manner.

[0097] In the case of some types of transistors, the channel aspect ratio of the first transistor and the channel aspect ratio of the discharge control transistor MD can be proportional, and the proportional value can be 100, 1000, 10000, or the like. The channel aspect ratio of the second transistor and the channel aspect ratio of the charge control transistor MC can be proportional, and the proportional value can be 100, 1000, 10000, or the like. This can make the on-resistance of the first transistor and the on-resistance of the discharge control transistor MD also the same proportion, and the on-resistance of the second transistor and the on-resistance of the charge control transistor MC also the same proportion. In addition, the channel aspect ratio / cell number of the first transistor and the channel aspect ratio / cell number of the second transistor can be set to be the same and proportional to the channel aspect ratio / cell number of the same discharge control transistor MD and the channel aspect ratio / cell number of the charge control transistor MC.

[0098] In the case of some types of transistors, the cell number of the first transistor and the cell number of the discharge control transistor MD can be proportional, and the proportional value can be 100, 1000, or 10000, or the like. The cell number of the second transistor and the cell number of the charge control transistor MC can be proportional, and the proportional value can be 100, 1000, or 10000, or the like. This can make the on-resistance of the first transistor and the on-resistance of the discharge control transistor MD also the same proportion, and the on-resistance of the second transistor and the on-resistance of the charge control transistor MC also the same proportion. The channel aspect ratio / cell number of the first transistor and the channel aspect ratio / cell number of the second transistor can also be set to be the same, and the channel aspect ratio / cell number of the discharge control transistor MD and the channel aspect ratio / cell number of the charge control transistor MC can be set to be the same.

[0099] In the present disclosure, the discharge control transistor MD, the first transistor, the second transistor, and the charge control transistor MC are integrated in one device, so that the four can ensure that the on-resistances of the discharge control transistor MD, the first transistor, the second transistor, and the charge control transistor MC change simultaneously when the temperature or process conditions change.

[0100] When the battery pack BAT is controlled to be charged, the discharge control signal DSG and the discharge current detection control signal DSG are low, and the charge control signal CHG and the charge current detection control signal CHG are high, so that the discharge control transistor MD is turned off, the first transistor MS1 is turned off, the charge control transistor MC is turned on, and the second transistor MS2 is turned on.

[0101] In this case, the charge current ICHG flows from the positive terminal of the battery pack BAT to the negative terminal of the battery pack BAT, flows through the charger, and flows back to the positive terminal of the battery pack BAT. The constant current IREF can flow to the charge control transistor MC through the second transistor MS2.

[0102] Thus, the voltage VS4 at the source S4 of the second transistor MS2 is VS4 = IREF x Ron(MS2) + ICHG x Ron(MC), where IREF is the current value of the constant current, Ron(MS2) is the resistance value of the on-resistance of the second transistor MS2, ICHG is the current value of the charge current, and Ron(MC) is the resistance value of the on-resistance of the charge control transistor MC.

[0103] As described above, since the on-resistance of the second transistor MS2 is significantly greater than the on-resistance of the charge control transistor MC, the voltage value generated by the charge control transistor MC due to the current value IREF of the constant current will be significantly less than the voltage value generated by the second transistor MS2 due to the current value IREF of the constant current, and thus the voltage value generated by the charge control transistor MC due to the current value IREF of the constant current can be omitted in the above formula.

[0104] The voltage VS4 at the source S4 of the second transistor MS2 is detected by the second voltage acquisition circuit. During the detection, the second switch SW2 of the second voltage acquisition circuit is turned on, so that the charge is transferred to the second capacitor CS2, and the second capacitor CS2 is equal to VS4. The voltage VS4 is detected by the second analog-to-digital converter ADC2. It should be noted that in the present disclosure, the voltages VS3 and VS4 need to be detected simultaneously. If they are not detected simultaneously, the charge current and the discharge current will change with time during the charging process or the discharging process, which will cause errors.

[0105] The voltage at the source S3 of the first transistor MS1 is detected simultaneously, the first switch SW1 of the first voltage acquisition circuit is turned on, so that the charge is transferred to the first capacitor CS1, and the voltage across the first capacitor CS1 is equal to the voltage at the source S3 of the first transistor MS1. The voltage VS3 is detected by the first analog-to-digital converter ADC1. Finally, the voltage VS3 at the source S3 of the first transistor MS1 is ICHG x Ron(MC).

[0106] As shown above, the first analog-to-digital converter ADC1 and the second analog-to-digital converter ADC2 can be different analog-to-digital converters or can be the same analog-to-digital converter. The analog-to-digital converter can receive a reference voltage provided by the reference voltage generation circuit, where the reference voltage sets a zero temperature coefficient voltage, that is, the reference voltage will not change with temperature. The analog-to-digital converter can convert the voltages VS3 and VS4 through the reference voltage, so that the voltage VS3 will be converted into the first digital signal DVS3, and the voltage VS4 will be converted into the second digital signal DVS4.

[0107] where K is a proportional coefficient.

[0108] Formula 2 can also be transformed as: After transformation, we can get: where the coefficient M is the ratio of the on-resistance of the second transistor MS2 and the on-resistance of the charge control transistor MC, since they are integrated in one integrated device, the on-resistance of the two will change accordingly with the change of the ambient temperature and the manufacturing process, so the coefficient M will not be affected by the change of the ambient temperature and the manufacturing process, the proportional coefficient K is the ratio between the first digital signal DVS3 and the second digital signal DVS4 detected by the analog-to-digital converter, the proportional coefficient K can be obtained by the output digital signal of the analog-to-digital converter, so it will not be affected by the change of the ambient temperature and the manufacturing process, IREF is the constant current provided by the constant current source, which will not be affected by the change of the ambient temperature and the manufacturing process.

[0109] Therefore, the charging current will not be affected by the change of the ambient temperature and the manufacturing process, and the detection value of the charging current obtained by the way of the present disclosure is completely not affected by the change of the ambient temperature and the manufacturing process.

[0110] In addition, the charge and discharge current collection circuit can also include an external resistance REXT, which can be used for calibration. The calibration of the on-resistance of the second transistor MS2 can be realized by comparing the voltage generated by the external resistance REXT and the voltage generated by the on-resistance of the second transistor MS2 when the constant current flows through the external resistance REXT and the second transistor MS2, so as to realize the calibration of the discharge control transistor MD and the charge control transistor MC, etc.

[0111] According to the embodiment of the present disclosure, those skilled in the art should understand that the embodiment can perfectly realize the accurate detection of the charging current without being affected by the change of the ambient temperature and the manufacturing process.

[0112] In optional embodiments of the present disclosure, the number of the first transistors and / or the second transistors can be more than two, the on-resistance of each first transistor can be set in proportion and the on-resistance of each second transistor can also be set in proportion, for example, 100, 1000, etc., and be set in parallel. In this case, a suitable second transistor and / or first transistor can be selected according to the size of the charging current value. The on-resistance value of the second transistor is significantly greater than the on-resistance value of the discharge control transistor MD. In the case of a relatively small charging current, if a second transistor with a large on-resistance is selected, the voltage generated by the second transistor will drown out the voltage generated by the discharge control transistor MD, thereby making the detection of the charging current inaccurate. By switching different proportions of the first transistors, the detection of the charging current can be made more accurate.

[0113] In the above description, the channel length-width ratio / cell number ratio of the second transistor to the charging control transistor is 1:M, the channel length-width ratio / cell number of the first transistor to the discharge control transistor, the channel length-width ratio / cell number of the second transistor and the first transistor to the channel length-width ratio / cell number of the charging control transistor and the discharge control transistor can be 1:M, where M is greater than 1. For example, the value of M can be 100, 1000, 10000, etc. The number of the second transistor and / or the first transistor is N, where N is an integer greater than or equal to 1, the channel length-width ratio / cell number ratio of the i-th second transistor and / or the first transistor to the channel length-width ratio / cell number ratio of the charging control transistor and / or the discharge control transistor is 1:M raised to the power of N-1, where i is an integer greater than or equal to 1, and the value of i changes as the value of N changes.

[0114] The above description is combined with Figure 4 The charging detection is described, but according to Figure 4 When discharging detection is performed, the principle is the same as charging detection, which will not be described here.

[0115] According to further embodiments of the present disclosure, an integrated device (electronic chip) is also provided. In the integrated device, at least the discharge control transistor, the charging control transistor, the first transistor, and the second transistor are integrated. In this way, the transistors can be made using the same process, avoiding differences between different manufacturers and differences between different batches of the same manufacturer. In addition, the constant current source, various switches, reference voltage generation circuit, etc. described above can also be integrated, and an analog-to-digital converter, etc. can also be integrated. In the integrated device, the functions of each component are the same as described above, and will not be described here.

[0116] It should be noted that although the above description uses the first transistor MS1 to detect the discharge current and the second transistor MS2 to detect the charging current, both the charging and discharging currents can also be detected using only the first transistor MS1. In this case, the first transistor MS1 can function as a detection transistor. Thus, when using the first transistor MS1 to detect the charging current, the connection method of the constant current source can be as follows: Figure 2 , Figure 3 As shown. Transistor MS1 is turned on during charging detection, while transistor MS2 is turned off. The charging current is thus determined by the relationship between the on-resistance of transistor MS1 and the on-resistance of transistor MC. This disclosure also provides a battery management system that can be used to manage a battery pack, such as controlling charging and discharging, and detecting the battery pack temperature. The battery pack can be charged by a charger and supply power to loads such as power tools, portable terminals, electric vehicles, etc.

[0117] Figure 5 A battery management system according to an embodiment of the present disclosure is illustrated. The battery management system may include the integrated device and related components described above (which can also be replaced by the current acquisition circuit described above; the integrated device will be used as an example below). It may also include a logic control unit for providing control signals to various transistors in the integrated device and / or providing switching signals to various switches, etc. Additionally, a temperature detection unit may be included for detecting the temperature of the battery pack. Of course, other components may be included in the battery management system as needed, such as a battery voltage detection unit for detecting the voltage of each battery cell.

[0118] In the description of this specification, the references to terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment / mode or example is included in at least one embodiment / mode or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments / modes or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.

[0119] In addition, the terms "first", "second", etc. are used only for the purpose of description, and should not be understood as indicating or implying relative importance or a specific number of the technical features indicated. Thus, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise explicitly and specifically limited.

[0120] Those skilled in the art will understand that the above-mentioned embodiments are only for the purpose of clearly illustrating the present disclosure, and are not intended to limit the scope of the present disclosure. Other changes or modifications can be made on the basis of the above disclosure, and these changes or modifications are still within the scope of the present disclosure.

Claims

1. A current acquisition circuit, wherein the current acquisition circuit is used to detect the charging current and / or discharging current of a battery / battery pack, and to control the charging and discharging of the battery / battery pack by means of a charging control transistor and a discharging control transistor connected in series with the battery / battery pack, wherein the drain of the charging control transistor and the drain of the discharging control transistor are connected, characterized in that, The current acquisition circuit includes: A first transistor and a second transistor are used to detect the discharge current and / or the charging current. The drain of the first transistor is connected to the drain of the discharge control transistor and the drain of the charging control transistor. The drain of the second transistor is connected to the drain of the discharge control transistor and the drain of the charging control transistor. There is a parasitic diode with reverse connection between the source and the drain of the discharge control transistor and a parasitic diode with reverse connection between the source and the drain of the charging control transistor. A first voltage acquisition circuit, wherein the input terminal of the first voltage acquisition circuit is connected to the source of the first transistor; The second voltage acquisition circuit has its input terminal connected to the source of the second transistor. The first voltage acquisition circuit and the second voltage acquisition circuit simultaneously detect the source voltage of the first transistor and the source voltage of the second transistor; and A constant current source is used to provide a constant current, and the output terminal of the constant current source is connected to the source of the first transistor or the source of the second transistor.

2. The current acquisition circuit as described in claim 1, characterized in that, The channel aspect ratio / cell count of the first transistor and / or the second transistor is proportional to the channel aspect ratio / cell count of the discharge control transistor and / or the charge control transistor.

3. The current acquisition circuit as described in claim 1, characterized in that, The on-resistance of the first transistor and / or the second transistor is proportional to the on-resistance of the discharge control transistor and / or the charge control transistor.

4. The current acquisition circuit as described in claim 1, characterized in that, The on-resistance of the first transistor and / or the second transistor is greater than the on-resistance of the discharge control transistor and / or the charge control transistor.

5. The current acquisition circuit as described in claim 1, characterized in that, The on-resistance of the first transistor and the second transistor, and / or the on-resistance of the discharge control transistor and / or the charge control transistor are the same.

6. The current acquisition circuit as described in claim 1, characterized in that, The first transistor, the second transistor, the discharge control transistor, and the charge control transistor are integrated into a single device.

7. The current acquisition circuit as described in claim 1, characterized in that, When the discharge current and / or the charging current is detected, the first transistor is turned on and the second transistor is turned off, or the second transistor is turned on and the first transistor is turned off.

8. The current acquisition circuit as described in claim 1, characterized in that, The first transistor, the second transistor, the discharge control transistor, and the charge control transistor are all NMOS transistors or PMOS transistors of the same type.

9. The current acquisition circuit as described in claim 1, characterized in that, The first voltage acquisition circuit includes a first switch and a first acquisition capacitor, and the second voltage acquisition circuit includes a second switch and a second acquisition capacitor. The first switch and the second switch are simultaneously turned on or off, and by turning on the first switch and the second switch, the voltage at the source of the first transistor is transferred to the first acquisition capacitor and the voltage at the source of the second transistor is transferred to the second acquisition capacitor, respectively.

10. The current acquisition circuit as described in claim 9, characterized in that, It also includes an analog-to-digital converter, which is used to convert the voltage of the first acquisition capacitor and the voltage of the second acquisition capacitor into digital signals.

11. The current acquisition circuit as described in claim 10, characterized in that, It also includes a reference voltage generation circuit for providing a temperature-independent reference voltage to the analog-to-digital converter, which converts the voltage of the first acquisition capacitor and the voltage of the second acquisition capacitor into digital signals based on the reference voltage.

12. The current acquisition circuit as described in claim 1, characterized in that, During the discharge detection process and / or charge detection process, the discharge current and / or the charge current are determined based on the source voltage of the first transistor, the source voltage of the second transistor, the current value of the constant current source, and the ratio of the channel aspect ratio / cell number of the first transistor and the discharge control transistor.

13. The current acquisition circuit as described in claim 1, characterized in that, During the discharge detection process and / or the charge detection process, the discharge current and / or the charge current are determined based on the source voltage of the second transistor, the source voltage of the first transistor, the current value of the constant current source, and the ratio of the channel aspect ratio / cell number of the second transistor and the charge control transistor.

14. The current acquisition circuit as described in claim 1, characterized in that, The gate control signal of the second transistor is low. During the discharge detection process, the gate control signal of the first transistor is the same as the gate control signal of the discharge control transistor. During the charging detection process, the gate control signal of the first transistor is the same as the gate control signal of the charging control transistor.

15. The current acquisition circuit as described in claim 1, characterized in that, The gate control signal of the first transistor is low. During the discharge detection process, the gate control signal of the second transistor is the same as the gate control signal of the discharge control transistor. During the charging detection process, the gate control signal of the second transistor is the same as the gate control signal of the charging control transistor.

16. The current acquisition circuit as described in claim 1, characterized in that, During discharge and / or charge detection, the gate control signal of the second transistor is low and the gate control signal of the first transistor is high, or during discharge and / or charge detection, the gate control signal of the second transistor is high and the gate control signal of the first transistor is low.

17. The current acquisition circuit as described in claim 1, characterized in that, The number of the first transistor and the second transistor is one or more. When the number of the first transistor and the second transistor is two or more, two or more first transistors are connected in parallel between the drain of the discharge control transistor and the input terminal of the first voltage acquisition circuit, and a first transistor is selected by a gating switch. Two or more second transistors are connected in parallel between the drain of the charge control transistor and the input terminal of the first voltage acquisition circuit, and a second transistor is selected by a gating switch.

18. The current acquisition circuit as described in claim 17, characterized in that, The on-resistances of two or more first transistors are proportional, and / or the on-resistances of two or more second transistors are proportional.

19. The current acquisition circuit as described in claim 17, characterized in that, The channel aspect ratio of two or more first transistors is proportional to the number of cells, and / or the channel aspect ratio of two or more second transistors is proportional to the number of cells.

20. The current acquisition circuit as described in any one of claims 1 to 19, characterized in that, The constant current is a constant current that is independent of temperature.

21. The current acquisition circuit as described in claim 1, characterized in that, It also includes a calibration resistor connected between the output of the constant current source and the ground terminal to calibrate the on-resistance of the constant current, discharge control transistor, charge control transistor, first transistor, and / or second transistor so as to be independent of temperature.

22. A battery management system, characterized in that, include: The current acquisition circuit as described in any one of claims 1 to 21; as well as A logic control circuit is used to provide gate control signals to the discharge control transistor, the charge control transistor, the first transistor, and the second transistor to control the conduction and disconnection of the discharge control transistor, the charge control transistor, the first transistor, and the second transistor, and to receive the detected charging current and / or discharging current.

23. The battery management system as described in claim 22, characterized in that, The gate control signal is provided based on the received charging current and / or discharging current.

Images