A track assignment method based on integer linear programming and two-stage partitioning strategy

Abstract

The present invention relates to a track allocation method based on integer linear programming and a two-stage partitioning strategy. Firstly, an effective integer linear programming model for solving the track allocation problem is proposed to minimize the overlap between iroutes and thus significantly improve the routability. Secondly, a parallel mechanism based on panel level and subpanel level is proposed, which can greatly improve the solution speed of the SPTA algorithm without sacrificing the quality of the track allocation solution. Then, an effective two-stage partitioning strategy is designed to further optimize the running time of the algorithm.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit computer-aided design, and in particular relates to a track allocation method based on integer linear programming and a two-stage partitioning strategy with good scalability and parallelism. Background Art

[0002] Physical design is one of the most important and time-consuming links in the design of Very Large Scale Integration (VLSI). The design results directly affect the performance, reliability, and manufacturing yield of the chip. In VLSI physical design, wiring is an extremely critical step. In order to reduce the complexity of the wiring process, it is usually divided into two steps: overall wiring and detailed wiring. With the continuous escalation of the complexity of detailed wiring problems and the continuous increase in wire density, the results of overall wiring are increasingly difficult to match the requirements of detailed wiring. Therefore, in order to reduce the difficulty of detailed wiring work and improve the utilization rate of overall wiring results, scholars introduced the step of track allocation to better match overall wiring and detailed wiring.

[0003] Nowadays, a series of track allocation-related allocation methods have been proposed, including WBM-TA, GTA, TROY, etc. The above traditional track allocation algorithms all maximize the number of allocated wires without allowing conflicts, without considering that unallocated wires may overlap with already allocated wires in the detailed wiring stage, resulting in extremely serious short circuit problems. This cannot provide effective wiring guidance for detailed wiring in actual industrial production.

[0004] In order to solve the above problems and improve the routability in the detailed routing stage, the novel track allocation technology allocates all wires to the track based on minimizing the wire length cost, overlap cost and obstacle cost. NTA, TA-HDPSO, RDTA and other technologies aim to allocate all wires to the track in the track allocation stage. Such a goal is more conducive to solving the short circuit problem in detailed routing and is easier to balance the mismatch between overall routing and detailed routing. Here, we call the problem model corresponding to the above novel track allocation technology the Routability-Driven Track Assignment (RDTA) problem.

[0005] The track allocation problem has been proven to be an NP-hard problem. The Integer Linear Programming (ILP) method is one of the optimization mathematical programming methods for decision-making systems, and has good application prospects in solving NP-hard problems and multivariable optimal decision-making problems. At present, the ILP method has been applied to many problems in the VLSI wiring process, such as overall wiring, track allocation, and detailed wiring. The above series of wiring works based on ILP have achieved relatively excellent results in terms of solution quality, reflecting the feasibility of applying ILP in the wiring field.

[0006] Existing routability-driven track allocation techniques are all based on heuristic methods, which are prone to falling into local optimality, making it impossible to obtain an accurate global optimal track allocation solution. In order to provide a more reliable track allocation solution and more accurate routability estimation for detailed routing, we proposed the SPTA algorithm, a track allocation method based on integer linear programming and a two-stage partitioning strategy with good scalability and parallelism. According to our research, this invention is the first research work to use the ILP method to solve RDTA. Summary of the invention

[0007] The object of the present invention is to provide a track allocation method based on integer linear programming and a two-stage partitioning strategy.

[0008] To achieve the above object, the technical solution of the present invention is: a track allocation method based on integer linear programming and a two-stage division strategy, comprising the following steps:

[0009] Step S1, propose a parallel mechanism based on panel level and subpanel level, and propose a two-stage division strategy based on the mechanism;

[0010] Step S2: Propose an integer linear programming model for solving the routability-driven track allocation problem to minimize the overlap between iroutes and thus significantly improve routability.

[0011] In one embodiment of the present invention, in step S1, the two-stage division strategy includes two sub-processes, namely the first-stage division strategy and the second-stage division strategy, wherein the first-stage division strategy refines the panel into several independent smaller subpanels, and the divided subpanels are completely independent, and the second-stage division strategy divides the current model solution scale into finer-grained units based on the first-stage division strategy.

[0012] In one embodiment of the present invention, in step S2, the track allocation problem driven by routability is described as follows: given a set of nets N to be tracked, N includes global nets and local nets, each net n includes a number of pins and extracted wires iroutes, let P represent a set of panels, each panel p is composed of a row or a column of wiring units, a panel composed of a row or a column of wiring units is a horizontal or vertical panel, and each panel contains a track set T to be allocated. p , the set of all obstacles B T and the set of iroutes to be assigned I p ; For each panelp to be routed, set I p All iroutes in are assigned to the set T p The goal is to minimize the total overlap cost, total obstacle cost, and total line length cost of the track assignment scheme; therefore, the integer linear programming model for solving the routability-driven track assignment problem is as follows:

[0013] 1) Decision variables

[0014] There are only two allocation situations of iroute on the track: allocated and unallocated. The allocation of iroute i on track t is defined as a simple binary variable x it , as shown in formula (1):

[0015]

[0016] When iroute i is assigned to track t, the decision variable x it The value of is 1; otherwise, the decision variable x it The value of is 0;

[0017] 2) Constraints

[0018] Exclusive constraint In an allocation, the exclusive constraint ensures that an iroute can and can only be allocated to one track in the panel to which it belongs, as shown in formula (2):

[0019]

[0020] Among them, for the set I p Any iroute i in |T p |The corresponding x it , if and only if |T p |x it The equation holds when the sum of is equal to 1; otherwise, the exclusive constraint is violated;

[0021] 3) Overlapping quantity legality constraints

[0022] The final overlap cost is obtained by calculating the overlap number by segmenting the panel. The entire panel is divided into several segments of different lengths. After the segmentation is completed, formula (3) can be used to calculate S t In particular, if no conductor is assigned to the kth segment of track t, then the onum obtained by formula (3) is tk The value of is -1. According to the meaning of the overlap number, the overlap number is a non-negative natural number. Formula (4) sets a lower bound for the overlap number to ensure the legitimacy of the overlap number.

[0023]

[0024]

[0025] Among them, onum tk is an integer variable, indicating the number of overlaps of track t on the kth segment, c ik For I p Whether iroutei exists on segment k, c ik is a known binary constant;

[0026] 4) Objective function

[0027] Since the goal of the track allocation problem is to minimize the various costs incurred during the wiring process, the optimization objective function can be expressed by formulas (5)-(8):

[0028] minimizeα×blkcost+β×overlapcost+γ×wlcost (5)

[0029]

[0030]

[0031]

[0032] Among them, blkcost, overlapcost and wlcost are the obstacle cost, overlap cost and line length cost generated in panelp respectively; olen(i,b) represents I p iroute i and B in the set T The overlap length between obstacles b in the set; slen tk represents the length of the kth segment of track t; distance(x ij,pin,j) represents the shortest distance between the position where iroute i is placed and other components in the line network where i is located. i,j,pin belong to the line network where i is located. i ; α, β and γ are custom parameters; Since the conflict between the wire and the obstacle is the top priority in the track allocation process, α is set to a very large value to ensure that the obstacle cost is as small as possible.

[0033] In one embodiment of the present invention, out of consideration for running time, during the model optimization process, the process of calculating the wire length cost is as follows: for iroutes extracted from the local network, they are assigned to the track with the shortest Manhattan distance therefrom; for iroutes extracted from the global network, the Manhattan distances between them and the components in the same network when placed on different tracks are calculated respectively, and then they are assigned to the track with the shortest Manhattan distance. It is worth noting that when calculating the Manhattan distance between the current iroute and other components in the global network, only the distance between the current iroute and the pins in the network and the iroute of the determined track is considered, while the iroute of the undetermined position will be ignored in this process. The distance calculated in this way is used as the basis for optimizing the wire length cost during the model optimization process.

[0034] Compared with the prior art, the present invention has the following beneficial effects: the present invention discloses for the first time the use of an ILP method to solve RDTA. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is the overall flow chart of the router.

[0036] Figure 2(a) Multi-layer overall wiring model.

[0037] The corresponding multi-layer track allocation model in Figure 2(b).

[0038] Figure 3(a) Overall wiring results.

[0039] Fig. 3(b) Schematic diagram of the wire model.

[0040] Figure 4 It is a schematic diagram of the calculation method of obstacle cost and overlap cost.

[0041] Figure 5(a) Top view of the wire mesh.

[0042] Fig. 5(b) Manhattan distance between wire mesh components.

[0043] Fig. 5(c) Weighted complete graph of wire mesh components.

[0044] Figure 5(d) 3D view of the components in the connection line network.

[0045] Figure 6It is a schematic diagram of the segmentation method and the overlapping quantity calculation method.

[0046] Figure 7 This is a schematic diagram of the first stage division strategy.

[0047] Figure 8 This is a schematic diagram of the second-stage partitioning strategy.

[0048] Fig. 9 is a parallel implementation model diagram. DETAILED DESCRIPTION

[0049] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings.

[0050] like Figure 1 As shown, a track allocation method based on integer linear programming and a two-stage partitioning strategy includes the following steps:

[0051] Step S1, propose a parallel mechanism based on panel level and subpanel level, and propose a two-stage division strategy based on the mechanism;

[0052] Step S2: Propose an integer linear programming model for solving the routability-driven track allocation problem to minimize the overlap between iroutes and thus significantly improve routability.

[0053] The invention discloses a track allocation method based on integer linear programming and a two-stage division strategy with good scalability and parallelism.

[0054] The specific design process includes the following:

[0055] 1. Designed a general wiring process. The input data of this process is the track set T of each panel. p 、iroute collection I p And the line network set N, the output data is the track allocation plan. This process contains two sub-processes, namely the two-stage division strategy and the track allocation process.

[0056] 2. A novel two-stage partitioning strategy is proposed. The two-stage partitioning strategy contains two sub-processes, namely the first-stage partitioning strategy and the second-stage partitioning strategy. This process can reduce the time cost of solving the track allocation process.

[0057] 3. The first phase division strategy breaks down the panel into several independent smaller subpanels, and the divided subpanels are completely independent.

[0058] 4. When the conditions for further division are met, the second-stage division strategy divides the current model solution scale into more fine-grained units based on the division in the first stage by subpanel.

[0059] 5. An effective ILP model for solving RDTA is proposed. The model takes into account the routing information of both local and global nets, and has a more accurate routability estimate than the traditional problem model, which reflects the practicality of applying the ILP method to solve RDTA. Under the condition that overlapping conflicts are allowed, the ILP model solution stage proposed by the present invention can obtain the optimal solution for RDTA.

[0060] 6. An effective parallel strategy based on panel level and subpanel level is proposed. Compared with many existing modern track allocation algorithms, SPTA achieves a good speedup ratio on multi-core machines, reflecting its excellent scalability.

[0061] The following is the specific implementation process of the present invention.

[0062] 1. Consider the wire model of the local network:

[0063] The overall routing stage determines the routing scheme for all wire nets, which minimizes the interconnection cost while ensuring the routability of the integrated circuit (IC) design. The track allocation stage allocates each wire in the routing scheme provided by the overall router to a suitable track, and minimizes the overlap cost between wires, the overlap cost between wires and obstacles, and the line length cost within each wire net. Since the traditional track allocation work is to maximize the number of allocated wires to obtain a solution with the lowest cost, there may be a situation where some wires are not allocated, and most track allocation work will not consider the wires in the local wire net, which will lead to inaccurate calculation of the cost generated during the routing process. Therefore, in addition to extracting wires from the global wire net, the problem model of the present invention also considers the extraction of wires in the local wire net, making full use of the information of the overall routing, so that the track allocation result is closer to the detailed routing.

[0064] In the multi-layer wiring problem, the wiring direction within the same layer is consistent (horizontal or vertical), and the wiring directions between adjacent layers are intersecting. Figures 2(a) and (b) are schematic diagrams of the multi-layer track allocation model. In Figure 2(a), there are wiring layers 1, 2, and 3. Wiring layers 1 and 3 are wired in the vertical direction, and 2 is wired in the horizontal direction. Each circle represents an abstract wiring unit, which we call a G-cell. The rectangle in Figure 2(b) is one of the wiring channels of each wiring layer, which we call a panel. The dotted lines in the panel represent tracks, and each panel contains several tracks for placing wires.

[0065] Figure 3 (a) and (b) are schematic diagrams of the wire model extracted by the algorithm. The circular dots are pins, the smallest rectangular area is called a wiring unit, the wire net where all pins exist in the same wiring unit is called a local wire net, and the wire net that spans multiple wiring units is called a global wire net. Figure 3 (a) is the overall wiring result of two wire nets, n1 is a local wire net with two pins, and n2 is a global wire net with two pins. Figure 3 (b) is the specific situation of SPTA extracting wires. Here, the present invention refers to the line segment that passes through one or more wiring units as a wire. w1 and w2 are wires extracted from the global wire net n2, and w3 is a wire extracted from the local wire net n1. The present invention refers to the extracted wire as iroute.

[0066] 2. Cost calculation method

[0067] 2.1 Obstacle Cost

[0068] According to the described wire model, the present invention extracts iroutes to be allocated from the global wire network and the local wire network. When an iroute is allocated to a certain track, if it partially or completely overlaps with one or more obstacles on the track, it is called a conflict between the iroute and the obstacle. The overlapping length caused by this conflict is called the obstacle cost.

[0069] 2.2 Overlapping costs

[0070] When an iroute is assigned to a track, if it partially or completely overlaps with one or more iroutes that have already been assigned to the track, this is called a conflict between iroutes. The length of the overlap caused by this conflict is called the overlap cost.

[0071] Figure 4 The figure shows the calculation method of obstacle cost and overlap cost. The panel shown in the figure contains three tracks, and the shaded rectangle is an obstacle that spans track 2 and track 3. The cost of each track is calculated as follows:

[0072] Track 1: Obstacle cost: 0; Overlap cost: 1×1+3×2+2×1=9;

[0073] track 2: obstacle cost: 0; overlap cost: 0;

[0074] track 3: obstacle cost: 2; overlap cost: 1×1=1;

[0075] 2.3 Line length cost

[0076] Pins and iroutes are components within a net, and a net contains several pins and iroutes. In the track allocation stage, a track is selected for each iroute and it is placed on the track. In the subsequent detailed routing stage, these placed iroutes will be connected to other components of the net in which they are located. The cost of connecting all components within a net together is the wire length cost.

[0077] Figures 5(a)-(d) are schematic diagrams of the calculation method of the wire length cost of a wire net. Figure 5(a) is a top view of a wire net, which contains 6 components (3 pins and 3 iroutes). P2 and ir2 are distributed on the horizontal panel, and the other four components are distributed on the vertical panel of the lower layer. Figure 5(b) lists the Manhattan distances between the components in the wire net. A weighted complete graph is generated using the information in the table, as shown in Figure 5(c). The 6 components are connected together through the minimum spanning tree algorithm, and the resulting tree length is the wire length cost of the wire net (the sum of the lengths of the solid line paths shown in Figure 5(c)). Figure 5(d) is a 3D view of the 6 components of the wire net connected together.

[0078] 3. Problem Model

[0079] Based on the discussion of the wire model and the three costs, the routability-driven track allocation problem solved by the present invention can be described in detail as follows:

[0080] Given a set of nets N (including global nets and local nets) to be assigned tracks, each net n contains a number of pins and iroutes. Let P represent a set of panels, where each panelp consists of a row or column of wiring units. A panel consisting of a row (column) of wiring units is a horizontal (vertical) panel, and each panel contains a set of tracks to be assigned T. p , the set of all obstacles B T and the set of iroutes to be assigned I p For each panelp to be routed, the present invention sets I p All iroutes in are assigned to the set T p The goal is to minimize the total overlap cost, total obstacle cost and total line length cost of the track assignment scheme.

[0081] 4. ILP model of the present invention

[0082] The traditional ILP model cannot be used to solve RDTA. Therefore, a track assignment algorithm based on integer linear programming model and two-stage partitioning strategy is proposed.

[0083] 1) Decision variables

[0084] There are only two types of iroute allocation on the track: allocated and unallocated. We can define the allocation of iroute i on track t as a simple binary variable x it , as shown in formula (1):

[0085]

[0086] When iroute i is assigned to track t, the decision variable x it The value of is 1; otherwise, the decision variable x it The value of is 0.

[0087] 2) Constraints

[0088] Definition 1 Exclusive constraint In an allocation, the exclusive constraint ensures that an iroute can and can only be allocated to one track in the panel to which it belongs, as shown in formula (2):

[0089]

[0090] Among them, for the set I p Any iroute i in |T p |The corresponding x it , if and only if |T p |x it The equality holds when the sum of is equal to 1; otherwise, the exclusive constraint is violated.

[0091] Definition 2 Iroutes Quantity Constraint In order to make the track allocation scheme better guide the detailed wiring work, it is necessary to more fully consider the wiring resources, so the present invention allocates all Iroutes extracted from a panel to the appropriate track.

[0092]

[0093] Among them, for each iroute set I p All |I p |×|T p |x it , if and only if |I p |×|T p |x it The sum of |I p |The equality holds; otherwise, the iroute quantity constraint is violated.

[0094] For the ILP model to solve the RDTA problem, it is necessary to satisfy both Definition 1 and Definition 2.

[0095] Theorem 1: In the ILP model used in the present invention to solve the RDTA problem, the exclusive constraint p1 is truly included in the iroute quantity constraint q1, that is,

[0096] Proof: If it is proved We only need to prove that p1 is a sufficient but not necessary condition for q1. Let p1 represent formula (2) and q1 represent formula (3).

[0097] ①Sufficient condition: Let |T P |=N,|I P |=M. Expanding p1 yields the following M sub-formulas (Formula (44)), and expanding q1 yields the M+1th sub-formula (Formula (5)). Adding the left and right sides of the equal sign in Formula (4) yields Formula (5). Let one solution of p1 be X, then Satisfies q1. It can be obtained that p1→q1.

[0098]

[0099] x 11 +x 12 +...+x 1N +...+x MN =I p | (5)

[0100] ② Non-essential condition: Let Y be a solution of q1, that is, x 11 =x 12 =...=x 1N =1,x 21 =x 22 =...=x MN =0.

[0101] At this time, Y does not satisfy p1.

[0102] Therefore, p1 is a sufficient but not necessary condition for q1.

[0103] In summary, the iroute quantity constraint can be satisfied by satisfying the exclusive constraint in the ILP model for solving the RDTA problem of the present invention. The ILP model of the present invention only needs to add the constraint shown in formula (2).

[0104] 3) Overlapping quantity legality constraints

[0105] In the ILP model proposed in this invention, we calculate the number of overlaps by panel segmentation to obtain the final overlap cost. Figure 6The panel in the figure is used as an example to illustrate. The solid rectangle in the figure is a panel, the dotted line is a track where an iroute can be placed, the shaded rectangle placed on the track is an obstacle, and the horizontally placed solid rectangle in the figure is an iroute. Before allocating iroute, the present invention marks the panel based on the starting point coordinates and the end point coordinates of all iroutes in the panel, and the marking result is shown by the vertical dotted line in the figure. We call the area between the two vertical dotted lines a segment. In this way, the entire panel is divided into several segments of different lengths, the starting segment is indicated by first in the figure, and the ending segment is indicated by last.

[0106] After the segmentation is completed, formula (6) can be used to calculate S t In particular, if no conductor is assigned to the kth segment of track t, then the onum obtained by formula (6) is tk The value of is -1. According to the meaning of the overlap number, the overlap number is a non-negative natural number. Formula (7) sets a lower bound for the overlap number to ensure the legitimacy of the overlap number.

[0107]

[0108]

[0109] Among them, onum tk is an integer variable, indicating the number of overlaps of track t on the kth segment, c ik For I p Whether iroutei exists on segment k, c ik is a known binary constant.

[0110] To ensure that the required overlapping cost is accurate and effective, the overlapping quantity value should meet the legality constraint. Figure 6 This is a track allocation solution for this panel. The panel shown at the bottom shows the overlap of each track on each segment. There are 3 iroutes placed on the 3rd segment of track 1, 0 iroutes placed on the 3rd segment of track 2, and 1 iroute placed on the 3rd segment of track 3. The overlap of tracks 1, 2, and 3 in the 3rd segment is 2, 0, and 0 respectively.

[0111] 4) Objective function

[0112] Since the goal of the track allocation problem is to minimize the various costs incurred during the wiring process, the optimization objective function can be expressed by formulas (8)-(11).

[0113] minimizeα×blkcost+β×overlapcost+γ×wlcost(8)

[0114]

[0115]

[0116]

[0117] Among them, blkcost, overlapcost and wlcost are the obstacle cost, overlap cost and line length cost generated in panel p respectively; olen(i,b) represents I p iroute i and B in the set T The overlap length between obstacles b in the set; slen tk represents the length of the kth segment of track t. distance(x ij ,pin,j) represents the shortest distance between the position where iroute i is placed and other components in the line network where i is located. i,j,pin belong to the line network where i is located. i α, β and γ are custom parameters. Since the conflict between the wire and the obstacle is the most important issue in the track allocation process, α is set to a very large value in the present invention to ensure that the obstacle cost is as small as possible. In the experimental part, the present invention provides the adjustment process of α, β and γ to ensure that the overlap cost and the line length cost are minimized while the obstacle cost reaches the optimal value.

[0118] Considering the running time, the process of calculating the wire length cost in the optimization process of this model is as follows: for the iroutes extracted from the local network, assign them to the track with the shortest Manhattan distance. For the iroutes extracted from the global network, calculate the Manhattan distance between them and the components in the same network when they are placed on different tracks, and then assign them to the track with the shortest Manhattan distance. It is worth noting that when calculating the Manhattan distance between the current iroute and other components in the global network, we only consider the distance between the current iroute and the pins in the network and the iroute of the determined track, while the iroute with an undetermined position will be ignored in this process. The distance calculated in this way is used as the basis for optimizing the wire length cost in the optimization process of this model. Under the premise of a slight decrease in the quality of the solution, using this approximate method to calculate the wire length cost can save more time cost than the minimum spanning tree method.

[0119] Due to the long solution time, the traditional ILP is usually manually stopped within a certain time or a certain number of iterations to meet the time requirements of the wiring design. SPTA does not interrupt the solution process of ILP nor set the number of iterations, but allows it to stop automatically after finding the optimal solution. Therefore, the ILP model of the present invention can obtain the optimal solution under the track allocation problem model of the present invention.

[0120] 5. Two-stage division strategy

[0121] Since ILP is NP-complete, the computational cost of SPTA is relatively high. Therefore, in this section, the present invention proposes a partitioning technique for the ILP model, referred to as a two-stage partitioning strategy, to reduce the size of the solution space in order to save time costs. Before the partitioning, the original problem is solved by establishing an ILP model based on panels. Now, the initial track allocation problem is divided into multiple sub-problems, that is, the panel is divided into multiple subsets according to a certain rule. The present invention calls the smaller unit formed after the division a subpanel. Then, the ILP method is applied to model and solve the track allocation problem of the subpanel.

[0122] (1) Phase I Division Strategy

[0123] The first phase division strategy is to subdivide the panel into several independent smaller subpanels. Figure 7 Schematic diagram of the first phase division strategy. Figure 7 The upper part is a complete panel before division, and the bottom part is the two subpanels formed after division. In the above section, we have completed the segmentation of the panel. Select the segment without any iroute as the basis for dividing the subpanel, that is, the blank segment indicated by the dotted circle in the figure. Figure 7 As shown, the first segment line is used as the starting coordinate of subpanel A, and the starting coordinate of the blank segment is used as the ending coordinate of subpanel A; the ending coordinate of the blank segment is used as the starting coordinate of subpanel B, and the last segment line is used as the ending coordinate of subpanel B. Thus, the panel is divided into two subpanels.

[0124] The first-stage division reduces the solution space, and the divided subpanels are completely independent, so the track allocation results before and after the first-stage division remain consistent, and the time cost is greatly reduced.

[0125] (2) Second-stage division strategy

[0126] The first-stage partitioning strategy only considers dividing the panel into irrelevant subpanels based on the blank segments, but there are still large subpanels. The existence of such subpanels makes the time cost of solving the ILP model too high. Therefore, the second-stage partitioning strategy is proposed.

[0127] Since the first-stage partitioning strategy has found all the partitioning situations that do not involve the wire position, we can then consider selecting the appropriate position within the subpanel to achieve the purpose of partitioning the large-scale subpanel. The present invention sets two cuttable conditions: the wire number condition and the cut number condition. If and only if both cuttable conditions are met, the subpanel will be further partitioned.

[0128] Define 3 wire number conditions: introduce a constant i_num, which represents the maximum number of iroutes that can be contained in a subpanel. A subpanel to be cut must satisfy |I subp |>i_num can become a candidate subpanel to be divided. In order to obtain a subpanel with a uniform number of iroutes after division, the present invention selects a cutting position within the interval of 1 / 3 to 2 / 3 of the segmentation mark of the subpanel.

[0129] Definition 4 Cutting number conditions: only considering the distribution of iroute after cutting, not considering the number of iroute cut may have a bad impact on the final track allocation result. Therefore, the present invention introduces the i_cut parameter, which indicates the number of iroute cuts that can be tolerated in one cut. A subpanel to be cut must satisfy iroutecut<i_cut to become a candidate subpanel to be divided. Among them, iroutecut is the minimum number of cutting wires in all cutting positions of the subpanel. The current subpanel will be divided if and only if conditions a and b are all met.

[0130] Figure 8 The top part shows the two results of the first-stage partitioning strategy, subpanelA and B. The two solid rectangles in the lower left corner show the results of further partitioning, subpanelA1 and A2. The dotted rectangle in the lower left corner shows the removed iroute set. If the two parameters i_num and i_cut are set to 4 and 3 respectively, then subpanelB does not meet the wire number condition and cannot be partitioned. Figure 8It can be seen that subpanelA has 6 segments and 7 segmentation marks (including the left and right edges of the subpanel). We take the segmentation marks in the interval (1 / 3, 2 / 3) as candidate cutting positions, which are the three dotted lines with checks in the figure. Among them, two dotted lines cut 3 wires each, and one dotted line cuts 2 wires. One of the dotted lines meets the cutting number condition, and finally, we cut subpanelA along the position of the dotted line. The two iroutes in the dotted box position in the figure will be cut and moved out to another container for storage. After subpanelA1 and A2 are allocated, the removed iroutes will be greedily allocated to the appropriate track, that is, the track with the minimum cost is selected.

[0131] 6. Proof of the validity of the partitioning method

[0132] The proposed first-stage partitioning strategy is based on panel division, and a single panel is analyzed: let the number of wires in the panel be I, the number of tracks be T, and the number of wires in the two subpanels after partitioning be I1 and I2, respectively, and I = I1 + I2.

[0133] Theorem 2: According to the ILP model, the number of decision variables of a panel is I×T, and the decision variable of this model is a binary variable. Then, the value of the decision variable x can only be 0 or 1. Therefore, the size of the panel search space before partitioning is 2 T×I , the sizes of the subpanel search spaces after division are and Then, there must be

[0134] Proof (proof by contradiction): Assumption Let a = 2 T , because T≥1, so a≥2. The original formula is converted to a I1 +a I2 >a I , divide both sides of the inequality by a I Then we get 1 / a I1 +1 / a I2 > 1. Because a≥2, so a I2 ≥2, then 1 / a I2 ≤1 / 2, and similarly 1 / a I1 ≤1 / 2. Therefore 1 / a I1 +1 / a I2 ≤1. It is inconsistent with the original formula, inequality 2 T×I1 +2 T×I2 <2 T×I Not true.

[0135] The proposed second-stage partitioning strategy divides the current model solution scale into more fine-grained units based on the partitioning in the first stage. The second-stage partitioning strategy is similar to the first stage in terms of the running time reduction principle. The proof process is shown in the proof of the first-stage partitioning, so I will not elaborate on it here.

[0136] In summary, the proposed two-stage partitioning strategy can effectively solve the problem of lengthy solution time for the ILP model. Moreover, after the first-stage partitioning, the track allocation results of the same quality as before the partitioning can still be obtained. By adjusting the wire number condition and the cut number condition, the second-stage partitioning can also ensure that the solution quality is high enough and achieve a significant improvement in solution speed.

[0137] 7. Parallel Strategy of SPTA Algorithm

[0138] Fig. 9 The parallel strategy implementation method adopted by the SPTA algorithm is demonstrated. All threads share the panel set containing all routing resources and the global and local network set. The SPTA algorithm performs parallel processing in two parts during the routing process. The first is to divide the panel into multiple small-scale subpanels, and the second is to establish an ILP model for each independent subpanel. Fig. 9 The panel rows and subpanel rows in the data. The present invention combines the parallel mechanisms of the panel level and the subpanel level to obtain a parallel strategy based on the panel level and the subpanel level. First, SPTA performs the first-stage partitioning operation and the second-stage partitioning operation on the current panel. After completing the two-stage partitioning strategy, a subpanel set is obtained. Then, SPTA performs ILP modeling solution on the current subpanel and redistribution operation of the removed iroutes after the solution. In particular, the parallel strategy of the present invention enables the two-stage partitioning operation and the ILP modeling solution to be performed simultaneously. That is, Fig. 9 There exists p1 to p m Multiple panels perform two-stage partitioning operations simultaneously, and multiple subpanels perform ILP modeling and solving operations simultaneously.

[0139] The parallel solution unit of SPTA without the two-stage partitioning strategy is panel. Since the routing resources between panels are independent of each other, namely tracks, iroutes, and obstacles, the panel-level parallel strategy is feasible and will not destroy the optimal solution of track allocation obtained by the ILP method. The parallel solution unit of SPTA with the first-stage partitioning strategy is subpanel, and the position of iroutes is not changed during the partitioning, and the allocation order of iroutes is fixed. Therefore, the track allocation result obtained by the SPTA algorithm with the first-stage partitioning strategy is still the optimal solution. The parallel solution unit of SPTA with the second-stage partitioning strategy is the finer-grained subpanel. However, the second-stage partitioning strategy fixes the allocation order of the removed iroutes, that is, the iroutes can only be allocated after the allocation of other iroutes in the subpanel to which the removed iroutes belong is completed. Therefore, the final track allocation result obtained by SPTA with the two-stage partitioning strategy is an approximate optimal solution. Finally, the experimental results prove that the parallel strategies based on the panel level and subpanel level are effective.

[0140] The above are preferred embodiments of the present invention. Any changes made according to the technical solution of the present invention, as long as the resulting functions do not exceed the scope of the technical solution of the present invention, belong to the protection scope of the present invention.

Claims

1. A track allocation method based on integer linear programming and a two-stage partitioning strategy, characterized in that: The steps include: Step S1, propose a parallel mechanism based on panel level and subpanel level, and propose a two-stage division strategy based on the mechanism; Step S2, proposing an integer linear programming model for solving the routability-driven track assignment problem to minimize the overlap between iroutes and thus significantly improve routability; In step S1, the two-stage partitioning strategy includes two sub-processes, namely the first-stage partitioning strategy and the second-stage partitioning strategy. The first-stage partitioning strategy refines the panel into several independent smaller subpanels, and the subpanels after the partitioning are completely independent. The second-stage partitioning strategy divides the current model solution scale into finer-grained units based on the first-stage partitioning strategy. In step S2, the routability-driven track allocation problem is described as follows: given a set of nets N to be assigned tracks, N includes global nets and local nets, each net n contains a number of pins and extracted wires iroutes, let P represent a set of panels, where each panel p consists of a row or a column of wiring units, and a panel consisting of a row or a column of wiring units is a horizontal or vertical panel, and each panel contains a set of tracks to be assigned T p , the set of all obstacles B T and the set of iroutes to be assigned I p ; For each panelp to be routed, set I p All iroutes in are assigned to the set T p The goal is to minimize the total overlap cost, total obstacle cost, and total line length cost of the track assignment scheme; therefore, the integer linear programming model for solving the routability-driven track assignment problem is as follows: 1) Decision variables There are only two allocation situations of iroute on the track: allocated and unallocated. The allocation of iroute i on track t is defined as a simple binary variable x it , as shown in formula (1): When iroute i is assigned to track t, the decision variable x it The value of is 1; otherwise, the decision variable x it The value of is 0; 2) Constraints Exclusive constraint In an allocation, the exclusive constraint ensures that an iroute can and can only be allocated to one track in the panel to which it belongs, as shown in formula (2): Among them, for the set I p Any iroute i in |T p |The corresponding x it , if and only if |T p |x it The equation holds when the sum of is equal to 1; otherwise, the exclusive constraint is violated; 3) Overlapping quantity legality constraints The final overlap cost is obtained by calculating the overlap number by segmenting the panel. The entire panel is divided into several segments of different lengths. After the segmentation is completed, formula (3) can be used to calculate S t The overlap number of each segment is calculated by summing all segment elements in . If no conductor is assigned to the kth segment of track t, then the onum obtained by formula (3) is tk The value of is -1. According to the meaning of the overlap number, the overlap number is a non-negative natural number. Formula (4) sets a lower bound for the overlap number to ensure the legitimacy of the overlap number. Among them, onum tk is an integer variable, indicating the number of overlaps of track t on the kth segment, c ik For I p Whether iroute i exists on segment k, c ik is a known binary constant; 4) Objective function Since the goal of the track allocation problem is to minimize the various costs incurred during the wiring process, the optimization objective function is expressed by formulas (5)-(8): minimize α×blkcost+β×overlapcost+γ×wlcost(5) Among them, blkcost, overlapcost and wlcost are the obstacle cost, overlap cost and line length cost generated in panelp respectively; olen(i,b) represents I p iroute i and B in the set T The overlap length between obstacles b in the set; slen tk represents the length of the kth segment of track t; distance(x ij ,pin,j) represents the shortest distance between the position where iroute i is placed and other components in the line network where i is located. i,j,pin belong to the line network where i is located. i ; α, β and γ are custom parameters; Since the conflict between the wire and the obstacle is the top priority in the track allocation process, α is set to a very large value to ensure that the obstacle cost is as small as possible.

2. A track allocation method based on integer linear programming and two-stage partitioning strategy according to claim 1, characterized in that: Out of consideration for running time, during the model optimization process, the process of calculating the wire length cost is as follows: for iroutes extracted from the local network, they are assigned to the track with the shortest Manhattan distance with them; for iroutes extracted from the global network, the Manhattan distances between them and the components in the same network when placed on different tracks are calculated respectively, and then they are assigned to the track with the shortest Manhattan distance. It is worth noting that when calculating the Manhattan distance between the current iroute and other components in the global network, only the distance between the current iroute and the pins in the network and the iroute of the determined track is considered, while the iroute with an undetermined position will be ignored in this process. The distance calculated in this way is used as the basis for optimizing the wire length cost during the model optimization process.

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