Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a preparation method thereof. The method comprises: sequentially depositing an insulating layer and a stop layer on a substrate, wherein the substrate comprises a high-voltage device region and a non-high-voltage device region, the thickness of the insulating layer above the high-voltage device region is greater than the thickness corresponding to the non-high-voltage device region; forming a plurality of first grooves and a plurality of second grooves penetrating through the stop layer and the insulating layer above the high-voltage device region and the non-high-voltage device region of the substrate, respectively; etching part of the stop layer above the first grooves, so that the opening width of the first grooves on the side far away from the substrate is greater than the opening width on the side close to the substrate; and further etching the bottoms of the plurality of first grooves and the plurality of second grooves to extend the depths of the first grooves and the second grooves into at least part of the substrate.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor design and manufacturing, and more particularly, to a semiconductor device and a method for manufacturing the same. BACKGROUND

[0002] With the development of semiconductor technology, the feature size of integrated circuits is getting smaller and smaller, and the number of transistors on a chip is gradually increasing. In order to further improve the storage performance of the memory, the number of chips included on each wafer is also increasing, wherein millions of semiconductor devices are included in the active area (AA) of each chip. The semiconductor devices in the active area of the chip generally use shallow trench isolation (STI) to avoid mutual interference between independent semiconductor devices.

[0003] Generally, a plurality of types of transistors, such as high-voltage transistors (HV MOS), low-voltage transistors (LV MOS), and low-low-voltage transistors (LLV MOS), are included on each wafer. The working voltages of different types of transistors are generally different, and the size or shape of the required shallow trench isolation is also generally different. Therefore, it is particularly important to satisfy the effective isolation between different transistors on the same die. SUMMARY

[0004] The present application provides a semiconductor device and a method for manufacturing the same, which can at least partially solve the above-mentioned problems in the prior art.

[0005] According to an aspect of the present application, a method for manufacturing a semiconductor device is provided, which can include: sequentially depositing an insulating layer and a stop layer on a substrate, wherein the substrate includes a high-voltage device region and a non-high-voltage device region, the thickness of the insulating layer above the high-voltage device region is greater than the thickness corresponding to the non-high-voltage device region; forming a plurality of first grooves and a plurality of second grooves above the high-voltage device region and the non-high-voltage device region of the substrate, respectively, the plurality of first grooves and the plurality of second grooves penetrating through the stop layer and the insulating layer; etching part of the stop layer above the first grooves, so that the opening width of the first grooves away from the substrate is greater than the opening width close to the substrate; and further etching the bottom of the plurality of first grooves and the plurality of second grooves so that the depth of the first grooves and the second grooves extends into at least part of the substrate.

[0006] In an embodiment of the present application, after the further etching process, the opening width of the second grooves away from the substrate can be equal to the opening width close to the substrate.

[0007] In one embodiment of the present application, the step of etching the stop layer above the first recesses can include filling and covering the second recesses by a patterned photoresist layer, so that only the stop layer in the first recesses is etched during the etching process.

[0008] In one embodiment of the present application, after the further etching process, the projection profiles of the first recesses along their respective recess extension directions can be the same.

[0009] In one embodiment of the present application, after the further etching process, the first recesses can include at least two kinds of recesses with different projection profiles along their recess extension directions.

[0010] In one embodiment of the present application, after the further etching process, the second recesses can include at least two kinds of recesses with different widths.

[0011] In one embodiment of the present application, after the further etching process, the widths of the second recesses can be the same.

[0012] In one embodiment of the present application, the step of sequentially depositing an insulating layer and a stop layer on the substrate can include depositing a first insulating layer on the substrate, removing at least a portion of the first insulating layer above the non-high-voltage device region of the substrate by an etching process, and depositing the stop layer on the insulating layer after the etching process.

[0013] In one embodiment of the present application, after etching the bottoms of the first recesses and the second recesses to extend the depths of the first recesses and the second recesses to at least a portion of the substrate, the method can further include filling the first recesses and the second recesses to form a filling layer.

[0014] In one embodiment of the present application, the material of the filling layer can include an insulating material.

[0015] In one embodiment of the present application, the high-voltage device region of the substrate can be used to form high-voltage transistor devices, and the non-high-voltage device region of the substrate can be used to form low-voltage transistor devices and low-low-voltage transistor devices.

[0016] Another aspect of the present application provides a semiconductor device, which can include: a substrate, the substrate being divided into a plurality of high-voltage device regions and a non-high-voltage region; a stack structure formed above the substrate; and a plurality of first recess structures formed by filling insulating material in first recesses that extend through the stack structure and to at least a portion of the substrate corresponding to the high-voltage device regions and have a larger opening width at a side away from the substrate than at a side close to the substrate; and a plurality of second recess structures formed by filling insulating material in second recesses that extend through the stack structure and to at least a portion of the substrate corresponding to the high-voltage device regions.

[0017] In one embodiment of the present application, the stack structure can include an insulating layer and a stop layer, wherein a thickness of the insulating layer above the high-voltage device regions can be greater than a thickness of the insulating layer above the non-high-voltage device regions.

[0018] In one embodiment of the present application, the plurality of first recesses can have the same projected profile along their respective recess extension directions.

[0019] In one embodiment of the present application, the plurality of first recesses can include at least two kinds of recesses having different projected profiles along their recess extension directions.

[0020] In one embodiment of the present application, the plurality of second recesses can include at least two kinds of recesses having different widths from each other.

[0021] In one embodiment of the present application, the widths of the second recesses can be the same.

[0022] In one embodiment of the present application, the high-voltage device regions of the substrate can be used to form high-voltage transistor devices, and the non-high-voltage device regions of the substrate can be used to form low-voltage transistor devices and low-low-voltage transistor devices.

[0023] According to the semiconductor device and the method for manufacturing the same of the present application, by etching trench structures of different shapes in high-voltage device regions and non-high-voltage device regions, the isolation requirements of transistors of different working voltages on the same substrate, such as high-voltage transistors (HV MOS), low-voltage transistors (LV MOS) and low-low-voltage transistors (LLV MOS), can be met at the same time, to a certain extent, the isolation effect between devices is improved, and the performance of the semiconductor device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0024] Other features, objects, and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments thereof as taken in conjunction with the accompanying drawings. In the drawings:

[0025] Figure 1A flow chart of a method for fabricating a semiconductor device according to embodiments of the present application; and

[0026] Figures 2A to 2F A flow chart of a method for fabricating a semiconductor device according to embodiments of the present application; and DETAILED DESCRIPTION

[0027] For a better understanding of the present application, various aspects of the present application will be described in greater detail below with reference to the accompanying drawings. It is to be understood that the detailed description is merely descriptive of exemplary embodiments of the present application and is not intended to limit the scope of the present application in any way. Throughout the specification, like reference numerals refer to like elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0028] In the drawings, the size, dimensions, and shapes of elements have been slightly adjusted for ease of illustration. The drawings are merely schematic and are not drawn to scale. As used in this document, the terms "substantially", "approximately", and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. Additionally, in the present application, the order of the steps of the process descriptions is not necessarily the order in which the processes occur in actual operation, unless otherwise specified or derivable from context.

[0029] It should also be understood that expressions such as "comprise", "include", "have", "contain", and / or "comprising", "including", "having", "contain", and / or "containing", and the like, are open-ended expressions that are used to specify the presence of stated features, elements, and / or components, but do not preclude the presence or addition of one or more other features, elements, components, and / or groups thereof. Furthermore, as used herein, expressions such as "at least one of" a list of items prefaced by "at least one of" indicates that at least one of any one of the listed items can be present, with one or more of the listed items possibly being present more than once. Additionally, when describing embodiments of the present application, the use of "can" means "one or more embodiments of the present application". Also, the use of the term "exemplary" is intended to present examples or illustrations, not a limitation.

[0030] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an overly literal or overly formal sense unless expressly so defined herein.

[0031] It should be noted that, where there is no conflict, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0032] Figure 1 This is a schematic diagram of a method for fabricating a semiconductor device 1000 according to an embodiment of this application. Figure 1 As shown, this application provides a method 1000 for fabricating a semiconductor device, comprising:

[0033] Step S110: Sequentially deposit an insulating layer and a stop layer on a substrate, wherein the substrate includes a high-voltage device region and a non-high-voltage device region, and the thickness of the insulating layer above the high-voltage device region is greater than the thickness corresponding to the non-high-voltage device region;

[0034] Step S120: A plurality of first grooves and a plurality of second grooves penetrating the stop layer and the insulating layer are formed above the high-voltage device region and the non-high-voltage device region of the substrate, respectively;

[0035] Step S130: Etch a portion of the stop layer above the first groove so that the opening width of the first groove on the side away from the substrate is greater than the opening width on the side closer to the substrate;

[0036] Step S140: Further etch the bottom of the plurality of first grooves and the plurality of second grooves so that the depth of the first grooves and the second grooves extends into at least a portion of the substrate.

[0037] The following will combine Figures 2A to 2F The specific processes for each step of the above preparation method 1000 are described in detail.

[0038] Step S110

[0039] like Figure 2AAs shown, a first insulating layer (not shown) is deposited on the semiconductor substrate 10, wherein the substrate 10 includes a high voltage device region (substrate within the dashed line) and a non-high voltage device region (substrate outside the dashed line), which can include a low voltage device region and a low-low voltage device region. The high voltage device region can be used for, for example, high voltage transistors (HV MOS), the low voltage device region can be used for low voltage transistors (LV MOS), and the low-low voltage device region can be used for low-low voltage transistors (LLV MOS). The semiconductor substrate 10 can be a single crystal silicon (Si) substrate, a single crystal germanium (Ge) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc. The material of the substrate 110 can also be a compound semiconductor. For example, the substrate 110 can be a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, or a silicon carbide (SiC) substrate, etc. It is worth noting that the substrate 10 of the present application can also be prepared using at least one of other semiconductor materials known in the art.

[0040] The first insulating layer above the low voltage device region and the low-low voltage device region is etched to form an insulating layer 20, which has a thickness above the high voltage device region of the substrate 10 greater than that of the non-high voltage device region, and then a stop layer 30 is deposited on the insulating layer 20. The material of the insulating layer 20 can be an insulating material, including silicon oxide, and the material of the stop layer 30 can be an insulating material, including silicon nitride, which is mainly used as a stop layer for subsequent chemical mechanical planarization. The stop layer 30 can then be planarized by chemical mechanical grinding (CMP). The method of depositing the first insulating layer and the stop layer 30 can include thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, which are not limited by the present application.

[0041] Step S120

[0042] As Figure 2BAs shown, the insulating layer 20 and the stop layer 30 can be etched using, for example, dry or wet etching processes to form a plurality of first grooves 21 and a plurality of second grooves 22 and 23 penetrating the stop layer 30 and the insulating layer 20. The plurality of first grooves 21 are located above the high-voltage device region of the substrate 10, and the plurality of second grooves 22 and 23 are located above the non-high-voltage device region of the substrate 10. For example, the second groove 22 is located above the low-voltage device region of the substrate 10, and the second groove 23 is located above the low-low-voltage device region of the substrate 10. The plurality of first grooves 21 may include grooves of at least two widths; alternatively, the plurality of first grooves 21 may have the same width. The plurality of second grooves 22 and 23 may include grooves of at least two widths; alternatively, the plurality of second grooves 22 and 23 may have the same width. This application does not impose specific limitations on the widths of the plurality of first grooves 21 and the plurality of second grooves 22 and 23, which can be specifically set according to the isolation conditions required for the subsequent formation of the semiconductor device.

[0043] Step S130

[0044] like Figure 2C As shown, a patterned photoresist layer 40 can be deposited above the stop layer 30. The patterned photoresist layer 40 is used to etch a portion of the stop layer 30 above the first groove 21. After etching, the photoresist layer 40 is removed. The semiconductor device after removing the photoresist layer 40 is as follows: Figure 2D As shown, after etching the portion of the stop layer 30 above the first groove 21, the opening width of the first groove 21 on the side away from the substrate is greater than the opening width on the side closer to the substrate.

[0045] Step S140

[0046] like Figure 2EAs shown, the bottoms of a plurality of first grooves 21 and a plurality of second grooves 22 and 23 are further etched so that the depths of the first grooves 21 and the second grooves 22 and 23 extend into at least a portion of the substrate 10. The projected profiles of the plurality of first grooves 21 along their respective groove extension directions are identical. Alternatively, the plurality of first grooves 21 may include at least two types of grooves with different projected profiles along their groove extension directions. The plurality of second grooves 22 and 23 may include at least two types of grooves with different widths. Alternatively, the second grooves 22 and 23 may have the same width. The portion of the first groove 21 in the substrate 10 has an inverted trapezoidal shape with a larger opening at the top and a smaller opening at the bottom. The side surfaces of the first groove 21 are at an angle to the plane of the substrate 10, which is more conducive to the isolation of high-voltage transistor devices. The plurality of second grooves 22 and 23 may be grooves with the same width at the top and bottom openings, which not only optimizes the process but also makes the groove shape more conducive to effective isolation between low-voltage transistor devices and low-to-low-voltage transistor devices. However, those skilled in the art will know that the depths of the first groove 21 and the second grooves 22 and 23 may be different, and their depths may be specified in accordance with the actual isolation requirements. This application does not impose any restrictions on this.

[0047] Formation as Figure 2E After the first groove 21 and the second grooves 22 and 23 of the shape shown are formed, they can be filled to form a filling layer 50. The filling layer 50 can then be planarized using chemical mechanical polishing (CMP). During planarization of the formed filling layer 50, the stop layer 30 can serve as a reference for CMP; that is, CMP can be stopped when the stop layer 30 is exposed. The planarized semiconductor device is as follows: Figure 2F As shown. The material of the filling layer 50 can be an insulating material, such as silicon oxide. Different materials may have different dielectric constants. In actual production, materials with appropriate dielectric constants can be selected according to the isolation requirements of semiconductor devices. This application does not impose any restrictions on this.

[0048] In the above embodiments of this application, by etching a portion of the semiconductor substrate and the insulating layer and stop layer located above the semiconductor, multiple first grooves and multiple second grooves of different shapes can be formed simultaneously. After filling the multiple first grooves and multiple second grooves, a groove structure is formed, which can effectively isolate different semiconductor devices, such as high-voltage transistor devices, low-voltage transistor devices, and low-low-voltage transistor devices. This can simultaneously meet the isolation requirements of transistor devices with different operating voltages on the same substrate. Furthermore, the different shaped groove structures improve the isolation effect between devices to a certain extent, which is beneficial to the improvement of semiconductor device performance.

[0049] In another embodiment of this application, a semiconductor device is also provided. The semiconductor device may include a substrate divided into multiple high-voltage device regions and non-high-voltage regions, a stacked structure formed on the substrate, multiple first groove structures, and multiple second groove structures. The multiple first groove structures are formed by filling the first grooves with insulating material. The first grooves penetrate the stacked structure and extend to at least a portion of the substrate corresponding to the high-voltage device regions, and the opening width on the side away from the substrate is greater than the opening width on the side closer to the substrate. The multiple second groove structures are formed by filling the second grooves that penetrate the stacked structure and extend to the substrate, corresponding to at least a portion of the high-voltage device regions, with insulating material.

[0050] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the invention. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: An insulating layer and a stop layer are sequentially deposited on a substrate, wherein the substrate includes a high-voltage device region and a non-high-voltage device region, and the thickness of the insulating layer above the high-voltage device region is greater than the thickness corresponding to the non-high-voltage device region; A plurality of first grooves and a plurality of second grooves are formed above the high-voltage device region and the non-high-voltage device region of the substrate, respectively, penetrating the stop layer and the insulating layer; The stop layer above the first groove is etched such that the opening width of the first groove on the side away from the substrate is greater than the opening width on the side closer to the substrate; and Further etching the bottoms of the plurality of first grooves and the plurality of second grooves extends the depth of the first grooves and the second grooves into at least a portion of the substrate, wherein the portions of the first grooves and the second grooves in the substrate have different shapes.

2. The method according to claim 1, characterized in that, After the further etching process, the opening width of the second groove on the side away from the substrate is equal to the opening width on the side closer to the substrate.

3. The method according to claim 1 or 2, characterized in that, The step of etching the portion of the stop layer above the first groove includes: The second groove is filled and covered by a patterned photoresist layer so that only the stop layer in the plurality of first grooves is etched during the etching process.

4. The method according to claim 1, characterized in that, After the further etching process, the projected contours of the plurality of first grooves along their respective groove extension directions are the same.

5. The method according to claim 1, characterized in that, After the further etching process, the plurality of first grooves include at least two types of grooves with different projected profiles along their groove extension direction.

6. The method according to claim 1, characterized in that, After the further etching process, the plurality of second grooves include at least two types of grooves with different widths.

7. The method according to claim 1, characterized in that, After the further etching process, the width of each of the second grooves is the same.

8. The method according to claim 1, characterized in that, The steps of sequentially depositing an insulating layer and a stop layer on a substrate include: A first insulating layer is deposited on the substrate; At least a portion of the first insulating layer located above the non-high voltage device region of the substrate is removed by etching; and The stop layer is deposited on the etched insulating layer.

9. The method according to claim 1, characterized in that, After etching the bottoms of the plurality of first grooves and the plurality of second grooves such that the depths of the first grooves and the second grooves extend to at least a portion of the substrate, the method further includes: The first groove and the second groove are filled to form a filling layer.

10. The method according to claim 9, characterized in that, The filling layer is made of insulating material.

11. The method according to claim 1, characterized in that, The high-voltage device region of the substrate is used to form high-voltage transistor devices, and the non-high-voltage device region of the substrate is used to form low-voltage transistor devices and low-low-voltage transistor devices.

12. A semiconductor device, characterized in that, include: A substrate, wherein the substrate is divided into multiple high-voltage device regions and non-high-voltage regions; A stacked structure is formed above the substrate; as well as A plurality of first groove structures are formed by filling the first grooves with insulating material, the first grooves penetrating the stacked structure and extending to at least a portion of the substrate corresponding to the high voltage device region; as well as Multiple second groove structures are formed by filling insulating material into at least a portion of the second grooves corresponding to the non-high voltage region that extend through the stacked structure and into the substrate. The first groove structure and the second groove structure have different shapes in the substrate; the opening width of the first groove structure on the side away from the substrate is greater than the opening width on the side closer to the substrate, and the width of the second groove structure on the side away from the substrate is equal to the width on the side closer to the substrate.

13. The semiconductor device according to claim 12, characterized in that, The stacked structure includes an insulating layer and a stop layer, wherein the thickness of the insulating layer above the high-voltage device region is greater than the thickness above the non-high-voltage device region.

14. The semiconductor device according to claim 12 or 13, characterized in that, The projected contours of the plurality of first grooves along their respective groove extension directions are identical.

15. The semiconductor device according to claim 12 or 13, characterized in that, The plurality of first grooves include at least two types of grooves with different projected profiles along their groove extension direction.

16. The semiconductor device according to claim 12 or 13, characterized in that, The plurality of second grooves includes at least two types of grooves with different widths.

17. The semiconductor device according to claim 12 or 13, characterized in that, Each of the second grooves has the same width.

18. The semiconductor device according to claim 12, characterized in that, The high-voltage device region of the substrate is used to form high-voltage transistor devices, and the non-high-voltage device region of the substrate is used to form low-voltage transistor devices and low-low-voltage transistor devices.

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