Method of manufacturing a three-dimensional memory structure and three-dimensional memory structure

Abstract

The application provides a method for manufacturing a three-dimensional memory structure and the three-dimensional memory structure. The method comprises: forming a plug in an upper portion of each of two groups of channel holes, the plug having a top end spaced from a top end of the channel hole, wherein the channel hole penetrates through a stack structure and an auxiliary layer located on the stack structure; performing hole expansion on a hole section of the channel hole which is higher than the plug, so that a portion of the auxiliary layer between any two adjacent hole sections of each group of channel holes is removed to form a filling space in the auxiliary layer, and a portion of the auxiliary layer located between the two groups of channel holes remains to form a top select gate isolation pattern; forming a first mask structure in the filling space; and removing the top select gate isolation pattern to form a top select gate isolation opening, and etching the stack structure through the top select gate isolation opening to form a top select gate isolation cutout.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more specifically, to a method for manufacturing a three-dimensional memory structure and the three-dimensional memory structure itself. Background Technology

[0002] With the continuous development of semiconductor technology, people are constantly pursuing semiconductor devices with smaller size and higher performance.

[0003] Three-dimensional (3D) memory can achieve greater storage capacity in a smaller volume compared to 2D memory. However, semiconductor manufacturers are still pursuing 3D memory with even higher storage density. In 3D memory, reducing the distance between memory strings can reduce the horizontal size of the 3D memory. Traditional 3D memory can have, for example, a nine-row channel structure within a memory block, with these channels densely arranged to reduce the horizontal size. However, when these channel structures are divided into two groups, the top select gate isolation cutout has to destroy the middle row of channel structures, thus wasting a row of channel structures and increasing the distance between the two groups of channel structures on either side. Those skilled in the art desire to reduce the horizontal size of 3D memory. Summary of the Invention

[0004] Embodiments of this application provide a method for manufacturing a three-dimensional storage structure, the method comprising: forming a plug at the top of each of two sets of channel holes with a apex spaced from the apex of the channel hole, wherein the channel holes penetrate a stacked structure and an auxiliary layer located on the stacked structure; enlarging the segments of the channel holes above the plugs such that a portion of the auxiliary layer between any two adjacent segments of each set of channel holes is removed to form a fill space in the auxiliary layer, and a portion of the auxiliary layer located between the two sets of channel holes remains to form a top select gate isolation pattern; forming a first mask structure in the fill space; and removing the top select gate isolation pattern to form a top select gate isolation opening, and etching the stacked structure through the top select gate isolation opening to form a top select gate isolation notch.

[0005] In one embodiment, prior to the step of forming the plug, the method further includes: forming two sets of channel holes, wherein the interval between the two sets of channel holes is greater than the interval between any two adjacent channel holes in each set of channel holes; and forming a channel structure in the channel holes, wherein the channel structure extends through the stacked structure.

[0006] In one embodiment, the step of forming the plug includes: providing a filling layer in the channel hole, wherein the filling layer is located on the channel structure; and removing a portion of the filling layer from the top end of the channel hole to form the plug having a top end spaced from the top end of the channel hole.

[0007] In one embodiment, prior to the step of forming two sets of channel holes, the method further includes: forming a stacked structure; and forming an auxiliary layer on the stacked structure, wherein the auxiliary layer includes an auxiliary stop layer and an auxiliary mask layer stacked in a direction away from the stacked structure, and wherein the top of the plug is above the auxiliary stop layer.

[0008] In one embodiment, the method further includes: filling the top selected gate isolation cutout with insulating material to form a top selected gate isolation structure; planarizing the plug, the top selected gate isolation structure, and the stacked structure to at least remove the first mask structure and the auxiliary layer.

[0009] In one embodiment, the plug is made of polycrystalline silicon.

[0010] In one embodiment, the stacked structure includes alternately stacked insulating layers and sacrificial layers; after planarizing the plug, the method further includes: forming a gate line slot through the stacked structure; replacing the sacrificial layer with a gate layer through the gate line slot; forming a gate line slot structure in the gate line slot; and planarizing the top of the stacked structure.

[0011] In one embodiment, after the step of forming the first mask structure and before the step of removing the top select gate isolation pattern, the method further includes: forming a second mask structure on the auxiliary layer; etching the second mask structure to form an opening exposing the top select gate isolation pattern; and after the steps of removing the top select gate isolation pattern to form a top select gate isolation opening and etching the stack structure through the top select gate isolation opening to form a top select gate isolation notch, the method further includes: removing the second mask structure.

[0012] In one embodiment, the material of the first mask structure includes polysilicon, and the material of the second mask structure includes photoresist.

[0013] Secondly, embodiments of this application provide a three-dimensional storage structure, including: a stacked structure; multiple channel structures penetrating the stacked structure; multiple conductive plugs, each correspondingly disposed on the channel structure; and a top select gate isolation structure extending downwards through the top of the stacked structure, dividing the stacked structure into two storage slices and separating the multiple channel structures into two groups of channel structures, such that one group of the two groups of channel structures is located in one of the two storage slices, and the other group of the two groups of channel structures is located in the other of the two storage slices, wherein the two sides of the top select gate isolation structure are equidistant from the two groups of channel structures.

[0014] The method for manufacturing a three-dimensional memory structure provided in this application employs a self-calibrating top select gate isolation (BSI) etching process to form a wavy top select gate isolation structure. This top select gate isolation structure better matches the channel structure, resulting in a closer distance between the two sets of channel structures and thus a smaller horizontal dimension for the three-dimensional memory structure. Furthermore, the method provided in this application achieves precise positioning of the top select gate isolation pattern relative to the channel holes by enlarging the holes, and the top select gate isolation pattern has a better shape. The method provided in this application effectively solves the overlay accuracy problem between the wavy top select gate isolation structure and the channel structure, and has lower requirements for the photolithography accuracy of the mask. The process cost of this method is far lower than the cost of directly photolithographically etching the wavy pattern. Attached Figure Description

[0015] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0016] Figure 1 This is a flowchart illustrating a method for manufacturing a three-dimensional storage structure according to an embodiment of this application; and

[0017] Figures 2 to 12 This is a process structure diagram according to the embodiments of this application. Detailed Implementation

[0018] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0019] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features. Therefore, without departing from the teachings of this application, the first mask structure discussed below may also be referred to as the second mask structure, and vice versa.

[0020] In the accompanying drawings, the thickness, dimensions, and shapes of the components have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. For example, the thickness of the substrate and the thickness of the stacked structure are not to scale in actual production. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0021] It should also be understood that the terms "comprising," "including," "having," "containing," and / or "comprising," when used in this specification, indicate the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to an example or illustration.

[0022] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0023] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0024] Figure 1 This is a flowchart of a method for manufacturing a three-dimensional storage structure according to an embodiment of this application. (Reference) Figure 1 The method 1000 provided in this application includes the following steps.

[0025] In step S101, a plug is formed at the top of the channel hole. There is a gap between the top of the plug and the top of the channel hole. The channel hole penetrates the stacked structure and the auxiliary layer located on the stacked structure. Specifically, according to the design position, multiple channel holes penetrate the stacked structure, and these channel holes can be divided into at least two groups.

[0026] Step S102 involves enlarging the section of the channel hole that extends above the plug. Specifically, the portion of the auxiliary layer located between any two adjacent sections in each group of channel holes is removed, meaning that the enlarged sections of two adjacent channel holes can be connected as one unit. Simultaneously, the remaining portion of the auxiliary layer between the two groups of channel holes forms the top selection gate isolation pattern.

[0027] Step S103: A first mask structure is formed in the space where the auxiliary layer material is removed.

[0028] Step S104: Remove the top select gate isolation pattern to form a top select gate isolation opening, and etch the stacked structure through the top select gate isolation opening to form a top select gate isolation cutout.

[0029] The following is in conjunction with the appendix Figures 2 to 12 The steps of the method 1000 provided in the embodiments of this application are described in detail.

[0030] refer to Figure 2 The diagram shows a schematic structural diagram of a semiconductor structure, with a simplified side view of the semiconductor structure. Specifically, prior to step S101, the following steps may be included.

[0031] An insulating layer 21 and a sacrificial layer 22 are alternately stacked on a substrate 1 to form a stacked structure 2. An auxiliary layer 3 is then formed on the stacked structure 2. Exemplarily, the auxiliary layer 3 is a composite layer, and the step of forming the auxiliary layer 3 further includes forming an auxiliary stop layer 31 and an auxiliary mask layer 32. The auxiliary stop layer 31 has etch selectivity compared to the auxiliary mask layer 32; for example, the etching process on the auxiliary mask layer 32 can be stopped at the auxiliary stop layer 31, thereby preventing etching damage to the stacked structure 2. Exemplarily, the auxiliary stop layer 31 is a silicon nitride layer, and the auxiliary mask layer 32 is a silicon oxide layer.

[0032] Then, channel holes 40A-40B are formed through the auxiliary layer 3 and the stacked structure 2. A functional layer 51 is formed on the sidewalls of the channel holes 40A-40B and on the auxiliary layer 3, followed by the formation of a first filler 52. The functional layer 51 includes a portion located in the channel holes 40A-40B and another portion located on the auxiliary layer 3, because material is deposited in the channel holes 40A-40B and some material is also deposited on the auxiliary layer 3 during the formation of the functional layer 51. Similarly, the first filler 52 includes a portion located in the channel holes 40A-40B and another portion located on the auxiliary layer 3.

[0033] In an exemplary embodiment, the method 1000 includes the step of forming two sets of channel holes 40A / 40B. The spacing between the two sets of channel holes 40A / 40B is greater than the spacing between any two adjacent channel holes 40A / 40B in each set. Exemplarily, the thickness of the auxiliary mask layer 32 is not less than the spacing between two adjacent channel holes 40A / 40B. By controlling the spacing between the two sets of channel holes 40A / 40B and the thickness of the auxiliary mask layer 32, it can be ensured that when the segments of two adjacent channel holes 40A / 40B in one set are enlarged and connected as a whole, a top selection gate isolation pattern remains between the two sets.

[0034] refer to Figure 2 The spacing between any two adjacent channel holes 40A in the first group of channel holes 40A is relatively small, and the spacing between any two adjacent channel holes 40B in the second group of channel holes 40B is also relatively small, while the spacing between the first group of channel holes 40A and the second group of channel holes 40B is relatively large.

[0035] The method 1000 provided in this application can be used to manufacture three-dimensional NAND flash memory, where each functional layer 51 is used to form a memory string. Furthermore, when designing the three-dimensional memory structure of this application, the two sets of vias 40A / 40B can belong to different memory slices.

[0036] Exemplarily, substrate 1 may include at least one of single-crystal silicon (Si), single-crystal germanium (Ge), group III-V compound semiconductor materials, group II-VI compound semiconductor materials, or other semiconductor materials known in the art. Channel vias 40A-40B may extend into substrate 1. Exemplarily, functional layer 51 in the portion corresponding to stacked structure 2 may include a barrier layer, a charge storage layer, a tunneling layer, and a channel layer (layered structure not shown) sequentially disposed from the outside to the inside.

[0037] refer to Figure 3 and Figure 4 The diagram illustrates a schematic structure of a semiconductor structure after further processing. Specifically, the following steps may be included before step S101: A portion of the first filler 52 is removed, retaining the insulating filler layer 521 corresponding to the stacked structure 2, thus forming a structure as shown in the diagram. Figure 3 The semiconductor structure shown. A second filling layer 53 is formed in the segments of the channel holes 40A-40B where material has been removed. Exemplarily, the insulating filling layer 521 is made of oxide. The second filling layer 53 is made of polysilicon.

[0038] A channel structure 5 is formed at the location corresponding to the stacked structure 2. The channel structure 5 includes a functional layer 51 and an insulating fill layer 521, and the channel structure 5 penetrates the stacked structure 2. The channel structure 5 can extend into the substrate 1. The second fill layer 53 can be considered as a structure above the channel structure 5. When forming the second fill layer 53, excess material such as polysilicon can also be deposited on the auxiliary layer 3. Exemplarily, a structure is formed as shown in the figure. Figure 4 The semiconductor structure shown.

[0039] After forming the second filling layer 53, the following can be obtained: Figure 4 The semiconductor structure shown. In some comparative examples, a planarization process can be performed subsequently, such as using chemical mechanical polishing (CMP) to remove the material on the auxiliary layer 3.

[0040] Step S101

[0041] Step S101 includes: forming a plug 53' on the upper part of the channel holes 40A~40B.

[0042] Specifically, a portion of the second filling layer 53 above the auxiliary layer 3 is removed, and a portion of the upper part of the second filling layer 53 within the channel holes 40A-40B is also removed. The portion of the second filling layer 53 remaining in the channel holes 40A-40B is a plug 53'. The tip of the plug 53' is lower than the tip of the channel hole 40A-40B in which it is located, i.e., there is a gap between the two tips. Further, the channel holes 40A-40B include hole segments 41A-41B above the plug 53'. After step S101, a structure is formed as shown... Figure 5 The semiconductor structure shown.

[0043] Step S102

[0044] Step S102 includes: enlarging the hole segments 41A-41B of the channel holes 40A-40B that are higher than the plug 53'.

[0045] For example, the functional layer 51 and the auxiliary mask layer 32 are etched by acid etching to enlarge the vias 41A-41B. During the enlargement process, the etching rate can be basically the same at each location, and the tip of the plug 53' can also be etched. When the distance between the two sets of channel vias 40A-40B is set to be large, by controlling the etching time, at least the portion of the auxiliary layer 3 located between any two adjacent vias 41A / 41B in each set of channel vias 40A / 40B can be removed, while the portion of the auxiliary layer 3 located between the two sets of channel vias 40A / 40B (or the two sets of channel structures 5A / 5B) still retains the top selection gate isolation pattern 321.

[0046] During the via enlargement process, each via segment 41A~41B is essentially ablated, meaning the removed material portion of the auxiliary layer 3 forms at least two spaces 301~302. The first space 301 corresponds to the position of the first group of channel structures 5A (i.e., the original first group of channel vias 40A), and the second space 302 corresponds to the position of the second group of channel structures 5B (i.e., the original second group of channel vias 40B). Furthermore, residual portions of the auxiliary layer 3 may remain outside of the two spaces 301~302, for example, at locations designed as gate line slot structures. The semiconductor structure after the via enlargement step is as follows: Figure 6A As shown.

[0047] refer to Figure 6A The axes of the two sets of channel structures 5A~5B are equidistant from the top selected gate isolation pattern 321 by a distance R. The center-to-center distance between two channel structures 5A / 5B within the same set of channel structures 5A / 5B at the top surface can be less than twice the value of distance R to ensure connectivity between adjacent hole segments 41A / 41B. The top selected gate isolation pattern 321 is generally wavy, with one side wall comprising multiple continuous arc segments. The concave side of the arcs faces horizontally outward, and the radius of the arcs is the distance R.

[0048] For example, such as Figure 6B As shown, the channel holes 40A / 40B in each group are densely arranged in a triangular pattern. When the hole segments 41A~41B are enlarged and the hole diameter 2R is made larger than the center distance L2 between two adjacent channel structures 5A / 5B, a gap pattern 322 can still remain within each group of channel holes 40A / 40B. Exemplarily, the subsequently formed third mask portion 61 and fourth mask portion 62 ( Figure 8 These gap patterns 322 can be covered. For example, the aperture 2R can be increased to remove the gap patterns 322, but the center distance L1 between the two sets of channel holes 40A~40B must be greater than the increased aperture 2R.

[0049] For example, the channel holes 40A~40B satisfy: .

[0050] like Figure 6B The arrangement of the channel holes 40A~40B shown can ensure the removal of the gap pattern 322, ensure the retention of the top selection gate isolation pattern 321, and ensure that the three-dimensional storage structure has a small size in the horizontal direction by controlling the center distance between the two sets of channel holes 40A~40B.

[0051] For example, the via enlargement step employs wet etching. In wet etching, all exposed surfaces of the auxiliary mask layer 32 are etched. After the surfaces of the auxiliary mask layer 32 exposed to the channel holes 40A / 40B are etched, at least the hole segments 41A~41B are enlarged; the etching of the exposed top surface makes the auxiliary mask layer 32 thinner overall. Therefore, it is necessary to control the thickness of the auxiliary mask layer 32, for example, to be greater than half of the actual spacing L3 between two adjacent hole segments 41A~41B. Furthermore, considering that the etching rate of the plug 53' may be smaller than the etching rate of the auxiliary mask layer 32, it is necessary to set the distance between the top surface of the auxiliary mask layer 32 and the plug 53' to be greater than half of the actual spacing L3 between two adjacent hole segments 41A~41B. This ensures that when two adjacent hole segments 41A~41B are connected due to via enlargement, the auxiliary mask layer 32 is not higher than the plug 53' in the thickness direction, that is, it ensures that the top selection gate isolation pattern 321 can be retained. For example, when the gap pattern 322 is etched away by the enlarged hole, the auxiliary mask layer 32 is still higher than the plug 53' in the thickness direction.

[0052] In an exemplary embodiment, the arrangement of each group of channel holes 40A / 40B can be modified according to actual needs, such as a rectangular arrangement or an arrangement with other angles. The dimensions that need to be controlled vary under different arrangement methods. Generally speaking, the actual interval between the two groups of channel holes 40A~40B is at least greater than the actual interval between two adjacent channel holes 40A / 40B in each group of channel holes 40A / 40B, and the interval between the auxiliary mask layer 32 and the plug 53' is controlled to be at least greater than half of the actual interval between two adjacent channel holes 40A / 40B, ensuring that a top selection gate isolation pattern 321 still exists between the two groups of channel holes 40A~40B when the space 301~302 is enlarged. Specifically, when etching away the portion similar to the gap pattern 322, the aforementioned dimensional relationship must ensure that the top selection gate isolation pattern 321 can be formed.

[0053] For example, when the auxiliary layer 3 includes an auxiliary stop layer 31 and an auxiliary mask layer 32, the top of the plug 53' is not lower than the top of the auxiliary stop layer 31, that is, the bottom of the hole segments 41A~41B is not lower than the top of the auxiliary stop layer 31, so that the top surface of the plug 53' is not too low after the hole is enlarged. For example, the bottom surface of the spaces 301~302 after the hole is enlarged is not lower than the auxiliary stop layer 31.

[0054] Step S103

[0055] Step S103 includes forming a first mask structure in the spaces 301-302 where the material in the auxiliary layer 3 has been removed. Specifically, the first mask structure can be formed by filling it with a first mask material, and can be formed as follows: Figure 7 The semiconductor structure shown.

[0056] Specifically, a first mask material is filled in the first space 301 to form a first mask portion 33, and a first mask material is filled in the second space 302 to form a second mask portion 34. Exemplarily, the materials of the first mask portion 33 and the second mask portion 34 may include, for example, polysilicon, a material with different etching properties than the material of the top select gate isolation pattern 321. Exemplarily, the first mask structures 33-34 may be made of the same material as the plug 53'.

[0057] The first mask structure 33-34 is attached to the sidewall of the top selection gate isolation pattern 321, and then the two mask parts 33 / 34 have the same image information as the two sidewalls of the top selection gate isolation pattern 321 after they are engaged.

[0058] Exemplarily, the method 1000 further includes the following steps: forming a second mask structure on the auxiliary layer 3, and then etching the second mask structure to form an opening 601 exposing the top selection gate isolation pattern 321, which can form as shown in the figure. Figure 8 The semiconductor structure shown.

[0059] For example, the material of the second mask structure includes photoresist. The steps of forming the second mask structure include: laying photoresist on the auxiliary layer 3, and then forming the opening 601 by exposing and developing the second mask structure made of photoresist. Due to the arrangement of the first mask portion 33 and the second mask portion 34, the positional accuracy, dimensional accuracy, and shape of the opening 601 do not need to be controlled too strictly, thereby greatly reducing the difficulty and cost of etching the photoresist.

[0060] While forming the opening 601, the remaining second mask material is also used to form the third mask portion 61 and the fourth mask portion 62. Exemplarily, the third mask portion 61 and the fourth mask portion 62 can be connected as one piece at the position where they bypass the top selection gate isolation pattern 321, thereby surrounding the top selection gate isolation pattern 321. Figure 8 The diagram may be part of a semiconductor structure. The third mask portion 61 and the fourth mask portion 62 respectively cover the remaining locations of the auxiliary layer 3 to protect the material beneath these locations.

[0061] Step S104

[0062] Remove the top selection gate isolation pattern 321 to form a top selection gate isolation opening 303. Etch the stacked structure 2 through the top selection gate isolation opening 303 to form a top selection gate isolation notch 701, which can form as follows: Figure 9 The semiconductor structure shown.

[0063] Under the protection of the first mask portion 33, the second mask portion 34, the third mask portion 61, and the fourth mask portion 62, this step yields the top selection gate isolation cutout 701. For example... Figure 9As shown, the left side of the top selection gate isolation cutout 701 extends downward from the edge of the first mask portion 33, and the right side of the top selection gate isolation cutout 701 extends downward from the edge of the second mask portion 34, effectively replicating the pattern information of the top selection gate isolation pattern 321. The wavy pattern information of the top selection gate isolation pattern 321 is actually the complexation pattern information obtained by enlarging the hole segments 41A-41B of the aforementioned channel holes 40A-40B. In other words, the top selection gate isolation cutout 701 was obtained through a self-calibration process based on the position and shape of the channel holes 40A-40B. The top selection gate isolation cutout 701 formed by the self-calibration process has higher accuracy relative to the channel structure 5A-5B, specifically, higher accuracy relative to the channel structure than the top selection gate isolation cutout formed by overlaying two sets of masks in related technologies.

[0064] The top selective gate isolation cutout 701 penetrates the auxiliary layer 3 from top to bottom and passes through the upper part of the stacked structure 2. Specifically, the top selective gate isolation cutout 701 penetrates multiple insulating layers 21 and sacrificial layers 22, and the actual number of layers penetrated can be determined according to design requirements.

[0065] In an exemplary embodiment, after obtaining the top selection gate isolation cutout 701, the method 1000 further includes: removing the second mask material. Removing the second mask structure, including the third mask portion 61 and the fourth mask portion 62, yields the following: Figure 10 The semiconductor structure shown.

[0066] Exemplarily, the method 1000 further includes the step of filling the top selected gate isolation cutout 701 with insulating material to form a top selected gate isolation structure 7. Specifically, this step can then form a structure as follows: Figure 11 The semiconductor structure is shown. After removing the third mask portion 61 and the fourth mask portion 62, the top surface of the auxiliary layer 3 can be re-exposed, and thus, while forming the top select gate isolation structure 7, the top surface of the auxiliary layer 3 can also be covered with some insulating material. Exemplarily, the insulating material includes oxide. The three-dimensional memory structure requires addressing each memory cell during use. The top select gate isolation structure is used to divide the three-dimensional memory structure into, for example, multiple memory slices arranged side-by-side. Specifically, the select gate layer is divided into electrically isolated different parts, and then the different memory slices can be controlled by the select gate layer to distinguish the channel structures located in different memory slices.

[0067] Furthermore, the method 1000 also includes: planarizing the plug 53' and the top selection gate isolation structure 7 to remove the first mask structure (first mask portion 33 and second mask portion 34) and the auxiliary layer 3. Specifically, this step can achieve the following: Figure 12 The semiconductor structure shown.

[0068] For example, the method 1000 for manufacturing a three-dimensional memory structure provided in this application can be further performed based on the semiconductor structure. Specifically, it may include the following steps to manufacture, for example, a three-dimensional NAND flash memory.

[0069] The remaining portion of plug 53' is ion implanted to form a conductive plug. Furthermore, method 1000 includes forming a gate line slot trench that extends through the stacked structure 2. The sacrificial layer 22 is then replaced with the gate layer through the gate line slot trench, and a gate line slot structure is formed within the gate line slot trench. Additionally, the top of the stacked structure can be re-planarized.

[0070] The method for manufacturing a three-dimensional memory structure provided in this application, by forming a wave-shaped top select gate isolation structure, allows the two sets of channel structures to be closer together, resulting in a smaller size of the three-dimensional memory structure in the direction of memory block arrangement. Furthermore, this method effectively solves the overlay accuracy problem between the wave-shaped top select gate isolation structure and the channel structure, and has lower processing costs. The manufactured three-dimensional memory structure has high storage density.

[0071] In another aspect, embodiments of this application also provide a three-dimensional memory structure. This three-dimensional memory structure includes: a stacked structure, at least two sets of channel structures, at least two sets of conductive plugs, and a top select gate isolation structure.

[0072] The channel structure runs through the stacked structure and is configured one-to-one with the conductive plugs. The top select gate isolation structure is located between the two sets of channel structures and extends downward through the top of the stacked structure. The top select gate isolation structure divides the stacked structure into two memory slices, with each set of channel structures located in one memory slice and controlled by the control gate layer of that memory slice.

[0073] The top select gate isolation structure provided in this application has a substantially equal distance to the channel structure. During mass production of 3D memory structures, the precision of the top select gate isolation structure can be maintained at a high level; specifically, it is more precise than the top select gate isolation structure formed by overlaying two sets of masks in related technologies. The high dimensional and positional precision of the top select gate isolation structure in this 3D memory structure allows for better control and reduction of the distance between the channel structures, resulting in a smaller horizontal dimension of the 3D memory structure. Furthermore, the higher precision of the physical structure leads to more stable electrical performance and better overall performance.

[0074] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the described technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions in this application.

Claims

1. A method for manufacturing a three-dimensional storage structure, characterized in that, include: A plug is formed at the top of each of the two sets of channel holes, with its top end spaced from the top end of the channel hole, wherein the channel hole penetrates the stacked structure and an auxiliary layer located on the stacked structure. The section of the channel hole above the plug is enlarged such that a portion of the auxiliary layer between any two adjacent sections of each group of channel holes is removed to form a filling space in the auxiliary layer, and a portion of the auxiliary layer between the two groups of channel holes remains to form a top selection gate isolation pattern. A first mask structure is formed in the filling space; and The top selected gate isolation pattern is removed to form a top selected gate isolation opening, and the stacked structure is etched through the top selected gate isolation opening to form a top selected gate isolation cutout.

2. The method according to claim 1, wherein, The procedure prior to forming the plug also includes: Two sets of channel holes are formed, wherein the interval between the two sets of channel holes is greater than the interval between any two adjacent channel holes in each set; and A channel structure is formed in the channel hole, wherein the channel structure penetrates the stacked structure.

3. The method according to claim 2, wherein, The steps for forming the plug include: A filling layer is provided in the channel hole, wherein the filling layer is located on the channel structure; and A portion of the filler layer is removed from the top of the channel hole to form the plug with its top end spaced from the top end of the channel hole.

4. The method according to claim 2, wherein, The procedure prior to the step of forming two sets of channel holes includes: Forming a stacked structure; and An auxiliary layer is formed on the stacked structure, wherein the auxiliary layer includes an auxiliary stop layer and an auxiliary mask layer stacked in a direction away from the stacked structure, and wherein the top of the plug is higher than the auxiliary stop layer.

5. The method according to claim 1, wherein, Also includes: The top selective gate isolation cut is filled with insulating material to form a top selective gate isolation structure; The plug, the top selection gate isolation structure, and the stacked structure are planarized to at least remove the first mask structure and the auxiliary layer.

6. The method according to claim 5, wherein, The plug is made of polycrystalline silicon.

7. The method according to claim 5, wherein, The stacked structure includes alternating stacked insulating layers and sacrificial layers; After flattening the plug, the method further includes: Forming grid line slots that penetrate the stacked structure; The sacrificial layer is replaced with the gate layer through the gate line slot; A grid wire slot structure is formed in the grid wire slot groove; and Flatten the top of the stacked structure.

8. The method according to claim 1, wherein, After the step of forming the first mask structure and before the step of removing the top selection gate isolation pattern, the method further includes: A second mask structure is formed on the auxiliary layer; The second mask structure is etched to form an opening that exposes the top selection gate isolation pattern; and After the steps of removing the top selected gate isolation pattern to form a top selected gate isolation opening, and etching the stacked structure through the top selected gate isolation opening to form a top selected gate isolation notch, the method further includes: Remove the second mask structure.

9. The method according to claim 8, wherein, The material of the first mask structure includes polycrystalline silicon, and the material of the second mask structure includes photoresist.

10. A three-dimensional storage structure, characterized in that, include: Stacked structure; Multiple channel structures, the channel structures extending through the stacked structure; Multiple conductive plugs are disposed on the channel structure in a corresponding manner; as well as The top selected gate isolation structure has a wave-like shape, extending downwards through the top of the stacked structure, dividing the stacked structure into two storage slices and separating the plurality of channel structures into two groups of channel structures, such that one group of the two groups of channel structures is located in one of the two storage slices, and the other group of the two groups of channel structures is located in the other of the two storage slices. The sidewall contours of the top selected gate isolation structure are respectively formed by the arc segments corresponding to the center lines connecting adjacent channel structures in the two groups of channel structures, and the distances between the two sides of the top selected gate isolation structure and the two groups of channel structures are equal.

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