A hardware implementation method and hardware system of batch processing FIR algorithm

Abstract

The application discloses a hardware implementation and a hardware system of batch processing FIR algorithm and belongs to the field of FIR algorithm and hardware implementation technology in digital signal processing. In view of the problems of insufficient performance of the FIR accelerator containing batch processing and low efficiency of digital signal processing in the prior art, the system comprises a control module, a source data address generation module, a coefficient address generation module, a result address generation module, a storage unit, a data carrying module and a calculation module, and the calculation module performs multiplication and accumulation operation in the FIR algorithm. The hardware system of the application adds the batch processing function, reduces the clock cycle consumption of configuration information and starting data carrying, improves the performance of the FIR accelerator and optimizes the hardware design of digital signal processing.

Description

Technical Field

[0001] This invention relates to the field of FIR algorithms and their hardware implementation in digital signal processing, and more specifically, to a hardware implementation method and hardware system for a batch processing FIR algorithm. Background Technology

[0002] Digital signal processing (DSP) technology is widely used in speech signal processing, radar imaging, aerospace, and other fields. It uses algorithms to extract feature parameters from signals and compares and matches them with known features. DSP technology plays a crucial role in modern engineering.

[0003] A Finite Impulse Response (FIR) filter is a filter whose impulse response has a line length; the pulse input signal becomes zero within a finite time. Batch processing is an important concept in modern hardware acceleration technology. From parallel computing to Single Instruction Multiple Data (SIMD), simultaneously processing multiple batches of common data can greatly reduce the control and data communication overhead in hardware, improving computational efficiency.

[0004] However, existing FIR accelerator designs often prioritize parallelism and pipelined computation in single-process calculations, neglecting the issue of low on-chip memory utilization for multiple batches of small-scale data. Furthermore, in multi-batch data processing scenarios, frequent calls to accelerator configuration instructions by the processor consume significant cycles in control logic, reducing the efficiency of digital signal processing.

[0005] Chinese patent application CN200980139643.1, published on May 7, 2014, discloses a hardware accelerator capable of operating in both FFT and FIR modes. The hardware accelerator receives input data and coefficient data and performs computations for the selected mode. In FFT mode, it computes a radix-2 FFT, producing four real-number outputs corresponding to two complex numbers. In FIR mode, it produces one real-number output. The hardware accelerator can use three multiplexers to convert between FFT and FIR modes. All FIR components can be used in FFT mode. Registers can be added to provide pipelined operation support. The hardware accelerator can support multiple numerical representation systems. While this method focuses on accelerating FIR algorithms, it still cannot achieve very high performance for applications involving batch processing. Summary of the Invention

[0006] 1. Technical problems to be solved

[0007] To address the issues of insufficient performance of existing FIR accelerators with batch processing capabilities and low efficiency in digital signal processing, this invention provides a hardware implementation method and system for a batch processing FIR algorithm. Considering the requirements of digital signal processing scenarios, area power consumption, and system computing speed, this invention proposes a hardware implementation method for an FIR algorithm with batch processing capabilities and a corresponding hardware system, thereby improving FIR accelerator performance and optimizing digital signal processing hardware design.

[0008] 2. Technical Solution

[0009] The objective of this invention is achieved through the following technical solutions.

[0010] A hardware implementation of a batch processing FIR algorithm includes a control module, a source data address generation module, a coefficient address generation module, a result address generation module, a calculation module, a storage unit, and a data transport module. The control module is connected to the source data address generation module, the coefficient address generation module, the result address generation module, the calculation module, and the data transport module. The source data address generation module and the coefficient address generation module are both connected to the calculation module, and the calculation module is also connected to the result address generation module. The source data address generation module, the coefficient address generation module, and the result address generation module are all connected to the storage unit, and the data transport module is also connected to the storage unit. The calculation module includes an m-way multiply-accumulate unit, where m is a positive integer.

[0011] Furthermore, the storage unit includes a source data area, a coefficient area, and a result area, with each storage unit comprising 4*m+1 memory modules. The source data area includes 2*m memory modules, the coefficient area includes 1 memory module, and the result area includes 2*m memory modules. Taking a scale of m=16 as an example, the storage unit includes 65 SRAMs, where SRAM0-31 is the source data area, SRAM32 is the coefficient area, and SRAM33-64 are the result areas. The data transfer module is used to perform data transfer between the DDR and SRAM.

[0012] Furthermore, the source data address generation module includes m vector channels, the coefficient address generation module includes one coefficient channel, and the result address generation module includes m result data channels. Both the vector channels and coefficient channels are connected to the input terminals of the calculation module, and the output terminals of the calculation module are connected to the result data channels. Taking m=16 as an example, the source data address generation module includes 16 vector channels, the result address generation module includes 16 result data channels, the 16 vector channels are connected to the 16 first input interfaces of the calculation module, the coefficient channels are simultaneously connected to the 16 second input interfaces of the calculation module, and the 16 output interfaces of the calculation module are connected to the 16 result data channels.

[0013] Furthermore, the multiply-accumulate unit includes a multiplier and an adder. The output of the multiplier is connected to the input of the first adder, the output of the first adder is connected to the input of the second adder, and the output of the second adder is connected to the input of the third adder. The outputs of the first, second, and third adders are all connected to their own inputs. There is a one-beat delay between the input and output of the multiplier and the adder.

[0014] Furthermore, the control module configuration is parsed into the number of batch processing records for each of the m channels. The control module is used to parse the external configuration, control each computing module and storage unit, and process the data for each of the m channels, thereby realizing multi-batch data processing.

[0015] A hardware implementation method for a batch processing FIR algorithm includes the following steps:

[0016] Set the parameters of the FIR algorithm, including the sequence length of a single batch, the length of the filter coefficients, and the number of batches processed. Organize the FIR accelerator hardware according to the set parameters.

[0017] Store the source data according to the data sequence and batch number to be processed;

[0018] Once the source data is stored, the calculation is performed. After all the result data has been processed, the result data is stored in the result area SRAM.

[0019] Furthermore, the source data is not padded with zeros during storage; this padding is performed during computation. Padding during computation saves storage space for the source data and improves storage efficiency.

[0020] Furthermore, when storing source data, the vector [m*n+0] of the source data is stored in the first memory of the storage unit, the vector [m*n+1] of the source data is stored in the second memory of the storage unit, and so on, for a total of m storage channels. These channels store the source data of each batch in turn, where n is a positive integer. The source data is stored according to the number of channels, supporting batch processing calculations of the system.

[0021] Furthermore, when the calculation module calculates the filtering results for multiple batches of sequences, all sequences in the batch share the same filtering coefficients and length.

[0022] Furthermore, the storage unit uses a left-right ping-pong method to store the source data and calculation results, and a deep ping-pong method to store the coefficients. The source data stored here is the filter vector, and the stored coefficients are the filter coefficients.

[0023] 3. Beneficial effects

[0024] Compared with the prior art, the advantages of this invention are:

[0025] This invention provides a hardware implementation of a batch processing FIR algorithm that adds batch processing functionality to the traditional FIR algorithm hardware structure. Based on multi-batch parallel computation of multiple data streams, zero padding is performed in the address generation module, reducing access to source data storage space and memory, thus improving data storage efficiency.

[0026] This invention enables the computation of multiple batches of data in a single startup, reducing clock cycle consumption during configuration information and startup data transfer, and improving the hardware execution performance of the FIR algorithm. By sharing filter weights across multiple batches of data, FIR computation can also achieve excellent performance in scenarios with a small number of data points. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the hardware system of the present invention;

[0028] Figure 2 This is a schematic diagram of the calculation process of the FIR algorithm of this invention;

[0029] Figure 3 This is a schematic diagram of the data storage distribution of the storage unit in this invention;

[0030] Figure 4 This is a schematic diagram of the multiply-accumulate unit of the calculation module of the present invention;

[0031] Figure 5 This is a schematic diagram of the ping-pong execution of the storage unit of the present invention;

[0032] Figure 6 This is a simulation diagram of the zero-padding waveform of the source data address generation module of the present invention. Detailed Implementation

[0033] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0034] Example 1

[0035] The FIR filter is an important digital signal processing method. To better understand this embodiment, the FIR filter will be explained first.

[0036] For an N-point, M-order FIR filter, the N-point vector representation is:

[0037] X=[x(0) x(1) x(2) … x(N-2) x(N-1)],

[0038] The M-order filtering system is represented as:

[0039] H=[h(0) h(1) h(2) ... h(M-2) h(M-1)],

[0040] The formula for calculating an N-point M-order FIR filter is:

[0041]

[0042] The above formula requires M+N-1 operations to obtain M+N-1 results, where each operation includes the multiplication and summation of two M-point vectors.

[0043] like Figure 2 As shown, the commonly used method for calculating FIR is the window method. Figure 2 As shown, when the filter coefficient window exceeds the range of the filter vector, N-1 zeros need to be padded before and after the filter vector. In existing filter designs, the source data memory not only needs to store the filter vector of length M, but also needs to store an additional 2*(N-1) zeros. During batch processing, assuming the batch size is B, an additional 2*B*(N-1) zeros need to be stored, consuming a large amount of unused space. This also prolongs the time spent writing the filter vector to the storage unit during data transfer.

[0044] This embodiment discloses a hardware system for an FIR algorithm, such as... Figure 1 As shown in the diagram, the system includes a control module, a source data address generation module, a coefficient address generation module, a result address generation module, a calculation module, a storage unit, and a data transport module. The control module is connected to the source data address generation module, the coefficient address generation module, the result address generation module, the calculation module, and the data transport module. The source data address generation module and the coefficient address generation module are both connected to the calculation module, and the calculation module is also connected to the result address generation module. The source data address generation module, the coefficient address generation module, and the result address generation module are all connected to the storage unit, and the data transport module is connected to the storage unit.

[0045] The computation module supports batch processing of m parallel data streams, where m is an integer greater than 0; this embodiment uses m = 16 for specific description. The computation module includes 16 multiply-accumulate units, each with a single-precision floating-point data type. The structure of the multiply-accumulate unit is as follows: Figure 4 As shown, it includes a multiplier and an adder. The output of the multiplier is connected to the input of the first adder, the output of the first adder is connected to the input of the second adder, and the output of the second adder is connected to the input of the third adder. The outputs of the first, second, and third adders are all connected to their own inputs. There is a one-beat delay between the input and output of the multiplier and the adder.

[0046] Compared to a design with one multiplier and two adders, the multiply-accumulator of this invention adds an additional adder. A multiply-accumulator with one multiplier and two adders supports an accumulation length greater than 8, while a multiply-accumulator with one multiplier and three adders reduces the number of registers used for timing delays and supports accumulation lengths from 1 to 7. The smaller accumulation length allows the entire FIR accelerator to support a smaller number of points, better demonstrating the performance advantage of the FIR accelerator in small-point batch processing scenarios.

[0047] The storage unit includes a source data area, a coefficient area, and a result area. The source data area stores the filter vector, the coefficient area stores the filter coefficients, and the result area stores the filter result. In this embodiment, the storage unit includes 65 SRAMs, each SRAM being 64 bits wide and 2k deep.

[0048] The storage unit uses a left-right ping-pong method to store the source data (filter vector) and the filtering result, and a deep ping-pong method to store the coefficients (filter coefficients). Left-right ping-pong means that source data of the same type is stored in two SRAMs partitioned together. One SRAM executes the calculation process of the first instruction, reading data; simultaneously, the other SRAM executes the data transfer process for the next instruction, writing data. Deep ping-pong means that source data of the same type is stored in different address segments of a single SRAM partitioned together. When executing the calculation process of the first instruction, data is read from the first half (or the second half) of the address segment. Simultaneously, data is written to the second half (or the first half) of the address segment when executing the data transfer process for the next instruction.

[0049] like Figure 5 As shown, the hardware SRAM0-31 of the storage unit is the source data area, SRAM32 is the coefficient area, and SRAM33-64 is the result area. SRAM0-15, addresses 0-1023 of SRAM32, and SRAM33-48 are the ping-pong areas, while SRAM16-31, addresses 1024-2047 of SRAM32, and SRAM49-64 are the pong-pong areas. When performing operations in the ping-pong area, if an external instruction is configured, the data transfer module moves the source data required for the next instruction from DDR to the pong-pong area.

[0050] The source data address generation module includes 16 vector channels, and the coefficient generation module includes 1 coefficient channel. The 16 vector channels of the source data address generation module are connected to the 16 first input interfaces of the calculation module; the coefficient channel of the coefficient generation module is also connected to the 16 second input interfaces of the calculation module; the result address generation module includes 16 result data channels, and these 16 result data channels are connected to the 16 output interfaces of the calculation module. Figure 6The simulation waveform diagram in the EDA tool shows that when the source data address generation module generates the address index and supplies data to the calculation module, it pads the data with zeros where the index is exceeded. Since the FIR filter uses fixed-length multiplication and accumulation for operation, zero padding is necessary at the beginning and end. The address generation module compares the generated address signal with the start and end addresses of the current data. If the address signal is out of range, the zero enable signal in the address generation module is pulled high, and after the same delay as the storage unit, the data zero is output to the calculation module.

[0051] The control module configuration is parsed as the number of batch processing entries for each of the 16 channels.

[0052] The hardware system of the batch processing FIR algorithm described in this example can be implemented in the form of an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). In other words, the hardware design described in this embodiment can be implemented using an FPGA or an ASIC chip.

[0053] Based on the above-described hardware system for a batch processing FIR algorithm, this embodiment discloses a hardware implementation method for a batch processing FIR algorithm, including the following steps:

[0054] Step S1: Set the parameters of the batch FIR algorithm and organize the FIR accelerator hardware.

[0055] The parameters of the batch FIR algorithm include the length of a single batch (fir_num), the length of the filter coefficients (fir_order), and the number of batches (batch_num). Assuming the SRAM depth is d, the parameters of the batch FIR algorithm have the following constraints:

[0056] 1. (fir_num+fir_order-1)*ceil(batch_num / 16) <d;

[0057] 2.0 <fir_order<d / 2;

[0058] 3. fir_num>4.

[0059] In this embodiment, the sequence length of a single batch is set to 16, and the number of batches is also 16. That is, the filter supports 16 parallel calculations of 16 batches of data when it is working. The execution process is based on sliding window multiply-accumulate operations. The sequence length and coefficient length of each batch of data are equal after zero padding, and a multiply-accumulate unit can be used to implement multiply-accumulate operations of a fixed order.

[0060] Step S2: Store the source data according to the data sequence and batch number to be processed.

[0061] When storing source data, vector [16n+0] is stored in SRAM0, vector [16n+1] is stored in SRAM1, and so on, for a total of 16 SRAM storage channels, which store each batch of data in turn. Zero padding of the source data does not need to be pre-written into the storage unit; the zero padding process is performed during the computation. When performing address indexing, the filter will determine the range of the current index and the source data. When the index exceeds the range of the source data stored in the storage unit, it will output zero elements to the computation module, saving storage space for the source data.

[0062] This storage method stores all batches of source data in the source data SRAM at a time, supporting 16-way multiply-accumulate processors to process data in parallel.

[0063] Step S3: After the source data is stored, perform the calculation; until all the result data has been calculated, store the result data in the result area SRAM, and the calculation is complete.

[0064] This embodiment of the batch processing FIR filter can compute multiple batches of source data at once. The multiple batches of source data are divided into 16 groups and stored in turn in 16 memory locations. When source data is moved from DDR to the memory locations via the data transfer unit, the source data is arranged in the memory locations according to... Figure 3 The distribution is performed. Similarly, after the calculation is completed, when the result data is moved from the storage unit to DDR through the data transfer unit, the result data is also distributed in the storage unit. Figure 3 The distribution is done in a certain way.

[0065] When calculating the filtering results for multiple batches of sequences, all sequences in the batch share the same filtering coefficients and length.

[0066] Following the above method, this arrangement method and zero-padding technique are applicable to the design of FIR filters with various parallel paths.

[0067] The simulation experiment compared the number of operation cycles for multiple data points by a single-batch FIR filter and a batch FIR filter with the same number of parallel paths. The results are shown in Table 1.

[0068] Table 1

[0069] design Vector length Coefficient length Batch number Number of cycles Single-batch FIR filters 29 4 4096 122880 Batch processing FIR filters 29 4 4096 32805

[0070] Table 1 discloses the performance advantages of the batch processing FIR filter in 128 batches. By eliminating significant configuration and startup time, the batch processing FIR filter substantially reduces the number of computation cycles, thus improving the performance of the FIR accelerator. This invention solves the problems of low data storage efficiency after zero-padding in traditional FIR accelerators for small data batches, as well as the frequent startup issues during data transfer, thereby improving the hardware execution performance of the FIR algorithm.

[0071] As described above, although the invention has been shown and described with reference to specific preferred embodiments, it should not be construed as limiting the invention itself. Various changes in form and detail may be made without departing from the spirit and scope of the invention as defined in the appended claims. Therefore, if a person skilled in the art, inspired by this description, designs a similar structure and embodiment without departing from the spirit of the invention, such design should fall within the scope of this patent. Furthermore, the word "comprising" does not exclude other elements or steps, and the word "a" preceding an element does not exclude the inclusion of "a plurality" of that element. Multiple elements stated in the product claims may also be implemented by a single element through software or hardware. The terms "first," "second," etc., are used to indicate names and do not indicate any specific order.

Claims

1. A hardware system for batch processing FIR algorithms, characterized in that, It includes a control module, a source data address generation module, a coefficient address generation module, a result address generation module, a calculation module, a storage unit, and a data transport module. The control module is connected to the source data address generation module, the coefficient address generation module, the result address generation module, the calculation module, and the data transport module. The source data address generation module and the coefficient address generation module are both connected to the calculation module. The calculation module is also connected to the result address generation module. The source data address generation module, the coefficient address generation module, and the result address generation module are all connected to the storage unit. The data transport module is also connected to the storage unit. The calculation module includes an m-way multiply-accumulate unit, where m is a positive integer. The storage unit includes a source data area, a coefficient area, and a result area. The storage unit includes 4*m+1 memory units; the source data area includes 2*m memory units, the coefficient area includes 1 memory unit, and the result area includes 2*m memory units. The multiply-accumulate unit includes a multiplier and an adder. The output of the multiplier is connected to the input of the first adder, the output of the first adder is connected to the input of the second adder, and the output of the second adder is connected to the input of the third adder. The outputs of the first, second, and third adders are all connected to their own inputs. There is a one-beat delay between the input and output of the multiplier and the adder. The source data is not padded with zeros during storage; the zero-padding operation is performed during the calculation process. When the calculation module calculates the filtering results for multiple batches of sequences, all sequences in the batch share the same filtering coefficients and length.

2. The hardware system for a batch processing FIR algorithm according to claim 1, characterized in that, The source data address generation module includes m vector channels, the coefficient address generation module includes 1 coefficient channel, and the result address generation module includes m result data channels; both the vector channels and the coefficient channels are connected to the input end of the calculation module, and the output end of the calculation module is connected to the result data channels.

3. The hardware system for a batch processing FIR algorithm according to claim 1, characterized in that, The control module configuration is parsed into the number of batch processing entries for each of the m channels.

4. A hardware system implementation method based on the batch processing FIR algorithm according to any one of claims 1-3, characterized in that, Includes the following steps: Set the parameters of the FIR algorithm, including the sequence length of a single batch, the length of the filter coefficients, and the number of batches processed. Organize the FIR accelerator hardware according to the set parameters. Store the source data according to the data sequence and batch number to be processed; Once the source data is stored, the calculation is performed. After all the result data has been processed, the result data is stored in the result area SRAM.

5. The hardware implementation method of the batch processing FIR algorithm according to claim 4, characterized in that, When storing source data, the vector [m*n+0] of the source data is stored in the first memory of the storage unit, the vector [m*n+1] of the source data is stored in the second memory of the storage unit, and so on. There are a total of m storage channels, which store each batch of source data in turn, where n is an integer greater than zero.

6. The hardware implementation method of the batch processing FIR algorithm according to claim 5, characterized in that, The storage unit uses a left-right ping-pong method to store source data and calculation results, and uses a deep ping-pong method to store coefficients.

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