An output buffer and source driver

Abstract

The present application discloses an output buffer and a source driver. The output buffer includes a pre-driver circuit, an output stage circuit, a first gate drive enhancement circuit, and a second gate drive enhancement circuit. The pre-driver circuit includes a first OR gate and a first AND gate. The output stage circuit includes a first P-type transistor and a first N-type transistor. The gate VPG of the first P-type transistor is connected to the output of the first OR gate via the first gate drive enhancement circuit. The first gate drive enhancement circuit is used to increase an overdrive voltage to the gate VPG of the first P-type transistor to enhance the driving capability of the first P-type transistor. The gate VNG of the first N-type transistor is connected to the output of the first AND gate via the second gate drive enhancement circuit. The second gate drive enhancement circuit is used to increase an overdrive voltage to the gate VNG of the first N-type transistor to enhance the driving capability of the first N-type transistor. The above solution can enhance the driving capability of the output stage.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to an output buffer and a source driver. Background Art

[0002] The output buffer generally includes a first P-type transistor and a first N-type transistor. When working, the first P-type transistor and the first N-type transistor are used to charge and discharge the capacitive load Cload of the output stage. At this time, the first P-type transistor and the first N-type transistor are equivalent to the first resistor and the second resistor, respectively. If the first resistor and the second resistor are large, the flipping process of charging and discharging Cload will be relatively slow, and even insufficient to flip to the highest potential and the lowest potential at the normal operating frequency. The first resistor and the second resistor represent the driving capability of the output buffer; when the output driving capability is insufficient, the output buffer cannot support the chip to operate at the rated operating frequency. At this time, either the output driving capability is enhanced or the external capacitive load Cload is reduced.

[0003] However, Cload is often determined by the external working environment and cannot be adjusted in many cases. The only solution is to enhance the output drive capability. The drive capability is related to the size of the first P-type transistor and the first N-type transistor and the operating voltage. For example, the larger the size of the first P-type transistor and the first N-type transistor, the smaller the equivalent output resistance and the greater the drive capability; however, increasing the size of the first P-type transistor and the first N-type transistor will increase the on-chip parasitic capacitance of the output stage. If the size of the first P-type transistor and the first N-type transistor is simply increased, the area of the output stage will be very large, increasing the chip cost. At the same time, the increased on-chip parasitic capacitance will also lead to an increase in the load capacitance, compromising the actual effect of the increase in the output stage size. For another example, the higher the operating voltage, the greater the overdrive voltage of the first P-type transistor and the first N-type transistor, the smaller the equivalent output resistance, and the greater the driving capability; however, the operating voltage of the output stage is determined by the chip application. In some applications, in order to reduce power consumption, the chip is even required to maintain high driving capability at an extremely low operating voltage to drive an external large capacitive load; for example, after a certain process is selected, the devices used in the output stage are often fixed. For example, a 5V device is selected, but the application circuit requires the output stage to operate at a voltage of 3.3V or even 1.8V. The threshold voltage Vth of the device is fixed. Low voltage will cause insufficient overdrive voltage on the gate of the output stage device, resulting in very weak driving capability. Even increasing the size of the output stage cannot meet the application requirements. Summary of the Invention

[0004] The main technical problem solved by the present application is to provide an output buffer and a source driver, which can enhance the driving capability of the output stage.

[0005] In order to solve the above problems, the present application provides an output buffer, which includes a pre-drive circuit, an output stage circuit, a first gate drive enhancement circuit and a second gate drive enhancement circuit; the pre-drive circuit includes a first OR gate and a first AND gate; the output stage circuit includes a first P-type transistor and a first N-type transistor; the gate VPG of the first P-type transistor is connected to the output end of the first OR gate through the first gate drive enhancement circuit, and the first gate drive enhancement circuit is used to increase the overdrive voltage to the gate VPG of the first P-type transistor to enhance the driving capability of the first P-type transistor; the gate VNG of the first N-type transistor is connected to the output end of the first AND gate through the second gate drive enhancement circuit, and the second gate drive enhancement circuit is used to increase the overdrive voltage to the gate VNG of the first N-type transistor to enhance the driving capability of the first N-type transistor.

[0006] The present invention has the following beneficial effects: Unlike the prior art, the output buffer of the present application includes a pre-driver circuit and an output stage circuit; the pre-driver circuit includes a first OR gate and a first AND gate; the output stage circuit includes a first P-type transistor and a first N-type transistor; the gate VPG of the first P-type transistor is connected to the output end of the first OR gate via a first gate drive enhancement circuit, the first gate drive enhancement circuit being used to increase an overdrive voltage to the gate VPG of the first P-type transistor to enhance the driving capability of the first P-type transistor; the gate VNG of the first N-type transistor is connected to the output end of the first AND gate via a second gate drive enhancement circuit, the second gate drive enhancement circuit being used to increase an overdrive voltage to the gate VNG of the first N-type transistor to enhance the driving capability of the first N-type transistor. By providing an overdrive voltage to the gate VPG of the first P-type transistor via the first gate drive enhancement circuit and increasing the overdrive voltage to the gate VNG of the first N-type transistor via the second gate drive enhancement circuit, the overdrive voltage of the output stage can be enhanced, thereby enhancing the driving capability of the output stage without increasing the size of the first P-type transistor and the first N-type transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic structural diagram of the first embodiment of the output buffer of the present application;

[0008] Figure 2a yes Figure 1 An equivalent principle diagram of the output stage circuit 12 in the output buffer;

[0009] Figure 2b It is a schematic diagram of the relationship between the output driving capability and output waveform of the output buffer;

[0010] Figure 31 is a structural diagram of an embodiment of the first gate drive enhancement circuit 14 in the output buffer of the present application;

[0011] Figure 4 1 is a structural diagram of an embodiment of the second gate drive enhancement circuit 16 in the output buffer of the present application;

[0012] Figure 5 yes Figure 3 A schematic diagram of the working principle of the first gate drive enhancement circuit 14;

[0013] Figure 6 is a structural diagram of the second embodiment of the output buffer of the present application;

[0014] Figure 7 is a schematic structural diagram of a third embodiment of the output buffer of the present application;

[0015] Figure 8 1 is a structural diagram of another embodiment of the first gate drive enhancement circuit 14 in the output buffer of the present application;

[0016] Figure 9 yes Figure 8 A structural diagram of an embodiment of a tri-state inverter in FIG.

[0017] Figure 10 1 is a structural diagram of another embodiment of the second gate drive enhancement circuit 16 in the output buffer of the present application;

[0018] Figure 11 It is a structural diagram of the fourth embodiment of the output buffer of the present application. DETAILED DESCRIPTION

[0019] The following describes the embodiments of the present application in detail with reference to the accompanying drawings.

[0020] In the following description, for the purpose of explanation rather than limitation, specific details such as specific system structures, interfaces, and technologies are provided to facilitate a thorough understanding of the present application.

[0021] The terms "system" and "network" are often used interchangeably in this document. The term "and / or" is simply a description of an association between related objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " generally indicates that the related objects are in an "or" relationship. Furthermore, "multiple" in this document means two or more than two.

[0022] See also Figure 1 , Figure 11 is a schematic diagram of the structure of the first embodiment of the output buffer of the present application. The output buffer of this embodiment includes a pre-driver circuit 10 and an output stage circuit 12; the pre-driver circuit 10 includes a first OR gate 100 and a first AND gate 102; the first OR gate 100 receives the output enable signal OE through the first inverter 104, receives the output signal DATA through the second inverter 106, and outputs the logic control signal VP; the first AND gate 102 receives the output enable signal OE, receives the output signal DATA through the second inverter 106, and outputs the logic control signal VN; the output stage circuit 12 includes a first P-type transistor 120 and a first N-type transistor 122, the source of the first P-type transistor 120 is connected to the VDDIO interface, the source of the first N-type transistor 122 is connected to the VSSIO interface, and the drain of the first P-type transistor 120 and the drain of the first N-type transistor 122 are connected. The electrodes are respectively connected to one end of the output stage load capacitor 124, and the other end of the output stage load capacitor 124 is grounded; the output buffer also includes a first gate drive enhancement circuit 14 and a second gate drive enhancement circuit 16; the gate VPG of the first P-type transistor 120 is connected to the output end of the first OR gate 100 through the first gate drive enhancement circuit 14, and the first gate drive enhancement circuit 14 is used to increase the overdrive voltage to the gate VPG of the first P-type transistor 120 to enhance the driving capability of the first P-type transistor 120; the gate VNG of the first N-type transistor 122 is connected to the output end of the first AND gate 102 through the second gate drive enhancement circuit 16, and the second gate drive enhancement circuit 16 is used to increase the overdrive voltage to the gate VNG of the first N-type transistor 122 to enhance the driving capability of the first N-type transistor 122.

[0023] It is understood that the output signal DATA is data that needs to be output outside the chip, and the output enable signal OE can control the output to a high-impedance state. The first P-type transistor 120 and the first N-type transistor 122 form a push-pull output buffer, wherein the gate VPG of the first P-type transistor 120 is controlled by a first OR gate 100, and the gate VNG of the first N-type transistor 122 is controlled by a first AND gate 102. The output stage load capacitor 124 can be composed of on-chip parasitic capacitance, package parasitic capacitance, PCB trace parasitic capacitance, input capacitance of the interactive chip, etc. During operation, the first P-type transistor 120 and the first N-type transistor 122 can charge or discharge the output stage load capacitor 124, thereby causing the output signal DATA to flip from 0 to 1 or from 1 to 0 after passing through the output buffer. In this application, 0 represents a low level and 1 represents a high level, and 0 is the potential of the VSSIO interface and 1 is the potential of the VDDIO interface.

[0024] Please combine Figure 2a and Figure 2b ,in, Figure 2a yes Figure 1 The equivalent principle diagram of the output stage circuit 12 in the output buffer is shown in FIG. Figure 2b It is a diagram showing the relationship between the output drive capability and the output waveform of the output buffer. When the output stage load capacitor 124 is charged and discharged, as shown in FIG. Figure 2a As shown, the first P-type transistor 120 can be equivalent to a first resistor 1200, and the first N-type transistor 122 can be equivalent to a second resistor 1220, and the charging and discharging time thereof is determined by the time constant of RC formed by the first resistor 1200, the second resistor 1220 and the output stage load capacitor 124. If the equivalent resistance of the first P-type transistor 120 and the first N-type transistor 122 is large, the signal flipping process will be relatively slow, so the first resistor 1200 and the second resistor 1220 represent the driving capability of the output buffer; it can be understood that the values of the first resistor 1200 and the second resistor 1220 may be equal or unequal, and the specific values of the first resistor 1200 and the second resistor 1220 need to be set corresponding to different designs. Figure 2b The output waveforms of the output buffer with different output drive capabilities are shown. In the ideal output waveform at the top, the resistance values of the first resistor 1200 and the second resistor 1220 are both 0. In this case, the output drive capability is infinite, but this is impossible to achieve in reality. Actual output waveforms 1 to 4 respectively represent the changing trends of the output waveform as the output drive capability gradually decreases from strong to weak. In actual output waveform 1, the output drive capability has little effect on the output waveform, and the signal flips normally. In actual output waveform 2, the rise and fall times of the output waveform have been significantly lengthened. In actual output waveform 3, the output waveform can only flip to the highest potential VDDIO and the lowest potential VSSIO. In actual output waveform 4, the output waveform deteriorates further. At the normal operating frequency, the signal is no longer able to flip to the highest potential VDDIO and the lowest potential VSSIO, and the output drive capability is clearly insufficient to support normal operation.

[0025] Therefore, in order to solve the problem of insufficient output drive capability of the output buffer at a standard operating voltage or even an extremely low operating voltage, the present application adds a first gate drive enhancement circuit 14 between the gate VPG of the first P-type transistor 120 and the output terminal of the first OR gate 100, and adds a second gate drive enhancement circuit 16 between the gate VNG of the first N-type transistor 122 and the output terminal of the first AND gate 102. The first gate drive enhancement circuit 14 is used to increase the overdrive voltage to the gate VPG of the first P-type transistor 120. The first gate drive enhancement circuit 14 provides the overdrive voltage to the gate VPG of the first P-type transistor 120, and the second gate drive enhancement circuit 16 increases the overdrive voltage to the gate VNG of the first N-type transistor 122, thereby enhancing the overdrive voltage of the output stage. Therefore, without increasing the size of the first P-type transistor 120 and the first N-type transistor 122, the drive capability of the output stage is enhanced at an operating voltage of 1 / 2 or even 1 / 4 of the standard operating voltage of the devices used, so that the output buffer achieves high drive capability and can drive large capacitive loads.

[0026] Please combine Figure 3 , Figure 31 is a schematic diagram of the structure of an embodiment of the first gate drive enhancement circuit 14 in the output buffer of the present application. In this embodiment, the first gate drive enhancement circuit 14 includes a third inverter 140, a fourth inverter 141, a second P-type transistor 142, a third P-type transistor 143, a second N-type transistor 144, a third N-type transistor 145, a fourth N-type transistor 146 and a first boost capacitor 147; the third inverter 140, the fourth inverter 141 and the first boost capacitor 147 are connected in series in sequence, and the input end of the third inverter 140 is connected to the output end of the first OR gate 100; the source of the second P-type transistor 142 is connected to the VDDIO interface, the drain of the second P-type transistor 142 is connected to the drain of the second N-type transistor 144, and the gate of the second P-type transistor 142 and the gate of the second N-type transistor 144 are respectively connected to the output end of the third inverter 140; the third P-type transistor 143, the fourth N-type transistor 146 and the third N-type transistor 145 are connected in series in sequence, the source of the third P-type transistor 143 is connected to the VDDIO interface, the drain of the third P-type transistor 143 and the drain of the fourth N-type transistor 146 are respectively connected to the gate VPG of the first P-type transistor 120, the source of the fourth N-type transistor 146 is connected to the drain of the third N-type transistor 145, the source of the third N-type transistor 145 is connected to the VSSIO interface, the gate of the third N-type transistor 145 is connected to the drain of the second P-type transistor 142, the gate of the third P-type transistor 143 and the gate of the fourth N-type transistor 146 are respectively connected to the output end of the third inverter 140, and the source of the second N-type transistor 144 and the end of the first boost capacitor 147 away from the fourth inverter 141 are respectively connected to the drain of the third N-type transistor 145.

[0027] It can be understood that when the logic control signal VP output by the first OR gate 100 is 1, the output is 0 after passing through the third inverter 140, so that the second P-type transistor 142 and the third P-type transistor 143 are in the on state, while the second N-type transistor 144 and the fourth N-type transistor 146 are turned off; thus, the second P-type transistor 142 can pull the gate of the third N-type transistor 145 to a high potential, so that the third N-type transistor 145 is in the on state, and at the same time, the third P-type transistor 143 turns the output stage circuit 12 The gate VPG of the first P-type transistor 120 is pulled to a high potential, turning off the first P-type transistor 120. At the same time, the signal is output as 1 after passing through the fourth inverter 141. Since the third N-type transistor 145 is in the on state, one end of the first boost capacitor 147 is connected to the output end of the fourth inverter 141, and the other end is connected to the drain of the third N-type transistor 145. Therefore, the two ends of the first boost capacitor 147 will be charged, and the voltage is equal to the voltage of VDDIO. The potential of the node VFP is VSSIO. When the logic control signal VP output by the first OR gate 100 is 0, the output of the third inverter 140 is 1, turning off the second P-type transistor 142 and the third P-type transistor 143, while turning on the second N-type transistor 144 and the fourth N-type transistor 146. The conduction of the second N-type transistor 144 pulls the gate of the third N-type transistor 145 to a low potential equal to the node VFP, turning off the third N-type transistor 145. Simultaneously, the output of the fourth inverter 141 is 0. Since the first boost capacitor 147 has stored a charge equal to the voltage VDDIO, the node VFP becomes a negative voltage. Since the fourth N-type transistor 146 is turned on, the negative voltage at the node VFP directly drives the gate VPG of the first P-type transistor 120. It can be understood that when the first P-type transistor 120 needs to be turned on, the negative voltage at the node VFP of the first gate drive enhancement circuit 14 can be used to provide an overdrive voltage to the first P-type transistor 120, thereby enhancing the driving capability of the first P-type transistor 120.

[0028] Please combine Figure 4 , Figure 41 is a schematic diagram of the structure of an embodiment of the second gate drive enhancement circuit 16 in the output buffer of the present application. In this embodiment, the second gate drive enhancement circuit 16 includes a fifth inverter 160, a sixth inverter 161, a fourth P-type transistor 162, a fifth P-type transistor 163, a sixth P-type transistor 164, a fifth N-type transistor 165, a sixth N-type transistor 166, and a second boost capacitor 167; the fifth inverter 160, the sixth inverter 161, and the second boost capacitor 167 are connected in series in sequence, and the input end of the fifth inverter 160 is connected to the output end of the first AND gate 102; the source of the sixth N-type transistor 166 is connected to the VSSIO interface, the drain of the sixth N-type transistor 166 is connected to the drain of the sixth P-type transistor 164, and the gate of the sixth N-type transistor 166 and the gate of the sixth P-type transistor 164 are respectively connected to the output end of the fifth inverter 160; the fourth P-type transistor 162, the fifth P-type transistor 165, the sixth N-type transistor 166, and the second boost capacitor 167 are connected in series in sequence, and the input end of the fifth inverter 160 is connected to the output end of the first AND gate 102; the source of the sixth N-type transistor 166 is connected to the VSSIO interface, the drain of the sixth N-type transistor 166 is connected to the drain of the sixth P-type transistor 164, and the gate of the sixth N-type transistor 166 and the gate of the sixth P-type transistor 164 are respectively connected to the output end of the fifth inverter 160; 163 and the fifth N-type transistor 165 are connected in series in sequence, the source of the fourth P-type transistor 162 is connected to the VDDIO interface, the drain of the fourth P-type transistor 162 is connected to the source of the fifth P-type transistor 163, the drain of the fifth P-type transistor 163 and the drain of the fifth N-type transistor 165 are respectively connected to the gate VNG of the first N-type transistor 122, the source of the fifth N-type transistor 165 is connected to the VSSIO interface, the gate of the fourth P-type transistor 162 is connected to the drain of the sixth N-type transistor 166, the gate of the fifth P-type transistor 163 and the gate of the fifth N-type transistor 165 are respectively connected to the output end of the fifth inverter 160, and the source of the sixth P-type transistor 164 and the end of the second boost capacitor 167 away from the sixth inverter 161 are respectively connected to the drain of the fourth P-type transistor 162.

[0029] When the logic control signal VN output by the first AND gate 102 is 0, the output is 1 after passing through the fifth inverter 160, so that the fifth N-type transistor 165 and the sixth N-type transistor 166 are in the on state, and the fifth P-type transistor 163 and the sixth P-type transistor 164 are turned off; then the sixth N-type transistor 166 can pull the gate of the fourth P-type transistor 162 to a low potential, so that the fourth P-type transistor 162 is in the on state, and at the same time the fifth N-type transistor 165 turns the first N-type transistor 165 in the output stage circuit 12 to the low potential. The gate VNG of the N-type transistor 122 is pulled to a low potential, turning off the first N-type transistor 122. At the same time, the signal is output as 0 after passing through the sixth inverter 161. Since the fourth P-type transistor 162 is in the on state, one end of the second boost capacitor 167 is connected to the output end of the sixth inverter 161, and the other end is connected to the drain of the fourth P-type transistor 162. Therefore, the two ends of the second boost capacitor 167 will be charged, and the voltage is equal to the voltage of VDDIO. The potential of the node VFN is VDDIO. When the logic control signal VN=1 output by the first AND gate 102, the output of the fifth inverter 160 is 0, causing the fifth N-type transistor 165 and the sixth N-type transistor 166 to be turned off, while the fifth P-type transistor 163 and the sixth P-type transistor 164 to be turned on. The conduction of the sixth P-type transistor 164 can pull the gate of the fourth P-type transistor 162 to a high potential equal to the node VFN, at which time the fourth P-type transistor 162 is turned off; at the same time, the output of the sixth inverter 161 is 1. Since the second boost capacitor 167 has stored a charge equal to the VDDIO voltage, the voltage of the node VFN will be higher than the VDDIO voltage. Since the fifth P-type transistor 163 is turned on, the high voltage of the node VFN will directly drive the gate VNG of the first N-type transistor 122. It is understandable that when the first N-type transistor 122 needs to be turned on, the high voltage of the node VFN of the second gate drive enhancement circuit 16 can be used to provide an overdrive voltage to the first N-type transistor 122, thereby enhancing the driving capability of the first N-type transistor 122.

[0030] Please combine Figure 5 , Figure 5 yes Figure 3Schematic diagram of the working principle of the first gate drive enhancement circuit 14. Furthermore, the capacitance of the first boost capacitor 147 is greater than the first gate parasitic capacitance 1201 of the first P-type transistor 120. It can be understood that due to the presence of the first gate parasitic capacitance 1201 at the gate VPG of the first P-type transistor 120, a portion of the charge across the first boost capacitor 147 will be charged to the first gate parasitic capacitance 1201. After stabilization, the negative voltage of the node VFP will not reach -VDDIO. However, as long as the capacitance of the first boost capacitor 147 is large enough, there will be sufficient negative voltage at the gate VPG of the first P-type transistor 120 to provide the first P-type transistor 120 with sufficient overdrive voltage, thereby enhancing the driving capability of the first P-type transistor 120.

[0031] Similarly, the operating principle of the second gate drive enhancement circuit 16 is similar to that of the first gate drive enhancement circuit 14. The capacitance of the second boost capacitor 167 is greater than the second gate parasitic capacitance (not shown) of the first N-type transistor 122. Due to the presence of the second gate parasitic capacitance at the gate VNG of the first N-type transistor 122, a portion of the charge across the second boost capacitor 167 is transferred to the second gate parasitic capacitance. After stabilization, the high voltage at the node VFN does not reach 2*VDDIO. However, as long as the capacitance of the second boost capacitor 167 is large enough, the gate VNG of the first N-type transistor 122 will have a sufficient high voltage to provide sufficient overdrive voltage to the first N-type transistor 122, thereby enhancing the driving capability of the first N-type transistor 122.

[0032] See also Figure 5The working principles of the first gate drive enhancement circuit 14 and the second gate drive enhancement circuit 16 are similar. Taking the first gate drive enhancement circuit 14 as an example, the first gate parasitic capacitance 1201 of the first P-type transistor 120 is shown in the figure. The first gate parasitic capacitance 1201 equivalently includes all gate parasitic capacitances including the gate-source parasitic capacitance Cgs, the gate-drain parasitic capacitance Cgd, etc. When both ends of the first boost capacitor 147 are fully charged and the positive end of the first boost capacitor 147 is driven to a low potential by the output 0 of the fourth inverter 141, the negative end of the first boost capacitor 147 actually needs to help charge the first gate parasitic capacitor 1201 in order to reach a negative potential. Since the direction of current is opposite to the direction of movement of negative charge, the current direction at this time flows from the first gate parasitic capacitor 1201 to the first boost capacitor 147, and the negative charge stored at the negative end of the first boost capacitor 147 will flow to the negative end of the first gate parasitic capacitor 1201, thereby pulling down the potential of the negative end of the first gate parasitic capacitor 1201, thereby allowing the gate VPG of the first P-type transistor 120 to become a negative potential. Furthermore, we use the boost capacitor Cb to collectively refer to the first boost capacitor 147 and the second boost capacitor 167, and use the gate parasitic capacitor Cbar to collectively refer to the first gate parasitic capacitor 1201 of the first P-type transistor 120 and the second gate parasitic capacitor of the first N-type transistor 122. Before the boost is performed, the two ends of the boost capacitor Cb are fully charged and the voltage is VDDIO. At this time, the two ends of the gate parasitic capacitor Cbar do not store any charge due to the equal potential. Then, during the boost process, the charge stored on the boost capacitor Cb will be redistributed with the gate parasitic capacitor Cbar. After the distribution, the voltage across the gate parasitic capacitor Cbar is the gate-source voltage Vgs of the first P-type transistor 120 or the first N-type transistor 122. Since the gate-source voltage Vgs of the first P-type transistor 120 and the first N-type transistor 122 are negative and positive respectively when turned on, the voltage across the gate parasitic capacitor Cbar at this time is recorded as the gate-source voltage |Vgs|. The magnitude of the gate-source voltage |Vgs| at this time is shown in formula (1):

[0033] |Vgs|=2*VDDIO*(Cb / (Cb+Cbar)) (1)

[0034] It can be found that when Cb>>Cpar, |Vgs|≈2*VDDIO. Therefore, the present application can enhance the over-drive voltage of the first P-type transistor 120 and the first N-type transistor 122 of the output stage circuit 12 through the action of the first gate drive enhancement circuit 14 and the second gate drive enhancement circuit 16, even to twice the original value, thereby enhancing the driving capability of the first P-type transistor 120 and the first N-type transistor 122.

[0035] See also Figure 6 , Figure 6is a schematic diagram of the structure of a second embodiment of the output buffer of the present application. The difference from the previous embodiment is that the output buffer of this embodiment further includes an enhancement circuit control circuit 18. The enhancement circuit control circuit 18 is configured to control the operating states of the first gate drive enhancement circuit 14 and the second gate drive enhancement circuit 16, respectively, based on the voltage value of the VDDIO interface, to adjust the magnitude of the overdrive voltage provided to the gate VPG of the first P-type transistor 120 and / or the gate VNG of the first N-type transistor 122. The absolute value of the gate-source voltage Vgs of the first P-type transistor 120 and the first N-type transistor 122 does not exceed the nominal voltage of the first P-type transistor 120 or the first N-type transistor 122. It is understood that due to the effects of the first gate drive enhancement circuit 14 and the second gate drive enhancement circuit 16, the overdrive voltage of the first P-type transistor 120 and the first N-type transistor 122 of the output stage circuit 12 can be enhanced. When the gate-source voltage exceeds the nominal operating voltage, the gate-source voltage is likely to be damaged due to overvoltage. Therefore, this embodiment can set the control circuit 18 of the enhancement circuit to adjust the size of the over-drive voltage provided to the gate VPG of the first P-type transistor 120 and / or the gate VNG of the first N-type transistor 122, so that the absolute value of the gate-source voltage Vgs of the first P-type transistor 120 and the first N-type transistor 122 does not exceed the nominal voltage of the first P-type transistor 120 or the first N-type transistor 122. While enhancing the driving capability, it can ensure that the gate-source overvoltage of the first P-type transistor 120 and the first N-type transistor 122 of the output stage circuit 12 will not occur, thereby ensuring the reliability of the output buffer.

[0036] As an implementable method, Figure 7 As shown, Figure 7 This is a schematic diagram of the structure of the third embodiment of the output buffer of this application. Figure 6The control circuit 18 of the enhancement circuit includes a control bus 180 and a VDDIO voltage detection circuit 181. The VDDIO voltage detection circuit 181 is used to detect the voltage value of the VDDIO interface. The control bus 180 is used to output a control signal according to the voltage value of the VDDIO interface to control the working status of the first gate drive enhancement circuit 14 and the second gate drive enhancement circuit 16. It can be understood that, according to the above formula (1), the overdrive voltage of the first P-type transistor 120 and the first N-type transistor 122 of the output stage circuit 12 can be enhanced to twice the voltage value of the VDDIO interface through the action of the first gate drive enhancement circuit 14 and the second gate drive enhancement circuit 16. Therefore, by detecting the voltage value of the VDDIO interface and then controlling the working state of the first gate drive enhancement circuit 14 and the second gate drive enhancement circuit 16 according to the voltage value of the VDDIO interface, the magnitude of the overdrive voltage of the first P-type transistor 120 and the first N-type transistor 122 of the output stage circuit 12 that is actually enhanced can be controlled, and the absolute value of the gate-source voltage Vgs of the first P-type transistor 120 and the first N-type transistor 122 can be prevented from exceeding the nominal voltage of the first P-type transistor 120 or the first N-type transistor 122.

[0037] Furthermore, please combine Figure 8 , Figure 8 FIG2 is a schematic diagram of the structure of another embodiment of the first gate drive enhancement circuit 14 in the output buffer of the present application. In this embodiment, the first gate drive enhancement circuit 14 further includes control bits VPEN, VPCB0, VPCB1, and VPCB2. Control signals output by a control bus control these control bits VPEN, VPCB0, VPCB1, and VPCB2, respectively, to control the operating state of the first gate drive enhancement circuit 14. The control signals, via the control bits VPEN, VPCB0, VPCB1, and VPCB2, control whether the first gate drive enhancement circuit 14 is in boost mode, and control the specific boost range when the first gate drive enhancement circuit 14 is in boost mode, thereby specifically adjusting the drive capability of the output stage circuit 12.

[0038] Specifically, the first gate drive enhancement circuit 14 includes a control bit VPEN, a control bit VPCB0, a control bit VPCB1, a control bit VPCB2, and a second AND gate 148; the fourth inverter 141 specifically includes a first tri-state inverter 1411, a second tri-state inverter 1412, and a third tri-state inverter 1413; the first boost capacitor 147 specifically includes a first sub-capacitor 1471, a second sub-capacitor 1472, and a third sub-capacitor 1473; wherein the second AND gate 148 is connected to the control bit VPEN, and the second AND gate 148 receives the logic control signal VP through the third inverter 140, the gate of the second P-type transistor 142 and the gate of the second N-type transistor 144 are respectively connected to the output end of the second AND gate 148; the first tri-state inverter 1411 is connected in series with the first sub-capacitor 1471, the control bit VPCB0 is connected to the first tri-state inverter 1411, and the first tri-state inverter 141 The input terminal of the first sub-capacitor 1471 is connected to the output terminal of the third inverter 140, and the end of the first sub-capacitor 1471 away from the first tri-state inverter 1411 is connected to the drain of the third N-type transistor 145. The second tri-state inverter 1412 is connected in series with the second sub-capacitor 1472, the control bit VPCB1 is connected to the second tri-state inverter 1412, the input terminal of the second tri-state inverter 1412 is connected to the output terminal of the third inverter 140, and the end of the second sub-capacitor 1472 away from the second tri-state inverter 1412 is connected to the drain of the third N-type transistor 145. The third tri-state inverter 1413 is connected in series with the third sub-capacitor 1473, the control bit VPCB2 is connected to the third tri-state inverter 1413, the input terminal of the third tri-state inverter 1413 is connected to the output terminal of the third inverter 140, and the end of the third sub-capacitor 1473 away from the third tri-state inverter 1413 is connected to the drain of the third N-type transistor 145. It can be understood that the first gate drive enhancement circuit 14 of this embodiment is Figure 3 Compared to the first gate drive enhancement circuit 14, the control bit VPEN, the control bit VPCB0, the control bit VPCB1, the control bit VPCB2, and the second AND gate 148 are added. The fourth inverter 141 is expanded into a first tri-state inverter 1411, a second tri-state inverter 1412, and a third tri-state inverter 1413. The first boost capacitor 147 is expanded into a first sub-capacitor 1471, a second sub-capacitor 1472, and a third sub-capacitor 1473. The control circuit 18 of the enhancement circuit controls the operating state of the first gate drive enhancement circuit 14 through the control bits VPEN, VPCB0, VPCB1, and VPCB2, thereby controlling the driving capability of the output stage circuit 12.

[0039] The first three-state inverter 1411, the second three-state inverter 1412 and the third three-state inverter 1413 are all inverters with three-state control. Figure 8 and Figure 9 , Figure 9 yes Figure 8 A structural diagram of an embodiment of a three-state inverter in the present application, any three-state inverter of the present application includes a seventh P-type transistor 1001, an eighth P-type transistor 1002, a seventh N-type transistor 1003 and an eighth N-type transistor 1004 connected in series in sequence, the source of the seventh P-type transistor 1001 is connected to the VDDIO interface, the drain of the eighth P-type transistor 1002 and the drain of the seventh N-type transistor 1003 are connected, and are respectively connected to the output terminal OUT of the three-state inverter, the source of the seventh N-type transistor 1003 is connected to the drain of the eighth N-type transistor 1004, the source of the eighth N-type transistor 1004 is connected to the VSSIO interface, the gate of the seventh P-type transistor 1001 and the gate of the eighth N-type transistor 1004 are respectively connected to the input terminal IN of the three-state inverter, and the gate of the eighth P-type transistor 1002 and the gate of the seventh N-type transistor 1003 are respectively connected to the input terminal TENB of the three-state inverter. Specifically, the control bit VPCB0 is connected to the input terminal TENB of the first tri-state inverter 1411, the control bit VPCB1 is connected to the input terminal TENB of the second tri-state inverter 1412, and the control bit VPCB2 is connected to the input terminal TENB of the third tri-state inverter 1413. When the input terminal TENB of a tri-state inverter is 0, the corresponding tri-state inverter operates like a normal inverter. When the input terminal TENB of a tri-state inverter is 1, the output OUT of the tri-state inverter is in a high-impedance state regardless of whether the input terminal IN of the tri-state inverter is 0 or 1.

[0040] Therefore, the control circuit 18 of the enhancement circuit can control whether the first gate drive enhancement circuit 14 is in the boost operation mode through the control bit VPEN, and control the size of the first boost capacitor 147 through the control bits VPCB0, VPCB1, and VPCB2. For example, when the control bit VPEN=1, the first gate drive enhancement circuit 14 is in the boost operation mode. At this time, the capacitance of the first boost capacitor 147 can be controlled by the control bits VPCB0~VPCB2. When the control bit VPCB0=0 and the control bit VPCB1=control bit VPCB2=1, the first tri-state inverter 1411 is equivalent to an ordinary inverter. At this time, the first sub-capacitor 1471 works as a boost capacitor, and the outputs of the third tri-state inverter 1413 and the fourth tri-state inverter 1611 are in a high-impedance state. The positive terminals of the second sub-capacitor 1472 and the third sub-capacitor 1473 are floating and do not work as boost capacitors. Moreover, the second sub-capacitor 1472 and the third sub-capacitor 1473 have no effect on the operation of the circuit. By configuring different values for the control bits VPCB0 to VPCB2, it is possible to control whether the first sub-capacitor 1471, the second sub-capacitor 1472, and the third sub-capacitor 1473 work as boost capacitors, respectively. This is equivalent to freely adjusting the capacitance of the first boost capacitor 147. When the control bit VPEN = 0, the first gate drive enhancement circuit 14 is in a non-boosting operating mode. At this time, the output of the second AND gate 148 is 0 due to the control bit VPEN = 0, turning on the second P-type transistor 142, thereby pulling the gate of the third N-type transistor 145 to a high potential, turning on the third N-type transistor 145. At the same time, the control bits VPCB0 to VPCB2 are all 1, so that the outputs of the first tri-state inverter 1411 to TINV1 are all in a high-impedance state, making the first sub-capacitor 1471, the second sub-capacitor 1472, and the third sub-capacitor 147 3 are all floating, and the first sub-capacitor 1471, the second sub-capacitor 1472, and the third sub-capacitor 1473 have no effect on the operation of the circuit; because the third N-type transistor 145 is turned on, and the third P-type transistor 143 and the fourth N-type transistor 146 form an inverter structure, the logic control signal VP can reach the gate VPG of the first P-type transistor 120 through the inverter structure composed of the third inverter 140 and the third P-type transistor 143 and the fourth N-type transistor 146. That is, the logic control signal VP directly controls the gate VPG of the first P-type transistor 120.

[0041] Please combine Figure 7 and Figure 8In one application scenario, the nominal voltage of all P-type transistors and N-type transistors is 5V; if the voltage value of VDDIO is 5V, then the VDDIO voltage detection circuit 181 will make the control bus 180 set the control bit VPEN=0 and the control bits VPCB0~VPCB2 are all 1. At this time, the first gate drive enhancement circuit 14 is in the non-boost working mode, which can prevent the gate-source voltage of the first P-type transistor 120 of the output stage circuit 12 from being damaged by overvoltage; if the voltage value of VDDIO is 4V, then the VDDIO voltage detection circuit 181 will make the control bus 180 set the control bit VPEN=0 and the control bits VPCB0~VPCB2 are all 1. The control bus 180 sets the control bit VPEN=1, the control bit VPCB0=0, and the control bit VPCB1=VPCB2=1. At this time, the first gate drive enhancement circuit 14 is in the boost operation mode, and the first sub-capacitor 1471 works as a boost capacitor. The above formula (1) is used to accurately match the first gate parasitic capacitance 1201 and the first sub-capacitor 1471, so that the gate-source voltage Vgs of the first P-type transistor 120 exceeds 4V but does not exceed 5V, thereby achieving the increase of the gate voltage VPG of the first P-type transistor 120 through the first gate drive enhancement circuit 14. Overdrive voltage but will not exceed the nominal voltage of the device and be damaged; if the voltage value of VDDIO = 3V, then the VDDIO voltage detection circuit 181 will let the control bus 180 set the control bit VPEN = 1, the control bit VPCB0 = VPCB1 = 0, and the control bit VPCB2 = 1. At this time, the first gate drive enhancement circuit 14 is in the boost working mode, and the first sub-capacitor 1471 and the second sub-capacitor 1472 work as boost capacitors. The above formula (1) is used to calculate the first gate parasitic capacitance 1201 and the first sub-capacitor 1471 and the second sub-capacitor 1472. By performing precise matching, the gate-source voltage Vgs of the first P-type transistor 120 can be made to exceed 3V but not exceed 5V, thereby achieving the goal of increasing the overdrive voltage to the gate VPG of the first P-type transistor 120 through the first gate drive enhancement circuit 14 without exceeding the nominal voltage of the device and causing damage; similarly, the voltage value of VDDIO is detected by the VDDIO voltage detection circuit 181, and then accurately calculated by the above formula (1), so that the first gate drive enhancement circuit 14 is in a boost working mode without damaging the circuit due to overvoltage, thereby greatly improving the reliability of the output buffer.

[0042] Furthermore, please combine Figure 10 , Figure 101 is a schematic diagram of the structure of another embodiment of the second gate drive enhancement circuit 16 in the output buffer of the present application. In this embodiment, the second gate drive enhancement circuit 16 further includes control bits VNEN, VNCB0, VNCB1, and VNCB2. Control signals output by the control bus control control bits VNEN, VNCB2, VNCB1, and VNCB0, respectively, to control the operating state of the second gate drive enhancement circuit. The control signals, via control bits VNEN, VNCB2, VNCB1, and VNCB0, can control whether the second gate drive enhancement circuit 16 is in boost mode, as well as the specific boost range when the second gate drive enhancement circuit 16 is in boost mode, thereby specifically adjusting the drive capability of the output stage circuit 12.

[0043] Specifically, the second gate drive enhancement circuit 16 includes a control bit VNEN, a control bit VNCB0, a control bit VNCB1, a control bit VNCB2, a seventh inverter 168, and a second OR gate 169; the sixth inverter 161 specifically includes a fourth three-state inverter 1611, a fifth three-state inverter 1612, and a sixth three-state inverter 1613; the second boost capacitor 167 specifically includes a fourth sub-capacitor 1671, a fifth sub-capacitor 1672, and a sixth sub-capacitor 1673; wherein the second OR gate 169 is connected to the control bit VNEN through the seventh inverter 168, and the second OR gate 169 receives the logic control signal VN through the fifth inverter 160, the gate of the sixth P-type transistor 164 and the gate of the sixth N-type transistor 166 are respectively connected to the output terminal of the second OR gate 169; the fourth three-state inverter 1611 is connected in series with the fourth sub-capacitor 1671, the control bit VPCB2 is connected to the fourth three-state inverter 1611, and the fourth sub-capacitor 1671 is connected to the sixth N-type transistor 166. The input end of the fourth three-state inverter 1611 is connected to the output end of the fifth inverter 160, and the end of the fourth sub-capacitor 1671 away from the fourth three-state inverter 1611 is connected to the drain of the fourth P-type transistor 162; the fifth three-state inverter 1612 is connected in series with the fifth sub-capacitor 1672, the control bit VPCB1 is connected to the fifth three-state inverter 1612, the input end of the fifth three-state inverter 1612 is connected to the output end of the fifth inverter 160, and the fifth sub-capacitor 1 672 is connected to the drain of the fourth P-type transistor 162 at one end away from the fifth tri-state inverter 1612; the sixth tri-state inverter 1613 is connected in series with the sixth sub-capacitor 1673, the control bit VPCB0 is connected to the sixth tri-state inverter 1613, the input end of the sixth tri-state inverter 1613 is connected to the output end of the fifth inverter 160, and the end of the sixth sub-capacitor 1673 is connected to the drain of the fourth P-type transistor 162. It can be understood that the second gate drive enhancement circuit 16 of this embodiment is connected to Figure 4Compared to the second gate drive enhancement circuit 16, the control bits VNEN, VNCB0, VNCB1, and VNCB2 are added, along with a second OR gate 169. The sixth inverter 161 is expanded into a fourth three-state inverter 1611, a fifth three-state inverter 1612, and a sixth three-state inverter 1613. The second boost capacitor 167 is expanded into a fourth sub-capacitor 1671, a fifth sub-capacitor 1672, and a sixth sub-capacitor 1673. The control circuit 18 of the enhancement circuit controls the operating state of the second gate drive enhancement circuit 16 through the control bits VNEN, VNCB0, VNCB1, and VNCB2, thereby controlling the drive capability of the output stage circuit 12.

[0044] For the structures and functions of the fourth three-state inverter 1611, the fifth three-state inverter 1612 and the sixth three-state inverter 1613, please refer to Figure 9 Related content of the tri-state inverter shown.

[0045] Therefore, the control circuit 18 of the enhancement circuit can control whether the second gate drive enhancement circuit 16 is in the boost operating mode through the control bit VNEN, and control the size of the second boost capacitor 167 through the control bits VNCB0, VNCB1, and VNCB2. Similar to the control method of the second gate drive enhancement circuit 16, when the control bit VNEN = 1, the second gate drive enhancement circuit 16 is in the boost operating mode, and the capacitance of the second boost capacitor 167 can be controlled by the control bits VNCB0-VNCB2. When the control bit VNEN = 0, the second gate drive enhancement circuit 16 is in the non-boost operating mode, at which time the control bits VNCB0-VNCB2 are all 1. The specific operating principle is similar to that of the first gate drive enhancement circuit 14 described above and will not be repeated here.

[0046] It can be understood that the control bits VPCB0~VPCB2 or VNCB0~VNCB2 are used as three-bit control bits in the above embodiment. In actual applications, the number of control bits can be set as needed to accurately control the value of the first boost capacitor 147 or the second boost capacitor 167.

[0047] As an implementable method, Figure 11 As shown, Figure 11This is a structural diagram of the fourth embodiment of the output buffer of the present application. The voltage value of the VDDIO interface does not exceed half of the nominal voltage of the first P-type transistor 120 or the first N-type transistor 122. The control circuit 18 of the enhancement circuit includes a digital register (not shown) and a control bus 180. The digital register is used to control the control bus 180 to output a control signal to control the working state of the first gate drive enhancement circuit 14 and the second gate drive enhancement circuit 16. It can be understood that, since the voltage value of the VDDIO interface is determined not to exceed half of the nominal voltage of the first P-type transistor 120 or the first N-type transistor 122, even if the overdrive voltage of the first P-type transistor 120 and the first N-type transistor 122 of the output stage circuit 12 is enhanced to twice the voltage value of the VDDIO interface by the first gate drive enhancement circuit 14 and the second gate drive enhancement circuit 16, the absolute value of the gate-source voltage Vgs of the first P-type transistor 120 and the first N-type transistor 122 will not exceed the nominal voltage of the first P-type transistor 120 or the first N-type transistor 122. Therefore, the digital control signal VM can be outputted by the digital register to control the control bus 180 to adjust the driving capability of the output stage circuit 12. For example, the overdrive voltage can be adjusted to perform a 2x boost, a 1.8x boost, a 1.5x boost, or no boost through the control bus 180, thereby achieving the purpose of controlling the driving capability of the output stage circuit 12. For example, if the nominal voltage of all first P-type transistors 120 or first N-type transistors 122 is 5V and the voltage value of the VDDIO interface is 1.8V, then even if the overdrive voltage is increased to twice the voltage value of the VDDIO interface, that is, 3.6V, there is no risk of gate-source overvoltage of the first P-type transistors 120 and the first N-type transistors 122 of the output stage circuit 12.

[0048] It can be understood that, in the output buffer of the third embodiment of the present application, after the voltage value of the VDDIO interface is detected by the VDDIO voltage detection circuit 181, the control bus 180 can control the potentials of the control bit VPEN and the control bits VPCB0-VPCB2 to 0 or 1, respectively, thereby respectively controlling whether the first sub-capacitor 1471, the second sub-capacitor 1472, and the third sub-capacitor 1473 operate as boost capacitors. Similarly, the control bus 180 can also control the potentials of the control bit VNEN and the control bits VNCB0-VNCB2 to 0 or 1, respectively, thereby respectively controlling whether the fourth sub-capacitor 1671, the fifth sub-capacitor 1672, and the sixth sub-capacitor 1673 operate as boost capacitors. Thus, the first sub-capacitor 1471, the second sub-capacitor 1472, and the third sub-capacitor 1473 can be combined to form the boost multiple actually required for the overdrive voltage, and the fourth sub-capacitor 1671, the fifth sub-capacitor 1672, and the sixth sub-capacitor 1673 can also be combined to form the boost multiple actually required for the overdrive voltage. In contrast, the output buffer in the fourth embodiment of the present application stores the correspondence between the voltage value of the VDDIO interface and the potential of the control bit in a digital memory in advance. During use, the voltage value of the VDDIO interface is automatically stored in the digital memory upon power-up. Based on the correspondence between the voltage value of the VDDIO interface and the potential of the control bit, the corresponding digital control logic can be found from the voltage value of the VDDIO interface. Similar to a table lookup method, the digital control logic can be used to adjust the overdrive voltage to the desired boost multiple. It can be seen that the output buffer in the third embodiment of the present application needs to adjust the desired boost multiple based on the voltage value of the VDDIO interface detected by the VDDIO voltage detection circuit 181 each time. That is, each time the drive capability of the output stage circuit 12 is adjusted, the voltage value of the VDDIO interface needs to be detected once. However, the output buffer in the fourth embodiment of the present application does not need to detect the voltage value of the VDDIO interface each time the drive capability of the output stage circuit 12 is adjusted.

[0049] The output buffer of the present application provides an overdrive voltage to the gate VPG of the first P-type transistor 120 through the first gate drive enhancement circuit 14, and increases the overdrive voltage to the gate VNG of the first N-type transistor 122 through the second gate drive enhancement circuit 16. This can greatly enhance the gate overdrive voltage of the first P-type transistor 120 and the first N-type transistor 122 of the output stage circuit 12. Even if it operates at 1 / 2 or even 1 / 4 of the standard operating voltage of the device, it can still provide high driving capability and can drive external large capacitive loads.

[0050] In the several embodiments provided herein, it should be understood that the disclosed output buffers can be implemented in other ways. For example, the output buffer implementations described above are merely illustrative. For example, the division into modules or units is merely a logical functional division. In actual implementation, other divisions may be employed, such as combining or integrating multiple units or components into another system, or omitting or disabling certain features. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between devices or units via some interface, which may be electrical, mechanical, or other means.

[0051] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0052] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0053] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) or a processor to execute all or part of the steps of each embodiment method of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

Claims

1. An output buffer, characterized in that: The output buffer includes a pre-driver circuit, an output stage circuit, a first gate driver enhancement circuit and a second gate driver enhancement circuit; The pre-driver circuit includes a first OR gate and a first AND gate; The output stage circuit includes a first P-type transistor and a first N-type transistor; a gate VPG of the first P-type transistor is connected to the output terminal of the first OR gate via a first gate drive enhancement circuit, the first gate drive enhancement circuit being configured to increase an overdrive voltage to the gate VPG of the first P-type transistor to enhance the driving capability of the first P-type transistor; a gate VNG of the first N-type transistor is connected to the output terminal of the first AND gate via a second gate drive enhancement circuit, the second gate drive enhancement circuit being configured to increase an overdrive voltage to the gate VNG of the first N-type transistor to enhance the driving capability of the first N-type transistor; The first gate drive enhancement circuit includes a third inverter, a fourth inverter, a second P-type transistor, a third P-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor and a first boost capacitor; The third inverter, the fourth inverter and the first boost capacitor are connected in series in sequence, and the input end of the third inverter is connected to the output end of the first OR gate; The source of the second P-type transistor is connected to the VDDIO interface, the drain of the second P-type transistor is connected to the drain of the second N-type transistor, and the gate of the second P-type transistor and the gate of the second N-type transistor are respectively connected to the output end of the third inverter; The third P-type transistor, the fourth N-type transistor and the third N-type transistor are connected in series in sequence, the gate of the third N-type transistor is connected to the drain of the second P-type transistor, and the source of the second N-type transistor and the end of the first boost capacitor away from the fourth inverter are respectively connected to the drain of the third N-type transistor.

2. The output buffer according to claim 1, wherein: The capacitance of the first boost capacitor is greater than the first gate parasitic capacitance of the first P-type transistor.

3. The output buffer according to claim 1, wherein: The second gate drive enhancement circuit includes a fifth inverter, a sixth inverter, a fourth P-type transistor, a fifth P-type transistor, a sixth P-type transistor, a fifth N-type transistor, a sixth N-type transistor, and a second boost capacitor; The fifth inverter, the sixth inverter and the second boost capacitor are connected in series in sequence, and the input end of the fifth inverter is connected to the output end of the first AND gate; The source of the sixth N-type transistor is connected to the VSSIO interface, the drain of the sixth N-type transistor is connected to the drain of the sixth P-type transistor, and the gate of the sixth N-type transistor and the gate of the sixth P-type transistor are respectively connected to the output end of the fifth inverter; The fourth P-type transistor, the fifth P-type transistor and the fifth N-type transistor are connected in series in sequence, the gate of the fourth P-type transistor is connected to the drain of the sixth N-type transistor, and the source of the sixth P-type transistor and the end of the second boost capacitor away from the sixth inverter are respectively connected to the drain of the fourth P-type transistor.

4. The output buffer according to claim 3, wherein: The capacitance of the second boost capacitor is greater than the second gate parasitic capacitance of the first N-type transistor.

5. The output buffer according to claim 1, wherein: The output buffer further comprises: a control circuit of the enhancement circuit, wherein the control circuit of the enhancement circuit is used to control the operating states of the first gate drive enhancement circuit and the second gate drive enhancement circuit respectively according to the voltage value of the VDDIO interface, so as to adjust the magnitude of the overdrive voltage provided to the gate VPG of the first P-type transistor and / or the gate VNG of the first N-type transistor. The output buffer according to claim 5 , wherein: The control circuit of the enhancement circuit includes a control bus and a VDDIO voltage detection circuit. The VDDIO voltage detection circuit is used to detect the voltage value of the VDDIO interface. The control bus is used to output a control signal according to the voltage value of the VDDIO interface to control the operating states of the first gate drive enhancement circuit and the second gate drive enhancement circuit.

7. The output buffer according to claim 5, wherein: The voltage value of the VDDIO interface does not exceed half of the nominal voltage of the first P-type transistor or the first N-type transistor; The control circuit of the enhancement circuit includes a digital register and a control bus. The digital register is used to control the control bus to output a control signal to control the working states of the first gate drive enhancement circuit and the second gate drive enhancement circuit.

8. The output buffer according to claim 6 or 7, characterized in that: The first gate drive enhancement circuit further includes a control bit VPEN, a control bit VPCB0, a control bit VPCB1, and a control bit VPCB2; The control signals respectively control the control bit VPEN, the control bit VPCB0, the control bit VPCB1, and the control bit VPCB2 to control the working state of the first gate drive enhancement circuit.

9. The output buffer according to claim 6 or 7, characterized in that: The second gate drive enhancement circuit further includes a control bit VNEN, a control bit VNCB0, a control bit VNCB1, and a control bit VNCB2; The control signals respectively control the control bit VNEN, the control bit VNCB2, the control bit VNCB1, and the control bit VNCB0 to control the working state of the second gate drive enhancement circuit.

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