Power down testing of firmware of a memory system

Abstract

The application provides a power-off test method of firmware of a memory system, a memory system, a computer device, a computer readable storage medium and a power-off test system. The power-off test method comprises triggering power-off test at multiple preset logical points of the firmware to be tested.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory, in particular to a power-off test method of firmware of a memory system, the memory system, a computer device, a computer readable storage medium and a power-off test system. BACKGROUND

[0002] The test method for performing power-off test on a UFS (Universal Flash Storage) device is that a series of commands are sent by upper software to drive the UFS device to run normally, and a power-off time point is randomly selected to cut off the voltage on the UFS device, for example, V CC , V CCQ , V CCQ2 (wherein, V CC is used to power the flash storage medium, V CCQ is used to power the flash input / output interface and the UFS device ground controller, and V CCQ2 is used to power some other low-voltage modules), so as to complete the power-off test on the UFS device.

[0003] However, since there are many running scenarios of the UFS device and the running speed is fast, the test method for performing power-off test on the UFS device by randomly selecting a power-off time point from the outside is difficult to cover all the running scenarios of the UFS device which need to be tested. SUMMARY

[0004] In one aspect, the present application provides a power-off test method of firmware of a memory system, the power-off test method comprising:

[0005] Triggering power-off test at a plurality of preset logical points of the firmware to be tested.

[0006] Further preferably, the power-off test method comprises:

[0007] Running the firmware to be tested, wherein the firmware to be tested is configured with a plurality of power-off trigger signal points set corresponding to the plurality of preset logical points, and when the firmware to be tested is run to the power-off trigger signal point, a power-off test instruction is sent;

[0008] In response to a power-off operation of the memory system, the memory system enters a power-off scenario at the preset logical point of the firmware to be tested, wherein the power-off operation is performed by a host coupled to the memory system in response to the power-off test instruction; and

[0009] In response to a power-up operation of the memory system, the memory system enters a power-up scenario, wherein the power-up operation is subsequent to the power-down operation and is performed by a host coupled to the memory system in response to the power-down test instruction.

[0010] Further preferably, the power-down operation comprises that the memory system is powered off by the host to enter a power-down scenario, and the power-up operation comprises that the memory system is powered on by the host to enter a power-up scenario.

[0011] Further preferably, the step of sending the power-down test instruction comprises:

[0012] sending the power-down test instruction to a test board where the memory system is located through a preset port of the memory system, wherein the test board is coupled to the host.

[0013] Further preferably, the power-down test instruction is a preset rising edge level and / or a preset falling edge level, and the preset port is a general input / output port.

[0014] Further preferably, the memory system comprises a general flash memory.

[0015] In another aspect, the present application also provides a memory system, comprising:

[0016] one or more memory devices for storing data information;

[0017] a memory controller for controlling the memory devices to perform data storage operation in response to an instruction of a host; and

[0018] a memory for storing a to-be-tested firmware executable by the memory controller;

[0019] wherein the memory controller is capable of implementing the steps of any one of the power-down test methods as described above when executing the to-be-tested firmware.

[0020] In another aspect, the present application also provides a power-down test method for a firmware of a memory system, comprising:

[0021] configuring a first power-down trigger signal point corresponding to a first preset logic point to a to-be-tested firmware of the memory system;

[0022] controlling a host connected to the memory system to drive the memory system to perform a first power-down test at the first preset logic point of the to-be-tested firmware;

[0023] if the to-be-tested firmware fails the power-off test at the first preset logical point, removing the first power-off trigger signal point and configuring the to-be-tested firmware with a second power-off trigger signal point of a second preset logical point, the second preset logical point being different from the first preset logical point; and

[0024] controlling a host connected to the memory system to drive the memory system to perform the second power-off test at the second preset logical point of the to-be-tested firmware.

[0025] Further preferably, the power-off test method further comprises:

[0026] if the to-be-tested firmware fails the power-off test at the first preset logical point or the second preset logical point, recording that the first preset logical point or the second preset logical point fails the power-off test.

[0027] Further preferably, the first power-off test and the second power-off test cover power-off tests of all preset logical points of the to-be-tested firmware.

[0028] Further preferably, the power-off test method is used to perform power-off tests on a flash translation layer of the to-be-tested firmware.

[0029] Further preferably, the power-off test method further comprises:

[0030] if the to-be-tested firmware successfully rebuilds a logical-to-physical mapping table during the process of driving the memory system to perform the first power-off test or the second power-off test, the to-be-tested firmware is considered to pass the power-off test at the first preset logical point or the second preset logical point.

[0031] In another aspect, the present application also provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, the processor being capable of implementing the steps of any of the above-mentioned power-off test methods when executing the computer program.

[0032] In another aspect, the present application also provides a computer-readable storage medium having a computer program stored thereon, the computer program being executable on a processor to implement the steps of any of the above-mentioned power-off test methods.

[0033] In another aspect, the present application also provides a power-off test system for performing power-off tests on firmware of a memory system, comprising:

[0034] a memory system to be tested, which is configured with firmware to be tested, wherein the firmware to be tested is configured with a plurality of power-off trigger signal points set according to a plurality of preset logic points, and the memory system is further configured to send a power-off test instruction when the firmware to be tested is run to the power-off trigger signal points;

[0035] a test board, which carries and couples the memory system;

[0036] a host, which is coupled with the memory system and is configured to, if the power-off test instruction corresponding to the memory system is received, successively control the memory system to be powered off to enter a power-off scenario and to be powered on to enter a power-on scenario;

[0037] a test device, which is configured to drive the host to configure the plurality of power-off trigger signal points for the firmware to be tested of the memory system. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the present application, the drawings required to be used in the following description of each embodiment according to the present application will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained according to these drawings without creative labor for those skilled in the art.

[0039] Figure 1 A flowchart of a power-off test method of firmware of a memory system according to an embodiment of the present application is shown.

[0040] Figure 2 A structural diagram of a memory system according to an embodiment of the present application is shown.

[0041] Figure 3 Another flowchart of a power-off test method of firmware of a memory system according to an embodiment of the present application is shown.

[0042] Figure 4 A structural diagram of a computer device according to an embodiment of the present application is shown.

[0043] Figure 5 A structural diagram of a power-off test system according to an embodiment of the present application is shown.

[0044] Embodiments of the present application

[0045] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0046] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.

[0047] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, or the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0048] In the present application, unless otherwise explicitly specified and limited, the "upper" or "lower" of the first feature to the second feature can include the direct contact of the first and second features, or can include the contact of the first and second features through another feature between them. Moreover, the "upper", "upper" and "upper" of the first feature to the second feature include the vertical direction of the first feature above and obliquely above the second feature, or only indicate that the horizontal height of the first feature is higher than that of the second feature. The "below", "below" and "below" of the first feature to the second feature include the vertical direction of the first feature below and obliquely below the second feature, or only indicate that the horizontal height of the first feature is less than that of the second feature.

[0049] The following disclosure provides many different embodiments, or examples, for implementing different structures of the present application. For the purpose of simplification, the components and arrangements of the specific examples are described in the following. Of course, they are only examples and the purpose is not to limit the present application. In addition, the present application can repeatedly refer to numbers and / or letters in different examples, and such repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or arrangements discussed. In addition, the present application provides various specific examples of processes and materials, but those of ordinary skill in the art can realize the application of other processes and / or the use of other materials.

[0050] Embodiments of the present application can solve the problem that the existing power-off test method cannot perform power-off test on all scenarios that need to be tested for power-off test of a general flash memory storage device.

[0051] Please refer to Figure 1 , Figure 1 The flowchart of the power-off test method of the firmware of the memory system according to an embodiment of the present application is shown, which is applied to the memory system, which triggers the power-off test at multiple preset logical points of the firmware to be tested of the memory system, and the specific process can include the following steps:

[0052] Running step S101: running the firmware to be tested, wherein the firmware to be tested is configured with multiple power-off trigger signal points set corresponding to multiple preset logical points, and when the firmware to be tested is run to the power-off trigger signal point, a power-off test instruction is sent;

[0053] Power-off step S102: in response to the power-off operation of the memory system, the memory system enters the power-off scenario at the preset logical point of the firmware to be tested, wherein the power-off operation is performed by the host coupled to the memory system in response to the power-off test instruction;

[0054] Power-on step S103: in response to the power-on operation of the memory system, the memory system enters the power-on scenario, wherein the power-on operation is performed by the host coupled to the memory system in response to the power-off test instruction, and the power-on operation is subsequent to the power-off operation.

[0055] It should be noted that in the embodiment of the present application, since the corresponding power-off trigger signal point can be configured through the preset logic point of the to-be-tested firmware which needs to be tested, when the to-be-tested firmware is run to the power-off trigger signal point, the memory system provided with the to-be-tested firmware will send out a power-off test instruction to the host coupled with the memory system to instruct the host to successively perform power-off operation and power-on operation on the memory system, so as to realize power-off test at the preset logic point of the to-be-tested firmware. Therefore, the power-off test method provided by the embodiment of the present application can effectively control the logic point of the to-be-tested firmware for power-off test, and improve the coverage of the logic point of the to-be-tested firmware for power-off test.

[0056] Specifically, the power-off operation can specifically include that the memory system is controlled to be powered off by the host to enter a power-off scenario; and the power-on operation can specifically include that the memory system is controlled to be powered on by the host to enter a power-on scenario.

[0057] Further, in the running step S101, the step of "sending a power-off test instruction" can specifically include:

[0058] sending the power-off test instruction to a test board where the memory system is located through a preset port of the memory system, wherein the test board is coupled with the host.

[0059] Specifically, the preset port can be a general purpose input / output port (GPIO), and the test board is used as a transmission bridge of the power-off test instruction between the memory system and the host. The power-off test instruction can be a preset rising edge level and / or a preset falling edge level. The memory system can be, but is not limited to, a universal flash storage (UFS) device.

[0060] Please refer to Figure 2 , Figure 2 Fig. 1 shows a structural schematic diagram of a memory system 100 according to an embodiment of the present application, as Figure 2 shown, the memory system 100 includes:

[0061] one or more memory devices 110 for storing data information;

[0062] a memory controller 120 for controlling the memory device 110 to perform data storage operation in response to an instruction of a host; and

[0063] a memory 121 storing a to-be-tested firmware 1211 executable by the memory controller 120;

[0064] The storage controller 120 can implement the steps in the power-off test method as described above when executing the firmware 1211 under test.

[0065] In an embodiment, the memory device 110 can include one or more memory dies, each including a memory array and corresponding peripheral circuitry; the memory dies can be, but are not limited to, flash memory devices, such as three-dimensional (3D) NAND flash memory devices; the memory 121 is distinguished from the memory device 110, which corresponds to the storage controller 120, and the firmware 1211 stored therein can be executed by the storage controller 120 to implement functions or operations such as FTL, reading, writing, erasing, and the like; the storage controller 120 can include a front-end interface device configured with multiple channels to communicate with the host 300 based on a protocol such as PCIe; the storage controller 120 can also include a back-end interface device configured with multiple channels to communicate with each memory device 110 based on a protocol such as Onfi.

[0066] The embodiment of the present application provides a power-off test method for firmware 1211 of a memory system 100, which can be applied to the memory system 100, and includes: triggering power-off test at multiple preset logical points of the firmware 1211 under test; in the power-off test method provided by the present application, since the corresponding power-off trigger signal point is configured at the preset logical point of the firmware 1211 under test, when the firmware 1211 under test is run to the preset logical point, the host coupled with the memory system 100 in which the firmware 1211 under test is arranged can be triggered to successively perform power-off operation and power-on operation on the memory system 100 through the configured power-off trigger signal point, so as to realize power-off test at the preset logical point of the firmware 1211 under test, thereby effectively controlling the logical point of the firmware 1211 under test for power-off test and improving the coverage of the logical point of the firmware 1211 under test for power-off test.

[0067] Please refer to Figure 3 , Figure 3 Another flowchart of a power-off test method for firmware of a memory system according to an embodiment of the present application is shown, which is applied to a test device, as shown in Figure 3 The specific flow of the power-off test method can be as follows:

[0068] A first configuration step S201: configuring a first power-off trigger signal point corresponding to a first preset logical point to firmware under test of a memory system;

[0069] The first power-off test step S202 is to control the host connected to the memory system, so as to drive the memory system to be tested at the first preset logic point of the firmware to be tested to trigger the first power-off test.

[0070] The second configuration step S203 is to remove the first power-off trigger signal point and configure the second power-off trigger signal point corresponding to the second preset logic point to the firmware to be tested if the firmware to be tested passes the power-off test at the first preset logic point.

[0071] The second power-off test step S204 is to control the host connected to the memory system, so as to drive the memory system to be tested at the second preset logic point of the firmware to be tested to trigger the second power-off test.

[0072] It should be noted that in the process of the above-mentioned first power-off test and second power-off test, the host is controlled by the test equipment to drive the memory system to enter the power-off scene and the power-on scene in sequence, so as to realize the power-off test of the firmware to be tested.

[0073] Further, the above-mentioned first power-off test and second power-off test can be used to test the firmware to be tested corresponding to the flash translation layer (FTL). Specifically, the flash translation layer can be used to complete the conversion or translation of the logical address (LBA) on the host to the physical address (PPA) on the flash memory storage array. For example, the flash translation layer can use the logical-to-physical mapping table (L2P mapping table) representing the logical address and physical address mapping relationship to perform address conversion. In the power-on process after the abnormal power-off of the flash memory, the flash memory generally re-establishes the L2P mapping table. Therefore, whether the firmware to be tested in the memory system passes the first power-off test or the second power-off test can be judged based on whether the firmware to be tested successfully rebuilds the L2P mapping table after entering the power-on scene.

[0074] It should be noted that, in the second configuration step S203, if the to-be-tested firmware fails the power-off test at the first preset logical point, specifically, for example, the to-be-tested firmware fails to re-establish the L2P mapping table after entering the power-on scenario at the first preset logical point, it is recorded that the first preset logical point fails the power-off test, and accordingly, after the second power-off test step S204, if the to-be-tested firmware fails the power-off test at the second preset logical point, specifically, for example, the to-be-tested firmware fails to re-establish the L2P mapping table after entering the power-on scenario at the second preset logical point, it is recorded that the second preset logical point fails the power-off test.

[0075] Specifically, through the first power-off test and the second power-off test, the power-off test of all preset logical points of the to-be-tested firmware can be covered, and the test device can quantitatively count the power-off test results of all preset logical points of the to-be-tested firmware.

[0076] Further, referring to Figure 4 , Figure 4 a structural schematic diagram of a computer device 600 according to an embodiment of the present application is shown, as shown in Figure 4 The computer device 600 includes a memory 601, a processor 602, and a computer program stored in the memory 601 and executable on the processor 602, wherein the processor 602 can implement the steps in the power-off test method described above when executing the computer program.

[0077] Further, the memory 601 in the embodiment of the present application has at least one computer readable storage medium, and the above computer program is stored on the computer readable storage medium.

[0078] Referring to Figure 5 , Figure 5 a structural schematic diagram of a power-off test system 500 according to an embodiment of the present application is shown, as shown in Figure 5 The power-off test system 500 includes:

[0079] The tested memory system 100 is configured with the to-be-tested firmware 1211, the to-be-tested firmware 1211 is configured with a plurality of power-off trigger signal points set corresponding to a plurality of preset logical points, and the memory system 100 is further configured to send a power-off test instruction when the to-be-tested firmware 1211 is run to the power-off trigger signal point;

[0080] The test board 200 carries and couples the memory system 100;

[0081] The host 300 is coupled with the memory system 100 and is configured to, if receiving a power-off test instruction corresponding to the memory system 100, successively control the memory system 100 to be powered off to enter a power-off scenario and to be powered on to enter a power-on scenario.

[0082] The test device 400 is configured to drive the host 300 to configure a plurality of power-off trigger signal points for the firmware 1211 to be tested of the memory system 100.

[0083] Specifically, the test board 200 can be, but is not limited to, a software development kit (SDK).

[0084] The embodiment of the present application also provides a power-off test method for firmware 1211 of a memory system 100, which is applied to a test device 400 and includes the following steps: configuring a first power-off trigger signal point corresponding to a first preset logic point for firmware 1211 to be tested of the memory system 100; controlling a host 300 connected with the memory system 100, thereby driving the memory system 100 to perform a first power-off test when the first preset logic point of the firmware to be tested is triggered; if the firmware 1211 to be tested passes the power-off test at the first preset logic point, removing the first power-off trigger signal point and configuring a second power-off trigger signal point corresponding to a second preset logic point for the firmware 1211 to be tested, the second preset logic point being different from the first preset logic point; and controlling the host 300 connected with the memory system 100, thereby driving the memory system 100 to perform a second power-off test when the second preset logic point of the firmware 1211 to be tested is triggered. In the power-off test method provided by the present application, since the corresponding power-off trigger signal point is configured at the preset logic point of the firmware 1211 to be tested, the power-off test can be triggered when the memory system 100 provided with the firmware 1211 to be tested runs the firmware 1211 to be tested to the preset logic point. Therefore, the power-off test method provided by the embodiment of the present application can effectively control the logic point of the firmware 1211 to be tested to perform the power-off test and improve the coverage of the logic point of the firmware 1211 to be tested to perform the power-off test.

[0085] In addition to the above-mentioned embodiments, the present application can have other implementation manners. Any technical solution formed by equivalent replacement or equivalent substitution falls within the protection scope of the present application.

[0086] To sum up, although the preferred embodiments of the present application have been disclosed above, the above-mentioned preferred embodiments are not used to limit the present application, and any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application is defined by the scope of the claims.

Claims

1. A power-down test method of firmware of a memory system, wherein, The power-off test method comprises: For a memory system, triggering power-off test at multiple preset logical points of firmware to be tested; For a test device, configuring a first power-off trigger signal point corresponding to a first preset logical point to firmware to be tested of the memory system; Controlling a host connected to the memory system, so as to drive the memory system to perform first power-off test at the first preset logical point of the firmware to be tested; If the firmware to be tested passes the power-off test at the first preset logical point, removing the first power-off trigger signal point and configuring a second power-off trigger signal point corresponding to a second preset logical point to the firmware to be tested, the second preset logical point being different from the first preset logical point; and Controlling the host connected to the memory system, so as to drive the memory system to perform second power-off test at the second preset logical point of the firmware to be tested.

2. The power down test method of claim 1, wherein, The power-off test method comprises: Running the firmware to be tested, wherein the firmware to be tested is configured with multiple power-off trigger signal points set corresponding to the multiple preset logical points, and sending a power-off test instruction when the firmware to be tested is run to the power-off trigger signal point; In response to a power-off operation of the memory system, the memory system enters a power-off scenario at the preset logical point of the firmware to be tested, wherein the power-off operation is performed by a host coupled to the memory system in response to the power-off test instruction; and In response to a power-on operation of the memory system, the memory system enters a power-on scenario, wherein the power-on operation is performed by the host coupled to the memory system in response to the power-off test instruction, and is subsequent to the power-off operation.

3. The power down test method of claim 2, wherein, The power-off operation comprises that the memory system is powered off by the host to enter the power-off scenario, and the power-on operation comprises that the memory system is powered on by the host to enter the power-on scenario.

4. The power down test method of claim 2, wherein, The step of sending the power-off test instruction comprises: Sending the power-off test instruction to a test board where the memory system is located through a preset port of the memory system, wherein the test board is coupled to the host.

5. The power down test method of claim 4, wherein, The power-off test instruction is a preset rising edge level and / or a preset falling edge level, and the preset port is a general-purpose input / output port.

6. The power down test method of claim 1, wherein, The memory system comprises a general-purpose flash memory.

7. The power down test method of claim 1, wherein, The power-off test method further comprises: If the firmware to be tested fails the power-off test at the first preset logical point or the second preset logical point, recording that the first preset logical point or the second preset logical point fails the power-off test.

8. The power down test method of claim 1, wherein, The first power-off test and the second power-off test cover power-off test of all preset logical points of the firmware to be tested.

9. The power down test method of claim 1, wherein, The power-off test method is used to perform power-off test on a flash translation layer of the firmware to be tested.

10. The power down test method of claim 9, wherein, The power-off test method further comprises: If the to-be-tested firmware successfully rebuilds the logical-to-physical mapping table during driving the memory system to perform the first power-off test or the second power-off test, it is considered that the to-be-tested firmware passes the power-off test at the first preset logical point or the second preset logical point.

11. A memory system, wherein, Comprising: one or more memory devices for storing data information; a memory controller for controlling the memory devices to perform data storage operations in response to instructions from a host; and, a memory storing to-be-tested firmware executable by the memory controller; wherein the memory controller is capable of implementing the steps of the power-off test method of claim 1 when executing the to-be-tested firmware.

12. A computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein, The processor is capable of implementing the steps of the power-off test method of claim 1 when executing the computer program.

13. A computer readable storage medium having stored thereon a computer program, wherein, The computer program is executable by a processor to implement the steps of the power-off test method of claim 1.

14. A power down test system for performing power down testing of firmware of a memory system, wherein, Comprising: a memory system under test configured with to-be-tested firmware, the to-be-tested firmware being configured with a plurality of power-off trigger signal points set corresponding to a plurality of preset logical points, and the memory system being further configured to send a power-off test instruction when the to-be-tested firmware is run to the power-off trigger signal point; a test board carrying and coupling the memory system; a host coupled to the memory system and configured to, if receiving the power-off test instruction corresponding to the memory system, successively control the memory system to be powered off to enter a power-off scenario and to be powered on to enter a power-on scenario; a test device configured to drive the host to configure the plurality of power-off trigger signal points to the to-be-tested firmware of the memory system; the test device is configured to configure a first power-off trigger signal point corresponding to a first preset logical point to the to-be-tested firmware of the memory system; controlling the host to which the memory system is connected, thereby driving the memory system to perform a first power-off test at the first preset logical point of the to-be-tested firmware; if the to-be-tested firmware passes the power-off test at the first preset logical point, removing the first power-off trigger signal point and configuring a second power-off trigger signal point corresponding to a second preset logical point to the to-be-tested firmware, the second preset logical point being different from the first preset logical point; and, controlling the host to which the memory system is connected, thereby driving the memory system to perform a second power-off test at the second preset logical point of the to-be-tested firmware.

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