Low-dropout voltage regulator and power management integrated circuit including the low-dropout voltage regulator

Abstract

The LDO regulator includes an error amplifier, a power transistor, a monitoring circuit and / or an adaptive pole adjustment circuit (APAC). The error amplifier compares a reference voltage with a feedback voltage to generate a first error voltage based on the comparison. A power transistor including a gate coupled to an output terminal of the buffer adjusts an input voltage based on a second error voltage, the second error voltage being generated based on the first error voltage to provide an output voltage to an output node. A monitoring circuit connected in parallel with the power transistor to the output terminal of the buffer generates a control voltage associated with a load current. The APAC connected between the output terminal of the error amplifier and a ground voltage selectively connects a regulating capacitor between the output terminal of the error amplifier and the ground voltage in response to the control voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2020-0075614, filed on Jun. 22, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the present disclosure relate to a voltage regulator, and more particularly, to a low dropout (LDO) regulator and a power management integrated circuit (PMIC) including the low dropout (LDO) regulator. Background Art

[0004] An LDO regulator is a device that provides a stable voltage. An LDO regulator can be a linear regulator that provides an output voltage that is lower than the input voltage.

[0005] Although LDO regulators have power loss because their output voltage is lower than the input voltage, LDO can provide a stable output voltage. LDO regulators can also have excellent line and load regulation characteristics. Therefore, LDO regulators can be used in various fields, such as PMIC. Summary of the invention

[0006] Example embodiments provide an LDO regulator capable of adaptively adjusting a pole frequency of an output of an error amplifier based on a load current.

[0007] Example embodiments provide a PMIC including an LDO regulator capable of adaptively adjusting a pole frequency of an output of an error amplifier based on a load current.

[0008] According to an example embodiment, the LDO regulator includes an error amplifier, a buffer, a power transistor, a feedback circuit, a monitoring circuit, and an adaptive pole adjustment circuit (APAC). The error amplifier compares a reference voltage with a feedback voltage to generate a first error voltage based on the comparison. The buffer connected to the output terminal of the error amplifier buffers the first error voltage to output a second error voltage. A power transistor including a gate coupled to the output terminal of the buffer adjusts the input voltage based on the second error voltage to provide an output voltage to an output node. The feedback circuit connected between the output node and the ground voltage divides the output voltage to provide a feedback voltage. The monitoring circuit connected to the output terminal of the buffer receives the second error voltage from the output terminal of the buffer and generates a control voltage associated with a load current flowing from the output node to the load based on the second error voltage and the input voltage. The APAC connected between the output terminal of the error amplifier and the ground voltage selectively connects the adjustment capacitor between the output terminal of the error amplifier and the ground voltage in response to the control voltage.

[0009] According to an example embodiment, the PMIC includes at least one switching regulator, a plurality of LDO regulators and a controller. At least one switching regulator generates a conversion voltage according to a battery voltage. The LDO regulator generates a plurality of output voltages based on the conversion voltage to provide a plurality of output voltages to a plurality of consumers, respectively. The controller generates a voltage control signal based on the conversion voltage to adjust the switching timing of at least one switching regulator. Each of the LDO regulators includes an error amplifier, a power transistor and an APAC. The error amplifier compares a reference voltage with a feedback voltage to generate a first error voltage based on the comparison. The power transistor adjusts the conversion voltage based on a second error voltage to provide a corresponding output voltage in a plurality of output voltages to an output node, the second error voltage being based on the first error voltage. The APAC connected between the output terminal of the error amplifier and the ground voltage selectively connects the adjustment capacitor between the output terminal of the error amplifier and the ground voltage in response to the second error voltage and a control voltage generated based on the conversion voltage.

[0010] According to an example embodiment, an LDO regulator includes an error amplifier, a buffer, a power transistor, a feedback circuit, a monitoring circuit, and an adaptive pole adjustment circuit (APAC). The error amplifier compares a reference voltage with a feedback voltage to generate a first error voltage based on the comparison. A buffer connected to an output terminal of the error amplifier performs buffering on the first error voltage to output a second error voltage. A power transistor including a gate coupled to an output terminal of the buffer adjusts an input voltage based on the second error voltage to provide an output voltage to an output node. A feedback circuit connected between the output node and a ground voltage divides the output voltage to provide a feedback voltage. A monitoring circuit connected to an output terminal of the buffer receives a second error voltage from the output terminal of the buffer and generates a control voltage associated with a load current flowing from the output node to a load based on the second error voltage and the input voltage. The APAC connected between the output terminal of the error amplifier and the ground voltage selectively connects a regulating capacitor between the output terminal of the error amplifier and the ground voltage in response to the control voltage. The monitoring circuit includes a first p-channel metal oxide semiconductor (PMOS) transistor and a monitoring resistor. The first PMOS transistor connected between the input voltage and the first node has a gate that receives the second error voltage. The monitoring resistor is connected between the first node and the ground voltage. The first PMOS transistor provides a mirror current corresponding to the load current to the first node. The monitoring circuit provides a control voltage corresponding to the mirror current at the first node.

[0011] Therefore, the monitoring circuit connected to the power transistor monitors the load current provided to the load and generates a control voltage associated with the magnitude of the load current. The APAC connected between the output terminal of the error amplifier and the ground voltage can adaptively adjust the pole frequency of the output of the error amplifier based on the control voltage. Therefore, the LDO regulator can operate stably under various load conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other features of the present disclosure will become more apparent by describing in detail example embodiments of the present disclosure with reference to the attached drawings.

[0013] Figure 1 is a block diagram illustrating a low dropout (LDO) regulator according to example embodiments.

[0014] Figure 2 is a diagram showing a method according to an example embodiment Figure 1 An example circuit diagram of the error amplifier in an LDO regulator.

[0015] Figure 3 is a diagram showing a method according to an example embodiment Figure 1 Circuit diagram of an example of a buffer in an LDO regulator.

[0016] Figure 4 is a diagram showing a method according to an example embodiment Figure 1 A circuit diagram of an example of a monitoring circuit within an LDO regulator.

[0017] Figure 5 is a diagram showing a method according to an example embodiment Figure 1 A circuit diagram of an example of a feedback circuit in an LDO regulator.

[0018] Figure 6 is a diagram showing a method according to an example embodiment Figure 1 An example circuit diagram of an LDO regulator in APAC.

[0019] Figure 7 is a circuit diagram illustrating an overall architecture of an LDO regulator according to example embodiments.

[0020] Figure 8 shows that when the load current consumed by the load is reduced Figure 7 Example of an LDO regulator.

[0021] Fig. 9 shows that when the load current consumed by the load increases Figure 7 Example of an LDO regulator.

[0022] Fig.10 It is used to illustrate and Figure 7A graph of the feedback factor associated with the feedback capacitor in the feedback circuit.

[0023] Fig.11 It is used to illustrate Figure 7 A graph of the gain margin of an LDO regulator.

[0024] Fig.12 FIG. 1 shows a schematic diagram of an exemplary embodiment of the present invention. Figure 7 A graph associated with the transfer function of an LDO regulator.

[0025] Fig.13 is a flow chart illustrating a method of operating an LDO regulator according to example embodiments.

[0026] Fig.14 is a block diagram illustrating an example of an electronic device including a power management integrated circuit (PMIC) according to example embodiments.

[0027] Fig.15 is a diagram showing a method according to an example embodiment Fig.14 A circuit diagram of an example of a DC-DC converter.

[0028] Fig.16 is a block diagram illustrating a communication device according to an example embodiment.

[0029] Fig.17 According to an example embodiment Fig.16 Block diagram of the antenna and RFIC in FIG.

[0030] Fig.18 is a block diagram schematically illustrating a mobile device according to an example embodiment.

[0031] Fig.19 is a diagram illustrating an example of a communication device according to an exemplary embodiment. DETAILED DESCRIPTION

[0032] Exemplary embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings.The same reference numerals throughout the drawings may represent the same elements.

[0033] Figure 1 is a block diagram illustrating a low dropout (LDO) regulator according to example embodiments.

[0034] Reference Figure 1 , the LDO regulator 10 may include an error amplifier (EA) 100 , a buffer (BUF) 200 , a pass element 310 including a power transistor 311 , a feedback circuit (FC) 350 , a monitoring circuit (MTC) 330 , and / or an adaptive pole adjustment circuit (APAC) 360 .

[0035] In addition, the LDO regulator 10 may further include a compensation capacitor Cc, a bias voltage generator 380 and / or a reference voltage generator 450. The compensation capacitor Cc is connected between an internal node of the error amplifier 100 and an output node NO.

[0036] exist Figure 1 , a load 340 and a load capacitor CL connected between the output node NO and the ground voltage VSS are also shown. The load capacitor CL is connected between the output node NO and the ground voltage VSS in parallel with the load resistor RL.

[0037] The error amplifier 100 is connected between an input voltage VIN and a ground voltage VSS, receives a reference voltage VREF and a feedback voltage VFB, compares the reference voltage VREF and the feedback voltage VFB, and amplifies the difference between the reference voltage VREF and the feedback voltage VFB based on the comparison to generate a first error voltage EV1 corresponding to the difference, and outputs the first error voltage EV1 to a first intermediate node 181 corresponding to the output terminal of the error amplifier 100.

[0038] The first error voltage EV1 may correspond to a difference between a reference voltage VREF and a feedback voltage VFB. The error amplifier 100 has a positive (+) input terminal for receiving the reference voltage VREF and a negative (-) input terminal for receiving the feedback voltage VFB. The reference voltage VREF may be provided from a reference voltage generator 450.

[0039] The buffer 200 is connected to the output terminal of the error amplifier 100 at the first intermediate node 181, buffers the first error voltage EV1, and outputs the second error voltage EV2 to the second intermediate node 183. The second intermediate node 183 corresponds to the output terminal of the buffer 200. The buffer 200 may have a gain of -1. Although not shown, the buffer 200 may be connected between the input voltage VIN and the ground voltage VSS.

[0040] The power transistor 311 is connected to the output terminal of the buffer 200 at the second intermediate node 183 and has a gate receiving the second error voltage EV2, and adjusts the input voltage VIN based on the second error voltage EV2 to provide the output voltage VOUT to the output node NO. A load current IL corresponding to the output voltage VOUT is provided from the output node NO to the load 340.

[0041] The power transistor 311 has a source coupled to the input voltage VIN, a gate for receiving the second error voltage EV2, and a drain coupled to the output node NO. When the load current IL increases, the level of the output voltage VOUT decreases, and the level of the first error voltage EV1 increases. In response to the increase in the level of the first error voltage EV1, the level of the second error voltage EV2 decreases. When the level of the second error voltage EV2 decreases, the level of the output voltage VOUT2 increases.

[0042] When the load current IL decreases, the level of the output voltage VOUT increases, and the level of the first error voltage EV1 decreases. The level of the second error voltage EV2 increases in response to the decrease in the level of the first error voltage EV1. When the level of the second error voltage EV2 increases, the level of the output voltage VOUT2 decreases.

[0043] Therefore, when the load current IL increases, the level of the second error voltage EV2 decreases, and when the load current IL decreases, the level of the second error voltage EV2 increases.

[0044] The feedback circuit 350 is connected between the output node NO and the ground voltage VSS, generates a feedback voltage VFB by dividing the output voltage VOUT, and provides the feedback voltage VFB to the error amplifier 100 .

[0045] The monitoring circuit 330 is connected to the output terminal of the buffer 200 at the second intermediate node 183 and receives the second error voltage EV2. The monitoring circuit 330 can be connected between the input voltage VIN and the ground voltage VSS. The monitoring circuit 330 can generate a control voltage VM based on the second error voltage EV2 and the input voltage VIN. The monitoring circuit 330 can monitor the load current IL provided from the power transistor 311 to the load 340 connected to the output node NO, and can generate a control voltage VM associated with the magnitude of the load current IL. The monitoring circuit 330 can provide the control voltage VM to the feedback circuit 350 and the APAC 360.

[0046] The APAC 360 is connected between the first intermediate node 181 and the ground voltage VSS, and can selectively connect an adjustment capacitor between the first intermediate node 181 and the ground voltage VSS. The APAC 360 can adaptively adjust the pole frequency of the output of the error amplifier 100 by selectively connecting the adjustment capacitor between the first intermediate node 181 and the ground voltage VSS.

[0047] The bias voltage generator 380 generates a first bias voltage VB1 and a second bias voltage VB2 based on the reference current IREF, and provides the first bias voltage VB1 and the second bias voltage VB2 to the error amplifier 100 .

[0048] The reference voltage generator 450 generates a reference voltage VREF and a reference current IREF, provides the reference voltage VREF to the error amplifier 100, and provides the reference current IREF to the bias voltage generator 380. The reference voltage generator 450 may be provided inside or outside the LDO regulator 10.

[0049] Figure 2 is a diagram showing a method according to an example embodiment Figure 1 An example circuit diagram of the error amplifier in an LDO regulator.

[0050] Reference Figure 2 , the error amplifier 100 may include: first to fourth p-channel metal oxide semiconductor (PMOS) transistors 121 , 123 , 125 , and 127 ; first to fourth n-channel metal oxide semiconductor (NMOS) transistors 131 , 133 , 111 , and 113 ; and a current source 115 .

[0051] The first PMOS transistor 121 is connected between the input voltage VIN and the first node N11. The second PMOS transistor 123 is connected between the input voltage VIN and the second node N12, and has a gate coupled to the gate of the first PMOS transistor 121. The gates of the first PMOS transistor 121 and the second PMOS transistor 123 receive a first bias voltage VB1.

[0052] The third PMOS transistor 125 is connected between the first node N11 and the third node N13. The fourth PMOS transistor 127 is connected between the second node N12 and the fourth node N14, and its gate is coupled to the gate of the third PMOS transistor 125. The gate of the third PMOS transistor 125 and the gate of the fourth PMOS transistor 127 receive the second bias voltage VB2.

[0053] The first NMOS transistor 131 is connected between the third node N13 and the ground voltage VSS, and its gate is coupled to the third node N13. The second NMOS transistor 133 is connected between the fourth node N14 and the ground voltage VSS, and its gate is coupled to the third node N13. Therefore, the first NMOS transistor 131 and the second NMOS transistor 133 can constitute a current mirror.

[0054] The third NMOS transistor 111 is connected between the first node N11 and the fifth node N15, and has a gate receiving a reference voltage VREF. The fourth NMOS transistor 113 is connected between the second node N12 and the fifth node N15, and has a gate for receiving a feedback voltage VFB. The current source 115 is connected between the fifth node N15 and the ground voltage VSS, and provides a constant current to the fifth node N15.

[0055] When a reference voltage VREF is provided to the gate of the third NMOS transistor 111 and a feedback voltage VFB is provided to the gate of the fourth NMOS transistor 113, currents provided to the drains of the third and fourth PMOS transistors 125 and 127 are determined based on the reference voltage VREF and the feedback voltage VFB, respectively.

[0056] Since the first and second NMOS transistors 131 and 133 may constitute a current mirror, the same current flows through the first and second NMOS transistors 131 and 133. Therefore, the first error voltage EV1 provided from the fourth node N14 to the buffer 200 has a level corresponding to the difference between the feedback voltage VFB and the reference voltage VREF.

[0057] The fourth node N14 may correspond to Figure 1 In addition, the compensation capacitor Cc may be coupled between the third node N13 and the output node NO. In addition, the APAC 360 may be connected between the fourth node N14 and the ground voltage VSS.

[0058] Figure 3 is a diagram showing a method according to an example embodiment Figure 1 Circuit diagram of an example of a buffer in an LDO regulator.

[0059] Reference Figure 3 , the buffer 200 may include a first PMOS transistor 211 , a first resistor R1 and / or a first NMOS transistor 213 .

[0060] The first PMOS transistor 211 is connected between the input voltage VIN and the second intermediate node 183, and has a gate coupled to the first intermediate node 181. The first resistor R1 is connected in parallel with the first PMOS transistor 211 between the input voltage VIN and the first intermediate node 181. The first NMOS transistor 213 is connected between the second intermediate node 183 and the ground voltage VSS, and has a gate receiving the first error voltage EV1. The APAC 360 is connected between the second intermediate node 183 and the ground voltage VSS.

[0061] A current corresponding to VIN / R1 is provided to the second intermediate node 183 through the first resistor R1. When the level of the second error voltage EV1 provided to the gate of the first NMOS transistor 213 decreases, the amount of current flowing from the second intermediate node 183 to the ground voltage VSS decreases. When the amount of current flowing from the second intermediate node 183 to the ground voltage VSS decreases, the level of the second intermediate node 183 (for example, the second error voltage EV2) increases, and the current provided from the input voltage VIN to the second intermediate node 183 through the first PMOS transistor 211 decreases. Because the current provided from the input voltage VIN to the second intermediate node 183 through the first PMOS transistor 211 decreases, the level of the second error voltage EV2 decreases.

[0062] Therefore, the buffer 200 buffers the first error voltage EV1 to provide the second error voltage EV2 which decreases as the first error voltage EV1 increases or increases as the first error voltage EV1 decreases.

[0063] Figure 4 is a diagram showing a method according to an example embodiment Figure 1 A circuit diagram of an example of a monitoring circuit within an LDO regulator.

[0064] Reference Figure 4 , the monitoring circuit 330 may include a first PMOS transistor 331 and / or a monitoring resistor RM. The first PMOS transistor 331 is connected between the input voltage VIN and the first node 333, and has a gate receiving the second error voltage EV2. Therefore, the first PMOS transistor 331 may provide a mirror current IM associated with the level of the second error voltage EV2 to the first node 333.

[0065] As reference Figure 1 As described, since the magnitude of the load current IL can vary according to the level of the second error voltage EV2, the mirror current IM can be associated with the magnitude of the load current IL. Therefore, when the level of the second error voltage EV2 increases, the magnitude of the mirror current IM decreases, and when the level of the second error voltage EV2 decreases, the magnitude of the mirror current IM increases.

[0066] Because the control voltage VM (the voltage of the first node 333) has a level corresponding to the product of the mirror current IM and the monitoring resistor RM, the monitoring circuit 330 can generate a control voltage VM associated with the magnitude of the load current IL by monitoring the load current IL, and can provide the control voltage VM to the feedback circuit 350 and the APAC 360.

[0067] In some example embodiments, the current driving capability of the first PMOS transistor 331 is less than Figure 1 In other words, the ratio of the channel width to the channel length of the first PMOS transistor 331 is less than the ratio of the channel width to the channel length of the power transistor 311. The current driving capability of the first PMOS transistor 331 and the current driving capability of the power transistor 311 may correspond to 1:n. In example embodiments, n is a natural number equal to or greater than 10.

[0068] Figure 5 is a diagram showing a method according to an example embodiment Figure 1 A circuit diagram of an example of a feedback circuit in an LDO regulator.

[0069] Reference Figure 5 , the feedback circuit 350 may include a first feedback resistor Rf1 , a second feedback resistor Rf2 , a feedback capacitor Cf and / or a second PMOS transistor 351 .

[0070] The first feedback resistor Rf1 and the second feedback resistor Rf2 are connected in series between the output node NO and the ground voltage VSS. The first feedback resistor Rf1 is connected between the output node NO and the feedback node FN, and the second feedback resistor Rf2 is connected between the feedback node FN and the ground voltage VSS.

[0071] The first feedback resistor Rf1 and the second feedback resistor Rf2 divide the output voltage VOUT by a ratio of Rf2 / (Rf1 + Rf2) to generate a feedback voltage VFB at a feedback node FN and provide the feedback voltage VFB to the error amplifier 100 .

[0072] The feedback capacitor Cf and the second PMOS transistor 351 are connected between the output node NO and the feedback node FN and in parallel with the first feedback resistor Rf1. The feedback capacitor Cf and the second PMOS transistor 351 are connected in series between the output node NO and the feedback node FN. The feedback capacitor Cf has a first terminal connected to the output node NO and a second terminal connected to the second PMOS transistor 351.

[0073] The second PMOS transistor 351 has a gate receiving a control voltage VM, is selectively turned on / off in response to the control voltage VM, and selectively connects the feedback capacitor Cf between the output node NO and the feedback node FN. When the second PMOS transistor 351 is turned on, the second terminal of the feedback capacitor Cf is connected to the feedback node FN. When the second PMOS transistor 351 is turned on, the second terminal of the feedback capacitor Cf is floated.

[0074] when Figure 1 When the load current IL decreases, Figure 4The mirror current IM in the feedback circuit 350 decreases, and the control voltage VM decreases in response to the decrease in the mirror current IM. The second PMOS transistor 351 is turned on in response to the decrease in the control voltage VM. When the second PMOS transistor 351 is turned on in response to the decrease in the control voltage VM, the second terminal of the feedback capacitor Cf is connected to the feedback node FN, and the capacitance of the feedback capacitor Cf is associated with the zero point of the feedback circuit 350.

[0075] when Figure 1 When the load current IL increases, Figure 4 The mirror current IM in the feedback circuit 350 increases, and the control voltage VM increases in response to the increase in the mirror current IM. The second PMOS transistor 351 is turned off in response to the increase in the control voltage VM. When the second PMOS transistor 351 is turned off in response to the increase in the control voltage VM, the second terminal of the feedback capacitor Cf is not connected to the feedback node FN. Therefore, the capacitance of the feedback capacitor Cf is not associated with the zero point of the feedback circuit 350, and the zero point of the feedback circuit 350 can be eliminated.

[0076] Figure 6 is a diagram showing a method according to an example embodiment Figure 1 An example circuit diagram of an LDO regulator in APAC.

[0077] Reference Figure 6 , the APAC 360 may include an adjustment capacitor Cad and / or an NMOS transistor 361 .

[0078] The regulating capacitor Cad may be coupled between the first intermediate node 181 and the first node 363. The regulating capacitor Cad may have a first terminal coupled to the first intermediate node 181 and a second terminal coupled to the first node 363. The NMOS transistor 361 may be connected between the first node 363 and the ground voltage VSS, and may have a gate receiving the control voltage VM. The NMOS transistor 361 may be selectively turned on / off in response to the control voltage VM to selectively connect the regulating capacitor Cad between the first intermediate node 181 and the ground voltage VSS.

[0079] when Figure 1 When the load current IL decreases, Figure 4 The mirror current IM in the error amplifier 100 is reduced, and the control voltage VM is reduced in response to the reduction of the mirror current IM. The NMOS transistor 361 is turned off in response to the reduction of the control voltage VM. When the NMOS transistor 361 is turned off, the second terminal of the adjustment capacitor Cad is not connected to the ground voltage VSS, and the capacitance of the adjustment capacitor Cad is not associated with the pole of the output of the error amplifier 100.

[0080] when Figure 1When the load current IL increases, Figure 4 The mirror current IM in the control voltage VM increases, and the control voltage VM increases in response to the increase of the mirror current IM. The NMOS transistor 361 is turned on in response to the increase of the control voltage VM. When the NMOS transistor 361 is turned on, the second terminal of the adjustment capacitor Cad is connected to the ground voltage VSS, and the adjustment capacitor Cad is coupled between the first intermediate node 181 and the ground voltage VSS.

[0081] When the adjustment capacitor Cad is coupled between the first intermediate node 181 and the ground voltage VSS, the capacitance of the adjustment capacitor Cad is associated with a pole of the output of the error amplifier 100. When the capacitance of the adjustment capacitor Cad is associated with a pole of the output of the error amplifier 100, the pole frequency of the output of the error amplifier 100 is lower than the pole frequency of the output of the error amplifier 100 when the adjustment capacitor Cad is not coupled between the first intermediate node 181 and the ground voltage VSS.

[0082] Figure 7 is a circuit diagram illustrating an overall architecture of an LDO regulator according to example embodiments.

[0083] Figure 8 shows that when the load current consumed by the load is reduced Figure 7 Example of an LDO regulator.

[0084] Reference Figure 1 , Figure 7 and Figure 8 When the load current IL flowing from the output node NO to the load 340 decreases (for example, when the load 340 is lightly loaded), the mirror current IM decreases, and the control voltage VM decreases in response to the decrease in the mirror current IM. The second PMOS transistor 351 is turned on in response to the decrease in the control voltage VM, and the capacitance of the feedback capacitor Cf is associated with the zero point of the feedback circuit 350.

[0085] In addition, the NMOS transistor 361 in the APAC 360 is turned off in response to the decrease in the control voltage VM. When the NMOS transistor 361 is turned off, the second terminal of the adjustment capacitor Cad is not connected to the ground voltage VSS, and the capacitance of the adjustment capacitor Cad is not associated with the pole of the output of the error amplifier 100.

[0086] Fig. 9 shows that when the load current consumed by the load increases Figure 7 Example of an LDO regulator.

[0087] Reference Figure 1 , Figure 7 and Fig. 9When the load current IL flowing from the output node NO to the load 340 increases (for example, when the load 340 is a heavy load), the mirror current IM increases, and the control voltage VM increases in response to the increase in the mirror current IM. The second PMOS transistor 351 is turned off in response to the increase in the control voltage VM, the feedback capacitor Cf is not coupled between the output node NO and the feedback node FN, and the capacitance of the feedback capacitor Cf is not associated with the zero point of the feedback circuit 350. Therefore, the zero point of the feedback circuit 350 can be eliminated.

[0088] In addition, the NMOS transistor 361 in the APAC 360 is turned on in response to the decrease in the control voltage VM. When the NMOS transistor 361 is turned on, the second terminal of the adjustment capacitor Cad is coupled between the first intermediate node 181 and the ground voltage VSS, and the capacitance of the adjustment capacitor Cad is associated with the pole frequency of the output of the error amplifier 100. When the adjustment capacitor Cad is coupled between the first intermediate node 181 and the ground voltage VSS, the pole frequency of the output of the error amplifier 100 is less than the pole frequency of the output of the error amplifier 100 when the adjustment capacitor Cad is not coupled between the first intermediate node 181 and the ground voltage VSS.

[0089] Fig.10 It is used to illustrate and Figure 7 A graph of the feedback factor associated with the feedback capacitor in the feedback circuit.

[0090] Reference Figure 7 and Fig.10 , when the feedback capacitor Cf is not coupled between the output node NO and the feedback node FN, the feedback factor β corresponds to Rf2 / (Rf1 + Rf2), and the feedback factor β has a constant value. When the feedback capacitor Cf is coupled between the output node NO and the feedback node FN, the slope of the feedback factor β depends on the frequency FREQ, and the feedback factor β is constant at the frequency f z has a zero point at frequency f p There is a peak somewhere.

[0091] exist Fig.10 , the horizontal axis represents frequency (Hz), and the vertical axis represents feedback factor β.

[0092] therefore, Figure 7 The LDO regulator 10 in FIG. 1 may adjust the feedback capacitor Cf associated with the zero point of the feedback circuit 350 by automatically adjusting the level of the control voltage VM based on the magnitude of the load current IL.

[0093] Fig.11 It is used to illustrate Figure 7 A graph of the gain margin of an LDO regulator.

[0094] exist Fig.11 In the graph 403, the horizontal axis represents the frequency (Hz), and the vertical axis represents the gain of the transfer function. In addition, in the graph 405, the horizontal axis represents the frequency (Hz), and the vertical axis represents the phase of the transfer function.

[0095] Reference Fig.11 , the gain margin GM may be defined as the difference between the gain at 0 dB in the curve 403 and the gain at a frequency where the phase has shifted by 180 degrees in the curve 405. When the frequency at which the gain is 0 dB is referred to as the unity gain frequency, the gain margin GM may increase as the unity gain frequency decreases. When the gain margin GM increases, a pole having a higher frequency may be located in a region where the frequency is greater than the unity gain frequency, and the stability of the LDO regulator 10 may increase.

[0096] Fig.12 FIG. 1 shows a schematic diagram of an exemplary embodiment of the present invention. Figure 7 A graph associated with the transfer function of an LDO regulator.

[0097] exist Fig.12 , reference numeral 411 indicates a transfer function of the LDO regulator 10 under a light load condition when the load current IL flowing into the load 340 is small, and reference numeral 412 indicates a transfer function of the LDO regulator 10 under a heavy load condition when the load current IL flowing into the load 340 is large.

[0098] As reference Figures 4 to 8 As described, in the case of light load, the mirror current IM decreases, and the control voltage VM decreases in response to the decrease in the mirror current IM. The second PMOS transistor 351 is turned on in response to the decrease in the control voltage VM, and the feedback capacitor Cf is coupled between the output node NO and the feedback node FN. In addition, the NMOS transistor 361 is turned off in response to the decrease in the control voltage VM. When the NMOS transistor 361 is turned off, the adjustment capacitor Cad is not connected between the first intermediate node 181 and the ground voltage VSS. Therefore, the transfer function of the LDO regulator 10 under light load conditions can be expressed by the following equation 1.

[0099] [Equation 1]

[0100]

[0101] In equation 1, g mN1 Indicates the transconductance of the error amplifier 100, g mPTR Indicates the transconductance of the power transistor 311, R EA represents the output impedance of the error amplifier 100, C EA represents the output capacitance of the error amplifier 100, 1 / g mN1indicates the impedance at the output node NO connected to the compensation capacitor Cc, and R INT Indicates the output impedance of the buffer 200.

[0102] Return to reference Fig.12 , the first pole P1L associated with the output of the error amplifier 100 has a second frequency f2, the first zero Z1L of the third node N13 of the error amplifier 100 coupled to the compensation capacitor Cc has a third frequency f3, the second pole P2L associated with the power transistor 311 has a fourth frequency f4, the second zero Z2L associated with the feedback circuit 350 has a fifth frequency f5, the third pole P3L associated with the output node NO has a sixth frequency f6, and the fourth pole P4L associated with the feedback circuit 350 has a sixth frequency f6 greater than the unity gain frequency UGF1. The unity gain frequency UGF1 with a gain of 0 dB has an eighth frequency f8.

[0103] That is, under light load conditions, the first pole P1L associated with the output of the error amplifier 100 has the second frequency f2 and the second zero Z2L associated with the feedback circuit 350 has the fifth frequency f5, and under light load conditions, stability may be increased.

[0104] As reference Figures 4 to 7 and Fig. 9 As described, under heavy load conditions, the mirror current IM increases, and the control voltage VM increases in response to the increase in the mirror current IM. The second PMOS transistor 351 is turned off in response to the increase in the control voltage VM, and the feedback capacitor Cf is not coupled between the output node NO and the feedback node FN. In addition, the NMOS transistor 361 is turned on in response to the increase in the control voltage VM. When the NMOS transistor 361 is turned on, the adjustment capacitor Cad is coupled between the first intermediate node 181 and the ground voltage VSS. Therefore, the transfer function of the LDO regulator 10 under heavy load conditions can be expressed by the following equation 2.

[0105] [Equation 2]

[0106]

[0107] When comparing Equation 2 to Equation 1, the second zero Z2L associated with the feedback circuit 350 is eliminated, and the first pole P1H associated with the output of the error amplifier 100 is associated with the adjustment capacitor Cad.

[0108] Therefore, the first pole P1H associated with the output of the error amplifier 100 has a first frequency f1, the first zero Z1H of the third node N13 of the error amplifier 100 has a third frequency f3, and the third pole P3H associated with the output node NO has a sixth frequency f6. The unity gain frequency UGF2 with a gain of 0 dB has a seventh frequency f7.

[0109] That is, in the case of heavy load, the first pole P1H associated with the output of the error amplifier 100 has a first frequency f1 less than the second frequency f2, the second zero Z2L associated with the feedback circuit 350 is eliminated, and the unit gain frequency UGF2 has a seventh frequency f7 less than the eighth frequency f8 of the unit gain frequency UGF1. That is, the LDO regulator 10 can ensure stability by eliminating the second zero associated with the feedback circuit in the case of heavy load, and can ensure sufficient gain margin by reducing the frequency of the first pole P1H in the case of heavy load to be less than the frequency of the first pole P1L in the case of light load. In addition, in the case of medium load, the stability margin can be ensured by the following measures: the zero of the error amplifier 100 is moved to the low frequency region due to the adjustment of the load Cad and the on-resistance of the NMOS transistor 631, and the zero is added due to the feedback circuit 350.

[0110] Therefore, as shown by reference numeral 413 , the first pole P1L in the light load case moves to the first pole P1H in the heavy load case, and as shown by reference numeral 414 , the unity gain frequency UGF1 in the light load case moves to the unity gain frequency UGF2 in the heavy load case.

[0111] Therefore, the LDO regulator 10 can stably operate under various load conditions and can provide the output voltage VOUT.

[0112] Fig.13 is a flow chart illustrating a method of operating an LDO regulator according to example embodiments.

[0113] Reference Figures 1 to 13 In the method of operating the LDO regulator 10, the LDO regulator 10 includes: an error amplifier 100, which amplifies the difference between a reference voltage VREF and a feedback voltage VF to output a first error voltage EV1; a buffer 200, which is connected to the output terminal of the error amplifier 100 at a first intermediate node 181, and buffers the first error voltage EV1 and outputs a second error voltage EV2; a power transistor 311, which receives the second error voltage EV2 at a second intermediate node 183; and a monitoring circuit 330, which is connected to the second intermediate node 183, and the monitoring circuit 330 monitors the load current IL provided from the power transistor 311 to the load (operation S110).

[0114] The monitoring circuit 330 generates a control voltage VM associated with the magnitude of the load current IL based on the monitored load current (operation S120 ).

[0115] The APAC 360 connected between the first intermediate node 181 and the ground voltage VSS may adaptively adjust a pole frequency of the output of the error amplifier 100 based on the control voltage VM (operation S130 ).

[0116] The APAC 360 may include a regulating capacitor Cad and an NMOS transistor 361 connected in series between the first intermediate node 181 and the ground voltage VSS. The NMOS transistor 361 may be selectively turned on / off in response to the control voltage VM to selectively connect the regulating capacitor Cad between the first intermediate node 181 and the ground voltage VSS. When the regulating capacitor Cad is coupled between the first intermediate node 181 and the ground voltage VSS, the pole frequency of the output of the error amplifier 100 is less than the pole frequency of the output of the error amplifier 100 when the regulating capacitor Cad is not coupled between the first intermediate node 181 and the ground voltage VSS.

[0117] Fig.14 is a block diagram illustrating an example of an electronic device including a power management integrated circuit (PMIC) according to example embodiments.

[0118] Reference Fig.14 , the electronic device 20 may include a PMIC 500 and a consumer group 560. The consumer group 560 may include a plurality of consumers 570a to 570n. In some example embodiments, the consumers 570a to 570n may be chips, modules, or other circuits in the electronic device 20. For example, the consumers 570a to 570n may be a modem, an application processor, a memory, a display, and / or other circuits. The consumers 570a to 570n may also include an operation block, a functional block, or an IP block in the electronic device 230. These examples include a multimedia block in an application processor, a storage controller, or other logic circuits. The consumers 570a to 570n may be referred to as, for example, a consumption block or a load.

[0119] The PMIC 500 may receive a battery voltage VBAT from a power source (e.g., an external power source) and generate a plurality of output voltages V1 to Vn for driving consumers 570a to 570n. The PMIC 500 may include at least one first regulator 510, a plurality of second regulators 520a to 520n, and a controller 540. The at least one first regulator 510 and the second regulators 520a to 520n may be connected to each other, for example, in a multi-step structure.

[0120] The first voltage regulator 510 may receive a battery voltage VBAT from an external voltage source (eg, a battery) and generate a conversion voltage CV according to the received battery voltage VBAT. The first voltage regulator 510 may adjust a switch timing associated with the conversion voltage CV based on a voltage control signal VCTL.

[0121] In some example embodiments, when at least one of the consumers 570a to 570n is powered off (and therefore at least one of the second regulators 520a to 520n is powered off), the conversion voltage CV may be reduced. In some example embodiments, although all of the consumers 570a to 570n are powered on, the conversion voltage CV may also be changed according to the operating state of the consumers 570a to 570n. For example, when one of the consumers 570a to 570n is in a standby or sleep state (and therefore the output current of the corresponding one of the consumers 570a to 570n is reduced), the conversion voltage CV may be reduced.

[0122] In some example embodiments, the first voltage regulator 510 may be a switching regulator that uses energy storage components (e.g., capacitors and inductors) and an output stage to generate a conversion voltage CV. For example, the first voltage regulator 510 may be a DC-DC converter. The first voltage regulator 510 is hereinafter referred to as a DC-DC converter. The DC-DC converter 510 may be a step-up converter (e.g., a boost converter) that converts a low battery voltage VBAT into a high conversion voltage CV, or a step-down converter (e.g., a buck converter) that converts a high battery voltage VBAT into a low conversion voltage CV.

[0123] The second voltage regulators 520a to 520n may be commonly connected to the DC-DC converter 510, receive the conversion voltage CV from the DC-DC converter 110, and generate a plurality of output voltages V1 to Vn according to the conversion voltage CV. The output voltages V1 to Vn may be different from each other and, for example, may be less than the conversion voltage CV. The second voltage regulators 520a to 520n may be, for example, linear regulators, such as LDO regulators. For the purpose of illustration, the second voltage regulators 520a to 520n are referred to as LDO regulators below.

[0124] Regardless of the input and output voltages, the DC-DC converter 510 may have substantially the same efficiency. Each of the LDO regulators 520a to 520n may have a variable efficiency with respect to the input and output voltages. The efficiency of each of the LDO regulators 520a to 520n may correspond to a ratio of each of the output voltages V1 to Vn relative to the conversion voltage VC. For example, the efficiency of the LDO regulator 520a may be a ratio of the output voltage V1 to the conversion voltage VC (e.g., V1 / Vout). Therefore, reducing the difference between the input voltage and the output voltage of the LDO regulators 520a to 520n may be performed to improve the efficiency of each of the LDO regulators 520a to 520n.

[0125] In the case where the difference between the input voltage and the output voltage of the LDO regulators 520a to 520n is large (e.g., higher than a predetermined level, or alternatively, a desired level), when the DC-DC converter 510 is in front of the LDO regulators 520a to 520n and the output of the DC-DC converter 510 is used as the input of each of the LDO regulators 520a to 520n, the conversion efficiency of the entire PMIC 500 can be improved. Therefore, for example, in the case where the output voltages V1 to Vn of the LDO regulators 520a to 520n are different from each other, when the DC-DC converters are respectively arranged in front of the LDO regulators 520a to 520n, the conversion efficiency of the PMIC 500 can be improved.

[0126] In some example embodiments, the LDO regulators 520a to 520n may be grouped, and the DC-DC converter 510 may be shared by the grouped LDO regulators 520a to 520n to reduce the area and manufacturing cost of the PMIC 500. In some example embodiments, when the LDO regulators 520a to 520n and the DC-DC converter are arranged separately, the difference between the input voltage and the output voltage of the LDO regulators 520a to 520n may be large (e.g., higher than a predetermined level, or alternatively, a desired level). Therefore, the conversion efficiency of the PMIC 500 may be reduced.

[0127] However, according to the present example embodiment, the first voltage regulator 510 may adjust the switching timing associated with the conversion voltage CV based on the voltage control signal VCTL, thereby improving the conversion efficiency of the PMIC 500 .

[0128] The controller 540 may generate a voltage control signal VCTL for adjusting a switching timing associated with a conversion voltage CV output from the DC-DC converter 510. The voltage control signal VCTL may be provided to the DC-DC converter 510.

[0129] Each of the LDO regulators 520a to 520n may adopt Figure 7 Therefore, each of the LDO regulators 520a to 520n may include an error amplifier, a buffer, a power transistor, a feedback circuit, a monitoring circuit, and / or an APAC.

[0130] The monitoring circuit can generate a control voltage by monitoring the load current provided from the output node to the load, and the APAC can adjust the pole frequency of the output of the error amplifier by selectively coupling the adjustment capacitor between the output terminal of the error amplifier and the ground voltage in response to the control voltage.

[0131] Fig.15 is a diagram showing a method according to an example embodiment Fig.14 A circuit diagram of an example of a DC-DC converter.

[0132] Reference Fig.15 The DC-DC converter (switching regulator) 510 may include a gate driver 511 , a first driving transistor 512 , a second driving transistor 513 , an inductor 514 , a capacitor C1 , a current sensor 515 and / or an on-time generator 516 .

[0133] The first drive transistor 512 is connected between the battery voltage VBAT and the switch node SN, and has a gate receiving the first drive control signal GP1. The first drive transistor 512 can be a PMOS transistor. The second drive transistor 513 is connected between the switch node SN and the ground voltage VSS, and has a gate receiving the second drive control signal GN. The second drive transistor 513 can be an NMOS transistor.

[0134] The inductor 514 is connected between the switch node SN and the first output node NO1. The inductor current IND flows from the switch node SN to the first output node NO1, and the capacitor C1 is coupled between the first output node NO1 and the ground voltage VSS. The conversion voltage CV is provided at the first output node NO1.

[0135] The current sensor 515 senses the inductor current IND flowing from the switch node SN to the first output node NO1 to generate a current signal CS based on the sensed current ISEN and provides the current signal CS to the on-time generator 516 .

[0136] The on-time generator 516 generates an on-time signal TON that determines the on-time of the first driving transistor 512 and the second driving transistor 513 based on the current signal CS and the control voltage signal VCTL, and provides the on-time signal TON to the gate driver 511. The gate driver 511 may determine the activation interval of the first driving control signal GP1 and the second driving control signal GN, and may provide the first driving control signal GP1 and the second driving control signal GN to the first driving transistor 512 and the second driving transistor 513, respectively.

[0137] Based on the first drive control signal GP1 and the second drive control signal GN, the first drive transistor 512 and the second drive transistor 513 are turned on / off respectively, and the magnitude of the inductor current IND can be determined thereby. Based on the first drive control signal GP1 and the second drive control signal GN, the first drive transistor 512 and the second drive transistor 513 are turned on / off complementarily.

[0138] The first driving transistor 512 and the second driving transistor 513 charge the battery voltage VBAT in the inductor 514 in response to the first driving control signal GP1 and the second driving control signal GN having the first logic level to increase the level of the conversion voltage CV. The first driving transistor 512 and the second driving transistor 513 discharge the voltage charged in the inductor 514 in response to the first driving control signal GP1 and the second driving control signal GN having the second logic level to reduce the level of the conversion voltage CV.

[0139] Fig.16 is a block diagram illustrating a communication device according to an example embodiment.

[0140] Reference Fig.16 , the communication device 600 may include an antenna 610, and may communicate with another communication device in a wireless communication system by transmitting / receiving signals via the antenna 610, and may be referred to as a wireless communication device.

[0141] The wireless communication system (in which the communication device 600 communicates with the corresponding communication device) can be a wireless communication system using a cellular network (for example, a next-generation communication system, a fifth-generation (5G) wireless system, a long-term evolution (LTE) system, an LTE-advanced system, a code division multiple access (CDMA) system, a global system for mobile communications (GSM), etc.), a wireless local area network (WLAN) system, or another arbitrary wireless communication system.

[0142] like Fig.16As shown, the communication device 600 may include an antenna 610 , a radio frequency integrated circuit (RFIC) 620 , and / or a signal processor 670 , and the antenna 610 and the RFIC 620 may be connected to each other via a feed line 615 .

[0143] In the current specification, the antenna 610 may be referred to as an antenna module, and the structure including the antenna 610 and the feed line 615 may be generally referred to as an antenna module. In addition, the antenna 610, the feed line 615, and the RFIC 620 may be generally referred to as an RF system or an RF device.

[0144] RFIC 620 may provide a signal to antenna 610 via feed line 615, wherein the signal is generated by processing a transmission signal TX from signal processor 670 in a transmit mode, and may provide a received signal RF to signal processor 670 by processing a signal sent from antenna 610 via feed line 615 in a receive mode. For example, RFIC 620 may include a transmitter, which may include a filter, a mixer, and / or a power amplifier (PA). In addition, RFIC 620 may include a receiver, which may include a filter, a mixer, and / or a low noise amplifier (LNA). In some example embodiments, RFIC 620 may include multiple transmitters and multiple receivers, or may include a transceiver that combines a transmitter with a receiver. In some example embodiments, RFIC 620 may include multiple transceivers.

[0145] The signal processor 670 may generate a transmission signal TX by processing a signal including information to be transmitted, and may generate a signal including information by processing a received signal RX. For example, the signal processor 670 may include an encoder, a modulator, and / or a digital-to-analog converter (DAC) to generate a transmission signal TX. In addition, the signal processor 670 may include an analog-to-digital converter (ADC), a demodulator, and / or a decoder to process the received signal RX. The signal processor 670 may generate a control signal for controlling the RFIC 620. The signal processor 300 may set a transmission mode or a reception mode, or adjust the electrical power and gain of an element included in the RFIC 620 via a control signal.

[0146] In some example embodiments, the signal processor 670 may include one or more cores and a memory storing instructions executed by the one or more cores, and at least a portion of the signal processor 670 may include a software block stored in the memory. In some example embodiments, the signal processor 670 may include a logic circuit designed by logic synthesis, and at least a portion of the signal processor 670 may include a hardware block implemented as a logic circuit.

[0147] Wireless communication systems can use high-frequency bands for large data transmission. For example, 5G cellular systems (or 5G wireless systems), formally designated as IMT-2020 by the International Telecommunication Union (ITU), use millimeter waves (mmWave) of 24 GHz or greater.

[0148] The antenna 610 according to the example embodiment may be configured to transmit / receive (or radiate electromagnetic waves in the RF band) signals in the RF band used for data transmission of millimeter waves, and the antenna 610 may be configured to transmit / receive signals in a relatively low frequency band compared to the RF band (or radiate electromagnetic waves in the low frequency band). The antenna 610 may be a multi-band antenna capable of supporting RF signal transmission / reception in at least two frequency bands. In addition, in addition to supporting multiple frequency bands, the antenna 610 may also be configured to perform multi-polarization radiation of electromagnetic waves.

[0149] Fig.17 According to an example embodiment Fig.16 Block diagram of the antenna and RFIC in FIG.

[0150] Fig.17 An antenna 610 including two antenna patches of a dual-feed, dual-polarization, and 3-stack structure and an RFIC 620 including first to fourth transceivers 641 to 644 are shown.

[0151] The RFIC 620 may be connected to the antenna 610 via four feed lines corresponding to the four ports of the antenna 610. For example, an antenna module including the antenna 610 and the feed line 616 may be disposed on the RFIC 620, and at least one connection may be formed on the upper surface of the RFIC 620 and the lower surface of the antenna module. The antenna 610 may receive a differential signal from the RFIC 620 via four feed lines 616 connected to four power feed points in the first antenna patch PC1 and the second antenna patch PC2, respectively. To this end, a pair of transceivers included in the RFIC 620 may generate one differential signal, and accordingly, the four transceivers 641 to 644 may generate two differential signals.

[0152] The switch / duplexer 630 can connect or disconnect the output terminals or input terminals of the four transceivers (ie, the first to fourth transceivers 641 to 644) to or from the four feeding lines 616 according to the transmission mode or the reception mode. Fig.17In the configuration shown, in some example embodiments, the first transceiver 641 and the second transceiver 642 can be connected to the first antenna patch PC1 via the switch / duplexer 630 to perform signal transmission / reception in the first frequency band Band1, and the third transceiver 643 and the fourth transceiver 644 can be connected to the second antenna patch PC2 and the third antenna patch PC3 via the switch / duplexer 630 to perform signal transmission / reception in the second frequency band Band2.

[0153] The PMIC 650 may include first to fourth LDO regulators 651 to 654. The first to fourth LDO regulators 651 to 654 may adjust an input voltage VIN to generate output voltages Vout1 to Vout4, respectively, and may provide the output voltages Vout1 to Vout4 to corresponding ones of the first to fourth LDO regulators 651 to 654.

[0154] Each of the first to fourth LDO regulators 651 to 654 may adopt Figure 7 LDO regulator 10. Therefore, each of the first to fourth LDO regulators 651-654 may include an error amplifier, a buffer, a power transistor, a feedback circuit, a monitoring circuit and / or an APAC. The monitoring circuit may generate a control voltage by monitoring a load current provided from an output node to a load, and the APAC may adjust a pole frequency of the output of the error amplifier by selectively coupling an adjustment capacitor between an output terminal of the error amplifier and a ground voltage in response to the control voltage.

[0155] Fig.18 is a block diagram schematically illustrating a mobile device according to an example embodiment.

[0156] Reference Fig.18 , the mobile device 700 may include a battery 710 , a PMIC 720 , an application processor (AP) 741 , an input / output interface unit (or input / output interface) 742 , a random access memory (RAM) 743 , an analog baseband chipset (ABB) 744 , a display device 745 and / or a nonvolatile memory 746 .

[0157] The PMIC 720 converts an input voltage VIN provided from the battery 710 into output voltages Vout1 to Vout6 having various levels and provides the output voltages Vout1 to Vout6 to various load devices. In an example embodiment, the RMIC 720 may include a plurality of LDO regulators LDO1 ˜LDOi.

[0158] Each of the multiple LDO regulators LDO1~LDOi can use Figure 7 LDO regulator 10. Therefore, each of the plurality of LDO regulators LDO1-LDOi may include an error amplifier, a buffer, a power transistor, a feedback circuit, a monitoring circuit and / or an APAC. The monitoring circuit may generate a control voltage by monitoring a load current provided from an output node to a load, and the APAC may adjust a pole frequency of the output of the error amplifier by selectively coupling an adjustment capacitor between an output terminal of the error amplifier and a ground voltage in response to the control voltage.

[0159] Various forms of packages may be used to mount the mobile device 700. For example, the PMIC 720, the AP 741, the input / output interface unit 742, the RAM 743, the ABB 744, the display device 745, and / or the nonvolatile memory 746 may be mounted using a package, examples of which are package on package (PoP), ball grid array (BGA), chip scale package (CSP), plastic lead chip carrier (PLCC), plastic dual in-line package (PDIP), wafer packaged die, wafer-shaped die, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline integrated circuit (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), thin quad flat package (TQFP), system-in-package (SIP), multi-chip package (MCP), wafer-level manufacturing package (WFP), and wafer-level processing stack package (WSP).

[0160] Fig.19 is a diagram illustrating an example of a communication device according to an exemplary embodiment.

[0161] In detail, Fig.19 An example is shown in which various wireless communication devices communicate with each other using WLAN in a wireless communication system. Fig.19 Each wireless communication device shown may include a multi-band and multi-polarization antenna in which a plurality of antenna patches are stacked, and an RFIC that provides differential signals to the multi-band and multi-polarization antenna.

[0162] The home gadget 821, the home appliance 822, the entertainment device 823, and the access point (AP) 810 may configure an Internet of Things (IoT) network system. Each of the home gadget 821, the home appliance 822, the entertainment device 823, and / or the AP 810 may include a transceiver according to one or more example embodiments as a component. The home gadget 821, the home appliance 822, and the entertainment device 823 may wirelessly communicate with the AP 810, or may wirelessly communicate with each other.

[0163] Example embodiments may be applied to various systems including a memory module and a memory controller including an ECC engine.

[0164] Any of the elements disclosed above may include or be implemented in a processing circuit, which may be, for example, hardware including a logic circuit; a hardware / software combination, for example, a processor that executes software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0165] While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims.

Claims

1. A low dropout LDO regulator, include: an error amplifier configured to compare a reference voltage and a feedback voltage to generate a first error voltage based on the comparison; a buffer connected to an output terminal of the error amplifier, the buffer being configured to buffer the first error voltage to output a second error voltage; a power transistor including a gate coupled to an output terminal of the buffer, the power transistor configured to adjust an input voltage based on the second error voltage to provide an output voltage to an output node; a feedback circuit connected between the output node and a ground voltage, wherein the feedback circuit is configured to divide the output voltage to provide the feedback voltage; a monitoring circuit connected to the output terminal of the buffer, the monitoring circuit being configured to: receive the second error voltage from the output terminal of the buffer, and generate a control voltage associated with a load current flowing from the output node to the load based on the second error voltage and the input voltage; as well as An adaptive pole adjustment circuit APAC is connected between the output terminal of the error amplifier and the ground voltage, and the APAC is configured to selectively connect an adjustment capacitor between the output terminal of the error amplifier and the ground voltage in response to the control voltage.

2. The LDO regulator according to claim 1, in, The feedback circuit is configured to selectively connect a feedback capacitor between the output node and a feedback node in response to the control voltage.

3. The LDO regulator according to claim 1, in, The monitoring circuit comprises: a first p-channel metal oxide semiconductor (PMOS) transistor connected between the input voltage and a first node, the first PMOS transistor having a gate receiving the second error voltage; and a monitoring resistor connected between the first node and the ground voltage, The first PMOS transistor is configured to provide a mirror current corresponding to the load current to the first node, and The monitoring circuit is configured to provide a control voltage corresponding to the mirror current at the first node.

4. The LDO regulator according to claim 3, in, A current driving capability of the first PMOS transistor is smaller than a current driving capability of the power transistor.

5. The LDO regulator according to claim 3, in, The feedback circuit comprises: a first feedback resistor connected between the output node and a feedback node; a second feedback resistor connected between the feedback node and the ground voltage; and a feedback capacitor and a second PMOS transistor connected in parallel with the first feedback resistor between the output node and the feedback node, and The feedback capacitor and the second PMOS transistor are connected in series between the output node and the feedback node.

6. The LDO regulator according to claim 5, in: the feedback capacitor comprising a first terminal coupled to the output node and a second terminal coupled to the second PMOS transistor; and The second PMOS transistor includes a source coupled to the second terminal of the feedback capacitor, a drain coupled to the feedback node, and a gate for receiving the control voltage.

7. The LDO regulator according to claim 6, in, The second PMOS transistor is configured to selectively connect the feedback capacitor between the output node and the feedback node in response to the control voltage.

8. The LDO regulator according to claim 6, in: When the load current supplied to the load decreases, the mirror current decreases, and the second PMOS transistor is turned on in response to the control voltage; and When a load current supplied to the load increases, the mirror current increases, and the second PMOS transistor is turned off in response to the control voltage.

9. The LDO regulator according to claim 8, in: When the second PMOS is turned on, the second terminal of the feedback capacitor is coupled to the second node, and the capacitance of the feedback capacitor is associated with the zero point of the feedback circuit; and When the second PMOS is turned off, the second terminal of the feedback capacitor is floated, and a zero point of the feedback capacitor is eliminated.

10. The LDO regulator according to claim 1, in, The APAC includes: the regulating capacitor having a first terminal connected to the output terminal of the error amplifier and a second terminal connected to the first node; and An n-channel metal oxide semiconductor (NMOS) transistor is connected between the first node and the ground voltage, and includes a gate for receiving the control voltage.

11. The LDO regulator according to claim 10, in: When a load current supplied to the load decreases, the NMOS transistor is turned off in response to a decrease in the level of the control voltage; and When a load current supplied to the load increases, the NMOS transistor is turned on in response to an increase in a level of the control voltage.

12. The LDO regulator according to claim 11, in: When the NMOS is turned off, the second terminal of the adjustment capacitor is floating, and the capacitance of the adjustment capacitor has no correlation with the pole frequency of the output of the error amplifier; and When the NMOS is turned on, the second terminal of the adjustment capacitor is coupled to the ground voltage, and the capacitance of the adjustment capacitor is associated with a pole frequency of the output of the error amplifier.

13. The LDO regulator according to claim 1, further comprising: include: a compensation capacitor connected between an internal node of the error amplifier and the output node; as well as a bias voltage generator configured to generate a first bias voltage and a second bias voltage based on a reference current, and The error amplifier includes a negative input terminal for receiving the feedback voltage and a positive input terminal for receiving the reference voltage.

14. The LDO regulator according to claim 13, in, The error amplifier comprises: A first p-channel metal oxide semiconductor (PMOS) transistor connected between the input voltage and the first node; a second PMOS transistor connected between the input voltage and a second node, the second PMOS transistor having a gate coupled to the gate of the first PMOS transistor; a third PMOS transistor connected between the first node and a third node; a fourth PMOS transistor connected between the second node and a fourth node, the fourth PMOS transistor having a gate coupled to the gate of the third PMOS transistor; a first n-channel metal oxide semiconductor (NMOS) transistor connected between the third node and the ground voltage, the first NMOS transistor having a gate coupled to the third node; a second NMOS transistor connected between the fourth node and the ground voltage, the second NMOS transistor having a gate coupled to the third node; a third NMOS transistor connected between the first node and the fifth node, the third NMOS transistor having a gate receiving the reference voltage; a fourth NMOS transistor connected between the second node and the fifth node, the fourth NMOS transistor having a gate receiving the feedback voltage; and a current source connected between the fifth node and the ground voltage, wherein the gate of the first PMOS transistor and the gate of the second PMOS transistor receive the first bias voltage, and The gate of the third PMOS transistor and the gate of the fourth PMOS transistor receive the second bias voltage.

15. The LDO regulator according to claim 14, in, The compensation capacitor is connected between the third node and the output node.

16. The LDO regulator according to claim 1, in, The buffer comprises: a first p-channel metal oxide semiconductor (PMOS) transistor connected between the input voltage and a first node corresponding to an output terminal of the buffer, the first PMOS transistor having a gate coupled to the first node; a first resistor connected in parallel with the first PMOS transistor between the input voltage and the first node; and A first n-channel metal oxide semiconductor (NMOS) transistor is connected between the first node and the ground voltage, and has a gate receiving the first error voltage.

17. A power management integrated circuit PMIC, include: at least one switching regulator configured to generate a conversion voltage based on a battery voltage; a plurality of low dropout (LDO) regulators configured to generate a plurality of output voltages based on the conversion voltage, so as to provide the plurality of output voltages to a plurality of consumers respectively; and a controller configured to generate a voltage control signal and provide the voltage control signal to the at least one switching regulator, the voltage control signal being used to adjust a switching timing associated with the conversion voltage output from the at least one switching regulator, Wherein, each of the plurality of LDO regulators comprises: an error amplifier configured to compare a reference voltage and a feedback voltage to generate a first error voltage based on the comparison; a power transistor configured to adjust the conversion voltage based on a second error voltage to provide a corresponding output voltage of the plurality of output voltages to an output node, the second error voltage being based on the first error voltage; and An adaptive pole adjustment circuit APAC is connected between the output terminal of the error amplifier and the ground voltage, and the APAC is configured to selectively connect an adjustment capacitor between the output terminal of the error amplifier and the ground voltage in response to the second error voltage and a control voltage generated based on the conversion voltage.

18. The PMIC according to claim 17, further comprising: include: a buffer connected to an output terminal of the error amplifier, the buffer being configured to buffer the first error voltage to output the second error voltage; a feedback circuit connected between the output node and the ground voltage, the feedback circuit being configured to divide the output voltage to provide the feedback voltage; as well as A monitoring circuit is connected to the output terminal of the buffer, and is configured to receive the second error voltage from the output terminal of the buffer and generate the control voltage based on the second error voltage and the conversion voltage.

19. The PMIC according to claim 17, in, The at least one switching regulator comprises: A first driving transistor connected between the battery voltage and a switch node, the first driving transistor having a gate receiving a first driving control signal; a second driving transistor connected between the switch node and the ground voltage, the second driving transistor having a gate for receiving a second driving control signal; an inductor connected between the switch node and a first output node providing the conversion voltage; a current sensor configured to: sense an inductor current flowing into the inductor to provide a current signal; an on-time generator configured to: generate an on-time signal based on the current signal and the control voltage signal, wherein the on-time signal determines the on-time of the first driving transistor and the second driving transistor; and The gate driver is configured to generate the first drive control signal and the second drive control signal based on the on-time signal.

20. A low dropout LDO regulator, include: an error amplifier configured to compare a reference voltage and a feedback voltage to generate a first error voltage based on the comparison; a buffer connected to an output terminal of the error amplifier, the buffer being configured to buffer the first error voltage to output a second error voltage; a power transistor including a gate coupled to an output terminal of the buffer, the power transistor configured to adjust an input voltage based on the second error voltage to provide an output voltage to an output node; a feedback circuit connected between the output node and a ground voltage, wherein the feedback circuit is configured to divide the output voltage to provide the feedback voltage; a monitoring circuit connected to the output terminal of the buffer, the monitoring circuit being configured to: receive the second error voltage from the output terminal of the buffer, and generate a control voltage associated with a load current flowing from the output node to the load based on the second error voltage and the input voltage; and an adaptive pole adjustment circuit APAC connected between the output terminal of the error amplifier and the ground voltage, wherein the APAC is configured to selectively connect an adjustment capacitor between the output terminal of the error amplifier and the ground voltage in response to the control voltage, The feedback circuit is configured to selectively connect a feedback capacitor between the output node and a feedback node in response to the control voltage. Wherein, the monitoring circuit comprises: a first p-channel metal oxide semiconductor (PMOS) transistor connected between the input voltage and a first node, the first PMOS transistor having a gate receiving the second error voltage; and a monitoring resistor connected between the first node and the ground voltage, The first PMOS transistor is configured to provide a mirror current corresponding to the load current to the first node, and The monitoring circuit is configured to provide a control voltage corresponding to the mirror current at the first node.

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