A verification method for a multi-layer integrated circuit system

Abstract

The present invention relates to the technical field of integrated circuits, and discloses a verification method for a multi-layer integrated circuit system. When verifying and analyzing the multi-layer integrated circuit system, the present invention generates a system netlist synthesis file to express the layout relationship of chips on each stacking layer of the multi-layer integrated circuit system and the connection relationship between each stacking layer, and then generates a three-dimensional layout according to the input stacking layer layout, verifies the three-dimensional layout according to the rules in the system rule synthesis file and the system netlist synthesis file, to determine whether there are violations that do not meet the requirements in the three-dimensional layout, and realizes the verification and analysis of the multi-layer integrated circuit system.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a verification method for a multi-layer integrated circuit system. Background Art

[0002] As the integration of integrated circuits becomes higher and higher, the development of integrated circuit technology in accordance with "Moore's Law" is slowing down, and the importance of packaging technology is highlighted, especially 2.5D integrated circuits (2.5D-IC) and 3D integrated circuits (3D-IC) using through silicon via (TSV) technology and their three-dimensional system integration-related advanced packaging technology. Because it can greatly shorten the chip signal transmission distance, improve bandwidth performance, reduce power consumption and save area, and can also vertically integrate heterogeneous chips to obtain higher processing speed and bandwidth, it has become an important technology for integrated circuits to break through and continue "Moore's Law".

[0003] Among them, 2.5D integrated circuits usually refer to semiconductor integrated systems with key features such as through silicon vias (TSV), redistribution layers (RDL), silicon interposers, and die-to-die interconnections; it has many advantages such as reducing chip size, increasing bandwidth, reducing power consumption, design reuse, and heterogeneous chip integration. Figure 1 Schematic diagram of 2.5D integrated circuit. 3D integrated circuit usually refers to a three-dimensional integrated system that no longer uses a passive silicon interposer with built-in through silicon vias (TSV), but directly stacks active chips vertically interconnected through built-in TSV. It has the characteristics of high integration, low power consumption, high bandwidth, small area, short interconnection lines, and support for heterogeneous integration. Figure 2 The schematic diagram of 3D integrated circuit. The three-dimensional system integration technology mainly includes various chip stacking technologies in the front end: such as chip-to-chip, chip-to-wafer, and wafer-to-wafer stacking technologies; and back-end chip system packaging integration technologies: such as the industry's mainstream CoWoS (Chip-on-Wafer-on-Substrate) packaging technology, integrated fan-out (InFO, Integrated Fan-Out) technology and system integrated chip SoIC (System-on-Integrated-Chips) technology.

[0004] Although 2.5D and 3D integrated circuit systems can continue, expand and surpass Moore's Law, the same advanced 2.5D integrated circuits and 3D integrated circuits have higher requirements for integration and packaging technology. For example, the chip stacking technology will become more difficult as the number of stacking layers increases, and the chip thinning process is more required; the three-dimensional integrated circuit has higher and higher requirements for the fine processing and manufacturing technology of through silicon vias (TSV) vertical interconnect devices, and its introduction will also increase the complexity of chip design; homogeneous and heterogeneous requirements also put forward new requirements for system integration technology. Therefore, the current three-dimensional integrated circuit technology is not mature enough, and its system heat dissipation, analysis, testing and verification technology are facing new challenges. However, existing commercial EDA tools and design methods can only support physical design rule checking (DRC) and logic function verification in single-chip systems, and cannot be effectively applied to three-dimensional chip integration systems. In particular, when chips or wafers are stacked and bonded together, physical defects such as micro-bumps, misaligned offsets, dangling and missing parts are prone to occur, and even redistribution layer (RDL) logic connection errors may occur. This may cause the three-dimensional integrated system to malfunction or even fail. To fully utilize three-dimensional integration and packaging technology, it is necessary to develop new EDA tools and explore new design methods and processes. Summary of the invention

[0005] In view of the shortcomings of the background technology, the present invention provides a verification method for a multi-layer integrated circuit system to detect and verify design violations in vertical interconnection, stacking and layout and wiring of chips in 2.5D or 3D integrated circuits.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions: a verification method of a multi-layer integrated circuit system, comprising the following steps:

[0007] S1: verify whether the chip and device layout and schematic diagram of each stacked layer of the multi-layer integrated circuit system conform to the design rules. If they conform, execute step S2. Otherwise, modify the stacked layers that do not conform to the design rules, and then re-execute step S1 until each stacked layer of the multi-layer integrated circuit system conforms to the design rules.

[0008] S2: Generate a system netlist synthesis file, wherein the system netlist synthesis file is used to describe and define the layout relationship of the chips on each stacking layer of the multi-layer integrated circuit system and the connection relationship between each stacking layer;

[0009] S3: synthesize and package the layout of each stacked layer of the integrated circuit system into an overall three-dimensional layout;

[0010] S4: generating a system rule synthesis file, wherein the system rule synthesis file is used as a verification standard for verifying the three-dimensional layout;

[0011] S5: Verify the three-dimensional layout to verify whether the three-dimensional layout meets the verification standard in the system rule synthesis file.

[0012] In some implementations, the steps of generating the system rule synthesis file in step S2 are specifically as follows:

[0013] S20: taking the netlist file of the chip or device on each stacking layer as input, extracting the chip netlist, the logic netlist of the silicon interposer with built-in passive TSV or the netlist of the TSV interconnected active chip and the netlist of the packaging substrate, wherein the chip netlist at least includes the signal port, clock port, power port and ground port information of the chip, the logic netlist of the silicon interposer with built-in passive TSV or the netlist of the TSV interconnected active chip at least includes the interconnection relationship information from the micro-bump to the C4-bump, and the netlist of the packaging substrate at least includes the distribution information of the BGA ball on the packaging substrate;

[0014] S21: taking a standard AIF format file of a chip or device on each stacking layer as input, extracting bump information on the three-dimensional integrated circuit system, wherein the bump information at least includes a name and location information of the bump;

[0015] S22: taking the layout / layout file of the chips and devices on each stacking layer as input, and extracting at least the position, size and orientation information of the chips or devices;

[0016] S23: Generate a system netlist synthesis file based on the information extracted in steps S20, S21 and S22.

[0017] In some implementations, the steps of generating a three-dimensional layout in step S3 are specifically as follows:

[0018] S30: defining a stacking position of each stacking layer in the multi-layer integrated circuit system;

[0019] S31: searching the metal layer information and the identification layer information on each stacking layer in the system netlist synthesis file to identify the stacking layer, and stacking the identified stacking layers according to the stacking position of each stacking layer to generate a three-dimensional layout.

[0020] In some implementations, the system rule synthesis file in step S4 includes a chip stacking and placement description file, physical design rules, a wiring relationship file, and a layout identification file.

[0021] In a certain embodiment, the step of verifying the three-dimensional layout in step S5 is as follows: performing physical rule checking and layout schematic comparison checking on the multi-layer integrated circuit system according to the system rule synthesis file, the physical rule checking includes checking whether the placement position, placement interval and placement spacing of chips and devices meet the requirements, including checking whether the bumps on each stacked layer are misplaced, and the layout schematic comparison checking is to compare and check the three-dimensional layout with the system netlist synthesis file to determine whether the bumps used to connect the stacked layers on the multi-layer integrated circuit system are open or short-circuited.

[0022] In a certain embodiment, when performing physical rule checking and layout schematic comparison checking in step S5, if the placement position, placement interval and placement spacing of the chip or device on the three-dimensional layout do not meet the requirements, the bumps on the stacked layer are misplaced, and the bumps used to connect the stacked layers are open or short-circuited, a corresponding error message is output.

[0023] In a certain implementation manner, based on the error information, an EDA tool is first used to analyze and modify the three-dimensional layout, and then step S3 is re-executed on the modified three-dimensional layout.

[0024] Compared with the prior art, the present invention has the following beneficial effects: when verifying and analyzing a multi-layer integrated circuit system, the present invention generates a system netlist synthesis file to describe the layout relationship of the chips on each stacked layer of the multi-layer integrated circuit system and the connection relationship between each stacked layer, and then generates a three-dimensional layout according to the input stacked layer layout, verifies the three-dimensional layout according to the rules in the system rule synthesis file and the system netlist synthesis file, to determine whether there are any violations that do not meet the requirements in the three-dimensional layout, and realizes the verification and analysis of the multi-layer integrated circuit system. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A system block diagram of a 2.5D integrated circuit using a silicon interposer;

[0026] Figure 2 This is a system block diagram of a 2.5D integrated circuit using an integrated fan-out InFO package;

[0027] Figure 3 A system structure diagram of a 3D integrated circuit system;

[0028] Figure 4 It is a schematic diagram of the I / O bump interconnection of the 2.5 integrated circuit system;

[0029] Figure 5 A schematic diagram of the I / O bump interconnection of a 3D integrated circuit system;

[0030] Figure 6A schematic diagram of an inter-layer interconnection interface of a 2.5D or 3D integrated circuit system;

[0031] Figure 7 is a flow chart of the present invention;

[0032] Figure 8 A flow chart for generating a system netlist synthesis file for a 2.5D integrated circuit system;

[0033] Fig. 9 A flow chart for generating a system netlist synthesis file for a 3D integrated circuit system;

[0034] Fig.10 A schematic diagram of the synthesis of the three-dimensional layout of a 2.5D integrated circuit system based on CoWoS packaging;

[0035] Fig.11 A schematic diagram of the synthesis of the three-dimensional layout of a 2.5D integrated circuit system based on an integrated fan-out InFO package;

[0036] Fig.12 A schematic diagram of a composite three-dimensional layout of a 3D integrated circuit system;

[0037] Fig.13 A synthesis schematic diagram of a system rule synthesis file for a multi-layer integrated circuit system;

[0038] Fig.14 Schematic diagram of the distribution of chips on the stacking layer;

[0039] Fig.15 Schematic diagram for bump error design of 3D multi-layer integrated circuit system;

[0040] Fig.16 Schematic diagram of interconnection errors designed for 2.5D multi-layer integrated circuit systems. DETAILED DESCRIPTION

[0041] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0042] Reference Figure 1 In a 2.5D integrated circuit system based on a silicon interposer, its stacking layers mainly include a packaging substrate, a silicon interposer packaged on the packaging substrate, and a chip packaged on the silicon interposer, wherein the chip is electrically connected to the silicon interposer through micro-bumps, and the silicon interposer is electrically connected to the packaging substrate through silicon vias and C4-bumps.

[0043] Reference Figure 2, unlike the 2.5 integrated circuit system based on silicon interposer, the middle layer of the 2.5D integrated circuit system based on integrated fan-out InFO package is the fan-out InFO rewiring layer, which is electrically connected to the package substrate through C4-bump. The connection diagram of I / O bumps between layers of the 2.5D integrated circuit system is shown in Figure 1. Figure 4 .

[0044] Reference Figure 3 The stacking layers of the 3D integrated circuit system mainly include the package substrate, chip Die2 and flip chip Die1. The flip chip Die1 includes the substrate and the chip front-end layer. The chip Die2 includes the chip back-end layer, the substrate and the chip front-end layer. The chip front-end layer of the flip chip Die1 is electrically connected to the chip back-end layer of the chip Die2 through micro-bumps. The chip back-end layer of the chip Die2 is electrically connected to the chip front-end layer of the chip Die2 through silicon vias. The chip front-end layer of the chip Die2 is electrically connected to the package substrate through C4-bump. The connection diagram of the I / O bump of the 3D integrated circuit system refers to Figure 5 .

[0045] The verification method of the semiconductor multi-layer integrated circuit system in this embodiment takes a 2.5D integrated circuit system and a 3D integrated circuit system as examples.

[0046] like Figure 7 As shown, a verification method for a multi-layer integrated circuit system includes the following steps:

[0047] S1: Verify whether the layout and schematic diagram of the chips and devices of each stacked layer of the multi-layer integrated circuit system meet the design rules. If they meet, execute step S2. Otherwise, modify the stacked layers that do not meet the design rules, and then re-execute step S1 until each stacked layer of the multi-layer integrated circuit system meets the design rules.

[0048] Specifically, in step S1, at least the layout of the chip and the device, the placement of the IP template, the wiring width and the wiring spacing are verified to be in compliance with the design rules;

[0049] S2: Generate a system netlist synthesis file, which is used to describe and define the layout relationship of the chips on each stacking layer of the multi-layer integrated circuit system and the connection relationship between each stacking layer;

[0050] Specifically, step S2 includes the following steps:

[0051] S20: taking the netlist file of the chip or device on each stacking layer as input, extracting the chip netlist, the logic netlist of the silicon interposer with built-in passive TSV or the netlist of the TSV interconnected active chip and the netlist of the packaging substrate, wherein the chip netlist at least includes the signal port, clock port, power port and ground port information of the chip, the logic netlist of the silicon interposer with built-in passive TSV or the netlist of the TSV interconnected active chip at least includes the interconnection relationship information from the micro-bump to the C4-bump, and the netlist of the packaging substrate at least includes the distribution information of the BGA ball on the packaging substrate; wherein the chip netlist at least includes the netlist of the system-on-chip SoC or the netlist of the high-bandwidth memory HBM chip;

[0052] Reference Figure 8 , when the integrated circuit system is a 2.5D integrated circuit system, the netlist file of the chip or device on each stacking layer of the 2.5D integrated circuit system includes the netlist of the SoC chip, the netlist of the HBM, the netlist of the silicon interposer, the netlist of the chip stacked on the wafer, and the netlist of the system-level package SiP, wherein the netlist of the SoC chip and the netlist of the HBM are chip netlists, and the netlist of the chip stacked on the wafer and the netlist of the system-level package SiP are netlists of the packaging substrate; refer to Fig. 9 When the integrated circuit system is a 3D integrated circuit system, the netlist file of the chip or device on each stacked layer of the 3D integrated circuit system includes the netlist of each chip in the stack, the netlist of the chip stacked on the chip, and the netlist of the system and package SIP, wherein the netlist of each chip in the stack is the chip netlist, the netlist of the chip stacked on the chip is the netlist of the TSV interconnected active chip, and the netlist of the system-level package SiP is the package netlist.

[0053] S21: taking a standard AIF format file of a chip or device on each stacking layer as input, extracting bump information on the three-dimensional integrated circuit system, wherein the bump information at least includes a name and location information of the bump;

[0054] exist Figure 8 In the 2.5D integrated circuit system, the AIF files of the chips or devices on each stacking layer include the AIF of the SoC chip, the AIF of the HBM, the AIF of the silicon interposer, the AIF of the integrated fan-out InFO, and the AIF of the system integrated package SiP. Fig. 9 In the 3D integrated circuit system, the AIF file of the chip or device on each stacking layer includes the AIF of each chip in the stack, the AIF of the chip stacked to the chip, and the AIF of the system-level package SiP.

[0055] S22: taking the layout / layout file of the chips and devices on each stacking layer as input, and extracting at least the name, size and orientation information of the chips or devices;

[0056] exist Figure 8 In the 2.5D integrated circuit system, the position, size and orientation information of the chip or device extracted includes the position, size and orientation information of the SoC chip, HBM chip, silicon interposer and substrate, where the size information includes the physical size, the position information includes the X and Y coordinate information, and the orientation information includes the rotation or flip view information and orientation information. Fig. 9 In the 3D integrated circuit system, the position, size and orientation information of the chip or device extracted includes the position, size and orientation information of each chip and substrate in the stack.

[0057] S23: Generate a system netlist synthesis file based on the information extracted in steps S20, S21 and S22.

[0058] S3: synthesize and package the layout of each stacked layer of the integrated circuit system into an overall three-dimensional layout;

[0059] Specifically, step S3 is as follows:

[0060] S30: defining a stacking position of each stacking layer in the multi-layer integrated circuit system;

[0061] S31: searching for metal layer information and identification layer information on each stacking layer in the system netlist synthesis file to identify the stacking layer, and stacking the identified stacking layers according to the stacking position of each stacking layer to generate a three-dimensional layout.

[0062] Reference Fig.10 When generating a three-dimensional layout of a 2.5D integrated circuit system based on a silicon interposer, the chip layout including the SOC chip layout and the HBM chip layout, the silicon interposer layout and the substrate layout are used as input files, and the interface information of these layouts is extracted by scanning, that is, the metal layer information and the identification layer information of the stacking layer are obtained to identify these layouts, and then the stacking position of each stacking layer is defined according to the stacking description file to synthesize and generate a three-dimensional layout, which is used as the verification input of the 2.5D integrated circuit system.

[0063] Reference Figure 4 and Figure 6In a 2.5D integrated circuit system, there are three levels of interlayer layout interface information, including the first level / top layer chip interface information, which has micro-bump ubump, contact layer layer and identification layer TEXT; the second level / middle layer silicon interposer layout interface information, which has micro-bump ubump, contact layer layer and identification layer TEXT on the front side, and C4-bump, contact layer layer and identification layer TEXT on the back side, or integrated fan-out RDL redistribution layer layout interface, which also has C4-bump, contact layer layer and identification layer TEXT on the back side; and the third level / bottom layer package substrate, which has ball grid array solder ball BGABall, contact layer layer and identification layer TEXT on the back side. Therefore, the stacked layer can be identified by extracting the metal layer information and identification layer information of each stacked layer.

[0064] Reference Fig.11 , when generating the 3D layout of a 2.5D integrated circuit system based on an integrated fan-out InFO package, Fig.10 The silicon interposer layout is replaced with the integrated fan-out InFO layout, and the subsequent 3D layout generation principle and Fig.10 The generation principle is the same as in , so I will not describe it in detail here.

[0065] Reference Fig.12 ,When generating a three-dimensional layout of a 3D integrated circuit system, the chip layout and the substrate layout are used as input files, and then the input layout is generated into a three-dimensional layout through interface information extraction and stacking description files.

[0066] S4: Generate a system rule synthesis file, which is used as a verification standard for the three-dimensional layout verification;

[0067] Reference Fig.13 The system rule synthesis file includes the description file of the chip part and stacking, the connection detection rule file, the description file of chip stacking and placement, the physical design rule detection file, the connection check rule file and the layout identification file.

[0068] S5: verifying the three-dimensional layout to verify whether the three-dimensional layout meets the verification standard in the system rule synthesis file;

[0069] The details are as follows: According to the system rule synthesis file, the multi-layer integrated circuit system is respectively subjected to physical rule checking and layout schematic comparison checking. The physical rule checking includes checking whether the placement position, placement interval and placement spacing of chips and devices meet the requirements, including checking whether the bumps on each stacked layer are misplaced. The layout schematic comparison checking is to compare and check the three-dimensional layout with the system netlist synthesis file, so as to determine whether the bumps used to connect the stacked layers on the multi-layer integrated circuit system are open or short-circuited.

[0070] Reference Fig.14 , Fig.14 There are two chips on the stacking layer in the embodiment, and the physical rule check of the stacking layer includes checking whether the distance D7 between the two chips, the distances D1 and D2 between the chip and the upper edge of the stacking layer, the distances D5 and D4 between the chip and the lower edge of the stacking layer, the distance D6 between the chip and the left edge of the stacking layer, and the distance D3 between the chip and the right edge of the stacking layer meet the requirements.

[0071] In addition, in actual use, when performing physical rule checking and layout schematic comparison checking in step S5, if the placement position, placement interval and placement spacing of the chip or device on the three-dimensional layout do not meet the requirements, the bumps on the stacked layer are misaligned, and the bumps used to connect the stacked layers are open or short-circuited, then the corresponding error information is output, and the error information includes the specific location of the error and the error type. Fig.15 , Fig.15 The types of bumps used to connect stacked layers that do not meet the requirements include misaligned bumps, missing or dangling bumps, shorted bumps, and open bumps. In addition, when checking whether the bumps are aligned, the lateral distance between the centers of the two bumps used for connection can be used to determine whether they are aligned. If the lateral distance between the centers of the two bumps exceeds the judgment threshold, it is considered that the two bumps are not aligned.

[0072] Finally, in step S5, when the 3D multi-layer stacked integrated circuit layout and schematic diagram are subjected to 3DLVS inspection, reference Fig.16 If there is a short circuit or open circuit in the interfaces of the top chip, the middle chip / device, and the bottom packaging substrate, it is equivalent to an open circuit or short circuit in the interconnection lines of each layer in the system. The output error information can be checked according to the connection rules.

[0073] In actual use, according to the error information, the EDA tool is first used to analyze and modify the three-dimensional layout, and then step S3 is re-executed on the modified three-dimensional layout to perform verification iterations, thereby realizing the verification, analysis and modification of the multi-layer integrated circuit system.

[0074] In summary, when verifying and analyzing a multi-layer integrated circuit system, the present invention generates a system netlist synthesis file to express the layout relationship of the chips on each stacked layer of the multi-layer integrated circuit system and the connection relationship between each stacked layer, and then generates a three-dimensional layout according to the input stacked layer layout, and verifies the three-dimensional layout according to the rules in the system rule synthesis file and the system netlist synthesis file to determine whether there are any violations that do not meet the requirements in the three-dimensional layout, thereby realizing verification and analysis of the multi-layer integrated circuit system.

[0075] The above is based on the present invention as an inspiration. Through the above description, relevant staff can make various changes and modifications without departing from the technical idea of ​​this invention. The technical scope of this invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A verification method for a multi-layer integrated circuit system, characterized in that: The steps include: S1: Verify whether the layout and schematic diagram of the chips and devices in each stacked layer of the multi-layer integrated circuit system meet the design rules. If they meet, execute step S2. Otherwise, modify the stacked layers that do not meet the design rules, and then re-execute step S1 until the chips and devices in each stacked layer of the multi-layer integrated circuit system meet the design rules. S2: Generate a system netlist synthesis file, wherein the system netlist synthesis file is used to describe and define the layout relationship of the chips on each stacking layer of the multi-layer integrated circuit system and the connection relationship between each stacking layer; The steps of generating the system netlist synthesis file in step S2 are as follows: S20: taking the netlist file of the chip or device on each stacking layer as input, extracting the chip netlist, the logic netlist of the silicon interposer with built-in passive TSV or the netlist of the TSV interconnected active chip and the netlist of the packaging substrate, wherein the chip netlist at least includes the signal port, clock port, power port and ground port information of the chip, the logic netlist of the silicon interposer with built-in passive TSV or the netlist of the TSV interconnected active chip at least includes the interconnection relationship information from the micro-bump to the C4-bump, and the netlist of the packaging substrate at least includes the distribution information of the BGA ball on the packaging substrate; S21: taking a standard AIF format file of a chip or device on each stacking layer as input, extracting bump information on the three-dimensional integrated circuit system, wherein the bump information at least includes a name and location information of the bump; S22: taking the layout / layout file of the chips and devices on each stacking layer as input, and extracting at least the position, size and orientation information of the chips or devices; S23: Generate a system netlist synthesis file based on the information extracted in steps S20, S21 and S22; S3: synthesize and package the layout of each stacked layer of the integrated circuit system into an overall three-dimensional layout; S4: generating a system rule synthesis file, wherein the system rule synthesis file is used as a verification standard for verifying the three-dimensional layout; S5: Verify the three-dimensional layout to verify whether the three-dimensional layout meets the verification standard in the system rule synthesis file.

2. A verification method for a multi-layer integrated circuit system according to claim 1, characterized in that: The steps of generating a three-dimensional layout in step S3 are as follows: S30: defining a stacking relationship of each stacking layer in the multi-layer integrated circuit system; S31: searching for metal layer information and identification layer information of each stacking layer on the layout of each stacking layer to identify the stacking layer, and stacking the identified stacking layers according to the stacking relationship of each stacking layer to generate a three-dimensional layout.

3. The verification method of a multi-layer integrated circuit system according to claim 1, characterized in that: The system rule synthesis file in step S4 includes chip stacking and placement description files, physical design rules, wiring relationship files and layout identification files.

4. The verification method of a multi-layer integrated circuit system according to claim 1, characterized in that: The steps of verifying the three-dimensional layout in step S5 are as follows: performing a physical rule check on the three-dimensional layout according to the system rule synthesis file, and performing a layout schematic comparison check on the three-dimensional layout according to the system netlist synthesis file. The physical rule check includes checking whether the placement position, placement interval and placement spacing of chips and devices meet the requirements, including checking whether the bumps on each stacked layer are misplaced. The layout schematic comparison check is to compare the three-dimensional layout with the system netlist synthesis file to determine whether the bumps used to connect the stacked layers on the multi-layer integrated circuit system are open or short-circuited.

5. A verification method for a multi-layer integrated circuit system according to claim 4, characterized in that: In step S5, when performing physical rule checks and layout schematic comparison checks, if the placement position, placement interval and placement spacing of the chip or device on the three-dimensional layout do not meet the requirements, the bumps on the stacked layer are misplaced, and the bumps used to connect the stacked layers are open or short-circuited, a corresponding error message is output.

6. A verification method for a multi-layer integrated circuit system according to claim 5, characterized in that: According to the error information, the three-dimensional layout is first analyzed and modified using an EDA tool, and then step S3 is re-executed on the modified three-dimensional layout.

Images