Through silicon via structure and method for forming the same

Abstract

The present invention provides a through silicon via structure and a method for forming the same, wherein the through silicon via structure comprises: a substrate, the substrate having a front side and a back side arranged opposite to each other; an active area located in the substrate, the active area being arranged close to the front side; a through silicon via located in the substrate, the through silicon via penetrating the front side and the back side, and at the same time, the through silicon via also penetrating the active area; and a metal silicide located between the through silicon via and the active area. The present invention has a metal silicide between the through silicon via and the active area, so other devices on the substrate can be connected to the active area through the through silicon via, and at the same time, the number of connectors used to connect other devices on the substrate to the active area can be reduced, thereby reducing the area of ​​the chip where the through silicon via is located. Furthermore, the through silicon via is formed in a hole formed by the metal silicide, and compared with the hole formed by etching in the prior art, there are no burrs on the wall of the metal silicide, and the formed through silicon via also has no burrs, thereby improving the quality of the through silicon via structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a through silicon via structure and a method for forming the same. Background Art

[0002] For wafer manufacturing, TSV (Through Silicon Via) means "through silicon channel" in Chinese, or through silicon via. TSV process is usually used to serve the back-end packaging process, connecting the metal PAD on the front of the wafer to the back of the wafer through TSV, thereby reducing the packaging area and achieving packaging effectiveness and convenience.

[0003] In the prior art, please refer to Figure 1 The method for forming a through silicon via structure is to provide a substrate 110, which may be a wafer, and the substrate 110 includes a front side and a back side arranged oppositely, and form an active area 120 in the substrate 110 near the front side of the substrate, and then etch a part of the active area 120 from the front side of the substrate 110 to form a hole 130, and fill the hole 130 with metal to form a through silicon via 140. A pad 150 is formed on the front side of the substrate, and the pad 150 covers the through silicon via 140 and a part of the front side of the substrate 110. Then, a part of the substrate 110 is ground from the back side of the substrate 110 to expose the through silicon via 140. Then, a connector is formed to lead out the active area 120. However, since the hole 130 is formed by etching, the side wall of the hole 130 has some burrs. When the metal filled forms the through silicon via 140, the burrs will affect the quality of the through silicon via 140, such as leakage or tip discharge. Furthermore, the connectors need to occupy some space, which indirectly increases the area of ​​the device and reduces the number of devices formed on a unit wafer. Summary of the invention

[0004] The object of the present invention is to provide a through silicon via structure and a method for forming the same, which can eliminate the burrs of the through silicon via, and at the same time, other devices on the substrate can be connected to the active area through the through silicon via.

[0005] In order to achieve the above object, the present invention provides a through silicon via structure, comprising:

[0006] A substrate having a front side and a back side arranged opposite to each other;

[0007] an active region located in the substrate, the active region being disposed close to the front surface of the substrate;

[0008] a through silicon via located in the substrate, the through silicon via penetrating the front side of the substrate and the back side of the substrate, and the through silicon via also penetrating the active area; and

[0009] A metal silicide is located between the through silicon via and the active area.

[0010] Optionally, the through silicon via structure further includes: a pad located on the front side of the substrate, wherein the pad covers the through silicon via and a portion of the front side of the substrate.

[0011] Accordingly, the present invention also provides a method for forming a through silicon via structure, comprising:

[0012] Providing a substrate having a front side and a back side disposed opposite to each other;

[0013] forming an active region in the substrate, wherein the active region is disposed close to the front surface of the substrate;

[0014] forming a first hole in the substrate, wherein the first hole is disposed close to the front surface of the substrate and passes through the active area;

[0015] Forming metal silicide on the bottom wall and sidewall of the first hole by growing a metal layer and performing a high temperature process on the metal layer, and at the same time, the metal silicide forms a second hole;

[0016] forming a through silicon via in the second hole; and

[0017] The back side of the substrate is ground to expose the through silicon via.

[0018] Optionally, in the method for forming the through silicon via structure, the method for forming the active area includes:

[0019] Implanting ions into the substrate from the front side of the substrate to form a lightly doped region;

[0020] Implanting ions into the lightly doped region to form a medium doped region; and

[0021] Ions are implanted into the medium doping region to form a heavily doped region.

[0022] Optionally, in the method for forming the through silicon via structure, the active region is at a certain distance from the back side of the substrate.

[0023] Optionally, in the method for forming the through silicon via structure, before forming the first hole, the method further includes: forming a hard mask layer on the front side of the substrate.

[0024] Optionally, in the method for forming the through silicon via structure, the method for forming the first hole further includes: etching the hard mask layer and etching a portion of the substrate below the active area.

[0025] Optionally, in the method for forming the through silicon via structure, the method for forming metal silicide by growing a metal layer on the bottom wall and the side wall of the first hole and performing a high temperature process on the metal layer includes:

[0026] forming a metal layer on the surface of the hard mask layer, wherein the metal layer also covers the bottom wall and the side wall of the first hole;

[0027] Performing a first high temperature process, the bottom wall of the first hole and the metal layer on the side wall of the first hole in the active area are subjected to the high temperature process to form a metal intermediate;

[0028] removing the remaining metal layer; and

[0029] A second high temperature process is performed, and the metal intermediate forms metal silicide.

[0030] Optionally, in the method for forming the through silicon via structure, the temperature of the first high temperature process is 500°C to 700°C, and the temperature of the second high temperature process is 700°C to 900°C.

[0031] Optionally, in the method for forming a through silicon via structure, the method for forming the through silicon via in the second hole includes:

[0032] Filling the second hole with metal, wherein the metal also covers the surface of the hard mask layer;

[0033] grinding the metal to expose the surface of the hard mask layer; and

[0034] The hard mask layer is ground to expose the front side of the substrate, and at the same time, the metal in the second hole is ground so that the surface of the metal is flush with the front side of the substrate.

[0035] Optionally, in the method for forming the through silicon via structure, after forming the through silicon via in the second hole, the method further includes: forming a pad on the front side of the substrate, wherein the pad covers the through silicon via and a portion of the front side of the substrate.

[0036] In the through silicon via structure and the formation method thereof provided by the present invention, there is a metal silicide between the through silicon via and the active area, so other devices on the substrate can be connected to the active area through the through silicon via. At the same time, compared with the prior art, the connectors used to connect other devices on the substrate with the active area can be reduced, thereby reducing the area of ​​the chip where the through silicon via is located. Furthermore, the through silicon via is formed in a hole formed by the metal silicide, and the metal silicide is formed by growing a metal layer. Therefore, compared with the cavity formed by etching in the prior art, there are no burrs on the wall of the metal silicide, and the formed through silicon via also has no burrs, thereby improving the quality of the through silicon via structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 and Figure 2 is a schematic diagram of a method for forming a through silicon via structure in the prior art;

[0038] Figure 3 is a schematic structural diagram of a through silicon via structure according to an embodiment of the present invention;

[0039] Figure 4 is a flow chart of a method for forming a through silicon via structure according to an embodiment of the present invention;

[0040] Figures 5 to 13 is a flow chart of a method for forming a through silicon via structure according to an embodiment of the present invention;

[0041] In the figure: 110-substrate, 120-active area, 130-hole, 140-silicon via, 150-pad, 210-substrate, 220-active area, 221-lightly doped area, 222-medium doped area, 223-heavily doped area, 230-hard mask layer, 240-first hole, 250-metal layer, 261-metal intermediate, 262-metal silicide, 270-second hole, 280-metal, 290-silicon via, 300-pad. DETAILED DESCRIPTION

[0042] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0043] Hereinafter, the terms "first", "second", etc. are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms used in this manner are interchangeable where appropriate. Similarly, if the method described herein includes a series of steps, the order of these steps presented herein is not necessarily the only order in which these steps can be performed, and some of the steps described may be omitted and / or some other steps not described herein may be added to the method.

[0044] Please refer to Figure 3 The present invention provides a through silicon via structure, comprising:

[0045] A substrate 210, wherein the substrate 210 has a front side and a back side that are oppositely disposed;

[0046] An active region 220 located in the substrate 210 , wherein the active region 220 is disposed close to the front surface of the substrate 210 ;

[0047] A through silicon via 290 located in the substrate 210, the through silicon via 290 penetrates the front side of the substrate 210 and the back side of the substrate 210, and at the same time, the through silicon via 290 also penetrates the active area;

[0048] A metal silicide 262 located between the through silicon via 290 and the active area 220;

[0049] The pad 300 is located on the front surface of the substrate 210 , and the pad 300 covers the through silicon via 290 and a portion of the front surface of the substrate 210 .

[0050] Please refer to Figure 4 The present invention also provides a method for forming a through silicon via structure, comprising:

[0051] S1: providing a substrate, wherein the substrate has a front side and a back side opposite to each other;

[0052] S2: forming an active region in the substrate, the active region being close to the front side of the substrate;

[0053] S3: forming a first hole in the substrate, the first hole is close to the front side of the substrate, and the first hole passes through the active area;

[0054] S4: forming a metal silicide on the bottom wall and sidewall of the first hole by growing a metal layer and performing a high temperature process on the metal layer, and at the same time, the metal silicide forms a second hole;

[0055] S5: forming a through silicon via in the second hole; and

[0056] S6: Grinding the back side of the substrate to expose the through silicon vias.

[0057] For specific formation methods, please refer to Figure 5 First, a substrate 210 is provided. The substrate 210 may be a silicon wafer. The substrate 210 has two oppositely disposed surfaces, namely a front surface and a back surface. Next, ions are implanted into the substrate 210 from the front surface of the substrate 210 to form a lightly doped region 221. The lightly doped region 221 is at a certain distance from the back surface of the substrate 210. Next, ions are implanted into the lightly doped region 221 to form a medium doped region 222. Next, ions are implanted into the medium doped region 222 to form a heavily doped region 223, thereby completing the formation of the active region 220.

[0058] Next, please refer to Figure 6 , a hard mask layer 230 is formed on the front surface of the substrate 210, and the hard mask layer 230 covers the entire front surface of the substrate 210. The material of the hard mask layer 230 can be silicon nitride. Figure 7, the hard mask layer 230 and a portion of the substrate 210 are etched from the surface of the hard mask layer 230, and the etching stops at a certain distance from the back of the substrate 210, forming a first hole 240. The first hole 240 includes a bottom wall and two side walls, the side walls are perpendicular to the surface of the hard mask layer 230, and the side walls are perpendicular to the bottom wall. The bottom wall of the hole is at a certain distance from the back of the substrate 210, and the depth of the first hole 240 is greater than the depth of the lightly doped region 221, that is, the bottom wall of the first hole 240 is located in the substrate 210 between the lightly doped region 221 and the back of the substrate 210.

[0059] Next, please refer to Figure 8 A metal layer 250, such as Ti, Co, or Ta, is formed on the remaining hard mask layer 230 and the bottom wall of the first hole 240 and the sidewall of the first hole 240. Fig. 9 , the entire device is subjected to the first high temperature process, the temperature can be 500℃~700℃. At this time, the metal layer 250 located on the bottom wall of the first hole 240 and the metal layer 250 on the side wall of the first hole 240 located in the lightly doped region 221 will react with the silicon of the active area 220 to form a metal intermediate 261. The metal layer 250 on the hard mask layer 230 and the metal layer 250 on the side wall of the first hole 240 located in the hard mask layer 230 will not react. Next, please refer to Fig.10 , using a chemical agent to remove the remaining metal layer 250, that is, to remove the metal layer 250 that has not reacted in the first high temperature process. At this time, the metal intermediate 261 will not react with the chemical agent, and thus will still remain on the sidewall of the first hole 240. Next, please refer to Fig.11 , the second high temperature process is continued, the metal intermediate 261 will continue to form a metal silicide 262, and the metal silicide 262 will also form a second hole 270. The second hole 270 is filled with a metal 280, such as tungsten. The metal 280 fills the entire second hole 270 and also covers the remaining hard mask layer 230.

[0060] Next, please refer to Fig.12 The metal 280 on the hard mask layer 230 and the remaining hard mask layer 230 are polished by chemical mechanical polishing process, and the metal 280 on the polished hard mask layer 230 and the remaining hard mask layer 230 are removed, and finally the front surface of the substrate 210 is exposed. While polishing the remaining hard mask layer 230, the metal 280 in the second hole 270 is partially polished, and the surface of the remaining metal 280 is flat.

[0061] Next, please refer to Fig.13, a pad 300 is formed on the front side of the substrate 210, and the pad 300 completely covers the surface of the metal 280 in the second hole 270 and a portion of the front side of the substrate 210. Next, the back side of the substrate 210 is ground to expose the metal 280 in the second hole 270, and the remaining metal 280 forms a through silicon via 290 connecting the front side and the back side of the substrate 210.

[0062] The present invention also has a layer of metal silicide 262 between the through silicon via 290 and the active area 220. The metal silicide 262 can connect the through silicon via 290 and the active area 220 together, and the metal silicide 262 connects the through silicon via 290 and the active area 220, and can lead the active area 220 out through the through silicon via 290. The device that needs to be connected to the active area 220 can be connected through the through silicon via 290, and the connected place is on the side wall of the second hole 270, and the range of connection is relatively large. Compared with the current technology, the connector can be removed, the steps and materials for forming the connector are reduced, thereby saving costs, and the space occupied by the connector is reduced, thereby reducing the space occupied by the entire device and increasing the number of devices per unit area of ​​the wafer. Furthermore, the side wall of the second hole 270 is smooth and has no burrs, so the formed through silicon via 290 is of good quality.

[0063] In summary, in the silicon through via structure and the method for forming the same provided in the embodiment of the present invention, there is metal silicide between the silicon through via and the active area, so other devices on the substrate can be connected to the active area through the silicon through via, and at the same time, compared with the prior art, the number of connectors used to connect other devices on the substrate to the active area can be reduced, thereby reducing the area of ​​the chip where the silicon through via is located. Furthermore, the silicon through via is formed in a hole formed by metal silicide, and the metal silicide is formed by growing a metal layer, so compared with the cavity formed by etching in the prior art, there are no burrs on the wall of the metal silicide, and the formed silicon through via has no burrs, thereby improving the quality of the silicon through via structure.

[0064] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A method for forming a through silicon via structure, characterized in that: include: Providing a substrate having a front side and a back side disposed opposite to each other; An active region is formed in the substrate, the active region is arranged close to the front surface of the substrate, the longitudinal section of the substrate after the active region is formed is U-shaped, and the active region is located in the U-shape; forming a first hole in the substrate, wherein the first hole is disposed close to the front surface of the substrate and passes through the active area; Forming metal silicide on the bottom wall and side wall of the first hole by growing a metal layer and performing a high temperature process on the metal layer, and at the same time, the metal silicide forms a second hole, and there is no burr on the wall of the metal silicide; forming a through silicon via in the second hole; as well as The back side of the substrate is ground to expose the through silicon via.

2. The forming method according to claim 1, characterized in that: The method of forming the active region includes: Implanting ions into the substrate from the front side of the substrate to form a lightly doped region; Implanting ions into the lightly doped region to form a medium doped region; and Ions are implanted into the medium doping region to form a heavily doped region.

3. The forming method according to claim 1, characterized in that: The active region is at a certain distance from the back side of the substrate.

4. The forming method according to claim 1, characterized in that: Before forming the first hole, the method further includes: forming a hard mask layer on the front side of the substrate.

5. The forming method according to claim 4, characterized in that: The method for forming the first hole further includes: etching the hard mask layer and etching a portion of the substrate below the active area.

6. The forming method according to claim 5, characterized in that: The method of forming metal silicide by growing a metal layer on the bottom wall and the side wall of the first hole and performing a high temperature process on the metal layer comprises: forming a metal layer on the surface of the hard mask layer, wherein the metal layer also covers the bottom wall and the side wall of the first hole; Performing a first high temperature process, the bottom wall of the first hole and the metal layer on the side wall of the first hole in the active area are subjected to the high temperature process to form a metal intermediate; removing the remaining metal layer; and A second high temperature process is performed, and the metal intermediate forms metal silicide.

7. The forming method according to claim 6, characterized in that: The temperature of the first high temperature process is 500°C to 700°C, and the temperature of the second high temperature process is 700°C to 900°C.

8. The forming method according to claim 6, characterized in that: The method of forming a through silicon via in the second hole comprises: Filling the second hole with metal, wherein the metal also covers the surface of the hard mask layer; grinding the metal to expose the surface of the hard mask layer; and The hard mask layer is ground to expose the front side of the substrate, and at the same time, the metal in the second hole is ground so that the surface of the metal is flush with the front side of the substrate.

9. The forming method according to claim 8, characterized in that: After forming a through silicon via in the second hole, the method further includes: forming a pad on the front side of the substrate, wherein the pad covers the through silicon via and a portion of the front side of the substrate.

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