Microelectronic devices having recessed conductive structures, and related methods and systems

Abstract

The present application relates to microelectronic devices having recessed conductive structures and related methods and systems. A microelectronic device includes a stack structure having a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. Conductive contact structures extend through the stack structure. Insulative material is between the conductive contact structures and the tiers of the stack structure. In a lower tier portion of the stack structure, one of the plurality of conductive structures has a portion extending a first width between a pair of the conductive contact structures. In a portion of the stack structure over the lower tier portion, another of the plurality of conductive structures has another portion extending a second width between the pair of conductive contact structures. The second width is greater than the first width. Related methods and electronic systems are also disclosed.

Description

[0001] Priority requirements

[0002] This application claims priority to U.S. Patent Application Serial No. 16 / 922,792, filed on July 7, 2020, entitled "Microelectronic Devices With Lower Recessed Conductive Structures and Related Methods and Systems". Technical Field

[0003] Embodiments of this disclosure relate to the field of microelectronic device design and manufacturing. More specifically, this disclosure relates to methods for forming microelectronic devices (e.g., memory devices, such as 3D NAND memory devices) having a layered stacked structure including vertically alternating conductive and insulating structures, to related systems, and to methods for forming such structures and devices. Background Technology

[0004] Memory devices provide data storage for electronic systems. Flash memory devices are one of various types of memory devices and have many uses in modern computers and other electronic devices. Conventional flash memory devices may include memory arrays having a large number of charge storage devices (e.g., memory cells, such as non-volatile memory cells) arranged in rows and columns. In NAND flash memory, memory cells arranged in columns are coupled in series, and the first memory cell in the column is coupled to a data line (e.g., a bit line).

[0005] In a “three-dimensional NAND” memory device (which may also be referred to herein as a “3D NAND” memory device), a type of vertical memory device is not merely memory cells arranged in rows and columns in a horizontal array, but rather layers of the horizontal array are stacked on top of each other (e.g., as vertical strings of memory cells) to provide a “three-dimensional array” of memory cells. The stack of layers has conductive material alternating vertically with insulating (e.g., dielectric) material. The conductive material acts as a control gate for, for example, access lines (e.g., word lines) of the memory cells. Vertical structures (e.g., pillars containing channel and tunnel structures) extend along the vertical strings of memory cells. The drain end of the string is adjacent to one of the top and bottom of the vertical structure (e.g., pillar), while the source end of the string is adjacent to the other of the top and bottom of the pillar. The drain end is operatively connected to a bit line, while the source end is operatively connected to a source line. 3D NAND memory devices also include, for example, electrical connections between access lines (e.g., word lines) and other conductive structures of the device, such that memory cells in the vertical strings can be selected for write, read, and erase operations.

[0006] To form some 3D NAND memory devices, the layers are initially stacked as an alternating structure of insulating and sacrificial materials, followed by the removal of the sacrificial materials and their replacement with conductive materials. Maintaining the structural integrity of the insulating materials during the removal of the sacrificial materials and the replacement of the conductive materials presents a challenge. Summary of the Invention

[0007] A microelectronic device is disclosed. The microelectronic device includes a stacked structure comprising a vertically alternating sequence of insulating and conductive structures arranged in layers. Conductive contact structures extend through the stacked structure. Insulating material is located between the conductive contact structures and the layers of the stacked structure. In a lower portion of the stacked structure, one of the plurality of conductive structures has a portion extending a first width between a pair of conductive contact structures. In a portion of the stacked structure above the lower portion, another conductive structure of the plurality of conductive structures has another portion extending a second width between the pair of conductive contact structures. The second width is greater than the first width.

[0008] A microelectronic device is also disclosed, comprising a stacked structure including a vertically alternating sequence of insulating and conductive structures arranged in layers. Contacts extend through the stacked structure. Insulating material is adjacent to the contacts and extends through the stacked structure. The insulating material includes insulating extensions that partially extend horizontally across the insulating structures in a lower vertical region of the stacked structure and alternate vertically with the insulating structures.

[0009] Furthermore, a method for forming a microelectronic device is disclosed. The method includes forming a stacked structure comprising a vertically alternating sequence of insulating and conductive structures arranged in layers. At least one opening is formed to extend through the stacked structure. A liner is formed within a portion of the at least one opening. This portion is located above a lower layer of the stacked structure. In the lower layer of the stacked structure, the sacrificial structure is recessed to form a groove along the at least one opening. An insulating material is formed within the at least one opening and the groove. At least one conductive contact structure is formed directly adjacent to the insulating material to fill the remaining portion of the at least one opening.

[0010] Furthermore, an electronic system is disclosed. This electronic system includes an input device, an output device, a processor device, and a memory device. The processor device is operatively coupled to the input and output devices. The memory device is operatively coupled to the processor device and includes at least a microelectronic device structure. The at least one microelectronic device structure includes contacts extending through a stacked structure of vertically alternating insulating and conductive structures arranged in layers. In a lower portion of the stacked structure, the conductive structure includes at least one lower conductive structure portion between adjacent pairs of contacts. In an additional portion of the stacked structure above the lower portion, at least one upper conductive structure portion is located between adjacent pairs of contacts. The at least one lower conductive structure portion has a width narrower than the at least one upper conductive structure portion. Attached Figure Description

[0011] Figure 1 This is a front cross-sectional view of a microelectronic device structure according to an embodiment of the present disclosure, wherein the insulating extension is adjacent to the substrate of the contact structure.

[0012] Figures 2 to 11 Combination Figure 1 Manufacturing is based on embodiments of this disclosure. Figure 1 The diagram shows cross-sectional front views of the microelectronic device structure during various stages of processing.

[0013] Figures 12 to 15 Manufacturing according to embodiments of this disclosure Figure 15 The diagram shows a cross-sectional front view of the microelectronic device structure during various stages of processing.

[0014] Figures 16 to 18 Combination Figures 2 to 6 Manufacturing according to embodiments of the present disclosure Figure 18 The diagram shows the various processing stages of the microelectronic device structure, in which... Figure 16 Phase Follow Figure 6 The stage.

[0015] Figure 19 and Figure 20 Combination Figures 12 to 14 Manufacturing according to embodiments of the present disclosure Figure 20 The diagram shows the various processing stages of the microelectronic device structure, in which... Figure 19 Phase Follow Figure 14 The stage.

[0016] Figure 21 This is a partial cross-sectional perspective view of a microelectronic device according to an embodiment of the present disclosure.

[0017] Figure 22 This is a block diagram of an electronic system according to an embodiment of the present disclosure.

[0018] Figure 23 This is a block diagram of a processor-based system according to an embodiment of the present disclosure. Detailed Implementation

[0019] Structures (e.g., microelectronic device structures), devices (e.g., microelectronic devices), and systems (e.g., electronic systems) according to embodiments of this disclosure include a stack of vertically alternating conductive and insulating structures in layers. Conductive contact structures extend through the stack. Insulating material is adjacent to the conductive contact structures, with extensions of the insulating material adjacent to the substrate of the conductive contact structures, for example, at the height of the stack occupied by the lower layer of the stack. When forming the microelectronic device structure, insulating extensions are formed prior to a replacement gate process that forms the conductive structures of the stack. In the replacement gate process, sacrificial material is removed from between the insulating structures, leaving gaps between the insulating structures, and then conductive material of the conductive structures is formed in the gaps. When gaps are present, the insulating structures have less physical support from above and below, and the insulating structures form cantilevered or spanned cantilevered laterally outwards from the insulating material adjacent to the conductive contact structures or between the insulating materials. In this stage including the gaps, the presence of the insulating extensions already formed in the lower layer portion shortens the distance of the insulating structure cantilevered or spanned in that lower layer portion. Therefore, these lower insulating structures are less susceptible to bending, collapse, sagging, or other structural degradation that might otherwise occur due to gravity or attraction. This allows for more reliable alternative gate processes where conductive structures are formed within the gaps between insulating structures.

[0020] As used herein, the term "opening" means a volume extending through at least one structure or at least one material, leaving a gap within that structure or material, or a volume extending between structures or materials, leaving a gap between them. Unless otherwise stated, an "opening" is not necessarily devoid of material. That is, an "opening" is not necessarily an empty space. An "opening" formed within or between a structure or material may contain a structure or material different from the structure or material in which or between the opening is formed. Furthermore, the structure or material "exposed" within an opening is not necessarily in contact with the atmosphere or a non-solid environment. The structure or material "exposed" within an opening may be adjacent to or in contact with other structures or materials disposed within the opening.

[0021] As used herein, the term "substrate" means and includes a base material or other construction on which components, such as those within a memory cell, are formed. A substrate can be a semiconductor substrate, a base semiconductor material on a support structure, a metal electrode, or a semiconductor substrate on which one or more materials, structures, or regions are formed. A substrate can be a conventional silicon substrate or other bulk substrate comprising a semiconductor material. As used herein, the term "bulk substrate" means and includes not only silicon wafers but also silicon-on-insulator ("SOI") substrates, such as silicon-on-sapphire ("SOS") or silicon-on-glass ("SOG") substrates, epitaxial layers of silicon on a base semiconductor, or other semiconductor or optoelectronic materials, such as silicon-germanium (Si... 1-x Ge x , where x is, for example, a mole fraction between 0.2 and 0.8), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP), etc. Furthermore, when “substrate” is mentioned in the following description, it refers to a material, structure, or junction formed in a basic semiconductor structure or base using prior process stages.

[0022] As used herein, the term "insulating" when used to refer to a material or structure means and includes materials or structures that are electrically insulating. An "insulating" material or structure may be made of at least one dielectric oxide material (e.g., silicon oxide (SiO2)). x Phosphorus silicate glass, borosilicate glass, borosilicate-phosphorus silicate glass, fluorosilicate glass, alumina (AlOx), hafnium oxide (HfO) x ), niobium oxide (NbO) x Titanium oxide (TiO) x Zirconium oxide (ZrO) x ), tantalum oxide (TaO) x ) and magnesium oxide (MgO) x One or more of the following), at least one dielectric nitride material (e.g., silicon nitride (SiN) y At least one dielectric oxide nitride material (e.g., silicon oxynitride (SiO2)). x Ny At least one dielectric carboxyl nitride material (e.g., silicon carboxyl nitride (SiO2)). x C z N y These constitute and include both (x), (y), and / or air. The chemical formulas included herein are one or more of the following: (e.g., SiO₂). x AlO x HfO x NbO x TiO x SiN y SiO x N y SiO x C z N y A chemical formula represents a material containing, for each atom of another element (e.g., Si, Al, Hf, Nb, Ti), an average ratio of "x" atoms of one element, "y" atoms of another element, and / or "z" atoms of another element (if any). Since a chemical formula represents relative atomic ratios rather than strict chemical structures, an insulating material or insulating structure may contain one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x," "y," and "z" (if any) may be integers or non-integers. As used herein, the term "non-stoichiometric compound" refers to and includes compounds having elemental composition that cannot be expressed by a ratio of well-defined natural numbers and violates the law of definite proportions. Furthermore, "insulating structure" refers to and includes structures formed of and comprising insulating materials.

[0023] As used herein, when referring to materials or structures, the term “sacrifice” means and includes materials or structures that are formed during the manufacturing process but removed (e.g., substantially removed) before the completion of the manufacturing process.

[0024] As used herein, the term "horizontal" or "lateral" refers to and includes a direction parallel to the main surface of the substrate on which the mentioned material or structure lies. The width and length of the corresponding material or structure can be defined as dimensions in the horizontal plane. Referring to the accompanying drawings, the "horizontal" direction can be perpendicular to the illustrated "Z" axis and parallel to the illustrated "X" axis.

[0025] As used herein, the terms "vertical" or "longitudinal" refer to and include a direction perpendicular to the main surface of the substrate on which the mentioned material or structure lies. The height of the corresponding material or structure can be defined as a dimension in the vertical plane. Referring to the accompanying drawings, the "vertical" direction can be parallel to the illustrated "Z" axis and can be perpendicular to the illustrated "X" axis.

[0026] As used herein, the term “width” refers to and includes a dimension along a horizontal plane (e.g., at a certain height, if determined), which defines the maximum distance of the material or structure along the plane. For example, the “width” of a structure that is at least partially hollow is the horizontal dimension between the outermost edges or sidewalls of the structure, such as the outer diameter of a hollow cylindrical structure.

[0027] As used herein, the terms “thickness” or “thinness” refer to and include a dimension in a straight line perpendicular to the nearest surface of a material or structure that has a different composition or can otherwise be distinguished from materials or structures whose thickness, thinness, or height is discussed.

[0028] As used herein, the term "between" is a spatial relative term used to describe the relative arrangement of a material, structure, or substructure with respect to at least two other materials, structures, or substructures. The term "between" can encompass arrangements in which a material, structure, or substructure is directly adjacent to other materials, structures, or substructures and arrangements in which a material, structure, or substructure is indirectly adjacent to other materials, structures, or substructures.

[0029] As used herein, the term "proximity" is a spatial relative term used to describe an arrangement in which one material, structure, or substructure is close to another material, structure, or substructure. The term "proximity" includes arrangements of indirect proximity, direct proximity, and internal proximity.

[0030] As used herein, when referring to a material or structure, the term "adjacent" means the next nearest material or structure having the defined component or feature. Materials or structures with other components or features besides the defined component or feature may be situated between a material or structure with the defined component or feature and its "adjacent" material or structure. For example, a structure of material X "adjacent" to a structure of material Y is, for example, a first material X structure of a plurality of material X structures, which is immediately adjacent to a specific structure of material Y. "Adjacent" materials or structures may be directly or indirectly adjacent to a structure or material with the defined component or feature.

[0031] As used herein, the term "consistent," when referring to the parameters, properties, or conditions of one structure, material, or feature compared to those of another, means and includes, with respect to at least the corresponding portions of such structures, materials, or features, that the parameters, properties, or conditions of the two such structures, materials, or features are equal, substantially equal, or approximately equal. For example, two structures having "consistent" thicknesses may each define the same, substantially the same, or substantially the same thickness at an X lateral distance from the feature, although the two structures are at different heights along the feature.

[0032] As used herein, the terms “about” and “approximately”, when used to refer to a numerical value of a particular parameter, include both the numerical value and the degree of deviation thereof, which will be understood by one of ordinary skill in the art to be within acceptable tolerances for the particular parameter. For example, “about” or “approximately” with respect to a numerical value may include additional values ​​within the range of 90.0% to 110.0% of the numerical value, such as within the range of 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0033] As used herein, the term "substantially" when referring to a parameter, property, or condition means and includes a parameter, property, or condition equal to or within a given value or a deviation from a given value, such that a person skilled in the art will understand that such a given value is acceptablely satisfied, for example, within acceptable manufacturing tolerances. For example, depending on the specific parameter, property, or condition that is substantially satisfied, the parameter, property, or condition may be "substantially" a given value when the value is satisfied at least 90.0%, at least 95.0%, at least 99.0%, or even at least 99.9%.

[0034] As used herein, referring to an element as “on” or “above” another element means and includes that the element is directly on top of the other element, adjacent to the other element (e.g., laterally adjacent, vertically adjacent), below the other element, or in direct contact with the other element. It also includes elements that are indirectly on top of, adjacent to (e.g., laterally adjacent, vertically adjacent), below, or near the other element, with other elements in between. Conversely, when an element is referred to as “directly on” or “directly adjacent” to another element, there are no intermediate elements.

[0035] As used herein, other spatially relative terms, such as “below,” “lower,” “bottom,” “above,” “upper,” “top,” etc., may be used for ease of description to describe the relationship of one element or feature to another, as illustrated in the accompanying drawings. Unless otherwise specified, spatially relative terms are intended to cover different orientations of material other than those depicted in the drawings. For example, if the material in the drawings is inverted, an element described as “below,” “below,” or “at its bottom” to another element or feature would be oriented as “above” or “at its top” to the other element or feature. Thus, depending on the context in which the term is used, the term “below” can include both above and below orientations, as will be apparent to those skilled in the art. Material may be oriented in other ways (rotated 90 degrees, inverted, etc.), and the spatially relative descriptors used herein shall be interpreted accordingly.

[0036] As used herein, the terms “level” and “height” are spatially relative terms used to describe the relationship of one material or feature to another, as shown in the figures, using the main surface of the substrate on which the reference material or structure is located as a reference point. As used herein, “level” and “height” are each defined by a horizontal plane parallel to the main surface. “Lower level” and “lower height” are closer to the main surface of the substrate, while “higher level” and “higher height” are further away from the main surface. Unless otherwise specified, these spatially relative terms are intended to cover different orientations of the material other than those depicted in the figures. For example, the material in the figures may be inverted, rotated, etc., while the spatially relative “height” descriptors remain unchanged because the reference main surface can also be reoriented.

[0037] As used herein, the terms “comprising,” “including,” “having,” and their grammatical equivalents are inclusive or open-ended terms that do not exclude additional, unlisted elements or method steps, but also include the more restrictive terms “consisting of” and “substantially consisting of” and their grammatical equivalents. Thus, a structure described as “comprising,” “including,” and / or “having” a material may be a structure that also includes additional materials in some embodiments and / or does not include any other materials in some embodiments. Similarly, a composition described as “comprising,” “including,” and / or “having” one substance (e.g., a gas) may be a composition that also includes other substances in some embodiments and / or does not include any other substances in some embodiments.

[0038] As used herein, the term “may” in relation to materials, structures, features, or method actions indicates that such terms are intended for use in implementing embodiments of this disclosure, and such terms are preferred over the more restrictive term “yes” in order to avoid any implication that other compatible materials, structures, features, and methods may be used in combination with them.

[0039] As used herein, “and / or” includes any and all combinations of one or more of the associated listed items.

[0040] As used in this article, the singular forms “a,” “an,” and “the” are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0041] As used herein, the terms “configured as” and “configured” refer to the size, shape, material composition, orientation, and arrangement of the mentioned material, structure, assembly, or equipment in order to facilitate the mentioned operation or characteristics of the mentioned material, structure, assembly, or equipment in a predetermined manner.

[0042] The description presented herein is not intended to be an actual view of any particular material, structure, substructure, region, subregion, device, system, or manufacturing stage, but is merely an idealized representation used to describe embodiments of this disclosure.

[0043] The embodiments are described herein with reference to cross-sectional views as schematic illustrations. Therefore, variations in the illustrated shapes are contemplated, for example, due to manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to the specific shapes or structures illustrated, but may include shape deviations, for example, due to manufacturing techniques. For instance, a structure illustrated or described as box-shaped may have rough and / or non-linear characteristics. Furthermore, acute angles shown may be rounded. Therefore, the materials, features, and structures shown in the drawings are schematic in nature, and their shapes are not intended to show the precise shape of the materials, features, or structures, and do not limit the scope of the claims.

[0044] The following description provides specific details, such as material types and processing conditions, to provide a comprehensive description of embodiments of the disclosed apparatus (e.g., devices, systems) and methods. However, those skilled in the art will understand that embodiments of the apparatus and methods can be practiced without these specific details. In fact, embodiments of the apparatus and methods can be implemented in conjunction with conventional semiconductor manufacturing techniques used in industry.

[0045] The manufacturing processes described herein do not form a complete process flow for processing equipment (e.g., apparatus, system) or its structure. The remainder of the process flow is known to those skilled in the art. Therefore, only the methods and structures necessary for understanding embodiments of the equipment (e.g., apparatus, system) and methods are described herein.

[0046] Unless the context otherwise requires, the materials described herein can be formed by any suitable technique, including but not limited to spin coating, blanket coating, chemical vapor deposition (“CVD”), atomic layer deposition (“ALD”), plasma-enhanced ALD, physical vapor deposition (“PVD”) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, those skilled in the art can choose the technique for depositing or growing the material.

[0047] Unless the context otherwise requires, the removal of the material described herein can be achieved by any suitable technique, including but not limited to etching (e.g., dry etching, wet etching, vapor phase etching), ion polishing, polishing planarization, or other known methods.

[0048] Referring to the accompanying drawings, the same reference numerals always denote the same components. The drawings are not necessarily drawn to scale.

[0049] Figure 1A microelectronic device structure 100 (e.g., a storage device structure, such as a 3D NAND storage device structure) according to an embodiment of the present disclosure is illustrated for a device (e.g., a storage device, such as a 3D NAND storage device) that may be included in a system. The microelectronic device structure 100 includes a stacked structure 102 having layers 104, and vertically alternating insulating structures 106 and conductive structures 108.

[0050] Below the stacked structure 102, one or more substrates or other base materials support the stacked structure 102. For example, the stacked structure 102 may be above a polysilicon structure 110, which may be above a conductive substrate structure 112 (e.g., containing one or more conductive materials, such as tungsten silicide), which may be above an additional substrate structure 114.

[0051] Conductive contacts 116 (e.g., support contacts, electrical contacts to underlying electrical components (e.g., CMOS (Complementary Metal-Oxide-Semiconductor) circuitry) extend through the height of the stacked structure 102, through the polysilicon structure 110, and into the conductive substrate structure 112. At least one insulating material 118 may be laterally adjacent to (e.g., laterally surrounding) the contacts 116, and the insulating material 118 may also extend through the height of the stacked structure 102, through the polysilicon structure 110, and into the conductive substrate structure 112.

[0052] In the lower portion 120 of the stacked structure 102 (e.g., the lower vertical region), insulating material 118 extends laterally outward away from the contact 116, forming an insulating extension 122 that alternates perpendicularly with the ends of the insulating structure 106 of the lower portion 120. Therefore, the width WL of a portion of the conductive structure 108 within the lower portion 120 (e.g., a portion of the conductive structure 108 laterally adjacent to the insulating extension 122 between adjacent contacts 116 of a pair of contacts 116) (e.g., lower conductive structure portion 124) is shorter than the width WU of at least some portions of the conductive structure 108 in the stacked portion above the lower portion 120 (e.g., upper conductive structure portion 126). Due to the gradual taper of adjacent materials, as further described below, the “width” of a particular portion of the conductive structure 108 above the lower portion 120 (e.g., upper conductive structure portion 126) can be its width along its uppermost surface, its width along its midline, its width along its lowermost surface, or an average of these.

[0053] In some embodiments, the lower portion 120 comprises a minimum of about 5% to about 20% of the total number (e.g., total number) of the layers 104 of the stacked structure 102. For example, in an embodiment where the stacked structure 102 comprises 200 layers 104, the lower portion 120 may comprise a minimum of about 10 layers 104 to a minimum of about 40 layers 104. The specific number of layers 104 included in the lower portion 120 may be selected or otherwise customized to the number most susceptible to bending, collapse, sagging, or other structural degradation without the insulating extension 122.

[0054] Contact 116 may taper in cross-sectional width (e.g., outer diameter) across the height of stacked structure 102 from its widest width at the top of stacked structure 102 to its narrowest width in conductive substrate structure 112. Insulating material 118 may also taper in cross-sectional width (e.g., outer diameter) across a portion of the height of stacked structure 102 from its widest width at the top of stacked structure 102 to its narrowest width immediately above the lower layer portion 120, before the width EW (e.g., outer diameter) of insulating extension 122 extending into lower layer portion 120. The width EW of insulating extension 122 may be greater than the widest width of insulating material 118 at the top of stacked structure 102.

[0055] In some embodiments, for example Figure 1 In the embodiments described herein, the liner 128 may be laterally adjacent to (e.g., laterally surrounding) the insulating material 118 in the portion of the stacked structure 102 located above the lower portion 120. The cross-sectional width (e.g., outer diameter) of the liner 128 gradually tapers from its widest width (e.g., width PW) at the top of the stacked structure 102 to its narrowest width immediately above the lower portion 120. The liner 128 may not be present in the lower portion 120.

[0056] A filler structure 130 (e.g., a region of filler material, such as polysilicon filler) extends through the stacked structure 102, dividing the stacked structure 102 into blocks, each block containing one or more of the contacts 116. The cross-sectional width (e.g., outer diameter) of the filler structure 130 gradually tapers from its widest width at the top of the stacked structure 102 to its narrowest width at or below the bottom of the stacked structure 102. Due to the presence of an insulating extension 122 in the lower portion 120, the width of a portion of the conductive structure 108 (e.g., within the lower portion 120 and between one of the contacts 116 and an adjacent one of the filler structures 130) is shorter than the width of a corresponding portion of at least one conductive structure 108 in the stacked portion above the lower portion 120 (e.g., the portion vertically above the lower portion and the portion between the same contact 116 and the same adjacent filler structure 130).

[0057] In any of the foregoing tapered materials or structures, at least in some embodiments, the slope of the corresponding taper may be substantially smooth, without grooves, extensions, steps, or other interruptions in the sidewalls that would otherwise define abrupt changes in slope. For example, the outer sidewall of the insulating material 118 may be substantially smooth until the insulating material 118 extends to define the insulating extension 122.

[0058] The insulating material of insulating structure 106 and / or insulating material 118 includes at least one electrically insulating material (e.g., a dielectric oxide material such as silicon dioxide; air). The insulating material of insulating structure 106 may be the same as or different from insulating material 118. In embodiments where insulating material 118 (and therefore insulating extension 122) and insulating structure 106 are formed of and comprise the same material, insulating structure 106 and insulating extension 122 may be visually indistinguishable in microelectronic device structure 100. If a liner 128 is present, it may also include one or more of the aforementioned insulating materials, which may be the same as or different from the insulating material of insulating structure 106 and / or insulating material 118.

[0059] The conductive material of the conductive structure 108 may include one or more conductive materials in one or more material regions. In some embodiments, the conductive structure 108 includes a conductive material (e.g., a metal such as tungsten) within an additional conductive material (e.g., a conductive liner such as tungsten nitride), the additional conductive material being disposed along a portion of the conductive structure 108 adjacent to the insulating structure 106 or other features of the microelectronic device structure 100, such as adjacent to the insulating material 118 of the adjacent contact 116.

[0060] In some embodiments, Figure 1 The stacked structure 102 of the microelectronic device structure 100 shown can represent one layer (e.g., the lowest layer) of a device structure comprising multiple layers, each layer comprising a stack of vertically alternating conductive and insulating layers. One or more of these additional stacks can be configured as Figure 1 The stacked structure 102 includes an insulating extension 122 of the substrate adjacent to the contacts 116 (e.g., along the lower layer portion 120). Each such stacked structure 102 can provide a “layer” of the microelectronic device structure 100. Therefore, the relative terms used to describe the structure of the stacked structure 102 (or other stacked structures) of this disclosure are not necessarily relative to another stacked structure of a multilayered microelectronic device structure. For example, when describing... Figure 1 When the content shown is shown, the “widest” width of the material is at least the widest width of the material relative to such visible portions of such material in the structure and / or device, and may or may not be the “widest” width of such material relative to all portions of such material in the whole structure and / or device.

[0061] Therefore, a microelectronic device is disclosed comprising a stacked structure having a vertically alternating sequence of insulating and conductive structures arranged in layers. Conductive contact structures extend through the stacked structure. Insulating material is located between the conductive contact structures and the layers of the stacked structure. In a lower portion of the stacked structure, one conductive structure (of the plurality of conductive structures) has a portion extending a first width between a pair of conductive contact structures. In a portion of the stacked structure above the lower portion, another conductive structure (of the plurality of conductive structures) has another portion extending a second width between the pair of conductive contact structures. The second width is greater than the first width.

[0062] A microelectronic device is also disclosed, comprising a stacked structure including a vertically alternating sequence of insulating and conductive structures arranged in layers. Contacts extend through the stacked structure. Insulating material is adjacent to the contacts and extends through the stacked structure. The insulating material includes insulating extensions that partially extend horizontally across the insulating structures in a lower vertical region of the stacked structure and alternate vertically with the insulating structures.

[0063] Microelectronic device structure, for example Figure 1 The microelectronic device structure 100 can be formed by a manufacturing method in which contact openings are formed (e.g., etched) according to a pattern defined in a hard mask through layers of a stacked structure of insulating structures 106 intersecting with a sacrificial structure, and then the sacrificial structure is recessed along the base of the contact openings in the lower layer portion 120. This recess effectively widens the base of the contact openings adjacent to the sacrificial structure without widening the size of the patterned openings in the hard mask. The recess is then filled with insulating material 118 before the process of replacing the remaining sacrificial material with conductive material to form the conductive structure 108, thereby forming an insulating extension 122. By recessing the sacrificial structure and filling it with insulating material 118, as a result of removing the sacrificial structure 206, the insulating structure 106 in the lower layer portion 120 includes shorter (e.g., narrower) cantilever or spanning portions that are less prone to bending, collapse, sagging, or other structural degradation during the formation of the conductive structure 108. Avoiding such structural degradation also enables the conductive structure 108 to be formed reliably.

[0064] exist Figures 2 to 11 as well as Figure 1 The diagram illustrates the various stages of the manufacturing process, in which... Figure 1 Indicates in Figure 11The method stages following the stages shown in the diagram. According to embodiments of this disclosure, the manufacturing method includes forming a stacked structure 202, wherein layers 204 provide vertically alternating insulating structures 106 and sacrificial structures 206. The sacrificial structure 206 comprises at least one sacrificial material, such as an insulating material that is different in composition from the insulating structure 106 (and different from the subsequently formed insulating material 118). Figure 1 The dielectric material of the at least one sacrificial material may include a dielectric nitride material, such as silicon nitride (e.g., in an embodiment where the insulating structure 106 includes an oxide dielectric material (e.g., silicon dioxide)).

[0065] Before forming the stacked structure 202, a conductive substrate structure 112 may be formed (e.g., deposited) on the substrate structure 114, and a polysilicon structure 110 may be formed (e.g., deposited) on the conductive substrate structure 112. Next, the stacked structure 202 can be formed by sequentially forming (e.g., depositing) insulating material of the insulating structure 106 and sacrificial material of the sacrificial structure 206 above the polysilicon structure 110, the conductive substrate structure 112, and the substrate structure 114 from a lower height to a higher height.

[0066] A hard mask 208 may be formed (e.g., deposited) over the stacked structure 202 and may define a pattern of patterned openings 210. Each patterned opening 210 defines the size of the contact opening to be formed (e.g., pattern width PW). The sizes of the patterned openings 210 may be the same as each other, or they may vary from one patterned opening 210 to another.

[0067] refer to Figure 3 Then, an opening 302 may be formed (e.g., etched) to partially extend through the stacked structure 202 to reach (but not through) the lower layer portion 120, depending on the number of layers 204 selected to be included in the lower layer portion 120, as discussed above. In some embodiments, the opening 302 may expose one of the insulating structures 106 at the top of the lower layer portion 120 at its bottom. In other embodiments, for example... Figure 3 In the embodiment described herein, opening 302 may expose one of the sacrificial structures 206 at the top of the lower portion 120 at its bottom. The depth of opening 302 can be customized by customizing other parameters of timing, etching chemistry, or material removal process.

[0068] refer to Figure 4 Then at least in the limited opening 302 ( Figure 3A liner 128 is formed (e.g., deposited, such as by ALD conformal deposition) on the sidewalls of the hard mask 208. In some embodiments, the liner 128 may also be formed in the substrate of the opening 302, for example on the upper surface of the lower portion 120 exposed in the opening 302. In these or other embodiments, the liner 128 may also be formed on the exposed surface of the hard mask 208.

[0069] The liner 128 can be relatively thin, with a thickness in the range of about 4 nm to about 40 nm.

[0070] The liner 128 may be formed of and include a non-conductive material having a composition that differs from, at least in terms of etching selectivity, from, the material of the sacrificial structure 206, so that the material of the sacrificial structure 206 may subsequently be etched without completely removing the liner 128.

[0071] Liner 128 may be sacrificial or non-sacrificial. In embodiments where lining 128 is configured as non-sacrificial, for example in... Figures 2 to 11 and Figure 1 In embodiments where the sacrificial structure 206 comprises silicon nitride or other materials having greater etch selectivity than the silicon dioxide of the liner 128, the liner 128 may be formed of and comprise, for example, an insulating material such as a dielectric oxide material (e.g., silicon dioxide). In embodiments where the liner 128 is configured as a sacrifice, such as in the embodiments discussed below, if the sacrificial structure 206 comprises silicon nitride or other materials having greater etch selectivity than the polysilicon of the liner 128, the liner 128 may be formed of and comprise, for example, polysilicon.

[0072] Then, as Figure 5 As shown, the liner opening 402 can be extended to form an extended opening 502. More specifically, selected portions of the liner 128 can be removed (e.g., etched) while leaving the liner 128 in place on the sidewalls of the extended opening 502 along the lower layer portion 120. For example, portions of the liner 128 covering previously exposed surfaces of the lower layer portion 120 can be removed, as well as optionally, portions of the liner 128 above the hard mask 208. The remaining portion of the liner 128 can provide protection to the stacked structure 102 and sacrificial structure 206 of the layer 204 above the lower layer portion 120 during subsequent processing.

[0073] While one might ideally desire to form an extended opening 502 with perfectly vertical sidewalls extending through the stacked structure 202, it should be understood in the art that practical limitations in material removal processes (e.g., etching processes) inherently result in more material being removed at the upper height of the stacked structure (e.g., stacked structure 202) than at the lower height. Therefore, in practice, the extended opening 502 may present its widest width from the top of the stacked structure 202 (e.g., Figure 2 The pattern width (PW) gradually tapers from its narrowest width at the base of the extended opening 502 (e.g., at the conductive substrate structure 112, below the lower portion 120) to its narrowest width (e.g., horizontal dimension, lateral dimension). Similarly, Figure 3 The opening 302 may also be tapered, such that the width (e.g., outer diameter) of the liner 128 may gradually decrease from the top of the stacked structure 202 to its bottom just above the lower portion 120.

[0074] Using this tapered shape, it should be noted that the insulating structure 106 and the sacrificial structure 206 widen with increasing depth from the top of the stacked structure 202. In other words, the width of the insulating structure 106 and the sacrificial structure 206 decreases with increasing height relative to the base structure 114. Therefore, in the lower layer portion 120, the insulating structure 106 is wider (e.g., longer in the horizontal dimension) than the insulating structure 106 above the lower layer portion 120. If the material of the sacrificial structure 206 is removed from layer 204 without further modification to the width of the insulating structure 106 or the sacrificial structure 206, then the insulating structure 106 in the lower layer portion 120 will include the longest cantilever and span portion unsupported from above and below, and is therefore most susceptible to bending, collapse, sagging, or other structural degradation when the material of the sacrificial structure 206 is removed. That is, shorter (e.g., narrower width) cantilever and span portions may be less susceptible to structural degradation than longer (e.g., wider) cantilever and span portions.

[0075] Then the hard mask 208 can be removed (e.g., stripped), as shown below. Figure 6 As shown. Simultaneously, before, or after, the sacrificial structure 206 within the lower portion 120 can be recessed. For example, the extended opening 502 can be selectively removed (e.g., etched, such as using a wet nitride etching chemical) relative to the insulating structure 106. Figure 5 The portion of the sacrificial structure 206 is such that the sacrificial structure 206 is recessed by a lateral distance D, for example, about 50 nm to about 60 nm, relative to the sidewall of the adjacent insulator 106 facing the opening.

[0076] The recessed sacrificial structure 206 effectively widens the extended opening 502 at the height of the sacrificial structure 206 in the lower portion 120. Figure 5The base of the base is such that a recess 604 of the sacrificial structure 206 adjacent to the lower portion 120 is formed by a base widened by an opening 602. Within the height of the sacrificial structure 206, the extended width EW of the widened bottom opening 602 (and therefore also the extended width EW of the recess 604, e.g., the outer diameter of the recess 604) is equal to the lateral distance D plus the width previously formed by the extended opening 502 ( Figure 5 Twice the width defined by the extended opening 502. Therefore, in embodiments where the sacrificial structure 206 is recessed by a lateral distance D between approximately 50 nm and approximately 60 nm, each recess 604 may have an outer diameter, for example, in the range of approximately 100 nm to approximately 120 nm, plus the width previously defined by the extended opening 502. Figure 5 The width defined by the initial opening 302. In some embodiments, the extended width EW may also be tapered, decreasing with increasing depth toward the substrate structure 114 (e.g., decreasing with decreasing height relative to the substrate structure 114), but interrupted by an insulating structure 106 that may not be recessed. The extended width EW (e.g., at least at the height of the uppermost sacrificial structure 206 of the lower portion 120) may be greater than that used to form the initial opening 302. Figure 3 The patterned size PW width.

[0077] The groove 604 shortens a portion of the sacrificial structure 206 in the lower portion 120, such that the lower sacrificial structure portion 606 (e.g., the portion of sacrificial structure 206 within the lower portion 120 and between a pair of adjacent base-enlarged openings 602) is shorter (e.g., narrower) than the upper sacrificial structure portion 608 (e.g., the portion of sacrificial structure 206 adjacent but above the lower portion 120 and between the same pair of adjacent base-enlarged openings 602).

[0078] refer to Figure 7 Then, an insulating material 118 can be formed (e.g., deposited) to fill the groove 604. Figure 6 This forms an insulating extension 122 of the sacrificial structure 206 in the adjacent lower portion 120. An insulating material 118 is also formed on the liner 128. The insulating material 118 may be formed to define a contact opening 702 extending through the stacked structure 202.

[0079] refer to Figure 8 The substrate portion of the insulating material 118 can then be removed (e.g., etched) to expose the contact opening 702. Figure 7 The surface of the conductive substrate structure 112 in the contact opening 702 is then used to form the contact 116 (e.g., by depositing conductive material of the contact 116).

[0080] refer to Figure 9Then, slits 902 can be formed (e.g., etched) through the stacked structure 202 to define the block portion. Figure 3 Opening 302 and Figure 5 Similar to the formation of the extended opening 502, the slit 902 may also present a tapered shape extending through the height of the stacked structure 202 due to practical limitations in material removal processes (e.g., etching processes).

[0081] Next, a gate replacement process is performed to remove (e.g., expose) the sacrificial material of the sacrificial structure 206, such as Figure 10 As shown, this forms a stacked structure 1002, which is essentially composed of an insulating structure 106 or consists of insulating structures that extend laterally from or between the insulating material 118 adjacent to the contact 116 and have gaps above and below. Due to the prior formation of the insulating extension 122, the sacrificial structure 206 is removed from the lower portion 120. Figure 9 The resulting lower layer void 1004 is formed by removing the sacrificial structure 206 from the adjacent but above the lower layer portion 120. Figure 9 The resulting upper-layer void 1006 is narrower.

[0082] The insulation structure 106 of the stacked structure 1002 includes a spanning portion 1008 that crosses between adjacent contacts 116 (e.g., extending laterally directly between insulating materials 118 adjacent to adjacent contacts 116). In the lower portion 120, the spanning portion 1008 extends between opposing insulating extensions 122. Due to the previously formed insulating extensions 122, the width WL of one of the spanning portions 1008 in the lower portion 120 of the stacked structure 1002 is smaller than the width WU of one of the spanning portions 1008 above but adjacent to the lower portion 120.

[0083] The insulation structure 106 of the stacked structure 1002 also includes a cantilever portion 1010 that extends laterally from one of the contacts 116 (e.g., directly from the insulating material 118 of an adjacent contact 116) to one of the slits 902. In the lower portion 120, each of the cantilever portions 1010 extends from a corresponding one of the insulating extensions 122. Due to the previously formed insulating extensions 122, the width CWL of one of the cantilever portions 1010 in the lower portion 120 of the stacked structure 1002 is smaller than the width CWU of an adjacent cantilever portion 1010 above the lower portion 120 of the stacked structure 1002.

[0084] Each span portion 1008 is substantially unsupported from above and below. Furthermore, each cantilever portion 1010 is substantially unsupported from above, below, and along one of the lateral sides of the covering slits 902. However, due to the relatively short width of the span portions 1008 and cantilever portions 1010 of the insulating structure 106 in the lower portion 120, these structures may be wider than they maintain their wider width (e.g., if structure 206 is sacrificed). Figure 9 It is less prone to bending, collapse, sagging or other structural degradation if it is not dented and if the insulating extension 122 is not formed before the sacrificial structure 206 is removed.

[0085] In removing (e.g., exposing) the sacrificial structure 206 ( Figure 9 After the sacrificial material is used, a conductive structure 108 can then be formed (e.g., Figure 1 The conductive material is used to fill the gaps (e.g., lower gap 1004 and upper gap 1006), such as Figure 11 As shown in the diagram. For example, a conductive liner (e.g., tungsten nitride) may first be formed to line the gaps (e.g., lower gap 1004 and upper gap 1006). Figure 10 On the exposed insulating structure 106 and insulating material 118, a conductive material (e.g., tungsten) may then be formed to fill the remaining space of the gap (e.g., lower gap 1004 and upper gap 1006). Figure 10 (the remaining space). The method for forming such conductive structures 108 in the gaps (e.g., lower gap 1004 and upper gap 1006) after the sacrificial material has been exposed is known in the art and therefore will not be described in detail herein.

[0086] Due to the improved structural integrity of the insulation structure 106 in the lower portion 120, and due to the previous recess of the sacrificial structure 206 ( Figure 6 ) and the prior formation of the insulating extension 122 ( Figure 7 This can prevent bending, collapse, sagging, or other structural degradation of the insulation structure 106 of the lower portion 120. That is, without the formation of recesses and insulation extensions 122, the insulation structures 106 most prone to bending, collapse, sagging, or other structural degradation may be more robust than they would otherwise be. Therefore, the gaps between the insulation structures 106 of the lower portion 120 (e.g., lower gap 1004) can prevent bending, collapse, sagging, or other structural degradation of the insulation structure 106. Figure 10 Conductive materials that can be opened more reliably and in which conductive structures 108 can be formed more easily.

[0087] After forming the conductive material of the conductive structure 108, the conductive material is formed to fill only the gaps (e.g., the lower gap 1004 and the upper gap 1006). Figure 10The slit 902 can be retained without extending further into the slit 902 or by overfilling the gap and then performing another material removal (e.g., etching) stage to reform the slit 902. The slit 902 can then be filled by forming a filler material (e.g., polysilicon material) within the slit 902 to form a shape such as... Figure 1 The filling material structure 130 shown forms a microelectronic device structure (e.g., Figure 1 Microelectronic device structure 100).

[0088] Therefore, a method for forming a microelectronic device is disclosed. The method includes forming a stacked structure comprising a vertically alternating sequence of insulating and sacrificial structures arranged in layers. At least one opening extending through the stacked structure is formed. A liner is formed within a portion of the at least one opening, the portion being above a lower layer portion of the stacked structure. In the lower layer portion of the stacked structure, the sacrificial structure is recessed to form a groove along the at least one opening. An insulating material is formed within the at least one opening and the groove. At least one conductive contact structure is formed directly adjacent to the insulating material to fill the remaining portion of the at least one opening. The sacrificial structure is replaced with a conductive structure.

[0089] Although Figures 2 to 11 and Figure 1 The method shown includes extending an opening through the lower portion 120 (e.g., forming an extension opening 502). Figure 5 The lining was formed 128 (before) Figure 4 However, in other methods, such as Figures 12 to 15 As shown, the lining 128 can be formed after the full-length opening has been formed. For example, see reference... Figure 12 The opening 1202 can be formed (e.g., etched) by using a hard mask 208 patterned to define the opening size PW, and the opening 1202 can be formed to extend fully through the height of the stacked structure 202 and reach or enter the conductive substrate structure 112. Due to practical limitations in the material removal (e.g., etching) process, the width of the opening 1202 can be gradually reduced.

[0090] Within the opening 1202, a liner 1302 is formed on the sidewall of the opening 1202 above the lower layer portion 120, forming an opening 1304 that partially forms the inner liner. For example, the liner 1302 may be formed of an oxide with a thickness between about 4 nm and about 40 nm (e.g., formed by a diffusion process via conformal deposition of ALD).

[0091] refer to Figure 14 The sacrificial structure 206 in the lower part 120 can be referenced above. Figure 6 The depressions are described in essentially the same way.

[0092] The manufacturing process can be referenced as above. Figures 7 to 11 as well as Figure 1 The process is carried out to form Figure 15 The microelectronic device structure 1500. Except for liner 1302 replacing liner 128 ( Figure 1 In addition to the above, the characteristics of the microelectronic device structure 1500 are as described above regarding... Figure 1 As stated, and individual material or feature dimensions can be derived from Figure 1 The dimensions shown change to Figure 15 The dimensions shown.

[0093] refer to Figures 16 to 18 According to the lining 128 ( Figure 6 This is an example of a sacrificial portion, illustrating various stages in a method of fabricating a microelectronic device structure, these stages being... Figures 2 to 6 Following this stage. More specifically, the sacrificial structure 206 in the recessed lower portion 120 forms a structure with an extended width EW. Figure 6 After the lining 128 is widened at the bottom 602, the lining 128 can be removed to form an opening 1602 with a widened bottom. Figure 16 The structure is shown. Therefore, the liner 128 can be formed of and include a sacrificial material, such as polycrystalline silicon.

[0094] refer to Figure 17 Then, insulating material 118 can be directly formed (e.g., deposited) on the sidewalls of insulating structure 106 and sacrificial structure 206 of layer 204 of stacked structure 202. In the lower layer portion 120, insulating material 118 fills groove 604 ( Figure 6 Because before extending the opening into the lower portion 120 (e.g., during the formation of...). Figure 5 The lining 128 (formed before the extended opening 502) Figure 6 The previous removal of the insulating material 118 allows the width of the resulting opening 1702 to gradually decrease from the top of the stacked structure 202 to at least the lower portion 120, and then decrease more abruptly to continue or further gradually decrease the width through the lower portion 120.

[0095] refer to Figure 18 Before forming (e.g., depositing) a conductive material in the opening 1702 to form the microelectronic device structure 1800 containing contacts 1802, a substrate portion of the insulating material 118 may be removed (e.g., etched) to form the conductive material in the opening 1702. Figure 17 A portion of the conductive substrate structure 112 is exposed in the contact 1802. The conductive material of the contact 1802 may be made of materials used for... Figure 1The contact 116 may be formed of or comprise any of the aforementioned materials. The contact 1802 may gradually decrease in width across the stacked structure 102 to at least the lower portion 120, and may then decrease more abruptly to continue or further gradually decrease in width across the lower portion 120.

[0096] refer to Figure 19 and Figure 20 According to its lining 1302 ( Figure 14 This is an example of a sacrificial portion, illustrating various stages in a method of fabricating a microelectronic device structure, these stages being... Figures 12 to 14 Following this stage. More specifically, the sacrificial structure 206 in the recessed lower portion 120 forms a structure with an extended width EW. Figure 14 After the lining 1302 is widened at the bottom, the lining can be removed to form an opening 1602 with a widened bottom. Figure 19 The structure is shown. Therefore, the liner 1302 can be formed of and include a sacrificial material, such as polycrystalline silicon.

[0097] refer to Figure 20 Then, insulating material 118 can be directly formed (e.g., deposited) on the sidewalls of insulating structure 106 and sacrificial structure 206 of layer 204 of stacked structure 202. In the lower layer portion 120, insulating material 118 fills groove 604 ( Figure 14 Before forming (e.g., depositing) a conductive material to form the microelectronic device structure 2000 having contacts 116, a base portion of the insulating material 118 may be removed (e.g., etched) to expose a portion of the conductive base structure 112. This is because after forming an opening that fully extends through the stacked structure 202 (including through the lower layer portion 120) (e.g., after forming...). Figure 12 The lining 1302 (formed after the opening 1202) Figure 14 The previous removal of the contact 116 results in a contact 116 that tapers in width from the top of the stacked structure 102 to (e.g.) the conductive substrate structure 112.

[0098] Figure 21 A partial cross-sectional perspective view of a portion of a microelectronic device 2100 (e.g., a storage device, such as a 3D NAND flash memory device) including a microelectronic device structure 2102 is shown. The microelectronic device structure 2102 may be substantially similar to... Figure 1 Microelectronic device structure 100 Figure 15 Microelectronic device structure 1500, Figure 18 Microelectronic device structure 1800 and / or Figure 20 The structure of microelectronic devices 2000. For example... Figure 21As shown, the microelectronic device structure 2102 may include a stepped structure 2104 defined for connecting access lines 2106 to a conductive layer 2108 (e.g., a conductive layer, conductive plate, such as conductive structure 108). Figure 1 , Figure 15 , Figure 18 , Figure 20 The contact area of ​​the microelectronic device structure 2102 may include vertical strings 2110 of memory cells 2114 coupled in series with each other. The vertical strings 2110 may extend perpendicularly (e.g., in the Z direction) and orthogonally relative to the conductive layer 2108 to the data lines 2112, and to the source layer 2116 (e.g., the stacked structure 102). Figure 1 , Figure 15 , Figure 18 , Figure 20 The conductive substrate structure 112 below Figure 1 , Figure 15 , Figure 18 , Figure 20 The gate extends to access line 2106, to first select gate 2118 (e.g., upper select gate, drain select gate (SGD)), to select line 2120, and to second select gate 2122 (e.g., lower select gate, source select gate (SGS)). The first select gate 2118 may be horizontally divided (e.g., in the Y direction) into multiple blocks 2124, passing through slits 2130 (e.g., filled with filler material structure 130). Figure 1 , Figure 15 , Figure 18 , Figure 20 ) slit 902 ( Figure 9 They are horizontally separated from each other (e.g., in the Y direction).

[0099] As shown in the figure, vertical conductive contact 2126 (e.g., contact 116) Figure 1 , Figure 15 , Figure 20 Contact 1802 Figure 18The components can be electrically coupled to each other, as shown in the figure. For example, select line 2120 can be electrically coupled to a first select gate 2118, and access line 2106 can be electrically coupled to conductive layer 2108. The microelectronic device 2100 may also include a control unit 2128 located below the memory array, which may include at least one of the following: string driver circuitry, through gates, circuitry for selecting gates, circuitry for selecting wires (e.g., data line 2112, access line 2106), circuitry for amplifying signals, and circuitry for sensing signals. The control unit 2128 may be electrically coupled to, for example, data line 2112, source layer 2116, access line 2106, first select gate 2118, and second select gate 2122. In some embodiments, the control unit 2128 includes CMOS (complementary metal-oxide-semiconductor) circuitry. In such embodiments, the control unit 2128 may be characterized as having an "under-array CMOS" ("CuA") configuration.

[0100] The first selection gate 2118 may extend horizontally in a first direction (e.g., the X direction) and may be coupled to a corresponding first set of vertical strings 2110 of the memory cell 2114 at a first end (e.g., the upper end). The second selection gate 2122 may be formed in a generally planar configuration and may be coupled to the vertical strings 2110 at a second opposite end (e.g., the lower end) of the vertical strings 2110 of the memory cell 2114.

[0101] Data lines 2112 (e.g., bit lines) may extend horizontally in a second direction (e.g., the Y direction) at an angle (e.g., vertical) to a first direction extending from the first select gate 2118. Data lines 2112 may be coupled at a first end (e.g., the upper end) of a vertical string 2110 to a corresponding second group of vertical strings 2110. The first group of vertical strings 2110 coupled to the corresponding first select gate 2118 may share a specific vertical string 2110 with the second group of vertical strings 2110 coupled to the corresponding data lines 2112. Therefore, a specific vertical string 2110 at the intersection of a specific first select gate 2118 and a specific data line 2112 can be selected. Thus, the first select gate 2118 can be used to select a memory cell 2114 of the vertical string 2110 of the memory cell 2114.

[0102] Conductive layers 2108 (e.g., word lines) may extend in a corresponding horizontal plane. The conductive layers 2108 may be vertically stacked such that each conductive layer 2108 is coupled to all vertical strings 2110 of the memory cells 2114, and the vertical strings 2110 of the memory cells 2114 extend vertically through the stack of conductive layers 2108. The conductive layers 2108 may be coupled to or may form the control gate of the memory cells 2114 coupled to the conductive layers 2108. Each conductive layer 2108 may be coupled to one memory cell 2114 of a particular vertical string 2110 of the memory cells 2114.

[0103] The first select gate 2118 and the second select gate 2122 are operable to select a specific vertical string 2110 of memory cells 2114 between a specific data line 2112 and the source layer 2116. Therefore, a specific memory cell 2114 can be selected and electrically coupled to the data line 2112 by the operation (e.g., by selection) of the appropriate first select gate 2118, second select gate 2122 and conductive layer 2108 coupled to the specific memory cell 2114.

[0104] The stepped structure 2104 can be configured to provide an electrical connection between the access line 2106 and the conductive layer 2108 via a vertical conductive contact 2126. In other words, a particular layer of the conductive layer 2108 can be selected via one of the access lines 2106 that are electrically connected to a corresponding one of the conductive contacts 2126 (which are electrically connected to the particular conductive layer 2108).

[0105] Data line 2112 can be electrically coupled to vertical string 2110 through conductive structure 2132.

[0106] Including microelectronic device structures (e.g., Figure 1 Microelectronic device structure 100 Figure 15 Microelectronic device structure 1500, Figure 18 Microelectronic device structure 1800 and / or Figure 20 The microelectronic device (e.g., microelectronic device 2100) of the microelectronic device structure 2000 can be used in embodiments of the electronic system disclosed herein. For example, Figure 22 This is a block diagram of an electronic system 2200 according to an embodiment of the present disclosure. The electronic system 2200 may include, for example, a computer or computer hardware component, a server or other networked hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or internet-enabled tablet computer (e.g.,...). or Tablet computers, e-book readers, navigation devices, etc. Electronic system 2200 includes at least one storage device 2202. Storage device 2202 may include embodiments of, for example, microelectronic devices and / or structures previously described herein (e.g., tablet computers, e-book readers, navigation devices, etc.). Figure 1 Microelectronic device structure 100 Figure 15 Microelectronic device structure 1500, Figure 18 Microelectronic device structure 1800, Figure 20 Microelectronic device structure 2000 Figure 21 The microelectronic device 2100 has a structure formed according to the method of the embodiments previously described herein.

[0107] The electronic system 2200 may also include at least one electronic signal processor device 2204 (generally referred to as a “microprocessor”). The processor device 2204 may optionally include embodiments of the microelectronic devices and / or microelectronic device structures previously described herein (e.g., Figure 1 Microelectronic device structure 100 Figure 15 Microelectronic device structure 1500, Figure 18 Microelectronic device structure 1800, Figure 20 Microelectronic device structure 2000 Figure 21 The electronic system 2200 may also include one or more input devices 2206 for users to input information into the electronic system 2200, such as a mouse or other pointing device, a keyboard, a touchpad, buttons, or a control panel. The electronic system 2200 may also include one or more output devices 2208 for outputting information to the user (e.g., visual or audio output), such as a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, the input device 2206 and the output device 2208 may include a single touchscreen device, which can be used both to input information into the electronic system 2200 and to output visual information to the user. The input device 2206 and the output device 2208 may be in electrical communication with one or more of the memory device 2202 and the electronic signal processor device 2204.

[0108] refer to Figure 23 A block diagram of a processor-based system 2300 is shown. The processor-based system 2300 may include various microelectronic devices manufactured according to embodiments of the present disclosure (e.g., Figure 21 Microelectronic device 2100) and microelectronic device structure (e.g., Figure 1 Microelectronic device structure 100 Figure 15 Microelectronic device structure 1500, Figure 18 Microelectronic device structure 1800, Figure 20The microelectronic device architecture 2000). The processor-based system 2300 can be any of various types, such as a computer, pager, cellular phone, personal manager, control circuitry, or other electronic device. The processor-based system 2300 may include one or more processors 2302, such as microprocessors, to control system functions and request processing within the processor-based system 2300. The processor 2302 and other sub-components of the processor-based system 2300 may include microelectronic devices manufactured according to embodiments of this disclosure (e.g., Figure 21 Microelectronic device 2100) and microelectronic device structure (e.g., Figure 1 Microelectronic device structure 100 Figure 15 Microelectronic device structure 1500, Figure 18 Microelectronic device structure 1800, Figure 20 Microelectronic device structure (2000).

[0109] The processor-based system 2300 may include a power supply 2304 operatively communicating with the processor 2302. For example, if the processor-based system 2300 is a portable system, the power supply 2304 may include one or more of a fuel cell, a power harvesting device, a permanent battery, a replaceable battery, and / or a rechargeable battery. The power supply 2304 may also include an AC adapter; thus, for example, the processor-based system 2300 can be plugged into a wall outlet. The power supply 2304 may also include a DC adapter, such that, for example, the processor-based system 2300 can be plugged into a vehicle cigarette lighter or a vehicle power port.

[0110] Depending on the functions performed by the processor-based system 2300, various other devices may be coupled to the processor 2302. For example, a user interface 2306 may be coupled to the processor 2302. The user interface 2306 may include one or more input devices, such as buttons, switches, keyboards, light pens, mice, digitizers and styluses, touchscreens, voice recognition systems, microphones, or combinations thereof. A display 2308 may also be coupled to the processor 2302. The display 2308 may include an LCD display, a SED display, a CRT display, a DLP display, a plasma display, an OLED display, an LED display, a 3D projector, an audio display, or combinations thereof. Furthermore, an RF subsystem / baseband processor 2310 may also be coupled to the processor 2302. The RF subsystem / baseband processor 2310 may include antennas coupled to an RF receiver and an RF transmitter. A communication port 2312 or more communication ports 2312 may also be coupled to the processor 2302. The communication port 2312 may be adapted to be coupled to one or more peripheral devices 2314 (e.g., modem, printer, computer, scanner, camera) and / or coupled to a network (e.g., local area network (LAN), remote area network, intranet, or Internet).

[0111] Processor 2302 can control processor-based system 2300 by implementing software programs stored in memory (e.g., system memory 2316). Software programs may include, for example, operating systems, database software, graphics software, word processing software, media editing software, and / or media playback software. Memory (e.g., system memory 2316) is operatively coupled to processor 2302 to store and facilitate the execution of various programs. For example, processor 2302 may be coupled to system memory 2316, which may include one or more of spin torque transfer magnetic random access memory (STT MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM), static random access memory (SRAM), track memory, and / or other known memory types. System memory 2316 may include volatile memory, non-volatile memory, or a combination thereof. System memory 2316 is typically large enough to store dynamically loaded applications and data. In some embodiments, system memory 2316 may include the aforementioned semiconductor devices (e.g., Figure 21 Microelectronic devices 2100) and structures (e.g., Figure 1 Microelectronic device structure 100 Figure 15 Microelectronic device structure 1500, Figure 18 Microelectronic device structure 1800, Figure 20 Microelectronic device structure 2000) or combination thereof.

[0112] Processor 2302 may also be coupled to non-volatile memory 2318, which does not mean that system memory 2316 must be volatile. Non-volatile memory 2318 may include one or more of STT-MRAM, MRAM, read-only memory (ROM) (e.g., EPROM, resistive read-only memory (RROM)), and flash memory used in conjunction with system memory 2316. The size of non-volatile memory 2318 is typically chosen to be just large enough to store any necessary operating system, applications, and fixed data. Additionally, non-volatile memory 2318 may include high-capacity memory (e.g., disk drive memory, such as a hybrid drive including resistive memory or other types of non-volatile solid-state memory). Non-volatile memory 2318 may include the aforementioned microelectronic devices (e.g., Figure 21 Microelectronic devices 2100) and structures (e.g., Figure 1 Microelectronic device structure 100 Figure 15 Microelectronic device structure 1500, Figure 18 Microelectronic device structure 1800, Figure 20 Microelectronic device structure 2000) or combination thereof.

[0113] Therefore, an electronic system comprising an input device, an output device, a processor device, and a memory device is disclosed. The processor device is operatively coupled to the input device and the output device. The memory device is operatively coupled to the processor device. The memory device includes at least one microelectronic device structure. The at least one microelectronic device structure includes contacts extending through a stacked structure of vertically alternating insulating and conductive structures arranged in layers. The conductive structure includes at least one lower conductive structure portion between adjacent pairs of contacts in the lower layer portion of the stacked structure. In an additional portion of the stacked structure above the lower layer portion, the conductive structure further includes at least one upper conductive structure portion between adjacent pairs of contacts. The at least one lower conductive structure portion has a width narrower than the at least one upper conductive structure portion.

[0114] Non-limiting exemplary embodiments may include, individually or in combination, the following:

[0115] Example 1: A microelectronic device comprising: a stacked structure including a vertically alternating sequence of insulating and conductive structures arranged in layers; conductive contact structures extending through the stacked structure; and an insulating material between the conductive contact structures and the layers of the stacked structure; in a lower portion of the stacked structure, one of the plurality of conductive structures has a portion extending a first width between a pair of conductive contact structures; in a portion of the stacked structure above the lower portion, another conductive structure of the plurality of conductive structures has another portion extending a second width between the pairs of conductive contact structures, the second width being greater than the first width.

[0116] Example 2: The microelectronic device according to Example 1, wherein the conductive contact structure gradually tapers in width from the widest width at the top of the stacked structure to the narrowest width at or below the bottom of the stacked structure.

[0117] Example 3: A microelectronic device according to any one of Examples 1 and 2, wherein: the insulating material passes through the portion above the lower layer of the stacked structure and gradually tapers in width; and the insulating material in the lower layer extends laterally to define an insulating extension perpendicularly adjacent to the end of the insulating structure of the lower layer.

[0118] Example 4: A microelectronic device according to any one of Examples 1 to 3, wherein the conductive structure of the lower portion of the stacked structure is laterally recessed relative to the insulating structure of the lower portion of the stacked structure.

[0119] Example 5: The microelectronic device according to any one of Examples 1 to 4 further includes a liner between the insulating material and the layers of the stacked structure in the portion of the stacked structure above the lower layer portion.

[0120] Example 6: The microelectronic device according to Example 5, wherein the liner comprises an oxide material.

[0121] Example 7: A microelectronic device according to any one of Examples 1 to 6, wherein the insulating material is directly adjacent to the ends of the conductive contact structure and the layers of the stacked structure.

[0122] Example 8: A microelectronic device according to any one of Examples 1 to 7, wherein the outer diameter of the insulating material at the height of the uppermost part of the conductive structure of the lower layer of the stacked structure is greater than the outer diameter of the insulating material at the height of the uppermost part of the conductive structure of the stacked structure.

[0123] Example 9: The microelectronic device according to Example 8, wherein the outer diameter of the insulating material at the uppermost height of the conductive structure in the lower layer is at least about 100 nm.

[0124] Example 10: A microelectronic device according to any one of Examples 1 to 9, wherein the lower layer comprises about 5% to about 20% of the total number of layers present in the stacked structure.

[0125] Example 11: A microelectronic device comprising: a stacked structure including a vertically alternating sequence of insulating and conductive structures arranged in layers; a contact extending through the stacked structure; and an insulating material adjacent to the contact and extending through the stacked structure, the insulating material including an insulating extension that partially extends horizontally across the insulating structure and vertically alternates with the insulating structure in a lower vertical region of the stacked structure.

[0126] Example 12: The microelectronic device according to Example 11, wherein the insulating material above the lower vertical region of the stacked structure does not include the insulating extension.

[0127] Example 13: A microelectronic device according to any one of Examples 11 and 12, wherein: the conductive structure of the stacked structure comprises: a lower conductive structure in a lower vertical region of the stacked structure; and an upper conductive structure in an upper vertical region of the stacked structure, the upper vertical region covering the lower vertical region; and a portion of the lower conductive structure is relatively shorter in horizontal dimension than a portion of the upper conductive structure, the portion of the lower conductive structure and the portion of the upper conductive structure extending between a pair of contacts.

[0128] Example 14: A microelectronic device according to any one of Examples 11 to 13, wherein the conductive structure in the lower vertical region is laterally recessed relative to other conductive structures in the conductive structure above the lower vertical region.

[0129] Example 15: A microelectronic device according to any one of Examples 11 to 14, wherein the lower vertical region of the stacked structure comprises about 10 layers to about 40 layers.

[0130] Example 16: A method of forming a microelectronic device, the method comprising: forming a stacked structure comprising a vertically alternating sequence of insulating structures and sacrificial structures arranged in layers; forming at least one opening extending through the stacked structure; forming a liner within a portion of the at least one opening, the portion being above a lower layer portion of the stacked structure; recessing the sacrificial structure in the lower layer portion of the stacked structure to form a groove along the at least one opening; forming an insulating material within the at least one opening and the groove; forming at least one conductive contact structure directly adjacent to the insulating material to fill the remaining portion of the at least one opening; and replacing the sacrificial structure with a conductive structure.

[0131] Example 17: According to the method of Example 16, forming the at least one opening extending through the stacked structure includes forming the at least one opening extending through the stacked structure using a hard mask that defines at least one opening size, the at least one opening size being smaller than the horizontal outer diameter of at least one of the grooves formed by recessing the sacrificial structure into the lower portion of the stacked structure.

[0132] Example 18: The method according to any one of Examples 16 and 17, wherein forming the at least one opening extending through the stacked structure and forming the liner within the portion of the at least one opening comprises: forming at least one partial opening extending through an upper portion of the stacked structure, the upper portion being above the lower portion; forming a material of the liner on a surface exposed within the at least one partial opening; and etching a base of the material of the liner through and through the lower portion to form the at least one opening extending through the stacked structure and the liner within the portion of the at least one opening.

[0133] Example 19: The method according to any one of Examples 16 and 17, wherein forming the at least one opening extending through the stacked structure precedes forming the liner within the portion of the at least one opening.

[0134] Example 20: The method according to any one of Examples 16 to 19, wherein forming the lining within the portion of the at least one opening comprises forming a non-sacrificial oxide material.

[0135] Example 21: The method according to any one of Examples 16 to 19, wherein forming the liner within the portion of the at least one opening comprises forming a sacrificial polycrystalline silicon material.

[0136] Example 22: The method according to any one of Examples 16 to 21, wherein recessing the sacrificial structure to form a groove along the at least one opening comprises recessing the insulating structure of the sacrificial structure relative to the lower portion of the stacked structure.

[0137] Example 23: An electronic system comprising: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and comprising at least one microelectronic device structure, the at least one microelectronic device structure comprising contacts extending through a vertically alternating stacked structure of insulating and conductive structures arranged in layers, the conductive structure comprising: at least one lower conductive structure portion in a lower portion of the stacked structure between adjacent pairs of contacts; and at least one upper conductive structure portion in another portion of the stacked structure above the lower portion between adjacent pairs of contacts; the at least one lower conductive structure portion having a width narrower than the at least one upper conductive structure portion.

[0138] Example 24: The electronic system according to Example 23, wherein the at least one microelectronic device structure further includes an insulating material between the contact and the layers of the stacked structure, the insulating material including an insulating extension adjacent to a substrate of the contact, the insulating extension being perpendicularly alternated with the end of the insulating structure in the lower layer portion of the stacked structure.

[0139] While the disclosed structures, devices (e.g., apparatuses), systems, and methods are readily adaptable and replaceable in their embodiments, specific embodiments are illustrated by way of example in the accompanying drawings and are described in detail herein. However, this disclosure is not intended to be limited to the specific forms disclosed. Rather, this disclosure includes all modifications, combinations, equivalents, variations, and substitutions falling within the scope of this disclosure as defined by the appended claims and their legal equivalents.

Claims

1. A microelectronic device comprising: A stacked structure comprising a vertically alternating sequence of insulating and conductive structures arranged in layers; Conductive contact structures extending through the stacked structure; and Insulating material between the layers of the conductive contact structure and the stacked structure. In the lower portion of the stacked structure, one of the plurality of conductive structures has a portion extending a first width between a pair of conductive contact structures. In a portion of the stacked structure above the lower portion, another conductive structure of the plurality of conductive structures has a portion extending a second width between the pairs of conductive contact structures, the second width being greater than the first width.

2. The microelectronic device according to claim 1, wherein, The width of the conductive contact structure gradually tapers from its widest width at the top of the stacked structure to its narrowest width at or below the bottom of the stacked structure.

3. The microelectronic device according to claim 2, wherein: The insulating material, passing through the portion of the stacked structure above the lower layer, gradually tapers in width; and The insulating material in the lower portion extends laterally to define an insulating extension perpendicularly adjacent to the end of the insulating structure of the lower portion.

4. The microelectronic device according to any one of claims 1 to 3, wherein, The conductive structure of the lower portion of the stacked structure is laterally recessed relative to the insulating structure of the lower portion of the stacked structure.

5. The microelectronic device according to any one of claims 1 to 3, further comprising a liner between the insulating material in the portion of the stacked structure above the lower layer portion and the layers of the stacked structure.

6. The microelectronic device according to claim 5, wherein, The lining comprises an oxide material.

7. The microelectronic device according to any one of claims 1 to 3, wherein, The insulating material is directly adjacent to the ends of the layers of the conductive contact structure and the stacked structure.

8. The microelectronic device according to any one of claims 1 to 3, wherein, The outer diameter of the insulating material at the height of the uppermost part of the conductive structure in the lower layer of the stacked structure is greater than the outer diameter of the insulating material at the height of the uppermost part of the conductive structure in the stacked structure.

9. The microelectronic device according to claim 8, wherein, The outer diameter of the insulating material at the height of the uppermost part of the conductive structure in the lower layer is at least about 100 nm.

10. The microelectronic device according to any one of claims 1 to 3, wherein, The lower layer comprises approximately 5% to approximately 20% of the total number of the layers present in the stacked structure.

11. A microelectronic device comprising: A stacked structure comprising a vertically alternating sequence of insulating and conductive structures arranged in layers; Contacts extending through the stacked structure; and An insulating material adjacent to the contact and extending through the stacked structure, the insulating material including an insulating extension that extends horizontally across the insulating structure and alternates vertically with the insulating structure in the lower vertical region of the stacked structure, the insulating extension horizontally separating the contact from the conductive structure in the lower vertical region of the stacked structure.

12. The microelectronic device according to claim 11, wherein, Above the lower vertical region of the stacked structure, the insulating material does not include the insulating extension.

13. The microelectronic device according to claim 11, wherein: The conductive structure of the stacked structure includes: The lower conductive structure in the lower vertical region of the stacked structure; and An upper conductive structure in the upper vertical region of the stacked structure, the upper vertical region covering the lower vertical region; as well as The portion of the lower conductive structure is relatively shorter in horizontal dimension than the portion of the upper conductive structure, and the portions of the lower conductive structure and the upper conductive structure extend between a pair of contacts.

14. The microelectronic device according to any one of claims 11 to 13, wherein, The conductive structure in the lower vertical region is laterally recessed relative to the other conductive structures above the lower vertical region.

15. The microelectronic device according to any one of claims 11 to 13, wherein, The lower vertical region of the stacked structure comprises approximately 10 to approximately 40 layers.

16. A method of forming a microelectronic device, the method comprising: A stacked structure is formed, the stacked structure comprising a vertically alternating sequence of insulating structures and sacrificial structures arranged in layers; Form at least one opening extending through the stacked structure; A liner is formed within a portion of the at least one opening, the portion being above the lower portion of the stacked structure; In the lower portion of the stacked structure, the sacrificial structure is recessed to form a groove along the at least one opening; An insulating material is formed within the at least one opening and the groove to form an insulating extension; At least one conductive contact structure is formed directly adjacent to the insulating material to fill the remaining portion of the at least one opening; as well as The sacrificial structure is replaced by a conductive structure, wherein the conductive structure of the lower portion of the stacked structure is horizontally spaced from the at least one conductive contact structure by the insulating extension.

17. The method of claim 16, wherein forming the at least one opening extending through the stacked structure comprises forming the at least one opening extending through the stacked structure using a hard mask defining at least one opening size, the at least one opening size being smaller than the horizontal outer diameter of at least one of the grooves formed by recessing the sacrificial structure into the lower portion of the stacked structure.

18. The method of any one of claims 16 and 17, wherein forming the at least one opening extending through the stacked structure and forming the liner within the portion of the at least one opening comprises: At least one partial opening is formed extending through the upper portion of the stacked structure, the upper portion being above the lower portion; The material on which the lining is formed is formed on the surface exposed within the at least one partial opening; as well as Etching through the base of the material of the liner and through the layer of the lower portion to form at least one opening extending through the stacked structure and the liner within the portion of the at least one opening.

19. The method according to any one of claims 16 and 17, wherein forming the at least one opening extending through the stacked structure precedes forming the liner within the portion of the at least one opening.

20. The method of any one of claims 16 and 17, wherein forming the lining within the portion of the at least one opening comprises forming a non-sacrificial oxide material.

21. The method of any one of claims 16 and 17, wherein forming the liner within the portion of the at least one opening comprises forming a sacrificial polycrystalline silicon material.

22. The method of any one of claims 16 and 17, wherein recessing the sacrificial structure to form a groove along the at least one opening comprises recessing the insulating structure of the sacrificial structure relative to the lower portion of the stacked structure.

23. An electronic system comprising: Input device; Output device; A processor device operatively coupled to the input device and the output device; as well as A memory device operatively coupled to the processor device and comprising at least one microelectronic device structure, the at least one microelectronic device structure including contacts extending through a stacked structure of vertically alternating insulating and conductive structures arranged in layers, the conductive structures comprising: In the lower portion of the stacked structure, at least one lower conductive structure portion is located between adjacent pairs of contacts; as well as In another portion of the stacked structure above the lower portion, at least one upper conductive structure portion between the adjacent pair of contacts, The at least one lower conductive structure portion has a width narrower than the at least one upper conductive structure portion.

24. The electronic system according to claim 23, wherein, The at least one microelectronic device structure further includes an insulating material between the contact and the layers of the stacked structure, the insulating material including an insulating extension adjacent to the substrate of the contact, the insulating extension being perpendicularly alternated with the ends of the insulating structure in the lower layer portion of the stacked structure.

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