Thin film transistor array substrate and display device

Abstract

Embodiments of the present disclosure relate to thin film transistor array substrates and display devices in which a semiconductor layer has a heterogeneous conductive structure including heterogeneous conductive portions having different electrical conductivities, and a gate insulator layer is not etched enough to expose the semiconductor layer between the source electrode portion and the gate electrode portion and between the drain electrode portion and the gate electrode portion, so that the possibility of damage to the semiconductor layer can be eliminated or minimized.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0076064, filed on June 22, 2020, which is incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0003] This disclosure relates to thin-film transistor array substrates and display devices. Background Technology

[0004] Transistors are widely used as switching or driving devices in the field of electronic devices. In particular, because thin-film transistors can be fabricated on glass or plastic substrates, they can be widely used as switching elements in display devices such as liquid crystal displays or organic light-emitting displays.

[0005] Thin-film transistors can be classified based on the material constituting the active layer into amorphous silicon thin-film transistors that use amorphous silicon as the active layer, polycrystalline silicon thin-film transistors that use polycrystalline silicon as the active layer, and oxide semiconductor thin-film transistors that use oxide semiconductors as the active layer.

[0006] Because amorphous silicon can be deposited to form an active layer in a short time, amorphous silicon thin-film transistors (a-Si TFTs) have the advantages of short manufacturing time and low production cost. On the other hand, amorphous silicon thin-film transistors have the disadvantage of relatively low current driving capability due to low mobility, and are limited to organic light-emitting display devices due to threshold voltage variations.

[0007] Polycrystalline silicon thin-film transistors (poly-Si TFTs) are fabricated by crystallizing amorphous silicon after deposition. The fabrication process for polycrystalline silicon TFTs requires a crystallization process for the amorphous silicon, thus increasing the number of processes and manufacturing costs. Furthermore, because the crystallization process is performed at high process temperatures, polycrystalline silicon TFTs are difficult to apply to large-area devices. In addition, due to the polycrystalline nature, it is difficult to ensure the uniformity of polycrystalline silicon TFTs.

[0008] Because oxides, which form the active layer, can be formed at relatively low temperatures, and oxides possess high mobility and large resistance variations dependent on oxygen content, oxide semiconductor thin-film transistors (TFTs) have the advantage of readily achieving the desired physical characteristics. Furthermore, due to the properties of oxides, oxide semiconductors are transparent, making them advantageous for realizing transparent displays. However, to apply an oxide semiconductor layer to a thin-film transistor, a separate conductivity process is required to form the connection between the source and drain electrodes.

[0009] Meanwhile, during the formation of thin-film transistors, a gate insulating layer is formed on the semiconductor layer and then etched for various reasons. In this case, there is a risk that the semiconductor layer may be lost, damaged, or cut off during the etching process of the gate insulating layer. Summary of the Invention

[0010] Embodiments of this disclosure can provide a thin-film transistor array substrate and a display device including thin-film transistors, the thin-film transistors having a structure that can eliminate or minimize the possibility of damage to the semiconductor layer.

[0011] Embodiments of this disclosure may provide a thin-film transistor array substrate and a display device, wherein the thin-film transistor has a structure that simultaneously provides excellent electrical characteristics (e.g., current characteristics, mobility, etc.) while eliminating or minimizing the possibility of damage to the semiconductor layer.

[0012] Embodiments of this disclosure may provide a thin-film transistor array substrate and a display device including thin-film transistors having a structure capable of preventing the formation of parasitic capacitances.

[0013] Embodiments of this disclosure may provide thin-film transistor array substrates and display devices having a structure capable of forming capacitors with a thin thickness.

[0014] Embodiments of this disclosure may provide a thin-film transistor array substrate, comprising: a semiconductor layer including a channel portion, a first conductive portion located on one side of the channel portion, and a second conductive portion located on the other side of the channel portion, the first conductive portion including a first main conductive portion and a first sub-conductive portion, and the second conductive portion including a second main conductive portion and a second sub-conductive portion; a gate insulating layer disposed on the semiconductor layer and having a first contact hole exposing a portion of the first main conductive portion and a second contact hole exposing a portion of the second main conductive portion; a main source electrode disposed on the gate insulating layer and electrically connected to the first main conductive portion through the first contact hole; a main drain electrode disposed on the gate insulating layer and electrically connected to the second main conductive portion through the second contact hole; a main gate electrode disposed on the gate insulating layer and overlapping the channel portion; and a functional insulating layer disposed on the main source electrode, the main gate electrode, and the main drain electrode.

[0015] In a thin-film transistor array substrate according to an embodiment of the present disclosure, a first sub-conductive portion may be located between a first main conductive portion and a channel portion, the first sub-conductive portion may not overlap with the main source electrode and the main gate electrode, and the first sub-conductive portion may have a conductivity different from that of the first main conductive portion.

[0016] In a thin-film transistor array substrate according to an embodiment of the present disclosure, a second sub-conductive portion may be located between a second main conductive portion and a channel portion, the second sub-conductive portion may not overlap with the main drain electrode and the main gate electrode, and the second sub-conductive portion may have a conductivity different from that of the second main conductive portion.

[0017] In a thin-film transistor array substrate according to an embodiment of the present disclosure, a first sub-conductive portion and a functional insulating layer may be separated by a gate insulating layer, and a second sub-conductive portion and a functional insulating layer may be separated by a gate insulating layer.

[0018] In the thin-film transistor array substrate according to embodiments of the present disclosure, among the first main conductive portion, the first sub-conductive portion, and the channel portion, the first main conductive portion may have the highest conductivity, and the channel portion may have the lowest conductivity. Furthermore, among the second main conductive portion, the second sub-conductive portion, and the channel portion, the second main conductive portion may have the highest conductivity, and the channel portion may have the lowest conductivity.

[0019] In the thin-film transistor array substrate according to embodiments of the present disclosure, the vertical separation distance between the first sub-conductive portion and the functional insulating layer may be less than or equal to the vertical separation distance between the first main conductive portion and the functional insulating layer. The vertical separation distance between the second sub-conductive portion and the functional insulating layer may be less than or equal to the vertical separation distance between the second main conductive portion and the functional insulating layer.

[0020] In a thin-film transistor array substrate according to an embodiment of the present disclosure, the main gate electrode and the main source electrode may be spaced apart by a first horizontal separation distance, such that a first upper surface of the gate insulator layer is exposed between the main gate electrode and the main source electrode. The main gate electrode and the main drain electrode may be spaced apart by a second horizontal separation distance, such that a second upper surface of the gate insulator layer is exposed between the main gate electrode and the main drain electrode. The first horizontal separation distance may correspond to the length of a first sub-conductive portion, and the second horizontal separation distance may correspond to the length of a second sub-conductive portion.

[0021] In a thin-film transistor array substrate according to an embodiment of the present disclosure, a functional insulating layer may be in contact with a first upper surface of a gate insulating layer and may be in contact with a second upper surface of a gate insulating layer.

[0022] In the thin-film transistor array substrate according to embodiments of the present disclosure, the functional insulating layer may be a hydrogen supply layer containing hydrogen, and may diffuse hydrogen into the first sub-conductive portion and the second sub-conductive portion. The hydrogen concentration of the functional insulating layer may be higher than the hydrogen concentration of the first sub-conductive portion and the second sub-conductive portion.

[0023] In the thin-film transistor array substrate according to embodiments of the present disclosure, the functional insulating layer may include at least one of silicon nitride (SiNx), silicon oxynitride (SiON), or silicon oxide (SiOx).

[0024] In a thin-film transistor array substrate according to an embodiment of the present disclosure, a hydrogen diffusion barrier layer may be disposed between a functional insulating layer and a channel portion. The hydrogen diffusion barrier layer may block the diffusion of hydrogen from the functional insulating layer to the channel portion, and the hydrogen diffusion barrier layer may include a main gate electrode.

[0025] The thin-film transistor array substrate according to embodiments of the present disclosure may further include: a first auxiliary source electrode, disposed between the gate insulating layer and the main source electrode, electrically contacting the main source electrode and electrically contacting the first main conductive portion through a first contact hole; a first auxiliary drain electrode, disposed between the gate insulating layer and the main drain electrode, electrically contacting the main drain electrode and electrically contacting the second main conductive portion through a second contact hole; and an auxiliary gate electrode, disposed between the gate insulating layer and the main gate electrode, electrically contacting the main gate electrode and overlapping the channel portion.

[0026] In a thin-film transistor array substrate according to an embodiment of the present disclosure, the main source electrode can be electrically connected to a first main conductive portion via a first auxiliary source electrode, and the main drain electrode can be electrically connected to a second main conductive portion via a first auxiliary drain electrode.

[0027] In the thin-film transistor array substrate according to embodiments of the present disclosure, the first auxiliary source electrode and the first auxiliary drain electrode may comprise the same material as the auxiliary gate electrode and may be located on the same layer. The main source electrode and the main drain electrode may comprise the same material as the main gate electrode and may be located on the same layer.

[0028] The thin-film transistor array substrate according to embodiments of the present disclosure may further include: a second auxiliary source electrode, the second auxiliary source electrode being configured to contact the upper surface of the first main conductive portion and electrically connecting the first auxiliary source electrode and the first main conductive portion; and a second auxiliary drain electrode, the second auxiliary drain electrode being configured to contact the upper surface of the second main conductive portion and electrically connecting the first auxiliary drain electrode and the second main conductive portion.

[0029] In a thin-film transistor array substrate according to an embodiment of the present disclosure, the second auxiliary source electrode may not overlap with the auxiliary gate electrode and the first sub-conductive portion, and the second auxiliary drain electrode may not overlap with the auxiliary gate electrode and the second sub-conductive portion.

[0030] Embodiments of this disclosure may provide a display device including a thin-film transistor array substrate on which a plurality of thin-film transistors are disposed.

[0031] In a display device according to an embodiment of the present disclosure, at least one of a plurality of thin-film transistors includes: a semiconductor layer including a channel portion, a first conductive portion located on one side of the channel portion, and a second conductive portion located on the other side of the channel portion, the first conductive portion including a first main conductive portion and a first sub-conductive portion, and the second conductive portion including a second main conductive portion and a second sub-conductive portion; a gate insulating layer disposed on the semiconductor layer and having a first contact hole exposing a portion of the first main conductive portion and a second contact hole exposing a portion of the second main conductive portion; a main source electrode disposed on the gate insulating layer and electrically connected to the first main conductive portion through the first contact hole; a main drain electrode disposed on the gate insulating layer and electrically connected to the second main conductive portion through the second contact hole; a main gate electrode disposed on the gate insulating layer and overlapping the channel portion; and a functional insulating layer disposed on the main source electrode, the main gate electrode, and the main drain electrode.

[0032] In a display device according to an embodiment of the present disclosure, a first sub-conductive portion may be located between a first main conductive portion and a channel portion, the first sub-conductive portion may not overlap with the main source electrode and the main gate electrode, and the first sub-conductive portion may have a conductivity different from that of the first main conductive portion.

[0033] In a display device according to an embodiment of the present disclosure, the second sub-conductive portion may be located between the second main conductive portion and the channel portion, the second sub-conductive portion may not overlap with the main drain electrode and the main gate electrode, and the second sub-conductive portion may have a conductivity different from that of the second main conductive portion.

[0034] In a display device according to an embodiment of the present disclosure, a first sub-conductive portion and a functional insulating layer may be separated by a gate insulating layer, and a second sub-conductive portion and a functional insulating layer may be separated by a gate insulating layer.

[0035] According to embodiments of the present disclosure, a thin-film transistor array substrate and a display device can be provided, wherein the thin-film transistor has a structure that can eliminate or minimize the possibility of damage to the semiconductor layer.

[0036] According to embodiments of the present disclosure, a thin-film transistor array substrate and a display device can be provided, wherein the thin-film transistor has a structure that simultaneously provides excellent electrical characteristics (e.g., current characteristics, mobility, etc.) while eliminating or minimizing the possibility of damage to the semiconductor layer.

[0037] According to embodiments of the present disclosure, a thin-film transistor array substrate and a display device including thin-film transistors can be provided. The thin-film transistors have the following structure: by providing a second auxiliary source electrode and a second auxiliary drain electrode in contact with a first main conductive portion and a second main conductive portion, the formation of parasitic capacitance can be prevented.

[0038] According to embodiments of this disclosure, by having a structure capable of forming capacitors with thin thickness, thin-film transistor array substrates and display devices that can increase aperture ratio can be provided. Attached Figure Description

[0039] Figure 1 This is a cross-sectional view showing the structure of a thin-film transistor formed on a thin-film transistor array substrate according to an embodiment of the present disclosure.

[0040] Figure 2 This is a cross-sectional view used to illustrate the structural features of a thin-film transistor formed on a thin-film transistor array substrate according to an embodiment of the present disclosure.

[0041] Figure 3 This is a cross-sectional view showing another structure of a thin-film transistor formed on a thin-film transistor array substrate according to an embodiment of the present disclosure.

[0042] Figures 4 to 6 This is a cross-sectional view showing an example of the location of the functional insulating layer in a thin-film transistor array substrate according to an embodiment of the present disclosure.

[0043] Figure 7 This is a cross-sectional view showing thin-film transistors and pixel electrodes formed on a thin-film transistor array substrate according to an embodiment of the present disclosure.

[0044] Figure 8 This is a cross-sectional view showing the partial conductivity of the functional insulating layer of a thin-film transistor array substrate to the semiconductor layer according to an embodiment of the present disclosure.

[0045] Figure 9 This is a diagram illustrating the surface contact structure between the first auxiliary source electrode and the first main conductive portion, and the surface contact structure between the first auxiliary drain electrode and the second main conductive portion, in a thin-film transistor formed on a thin-film transistor array substrate according to an embodiment of the present disclosure.

[0046] Figure 10This is a cross-sectional view showing a thin-film transistor and a light-shielding layer formed on a thin-film transistor array substrate according to an embodiment of the present disclosure.

[0047] Figure 11 This is a cross-sectional view showing the structure of a capacitor formed on a thin-film transistor array substrate according to an embodiment of the present disclosure.

[0048] Figure 12 This is a cross-sectional view showing another structure of a thin-film transistor formed on a thin-film transistor array substrate according to an embodiment of the present disclosure.

[0049] Figure 13 This is a graph showing the drain current in a thin-film transistor on a thin-film transistor array substrate according to an embodiment of the present disclosure, for each hydrogen doping length of the first and second subconducting portions, as a function of carrier concentration.

[0050] Figure 14 It is a graph showing the drain current as a function of the gate voltage of a thin-film transistor formed on a thin-film transistor array substrate according to an embodiment of the present disclosure.

[0051] Figure 15 It is used to explain in Figure 12 A cross-sectional view of the overlap length between the second auxiliary source electrode and the auxiliary gate electrode, and the overlap length between the second auxiliary drain electrode and the auxiliary gate electrode, in a thin-film transistor formed on a thin-film transistor array substrate according to an embodiment of the present disclosure.

[0052] Figure 16 It is shown in Figure 12 The graph shows the drain current of a thin-film transistor formed on a thin-film transistor array substrate according to an embodiment of the present disclosure, with respect to the overlap length for each carrier concentration.

[0053] Figure 17 It is shown that, according to Figure 12 The graph shows the drain current variation of the gate voltage of a thin-film transistor formed on a thin-film transistor array substrate according to an embodiment of the present disclosure.

[0054] Figure 18 It is a graph showing the mobility of a thin-film transistor formed on a thin-film transistor array substrate according to an embodiment of the present disclosure as a function of carrier concentration.

[0055] Figure 19 This is a diagram illustrating a display device according to an embodiment of the present disclosure. Detailed Implementation

[0056] In the following description of examples or embodiments of the invention, reference will be made to the accompanying drawings, in which specific examples or embodiments that may be implemented are illustrated by means of illustration, and wherein the same reference numerals may be used to denote the same or similar parts, even if they are shown in different drawings. Furthermore, in the following description of examples or embodiments of the invention, detailed descriptions of well-known functions and parts incorporated herein may be omitted where such descriptions may obscure the subject matter of some embodiments of the invention. Terms such as “comprising,” “having,” “including,” “constituting,” “forming,” and “forming” as used herein are generally intended to allow for the addition of additional parts, unless these terms are used in conjunction with the term “only.” As used herein, the singular forms are intended to include the plural forms unless the context clearly indicates otherwise.

[0057] In this document, terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used to describe elements of the invention. Each of these terms is not intended to define the nature, order, sequence, or number of elements, but is only used to distinguish the corresponding element from other elements.

[0058] When referring to the first element and the second element as "connected or coupled," "in contact or overlapping," etc., it should be interpreted as meaning that not only can the first element be "directly connected or coupled" or "directly in contact or overlapping" with the second element, but a third element can also be "inserted" between the first and second elements, or the first and second elements can be "connected or coupled," "in contact or overlapping," etc., with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or coupled," "in contact or overlapping," etc., with each other.

[0059] When time-related terms (such as “after,” “following,” “next,” “before,” etc.) are used to describe the process or operation of an element or configuration, or the flow or step in an operation, processing, or manufacturing method, the above terms may be used to describe discontinuous or non-sequential processes or operations unless used with the terms “directly” or “immediately.”

[0060] Furthermore, when referring to any size, relative size, etc., it should be assumed that the numerical values ​​or corresponding information (e.g., levels, ranges, etc.) of a component or feature include tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is provided. Additionally, the term "may" fully encompasses all the meanings of the term "can."

[0061] In the following, a thin-film transistor array substrate 100 and a display device including the thin-film transistor array substrate 100 according to an exemplary embodiment will be described in detail with reference to the accompanying drawings.

[0062] Figure 1 This is a cross-sectional view showing the structure of a thin-film transistor formed on a thin-film transistor TFT array substrate 100 according to an embodiment of the present disclosure.

[0063] Reference Figure 1 According to embodiments of the present disclosure, the thin-film transistor (TFT) array substrate 100 may include a semiconductor layer 120, a gate insulating layer 130, a main source electrode 141, a main drain electrode 142, a main gate electrode 143, a functional insulating layer 150, etc.

[0064] Reference Figure 1 The semiconductor layer 120 can be disposed on the substrate 110. The substrate 110 can be a glass substrate or a plastic substrate. The substrate 110 can be a flexible substrate, a bendable substrate, or a stretchable substrate.

[0065] Reference Figure 1 The semiconductor layer 120 may include a channel portion 123, a first conductive portion 121 located on one side of the channel portion 123, and a second conductive portion 122 located on the other side of the channel portion 123. For example, the semiconductor layer 120 may be an oxide semiconductor layer, and in some cases, it may be a polycrystalline silicon semiconductor layer or an amorphous silicon semiconductor layer.

[0066] Reference Figure 1 The first conductive portion 121 may include a first main conductive portion 121M and a first sub-conductive portion 121A. The second conductive portion 122 may include a second main conductive portion 122M and a second sub-conductive portion 122A.

[0067] The first main conductive portion 121M and the second main conductive portion 122M are connection portions electrically connected to the main source electrode 141 and the main drain electrode 142, respectively. The first sub-conductive portion 121A and the second sub-conductive portion 122A are not connected to the main source electrode 141 and the main drain electrode 142, but have different electrical characteristics from the channel portion 123, and have similar conductive characteristics to the first main conductive portion 121M and the second main conductive portion 122M.

[0068] Reference Figure 1 A gate insulating layer 130 may be disposed on the semiconductor layer 120. The gate insulating layer 130 may have a first contact hole CNT1 that exposes a portion of the first main conductive portion 121M and a second contact hole CNT2 that exposes a portion of the second main conductive portion 122M.

[0069] Reference Figure 1The main source electrode 141, the main drain electrode 142, and the main gate electrode 143 can be located on the gate insulating layer 130. For example, the main source electrode 141, the main drain electrode 142, and the main gate electrode 143 can be located on the same layer and can be made of the same material.

[0070] Reference Figure 1 The main source electrode 141 can be electrically connected to the first main conductive portion 121M through the first contact hole CNT1. The main drain electrode 142 can be electrically connected to the second main conductive portion 122M through the second contact hole CNT2. The main gate electrode 143 can overlap with the channel portion 123.

[0071] Reference Figure 1 The functional insulating layer 150 can be disposed on the main source electrode 141, the main gate electrode 143 and the main drain electrode 142.

[0072] For example, refer to Figure 1 The functional insulating layer 150 can be configured to cover the main source electrode 141, the main gate electrode 143, and the main drain electrode 142. That is, the functional insulating layer 150 can be located on the upper and side surfaces of each of the main source electrode 141, the main gate electrode 143, and the main drain electrode 142, and can also be located on a portion of the gate insulating layer 130.

[0073] Reference Figure 1 The first sub-conductive portion 121A can be located along the horizontal plane between the first main conductive portion 121M and the channel portion 123. The second sub-conductive portion 122A can be located along the horizontal plane between the second main conductive portion 122M and the channel portion 123.

[0074] Reference Figure 1 The first sub-conductive portion 121A may not overlap with the main source electrode 141 and the main gate electrode 143. Therefore, there is no metal material layer between the first sub-conductive portion 121A of the semiconductor layer 120 and the functional insulating layer 150. Thus, as will be described later, the first sub-conductive portion 121A of the semiconductor layer 120 can receive hydrogen from the functional insulating layer 150 and can be made conductive by the supplied hydrogen.

[0075] Reference Figure 1 The second sub-conductive portion 122A may not overlap with the main source electrode 141 and the main drain electrode 142. Therefore, there is no metal material layer between the second sub-conductive portion 122A of the semiconductor layer 120 and the functional insulating layer 150. Thus, as will be described later, the second sub-conductive portion 122A of the semiconductor layer 120 can receive hydrogen from the functional insulating layer 150 and can be conductive by the supplied hydrogen.

[0076] Reference Figure 1The first sub-conductive portion 121A and the functional insulating layer 150 can be spaced apart by the gate insulating layer 130. The second sub-conductive portion 122A and the functional insulating layer 150 can be spaced apart by the gate insulating layer 130. That is, in the thin-film transistor array substrate 100 according to the embodiments of the present disclosure, each thin-film transistor TFT can have the following structure (hereinafter also referred to as a gate insulating layer etch-free structure): the gate insulating layer 130 is not etched between the source contact region and the channel region and between the drain contact region and the channel region.

[0077] Therefore, the loss of the semiconductor layer 120 of the thin-film transistor TFT can be prevented or at least reduced, and damage to the source contact portion between the main source electrode 141 and the first main conductive portion 121M and the drain contact portion between the main drain electrode 142 and the second main conductive portion 122M in the thin-film transistor TFT can be prevented.

[0078] Reference Figure 1 The first sub-conductive portion 121A may have a conductivity different from that of the first main conductive portion 121M. Therefore, based on the difference in conductivity between the first main conductive portion 121M and the first sub-conductive portion 121A, the first main conductive portion 121M and the first sub-conductive portion 121A can be distinguished from each other in the first conductive portion 121.

[0079] Reference Figure 1 The second sub-conductive portion 122A may have a conductivity different from that of the second main conductive portion 122M. Therefore, based on the difference in conductivity between the second main conductive portion 122M and the second sub-conductive portion 122A, the second main conductive portion 122M and the second sub-conductive portion 122A can be distinguished from each other in the second conductive portion 122.

[0080] Among the first main conductive portion 121M, the first sub-conductive portion 121A, and the channel portion 123, the first main conductive portion 121M can have the largest conductivity, and the channel portion 123 can have the smallest conductivity.

[0081] Among the second main conductive portion 122M, the second sub-conductive portion 122A, and the channel portion 123, the conductivity of the second main conductive portion 122M can be the largest, and the conductivity of the channel portion 123 can be the smallest.

[0082] Figure 2 This is a cross-sectional view used to illustrate the structural features of a thin-film transistor TFT formed on a thin-film transistor array substrate 100 according to an embodiment of the present disclosure.

[0083] Reference Figure 2In the region outside the first contact hole CNT1, the vertical separation distance H1a between the first sub-conductive portion 121A and the functional insulating layer 150 can be less than or equal to the vertical separation distance H1m between the first main conductive portion 121M and the functional insulating layer 150. That is, the maximum vertical separation distance H1a between the first sub-conductive portion 121A and the functional insulating layer 150 can be less than or equal to the maximum vertical separation distance H1m between the first main conductive portion 121M and the functional insulating layer 150.

[0084] For example, when the functional insulating layer 150, described later, is disposed below the passivation layer 400, the vertical separation distance H1a between the first sub-conductive portion 121A and the functional insulating layer 150 in the area outside the first contact hole CNT1 can be smaller than the vertical separation distance H1m between the first main conductive portion 121M and the functional insulating layer 150.

[0085] For example, when the functional insulating layer 150, which will be described later, is disposed on the passivation layer 400, the vertical separation distance H1a between the first sub-conductive portion 121A and the functional insulating layer 150 in the region outside the first contact hole CNT1 can correspond to the vertical separation distance H1m between the first main conductive portion 121M and the functional insulating layer 150.

[0086] In the region outside the second contact hole CNT2, the vertical separation distance H2a between the second sub-conductive portion 122A and the functional insulating layer 150 can be less than or equal to the vertical separation distance H2m between the second main conductive portion 122M and the functional insulating layer 150. That is, the maximum vertical separation distance H2a between the second sub-conductive portion 122A and the functional insulating layer 150 can be less than or equal to the maximum vertical separation distance H2m between the second main conductive portion 122M and the functional insulating layer 150.

[0087] For example, when the functional insulating layer 150, which will be described later, is disposed below the passivation layer 400, the vertical separation distance H2a between the second sub-conductive portion 122A and the functional insulating layer 150 in the region other than the second contact hole CNT2 can be less than the vertical separation distance H2m between the second main conductive portion 122M and the functional insulating layer 150.

[0088] For example, when the functional insulating layer 150, which will be described later, is disposed on the passivation layer 400, the vertical separation distance H2a between the second sub-conductive portion 122A and the functional insulating layer 150 in the region outside the second contact hole CNT2 can correspond to the vertical separation distance H2m between the second main conductive portion 122M and the functional insulating layer 150.

[0089] Reference Figure 2The main gate electrode 143 and the main source electrode 141 can be spaced apart by a first horizontal separation distance D1 to expose the first upper surface 210 of the gate insulator layer 130 between the main gate electrode 143 and the main source electrode 141.

[0090] The main gate electrode 143 and the main drain electrode 142 may be spaced apart by a second horizontal separation distance D2 to expose the second upper surface 220 of the gate insulator layer 130 between the main gate electrode 143 and the main drain electrode 142.

[0091] Reference Figure 2 The first horizontal separation distance D1 can correspond to the length L1a of the first sub-conductive portion 121A, and the second horizontal separation distance D2 can correspond to the length L2a of the second sub-conductive portion 122A.

[0092] Reference Figure 2 The functional insulating layer 150 can contact the first upper surface 210 of the gate insulating layer 130 and can contact the second upper surface 220 of the gate insulating layer 130.

[0093] Reference Figure 2 Since the first sub-conductive portion 121A and the second sub-conductive portion 122A are formed in the semiconductor layer 120, the length of the channel portion 123 of the semiconductor layer 120 can be shortened. Therefore, a short channel for the thin-film transistor TFT can be easily realized. Consequently, the mobility of the thin-film transistor TFT can be improved.

[0094] Figure 3 This is a cross-sectional view showing another structure of a thin-film transistor TFT formed on a thin-film transistor array substrate 100 according to an embodiment of the present disclosure.

[0095] Reference Figure 3 The thin-film transistor TFT formed on the thin-film transistor array substrate 100 according to the embodiments of the present disclosure may further include a first auxiliary source electrode 310, a first auxiliary drain electrode 320 and an auxiliary gate electrode 330.

[0096] The first auxiliary source electrode 310 is disposed between the gate insulating layer 130 and the main source electrode 141, and can make electrical contact with the main source electrode 141. It can also make electrical contact with the first main conductive portion 121M through the first contact hole CNT1.

[0097] Therefore, the main source electrode 141 can be electrically connected to the first main conductive portion 121M through the first auxiliary source electrode 310.

[0098] The first auxiliary drain electrode 320 is disposed between the gate insulating layer 130 and the main drain electrode 142, and can make electrical contact with the main drain electrode 142. It can also make electrical contact with the second main conductive portion 122M through the second contact hole CNT2.

[0099] Therefore, the main drain electrode 141 can be electrically connected to the second main conductive portion 122M through the first auxiliary drain electrode 320.

[0100] The auxiliary gate electrode 330 can be disposed between the gate insulating layer 130 and the main gate electrode 143, and can be in electrical contact with the main gate electrode 143.

[0101] The auxiliary gate electrode 330 may overlap with the channel portion 123.

[0102] Reference Figure 3 The first auxiliary source electrode 310 and the first auxiliary drain electrode 320 may include the same material as the auxiliary gate electrode 330 and may be located on the same layer. For example, the first auxiliary source electrode 310, the first auxiliary drain electrode 320 and the auxiliary gate electrode 330 may include an alloy material such as molybdenum-titanium (MoTi), and in some cases, may include a single metal material such as copper (Cu), aluminum (Al), molybdenum (Mo) or titanium (Ti).

[0103] The main source electrode 141 and the main drain electrode 142 may be made of the same material as the main gate electrode 143 and may be located on the same layer. For example, the main source electrode 141, the main drain electrode 142 and the main gate electrode 143 may be made of a single metal material such as copper (Cu), aluminum (Al), molybdenum (Mo) or titanium (Ti), and in some cases, may be made of an alloy material such as molybdenum-titanium (MoTi).

[0104] Reference Figure 3 Since the first sub-conductive portion 121A and the second sub-conductive portion 122A are formed in the semiconductor layer 120, the length of the channel portion 123 of the semiconductor layer 120 can be shortened. Therefore, a short channel for the thin-film transistor TFT can be easily realized. Consequently, the mobility of the thin-film transistor TFT can be improved.

[0105] Figures 4 to 6 This is a cross-sectional view showing an example of the location of the functional insulating layer 150 in a thin-film transistor array substrate 100 according to an embodiment of the present disclosure.

[0106] Reference Figures 4 to 6 The thin-film transistor array substrate 100 according to embodiments of the present disclosure may further include a passivation layer 400 for protecting or electrically stabilizing thin-film transistor TFTs. The passivation layer 400 may be disposed on the thin-film transistor TFTs. The passivation layer 400 is also referred to as a protective layer.

[0107] Reference Figure 4 The functional insulating layer 150 can be disposed below the passivation layer 400. In this case, due to the electrodes formed on the gate insulating layer 130, the functional insulating layer 150 can be formed at an irregular height.

[0108] Here, the electrodes formed on the gate insulating layer 130 may include a main source electrode 141, a first auxiliary source electrode 310, a main gate electrode 143, an auxiliary gate electrode 330, a main drain electrode 142, and a first auxiliary drain electrode 320.

[0109] Reference Figure 5 The functional insulating layer 150 can be disposed on the passivation layer 400. The upper surface of the passivation layer 400 can be flat, or its height can remain relatively constant. Therefore, the functional insulating layer 150 can be formed on the passivation layer 400 in a flat state, or it can be formed without significant changes in height.

[0110] Reference Figure 6 The passivation layer 400 may include multiple sub-passivation layers 610 and 620. The functional insulating layer 150 may be located between the multiple sub-passivation layers 610 and 620.

[0111] As described above, the functional insulating layer 150 can be based on the location of the passivation layer 400, such as... Figure 4 As shown, it is located below the passivation layer 400, or it can be as follows: Figure 5 As shown, it is positioned above the passivation layer 400, or it can be as follows: Figure 6 As shown, it is located between multiple passivation layers 400 (610, 620).

[0112] However, as will be described later, when considering the hydrogen supply function of the functional insulating layer 150 and the hydrogen conductivity of the first sub-conductive portion 121A and the second sub-conductive portion 122A, compared with Figure 5 and Figure 6 Compared to the situation, such as Figure 4 The case where the functional insulating layer 150 is located below the passivation layer 400 may be more advantageous because the vertical distance between the functional insulating layer 150 and the semiconductor layer 120 is less than [the distance between them]. Figure 5 and Figure 6 The distance in the implementation method. Therefore, in Figure 4 In the example, the conductivity of the first sub-conductive portion 121A and the second sub-conductive portion 122A is improved by the hydrogen supplied from the functional insulating layer 150.

[0113] Figure 7 This is a cross-sectional view showing a thin-film transistor TFT and a pixel electrode 700 formed on a thin-film transistor array substrate 100 according to an embodiment of the present disclosure.

[0114] Reference Figure 7 In the thin-film transistor array substrate 100 according to the embodiments of the present disclosure, the main source electrode 141, the main gate electrode 143, the main drain electrode 142 and the semiconductor layer 120 can constitute a thin-film transistor TFT.

[0115] Reference Figure 7 The thin-film transistor array substrate 100 according to embodiments of the present disclosure may further include a pixel electrode 700 electrically connected to the main source electrode 141 or the main drain electrode 142 of the thin-film transistor TFT.

[0116] Reference Figure 7 The passivation layer 400 can be disposed on the main source electrode 141, the main gate electrode 143 and the main drain electrode 142, and can have a third contact hole CNT3 to expose a portion of the main source electrode 141 or the main drain electrode 142.

[0117] Reference Figure 7 The pixel electrode 700 can be located on the passivation layer 400 and can be electrically contacted with the exposed main source electrode 141 or main drain electrode 142 through the third contact hole CNT3.

[0118] exist Figure 7 In the example, pixel electrode 700 is connected to main source electrode 141.

[0119] Reference Figure 7 The thin-film transistor (TFT) connected to the pixel electrode 700 via the main source electrode 141 or the main drain electrode 142 may be a driving transistor included in each sub-pixel.

[0120] For example, a thin-film transistor (TFT) can be a driving transistor for driving organic light-emitting diodes in each sub-pixel of an organic light-emitting diode (OLED) display device. Alternatively, a thin-film transistor (TFT) can be a driving transistor connected to a pixel electrode in each sub-pixel of a liquid crystal display (LCD).

[0121] Figure 8 This is a cross-sectional view showing that the functional insulating layer 150 of the thin-film transistor array substrate 100, according to an embodiment of the present disclosure, is partially conductive to the semiconductor layer 120.

[0122] Reference Figure 8 According to embodiments of the present disclosure, the functional insulating layer 150 of the thin-film transistor array substrate 100 may be a hydrogen supply layer containing hydrogen (H).

[0123] The functional insulating layer 150 can be a hydrogen supply layer and can diffuse hydrogen (H) into the first sub-conductive portion 121A and the second sub-conductive portion 122A. Therefore, in the semiconductor layer 120, the first sub-conductive portion 121A and the second sub-conductive portion 122A can be formed as conductive regions.

[0124] Reference Figure 8 The first sub-conductive portion 121A and the second sub-conductive portion 122A can also be referred to as "hydrogen conductive portions". The first main conductive portion 121M and the second main conductive portion 122M can also be referred to as "dry etch conductive portions".

[0125] Reference Figure 8 The hydrogen concentration of the functional insulating layer 150 can be higher than the hydrogen concentration of the first sub-conductive portion 121A and the second sub-conductive portion 122A.

[0126] For example, the functional insulating layer 150 of the thin-film transistor array substrate 100 according to embodiments of the present disclosure may include one or more of silicon nitride (SiNx), silicon oxynitride (SiON), and silicon oxide (SiOx).

[0127] Reference Figure 8 By using the functional insulating layer 150 as a hydrogen supply layer, the resistance in the region of the semiconductor layer 120 other than the first main conductive portion 121M and the second main conductive portion 122M can be reduced, and the region with reduced resistance can be formed as the first sub-conductive portion 121A and the second sub-conductive portion 122A. Furthermore, the formation of the first sub-conductive portion 121A and the second sub-conductive portion 122A by the functional insulating layer 150 as a hydrogen supply layer allows for the following effect: self-alignment of the boundary between the first conductive portion 121, the channel portion 123, and the second conductive portion 122 in the semiconductor layer 120.

[0128] Reference Figure 8 The channel portion 123 of the thin-film transistor (TFT) is a region in the semiconductor layer 120 that should not be conductive. Therefore, it is necessary to prevent excessive diffusion of hydrogen (H) released from the functional insulating layer 150 into the channel portion 123. In other words, it is necessary to prevent the channel portion 123 from becoming conductive by the hydrogen (H) released from the functional insulating layer 150.

[0129] Therefore, the thin-film transistor array substrate 100 according to embodiments of the present disclosure may include a hydrogen diffusion barrier layer 800 between the functional insulating layer 150 and the channel portion 123.

[0130] Reference Figure 8The hydrogen diffusion barrier layer 800 can block the diffusion of hydrogen from the functional insulating layer 150 to the channel portion 123. The hydrogen diffusion barrier layer 800 may include a main gate electrode 143. The hydrogen diffusion barrier layer 800 may also include an auxiliary gate electrode 330.

[0131] Figure 9 This is a diagram showing the source and drain contacts in a thin-film transistor TFT formed on a thin-film transistor array substrate 100 according to an embodiment of the present disclosure.

[0132] Reference Figure 9 In the source contact of a thin-film transistor (TFT), the first auxiliary source electrode 310 and the first main conductive portion 121M can be in electrical contact with each other. In this case, the first auxiliary source electrode 310 can be in contact with the surface of the first main conductive portion 121M. That is, the lower surface of the first auxiliary source electrode 310 can contact the first main conductive portion 121M.

[0133] Reference Figure 9 In the drain contact of a thin-film transistor (TFT), the first auxiliary drain electrode 320 and the second main conductive portion 122M can be in electrical contact with each other. The first auxiliary drain electrode 320 can be in contact with the surface of the second main conductive portion 122M. That is, the lower surface of the first auxiliary drain electrode 320 can contact the second main conductive portion 122M.

[0134] Therefore, a stable electrical connection can be provided between the first auxiliary source electrode 310 and the first main conductive portion 121M, as well as between the first auxiliary drain electrode 320 and the second main conductive portion 122M. This improves the operational performance of the thin-film transistor (TFT).

[0135] The thin-film transistor array substrate 100 according to embodiments of the present disclosure can be deformable. For example, the thin-film transistor array substrate 100 according to embodiments of the present disclosure can be a flexible substrate, a bendable substrate, or a stretchable substrate.

[0136] In this case, despite the deformation of the thin-film transistor array substrate 100, the thin-film transistor TFT can perform stable operation due to the surface contact between the first auxiliary source electrode 310 and the first main conductive portion 121M and the surface contact between the first auxiliary drain electrode 320 and the second main conductive portion 122M.

[0137] Figure 10 This is a cross-sectional view showing a thin-film transistor TFT and a light-shielding layer 1010 formed on a thin-film transistor array substrate 100 according to an embodiment of the present disclosure.

[0138] Reference Figure 10The thin-film transistor array substrate 100 according to the embodiments of the present disclosure may further include a buffer layer 1020 disposed below the semiconductor layer 120 and a light-shielding layer 1010 disposed below the buffer layer 1020.

[0139] Reference Figure 10 The light-shielding layer 1010 can be configured to overlap with the channel portion 123 of the thin-film transistor TFT.

[0140] If the channel portion 123 of the semiconductor layer 120 is exposed to light, the channel characteristics of the semiconductor layer 120 may change, and the operating characteristics of the thin-film transistor (TFT) may also change.

[0141] Therefore, since the light-shielding layer 1010 is configured to overlap with the channel portion 123 of the thin-film transistor TFT, the exposure of the channel portion 123 to light can be prevented or at least reduced. Thus, stable operating characteristics of the thin-film transistor TFT can be provided.

[0142] Reference Figure 10 The first auxiliary source electrode 310 or the first auxiliary drain electrode 320 of the thin-film transistor TFT can make electrical contact with the light-shielding layer 1010 through the fourth contact hole CNT4 passing through the gate insulating layer 130 and the buffer layer 1020.

[0143] exist Figure 10 In the example, the first auxiliary drain electrode 320 is electrically contacted with the light-shielding layer 1010 through the fourth contact hole CNT4. This is merely for ease of description, and the first auxiliary source electrode 310 can also be electrically contacted with the light-shielding layer 1010 through the fourth contact hole CNT4.

[0144] As described above, since the first auxiliary source electrode 310 or the first auxiliary drain electrode 320 of the thin-film transistor TFT is in electrical contact with the light-shielding layer 1010, the electrical characteristics (e.g., threshold voltage characteristics) of the thin-film transistor TFT can be stabilized. For example, since the first auxiliary source electrode 310 or the first auxiliary drain electrode 320 of the thin-film transistor TFT is in electrical contact with the light-shielding layer 1010, abnormal shift of the threshold voltage corresponding to the intrinsic characteristic value of the thin-film transistor TFT can be prevented.

[0145] The light-shielding layer 1010 can be a single layer. Alternatively, such as... Figure 10 As shown, the light-shielding layer 1010 may include two layers 1011 and 1012. In some cases, the light-shielding layer 1010 may include three or more layers.

[0146] Reference Figure 10The light-shielding layer 1010 may include a main light-shielding layer 1012 and a sub-light-shielding layer 1011. For example, the main light-shielding layer 1012 may include a single metal material such as copper (Cu), aluminum (Al), molybdenum (Mo), or titanium (Ti), and the sub-light-shielding layer 1011 may include an alloy material such as molybdenum-titanium (MoTi).

[0147] The main light-shielding layer 1012 can be electrically connected to the first auxiliary source electrode 310 or the first auxiliary drain electrode 320. The sub-light-shielding layer 1011 can be disposed below the main light-shielding layer 1012 and can be electrically contacted by the main light-shielding layer 1012.

[0148] Figure 11 This is a cross-sectional view showing the structure of a capacitor CAP formed on a thin-film transistor array substrate 100 according to an embodiment of the present disclosure.

[0149] Reference Figure 11 The thin-film transistor array substrate 100 according to embodiments of the present disclosure may further include a plurality of sub-pixels, the sub-pixels including thin-film transistors (TFTs) and capacitors (CAPs).

[0150] As described above, a thin-film transistor (TFT) may include a semiconductor layer 120, a main source electrode 141, a main drain electrode 142, a main gate electrode 143, etc.

[0151] Reference Figure 11 The capacitor CAP may include a first plate 1110, a second plate 1120 on the first plate 1110, and a third plate 1130 on the second plate 1120.

[0152] Reference Figure 11 The first plate 1110 and the third plate 1130 of the capacitor CAP can be metal plates. Conversely, the second plate 1120 of the capacitor CAP can be another semiconductor layer located on the same layer as the semiconductor layer 120 of the thin-film transistor TFT and in a conductive state.

[0153] Reference Figure 11 The first plate 1110 of the capacitor CAP can be a light-shielding layer 1010. Alternatively, the first plate 1110 of the capacitor CAP can be disposed on the same layer as the light-shielding layer 1010, and can be made of the same metal as the light-shielding layer 1010.

[0154] like Figure 10 As shown, when the light-shielding layer 1010 includes multiple layers 1011 and 1012, the first plate 1110 of the capacitor CAP may also include multiple layers 1111 and 1112.

[0155] Reference Figure 11The multiple layers 1111 and 1112 included in the first plate 1110 can be formed of the same material as the multiple layers 1011 and 1012 included in the light-shielding layer 1010.

[0156] Reference Figure 11 The first plate 1111 in the first plate 1110 and the first plate 1112 can correspond to the position and material of the sub-shielding layer 1011 in the main shielding layer 1012 and the sub-shielding layer 1011 in the shielding layer 1010.

[0157] Reference Figure 11 The first plate 1112 in the first plate 1110 can correspond to the position and material of the main light-shielding layer 1012 in the main light-shielding layer 1012 and the sub-light-shielding layer 1011 in the light-shielding layer 1010.

[0158] Reference Figure 11 The third plate 1130 can be the main gate electrode 143 and the auxiliary gate electrode 330, or it can be a metal disposed on the same layer as the main gate electrode 143 and the auxiliary gate electrode 330.

[0159] Reference Figure 11 The third plate 1130 may include the third plate 1131 and the third plate 2 1132.

[0160] Reference Figure 11 The third plate 1131 of the third plate 1130 can be the auxiliary gate electrode 330. Alternatively, the third plate 1131 of the third plate 1130 can be disposed on the same layer as the auxiliary gate electrode 330, and can be a metal of the same material as the auxiliary gate electrode 330.

[0161] Reference Figure 11 The third plate 1132 of the third plate 1130 can be the main gate electrode 143. Alternatively, the third plate 1132 of the third plate 1130 can be located on the same layer as the main gate electrode 143 and can be made of the same metal as the main gate electrode 143.

[0162] Reference Figure 11 In the thin-film transistor array substrate 100 according to an embodiment of the present disclosure, the capacitor CAP may include a first capacitor Cb between the first plate 1110 and the second plate 1120 and a second capacitor Ca between the second plate 1120 and the third plate 1130.

[0163] Reference Figure 11In the thin-film transistor array substrate 100 according to an embodiment of the present disclosure, the capacitor CAP has the above-described structure, thereby reducing the thickness T. The structural reasons for reducing the thickness T of the capacitor CAP in the thin-film transistor array substrate 100 according to an embodiment of the present disclosure will be described below.

[0164] Since the thin-film transistor array substrate 100 according to the embodiments of the present disclosure has a gate insulator layer etch-free (GI etch-free) structure, the gate insulator layer 130 can be provided to simultaneously cover the second plate 1120 on the buffer layer 1020. Therefore, the second capacitor Ca can be formed in the structure where the gate insulator layer 130 is disposed between the second plate 1120 and the third plate 1130. If the thin-film transistor array substrate 100 according to the embodiments of the present disclosure does not have a gate insulator layer etch-free structure, a passivation layer 400 can be provided to simultaneously cover the second plate 1120 on the buffer layer 1020. In this case, the second capacitor Ca will inevitably be formed in the structure where the passivation layer 400 exists between the second plate 1120 and the third plate 1130. Typically, the gate insulator layer 130 can be formed to be much thinner than the passivation layer 400. Therefore, the thin-film transistor array substrate 100 according to the embodiments of this disclosure has an etch-free gate insulator layer structure, thereby allowing the second capacitor Ca to be thinly formed in a structure where the gate insulator layer 130 exists between the second plate 1120 and the third plate 1130. Thus, due to the etch-free gate insulator layer structure, the thickness T of the capacitor CAP can be reduced.

[0165] Furthermore, in the thin-film transistor array substrate 100 according to the embodiments of the present disclosure, the capacitance is increased by forming a capacitor CAP by overlapping three conductors 1110, 1120, and 1130. Therefore, it is not necessary to increase the area of ​​the capacitor CAP to increase the capacitance. That is, since the area of ​​the capacitor CAP can be designed to be smaller to obtain the same capacitance, the aperture ratio of the display panel can be increased.

[0166] Figure 12 This is a cross-sectional view showing another structure of a thin-film transistor TFT formed on a thin-film transistor array substrate 100 according to an embodiment of the present disclosure.

[0167] Reference Figure 12 The thin-film transistor TFT formed on the thin-film transistor array substrate 100 according to embodiments of the present disclosure may further include a second auxiliary source electrode 1210 and a second auxiliary drain electrode 1220. For example, the second auxiliary source electrode 1210 and the second auxiliary drain electrode 1220 may include an alloy material such as molybdenum-titanium (MoTi), or may include a single metal material such as copper (Cu), aluminum (Al), molybdenum (Mo), or titanium (Ti).

[0168] The second auxiliary source electrode 1210 can be configured to contact the upper surface of the first main conductive portion 121M, and can be electrically connected to the first auxiliary source electrode 310 and the first main conductive portion 121M.

[0169] The second auxiliary drain electrode 1220 can be configured to contact the upper surface of the second main conductive portion 122M, and can be electrically connected to the first auxiliary drain electrode 320 and the second main conductive portion 122M.

[0170] The second auxiliary source electrode 1210 may not overlap with the auxiliary gate electrode 330 and the first sub-conductive portion 121A. The second auxiliary drain electrode 1220 may not overlap with the auxiliary gate electrode 330 and the second sub-conductive portion 122A.

[0171] The second auxiliary source electrode 1210 may not be inserted between the functional insulating layer 150 and the first sub-conductive portion 121A. The second auxiliary drain electrode 1220 may not be inserted between the functional insulating layer 150 and the second sub-conductive portion 122A.

[0172] Therefore, the first sub-conductive portion 121A and the second sub-conductive portion 122A can be formed in the semiconductor layer 120.

[0173] Hydrogen generated in the functional insulating layer 150 can diffuse into the surrounding environment.

[0174] Hydrogen generated in the functional insulating layer 150 can be blocked by the main source electrode 141, the first auxiliary source electrode 310 and the second auxiliary source electrode 1210, the main gate electrode 143 and the auxiliary gate electrode 330, and can be further blocked by the main drain electrode 142, the first auxiliary drain electrode 320 and the second auxiliary drain electrode 1220.

[0175] Hydrogen generated in the functional insulating layer 150 can be doped into regions of the semiconductor layer 120 that are not covered by the metal pattern. Some regions of the hydrogen-doped semiconductor layer 120 can be made conductive (hydrogen-conductive). Some regions of the hydrogen-doped semiconductor layer 120 can be a first sub-conductive portion 121A and a second sub-conductive portion 122A.

[0176] Reference Figure 12 The second auxiliary source electrode 1210 should not overlap with the auxiliary gate electrode 330. In this case, hydrogen conduction does not occur in a portion of region 121A of the semiconductor layer 120, and the first sub-conducting portion 121A is not formed.

[0177] Reference Figure 12The second auxiliary drain electrode 1220 should not overlap with the auxiliary gate electrode 330. In this case, hydrogen conduction does not occur in a portion of region 122A of the semiconductor layer 120, and the second sub-conducting portion 122A is not formed.

[0178] Reference Figure 12 If the second auxiliary source electrode 1210 is not disposed on the first main conductive portion 121M and the second auxiliary drain electrode 1220 is not disposed on the second main conductive portion 122M, and the gate insulating layer 130 is etched to connect the first main conductive portion 121M to the first auxiliary source electrode 310 and the second main conductive portion 122M to the first auxiliary drain electrode 320, there is a possibility that the first main conductive portion 121M and the second main conductive portion 122M may be damaged or broken.

[0179] However, as Figure 12 As shown, a second auxiliary source electrode 1210 is disposed on the first main conductive portion 121M, and a second auxiliary drain electrode 1220 is disposed on the second main conductive portion 122M. In this state, the gate insulating layer 130 is etched to connect the first main conductive portion 121M to the first auxiliary source electrode 310 and to connect the second main conductive portion 122M to the first auxiliary drain electrode 320, thereby preventing or at least reducing damage or breakage of the first main conductive portion 121M and the second main conductive portion 122M through the second auxiliary source electrode 1210 and the second auxiliary drain electrode 1220.

[0180] Reference Figure 12 Since the second auxiliary source electrode 1210 does not overlap with the auxiliary gate electrode 330, no parasitic capacitance can be formed between the second auxiliary source electrode 1210 and the auxiliary gate electrode 330.

[0181] Furthermore, since the second auxiliary drain electrode 1220 does not overlap with the auxiliary gate electrode 330, no parasitic capacitance can be formed between the second auxiliary drain electrode 1220 and the auxiliary gate electrode 330. Therefore, the performance of the thin-film transistor (TFT) can be improved.

[0182] Reference Figure 12 By forming a first sub-conductive portion 121A and a second sub-conductive portion 122A in the semiconductor layer 120 through hydrogen conductivity, the length of the channel portion 123 can be shortened. Therefore, a short channel for a thin-film transistor (TFT) can be easily achieved. Consequently, the mobility of the TFT can be improved.

[0183] At the same time, such as Figure 12 As shown, when the second auxiliary source electrode 1210 is disposed on the first main conductive portion 121M and the second auxiliary drain electrode 1220 is disposed on the second main conductive portion 122M, as Figure 12As shown, the second plate 1120 of the capacitor CAP can be formed of the same material as the semiconductor layer 120 of the thin-film transistor TFT, and can include another semiconductor layer 1251 in a conductive state. Additionally, an additional metal layer 1252 can be further included on the other semiconductor layer 1251. Here, the additional metal layer 1252 can be one of the second auxiliary source electrode 1210 and the second auxiliary drain electrode 1220, or it can be a metal of the same material as the second auxiliary source electrode 1210 and the second auxiliary drain electrode 1220, and located on the same layer as the second auxiliary source electrode 1210 and the second auxiliary drain electrode 1220. For example, the additional metal layer 1252 can include an alloy material such as molybdenum-titanium (MoTi) and a single metal such as copper (Cu), aluminum (Al), molybdenum (Mo), or titanium (Ti).

[0184] Figure 13 This is a graph showing the drain current Ids (on-state current) of the thin-film transistor TFT in the thin-film transistor array substrate 100 according to an embodiment of the present disclosure, for each hydrogen doping length of the first sub-conducting portion 121A and the second sub-conducting portion 122A, as a function of carrier concentration.

[0185] Reference Figure 13 The x-axis of the graph represents the carrier concentration. The y-axis of the graph represents the current Ids flowing between the drain and source of the thin-film transistor (TFT).

[0186] When the functional insulating layer 150 of the thin-film transistor TFT is a hydrogen supply layer, the first sub-conductive portion 121A and the second sub-conductive portion 122A of the thin-film transistor TFT can be doped with hydrogen diffused from the functional insulating layer 150. Therefore, each of the length L1a of the first sub-conductive portion 121A and the length L2a of the second sub-conductive portion 122A of the thin-film transistor TFT can correspond to the hydrogen doping length.

[0187] For the first sub-conductive portion 121A and the second sub-conductive portion 122A, there are four thin-film transistor TFTs with four hydrogen doping lengths, in Figure 13 The results of measuring the change in current based on changes in carrier concentration are shown in the figure.

[0188] The four hydrogen doping lengths can include 0 μm, 1 μm*2, 2 μm*2, and 3 μm*2.

[0189] A hydrogen doping length of 0 μm can mean that, in a thin-film transistor (TFT), the first sub-conductive portion 121A and the second sub-conductive portion 122A are not hydrogen-conductive, but are dry-etched conductive portions, such as the first main conductive portion 121M and the second main conductive portion 122M. A hydrogen doping length of 1 μm*2 can mean that, in a TFT, the length L1a of the first sub-conductive portion 121A is 1 μm, and the length L2a of the second sub-conductive portion 122A is 1 μm. A hydrogen doping length of 2 μm*2 can mean that, in a TFT, the length L1a of the first sub-conductive portion 121A is 2 μm, and the length L2a of the second sub-conductive portion 122A is 2 μm. A hydrogen doping length of 3 μm*2 can mean that, in a TFT, the length L1a of the first sub-conductive portion 121A is 3 μm, and the length L2a of the second sub-conductive portion 122A is 3 μm.

[0190] Reference Figure 13 When the hydrogen doping length is 0 μm, even if the carrier concentration of the semiconductor layer 120 is changed, the drain current Ids of the thin film transistor TFT will not change significantly.

[0191] Reference Figure 13 However, when the hydrogen doping lengths of each of the first subconducting portion 121A and the second subconducting portion 122A are 1 μm, 2 μm and 3 μm, the drain current Ids of the thin film transistor TFT may be affected by the carrier concentration of the semiconductor layer 120.

[0192] Reference Figure 13 As the hydrogen doping length of each of the first subconducting portion 121A and the second subconducting portion 122A of the thin-film transistor TFT increases, the drain current Ids of the thin-film transistor TFT may be further affected by the change in carrier concentration.

[0193] Reference Figure 13 When the hydrogen doping lengths of each of the first sub-conductive portion 121A and the second sub-conductive portion 122A are 1 μm, 2 μm, and 3 μm, and the carrier concentration of the semiconductor layer 120 varies within the range of n0 to n2, the drain current Ids of the thin-film transistor TFT is not significantly affected by the carrier concentration of the semiconductor layer 120. Here, n0 can be the carrier concentration of the first main conductive portion 121M and the second main conductive portion 122M, which are dry-etched conductive portions. For example, n0 can be 10. 20 cm -3 n2 can be 10 18 cm -3 .

[0194] Reference Figure 13When the hydrogen doping lengths of each of the first sub-conductive portion 121A and the second sub-conductive portion 122A in the thin-film transistor TFT are 1 μm, 2 μm, and 3 μm, respectively, the drain current Ids of the thin-film transistor TFT is largely affected by the carrier concentration of the semiconductor layer 120 when the carrier concentration of the semiconductor layer 120 varies within a range less than n². That is, as the carrier concentration of the semiconductor layer 120 decreases, the drain current Ids of the thin-film transistor TFT further decreases.

[0195] Reference Figure 13 When the hydrogen doping lengths of each of the first sub-conductive portion 121A and the second sub-conductive portion 122A in the thin-film transistor TFT are 1 μm, 2 μm, and 3 μm, respectively, when the carrier concentration of the semiconductor layer 120 becomes less than n2, the drain current Ids of the thin-film transistor TFT decreases as the carrier concentration of the semiconductor layer 120 decreases, thereby making the mobility of the thin-film transistor TFT smaller outside the desired mobility range (μ1 to μ2). Therefore, the minimum carrier concentration value n2 that can keep the mobility of the thin-film transistor TFT within the desired mobility range (μ1 to μ2) can be set as the "optimal carrier concentration" of each of the first sub-conductive portion 121A and the second sub-conductive portion 122A that has been hydrogen-conductive.

[0196] Figure 14 It is a graph showing the drain current as a function of the gate voltage of a thin-film transistor TFT formed on a thin-film transistor array substrate 100 according to an embodiment of the present disclosure.

[0197] Reference Figure 14 The left curve 1410 shows the reference drain current at the desired level according to the gate voltage variation, and the right curve 1420 shows the current at... Figure 1 Thin-film transistor structure and Figure 3 In the case of a thin-film transistor structure, the drain current varies with the gate voltage.

[0198] Reference Figure 14 When performing experiments to measure a reference drain current at a desired level according to a gate voltage variation for each of cases 1410 (which does not have a thin-film transistor structure according to an embodiment of the present disclosure but exhibits the desired performance level) and 1420 (which has a thin-film transistor structure according to an embodiment of the present disclosure), the experiments are repeated for both cases 1 and 2. The first case (case 1) is when the drain-source voltage Vds of the thin-film transistor TFT is high (e.g., 10V), and the second case (case 2) is when the drain-source voltage Vds of the thin-film transistor TFT is low (e.g., 0.1V).

[0199] Figure 1 The thin-film transistor structure may include a gate insulator layer etch-free (GI etch-free) structure, and the semiconductor layer 120 may have a heterogeneous conductive structure, which includes a first sub-conductive portion 121A and a second sub-conductive portion 122A that have been hydrogen-conductive, in addition to the first main conductive portion 121M and the second main conductive portion 122M.

[0200] Figure 3 Thin-film transistor structures can also include, in addition to Figure 1 An auxiliary electrode structure, including a first auxiliary source electrode 310 and a first auxiliary drain electrode 320, is included in addition to the thin-film transistor structure (a gate insulator layer without etching structure and a heterogeneous conductive structure).

[0201] Reference Figure 14 When comparing the left curve 1410, which is used as a reference, and the right curve 1420, which is related to the thin-film transistor structure according to the embodiments of the present disclosure, it can be seen that the drain current based on the gate voltage is measured at a similar level.

[0202] Therefore, through Figure 1 Thin-film transistor structure or Figure 3 The thin-film transistor structure can prevent the loss of the semiconductor layer 120 of the thin-film transistor TFT and can maintain the drain current according to the gate voltage at a desired level, while preventing damage to the source contact portion between the main source electrode 141 and the first main conductive portion 121M and the drain contact portion between the main drain electrode 142 and the second main conductive portion 122M in the thin-film transistor TFT.

[0203] Here, the fact that the drain current is maintained at the desired level based on the gate voltage can mean that it has Figure 1 Thin-film transistor structure or Figure 3 Thin-film transistor (TFT) structures exhibit the desired levels of switching characteristics (on / off characteristics) and mobility performance.

[0204] Figure 15 It is used to explain in Figure 12 The cross-sectional view of the overlap length OL between the second auxiliary source electrode 1210 and the auxiliary gate electrode 330 and the overlap length OL between the second auxiliary drain electrode 1220 and the auxiliary gate electrode 330 in the thin film transistor TFT formed on the thin film transistor array substrate 100 according to the embodiment of the present disclosure. Figure 16 It is shown in Figure 12 The graph shows the drain current of a thin-film transistor (TFT) formed on a thin-film transistor array substrate 100 according to an embodiment of the present disclosure, with respect to the change in overlap length OL for each carrier concentration.

[0205] Figure 15 and Figure 16 This diagram illustrates the experimental results of determining the formation lengths L1a and L2a of the first sub-conductive portion 121A and the second sub-conductive portion 122A, which are hydrogen-conductive, to form an etch-free gate insulator layer and a heterogeneous conductive structure while simultaneously achieving desired levels of characteristics (e.g., mobility, drain current, etc.) for the thin-film transistor (TFT) and semiconductor layer 120. The length L1a of the first sub-conductive portion 121A can correspond to the separation distance between the second auxiliary source electrode 1210 and the auxiliary gate electrode 330, and the length L2a of the second sub-conductive portion 122A can correspond to the separation distance between the second auxiliary drain electrode 1220 and the auxiliary gate electrode 330. In the following description, only the source region will be described, for ease of description.

[0206] Reference Figure 15 and Figure 16 The fact that the overlap length OL has a positive value (+) means that the second auxiliary source electrode 1210 and the auxiliary gate electrode 330 overlap each other.

[0207] Therefore, hydrogen emitted from the functional insulating layer 150 is blocked by the second auxiliary source electrode 1210, thus preventing hydrogen conductivity from occurring in the semiconductor layer 120. For this reason, the first sub-conductive portion 121A may not be formed in the semiconductor layer 120.

[0208] Reference Figure 15 and Figure 16 ,exist Figure 12 In the structure of the thin-film transistor TFT formed on the thin-film transistor array substrate 100 according to the embodiment of the present disclosure, the overlap length OL between the second auxiliary source electrode 1210 and the auxiliary gate electrode 330 has a negative value (-).

[0209] Reference Figure 15 and Figure 16 The fact that the overlap length OL has a negative value (-) means that the second auxiliary source electrode 1210 and the auxiliary gate electrode 330 do not overlap with each other.

[0210] Reference Figure 15 and Figure 16 The fact that the overlap length OL has a negative value (-) means that: Figure 12 As shown, the second auxiliary source electrode 1210 and the auxiliary gate electrode 330 are horizontally spaced apart.

[0211] Furthermore, the hydrogen released from the functional insulating layer 150 is not blocked by the second auxiliary source electrode 1210, and hydrogen conduction occurs in the semiconductor layer 120, thereby forming a first sub-conducting portion 121A as a hydrogen conducting portion in the semiconductor layer 120.

[0212] Reference Figure 15 and Figure 16 To confirm the effect of a thin-film transistor TFT with a structure in which the second auxiliary source electrode 1210 and the auxiliary gate electrode 330 do not overlap (i.e., the overlap length OL has a negative value (-)), the drain current Ids is compared for thin-film transistor TFTs with a negative value (-) overlap length OL and thin-film transistors with a positive value (+) overlap length OL.

[0213] Figure 16 The curve is a curve of drain current measured when the overlap length OL is changed to 2μm, 1μm, 0μm, -1μm, -2μm, and -3μm for the offset carrier concentration (n) of n0, n1, n2, n3, and n4.

[0214] Here, the carrier concentrations (n) are in the order n0 > n1 > n2 > n3 > n4. n0 is the carrier concentration of the semiconductor layer 120 before hydrogen conductivity is formed, while n1 to n4 are the carrier concentrations of the semiconductor layer 120 when hydrogen conductivity is formed. For example, n0 could be 10... 20 cm -3 And n2 can be 10 18 cm -3 .

[0215] Positive (+) overlap lengths OL of 2 μm and 1 μm represent the overlap between the second auxiliary source electrode 1210 and the auxiliary gate electrode 330. When the overlap length OL is 2 μm, the second auxiliary source electrode 1210 and the auxiliary gate electrode 330 can overlap by 2 μm. When the overlap length OL is 1 μm, the second auxiliary source electrode 1210 and the auxiliary gate electrode 330 can overlap by 1 μm.

[0216] The negative values ​​(-) of the overlap length OL of -1μm, -2μm and -3μm can correspond to the case where the second auxiliary source electrode 1210 and the auxiliary gate electrode 330 do not overlap.

[0217] When the overlap length OL is -1 μm, the second auxiliary source electrode 1210 and the auxiliary gate electrode 330 are spaced 1 μm apart. When the overlap length OL is -2 μm, the second auxiliary source electrode 1210 and the auxiliary gate electrode 330 are spaced 2 μm apart. When the overlap length OL is -3 μm, the second auxiliary source electrode 1210 and the auxiliary gate electrode 330 are spaced 3 μm apart.

[0218] When the overlap length OL is -1 μm, the second auxiliary source electrode 1210 and the auxiliary gate electrode 330 are separated by 1 μm, so that the length L1a of the first sub-conductive portion 121A can have 1 μm or a similar value. When the overlap length OL is -2 μm, the second auxiliary source electrode 1210 and the auxiliary gate electrode 330 are separated by 2 μm, so that the length L1a of the first sub-conductive portion 121A can have 2 μm or a similar value. When the overlap length OL is -3 μm, the second auxiliary source electrode 1210 and the auxiliary gate electrode 330 are separated by 3 μm, so that the length L1a of the first sub-conductive portion 121A can have 3 μm or a similar value.

[0219] Reference Figure 16 When the overlap length OL of the second auxiliary source electrode 1210 and the auxiliary gate electrode 330 is 0 (zero) or has a positive value greater than 0 (1 μm, 2 μm), hydrogen conduction does not occur in the semiconductor layer 120 of the thin film transistor TFT, and the thin film transistor TFT has a similar drain current Ids regardless of the magnitude of the carrier concentration of the semiconductor layer 120.

[0220] Reference Figure 16 If the overlap length OL of the second auxiliary source electrode 1210 and the auxiliary gate electrode 330 increases from 0 to the positive direction (+) (i.e., 0μm->1μm->2μm), the drain current Ids increases significantly regardless of the carrier concentration of the semiconductor layer 120.

[0221] Reference Figure 16 If the overlap length OL between the second auxiliary source electrode 1210 and the auxiliary gate electrode 330 increases from 0 to the negative direction (-), that is, if the separation distance between the second auxiliary source electrode 1210 and the auxiliary gate electrode 330 increases in the order of 1 μm, 2 μm and 3 μm, the drain current Ids decreases. This decrease in drain current becomes more significant as the carrier concentration of the semiconductor layer 120 decreases.

[0222] Reference Figure 16 From the perspective of the magnitude of the drain current Ids of the thin-film transistor TFT, in order to form an etch-free gate insulator layer and a heterogeneous conductive structure, while the thin-film transistor TFT and the semiconductor layer 120 have desired levels of characteristics (e.g., mobility, drain current, etc.) (e.g., mobility μ has a value in the range of μ1 to μ2), the case 1800 with an overlap length OL of -1 μm and -2 μm and a carrier concentration of n1, n2 and n3 may be appropriate.

[0223] In other words, when the following structure is formed (a gate insulator layer without etching and a heterogeneous conductive structure): the second auxiliary source electrode 1210 and the auxiliary gate electrode 330 are designed such that the separation distance between the second auxiliary source electrode 1210 and the auxiliary gate electrode 330 is 1 μm and 2 μm and the length L1a of the first sub-conductive portion 122A is 1 μm and 2 μm, when the carrier concentration of the semiconductor layer 120 has n1, n2 and n3, the thin film transistor TFT and the semiconductor layer 120 can have the desired level of characteristics (e.g., the mobility μ has a level of value in the range of μ1 to μ2).

[0224] Figure 17 It is shown that, according to Figure 12 The graph shows the drain current variation of the gate voltage of a thin-film transistor TFT formed on a thin-film transistor array substrate 100 according to an embodiment of the present disclosure.

[0225] Reference Figure 17 The left curve 1710 shows the reference drain current at the desired level according to the gate voltage variation, and the right curve 1720 shows the drain current at the desired level with the gate voltage variation. Figure 12 In the case of a thin-film transistor structure, the drain current varies with the gate voltage.

[0226] Reference Figure 17 When performing experiments to measure a reference drain current at a desired level according to a gate voltage variation for each of cases 1710 (which does not have a thin-film transistor structure according to an embodiment of the present disclosure but exhibits the desired performance level) and 1720 (which has a thin-film transistor structure according to an embodiment of the present disclosure), the experiments for cases 1 and 2 are repeated. The first case (case 1) is when the drain-source voltage Vds of the thin-film transistor TFT is high (e.g., 10V), and the second case (case 2) is when the drain-source voltage Vds of the thin-film transistor TFT is low (e.g., 0.1V).

[0227] Figure 12 The thin-film transistor structure may include a gate insulator layer etch-free (GI etch-free) structure, and the semiconductor layer 120 may have a heterogeneous conductive structure, which includes a first sub-conductive portion 121A and a second sub-conductive portion 122A that have been hydrogen-conductive in addition to the first main conductive portion 121M and the second main conductive portion 122M, and may have a dual auxiliary electrode structure that also includes a second auxiliary source electrode 1210 and a second auxiliary drain electrode 1220.

[0228] Reference Figure 17When comparing the left curve 1710 used as a reference with the right curve 1720 related to the thin-film transistor structure according to the embodiments of the present disclosure, it can be seen that the drain current based on the gate voltage is measured at a similar level.

[0229] Therefore, through Figure 12 The thin-film transistor structure can prevent the loss of the semiconductor layer 120 of the thin-film transistor TFT and can maintain the drain current according to the gate voltage at a desired level. At the same time, it can prevent damage to the source contact portion between the main source electrode 141 and the first main conductive portion 121M and the drain contact portion between the main drain electrode 142 and the second main conductive portion 122M in the thin-film transistor TFT, and stably provide a hydrogen conduction region.

[0230] Here, the fact that the drain current remains at the desired level based on the gate voltage can mean that it has Figure 12 Thin-film transistor (TFT) structures exhibit the desired levels of switching characteristics (on / off characteristics) and mobility performance.

[0231] Figure 18 It is a graph showing the mobility of a thin-film transistor TFT formed on a thin-film transistor array substrate 100 according to an embodiment of the present disclosure as a function of carrier concentration.

[0232] In the thin-film transistor TFT formed on the thin-film transistor array substrate 100 according to the embodiments of the present disclosure, the semiconductor layer 120 can be prevented from being lost due to the unetched structure of the gate insulator layer and the heterogeneous conductive structure of the semiconductor layer 120, and the source and drain contacts in the semiconductor layer 120 can be prevented from being damaged.

[0233] The thin-film transistor TFT formed on the thin-film transistor array substrate 100 according to the embodiments of the present disclosure can have a mobility μ in a desired range (μ1 to μ2) while having the advantages mentioned above.

[0234] Reference Figure 18 Even if the carrier concentrations of the first sub-conductive portion 121A and the second sub-conductive portion 122A have values ​​in the range of n1 to n2 that are less than n0 (n0 is the carrier concentration of the first main conductive portion 121M and the second main conductive portion 122M), the thin film transistor TFT can still have a mobility μ in the desired range (μ1 to μ2).

[0235] Figure 19 This is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0236] Reference Figure 19The display device according to the embodiments of the present disclosure may include a display panel 1910, a data driving circuit 1920, a gate driving circuit 1930, a controller 1940, etc.

[0237] The display panel 1910 may include a display area DA and a non-display area NDA, where the non-display area NDA is the area outside the display area DA. Multiple data lines DL, multiple gate lines GL, and multiple sub-pixels SP can be configured.

[0238] The data driver circuit 1920 can output data voltage VDATA to multiple data lines DL to drive multiple data lines DL.

[0239] The data drive circuit 1920 can be implemented in tape-on-carrier (TCP), chip-on-glass (COG), chip-on-panel (COP), or chip-on-film (COF) types.

[0240] When the data drive circuit 1920 is implemented as a COG type or a COP type, the data drive circuit 1920 can be bonded to the pad portion formed in the non-display area NDA of the display panel 1910.

[0241] When the data driving circuit 1920 is implemented in the COF type, the data driving circuit 1920 can be mounted on the circuit film, and one side of the circuit film can be bonded to the pad portion formed in the non-display area NDA.

[0242] The gate drive circuit 1930 can output scan signals SCAN to multiple gate lines GL to drive multiple gate lines GL.

[0243] The gate drive circuit 1930 can be implemented as TCP type, COG type, COP type, COF type, gate in panel (GIP) type, etc.

[0244] When the gate drive circuit 1930 is implemented in COG or COP type, the gate drive circuit 1930 can be bonded to the pad portion formed in the non-display area NDA of the display panel 1910.

[0245] When the gate drive circuit 1930 is implemented in the COF type, the gate drive circuit 1930 can be mounted on the circuit film, and one side of the circuit film can be bonded to the pad portion formed in the non-display area NDA of the display panel 1910.

[0246] When the gate drive circuit 1930 is implemented in a GIP type, the gate drive circuit 1930 can be formed in a portion of the non-display area NDA of the display panel 1910. When the gate drive circuit 1930 is implemented in a GIP type, the gate drive circuit 1930 can be formed together with other electrodes or lines in the display area DA during the manufacturing process of the display panel 1910.

[0247] The controller 1940 can control the data drive circuit 1920 and the gate drive circuit 1930.

[0248] The controller 1940 can provide the data drive circuit 1920 with various data drive control signals DCS and image digital data Data for controlling the data drive timing. The data drive circuit 1920 can convert the image digital data Data into a data voltage VDATA corresponding to an analog voltage, and can output the data voltage VDATA to the data line DL based on the data drive control signal DCS.

[0249] The controller 1940 can provide the gate drive circuit 1930 with various gate drive control signals GCS for controlling the gate drive timing and various signals required to generate the scan signal SCAN. The gate drive circuit 1930 can output the scan signal SCAN with an on-level gate voltage to the gate line GL at a predetermined timing based on the gate drive control signal GCS.

[0250] The display device according to embodiments of this disclosure can be of various types, such as an organic light-emitting diode (OLED) display, a quantum dot display, or a liquid crystal display (LCD). See also... Figure 19 If the display device according to the embodiments of this disclosure is an organic light-emitting diode (OLED) display device, then each sub-pixel SP of the display panel 1910 may include a light-emitting device ED, a driving transistor DRT, a scanning transistor SCT, and a capacitor Cst.

[0251] A light-emitting device (ED) may include a first electrode, a light-emitting layer, and a second electrode. The light-emitting layer may be disposed between the first and second electrodes. The first electrode may be an anode electrode, and the second electrode may be a cathode electrode. Conversely, the first electrode may be a cathode electrode, and the second electrode may be an anode electrode. When the second electrode is a cathode electrode, a base voltage VSS may be applied to the second electrode. For example, the base voltage VSS may be ground voltage or a voltage similar to ground voltage. For example, the light-emitting device (ED) may be an organic light-emitting diode (OLED), a light-emitting diode (LED), a quantum dot light-emitting device, etc.

[0252] The driving transistor DRT is a transistor used to drive the light-emitting device ED and can control the current flowing to the light-emitting device ED.

[0253] The driving transistor DRT may include a first node N1, a second node N2, a third node N3, etc. The first node N1 of the driving transistor DRT may be a gate node and can be electrically connected to the source or drain node of the scanning transistor SCT. The second node N2 of the driving transistor DRT may be electrically connected to the first electrode of the light-emitting device ED and can be either a source or drain node. The third node N3 of the driving transistor DRT is the node to which the driving voltage VDD is applied and can be electrically connected to the driving voltage line DVL that provides the driving voltage VDD; it can also be either a drain or source node.

[0254] In response to the scan signal SCAN, which is a gate signal provided from the gate line GL, the scan transistor SCT can control the connection between the first node N1 of the drive transistor DRT and the corresponding data line DL.

[0255] The drain or source node of the scan transistor SCT can be electrically connected to the corresponding data line DL. The source or drain node of the scan transistor SCT can be electrically connected to the first node N1 of the driving transistor DRT. The gate node of the scan transistor SCT can be electrically connected to the gate line GL to receive the scan signal SCAN.

[0256] The scanning transistor SCT can be turned on by the scanning signal SCAN with a turn-on voltage, so that the data signal VDATA provided from the corresponding data line DL can be transmitted to the first node N1 of the driving transistor DRT.

[0257] The scanning transistor SCT can be turned on by a scanning signal SCAN with an on-level voltage, and turned off by a scanning signal SCAN with an off-level voltage. Here, when the scanning transistor SCT is n-type, the on-level voltage can be a high level voltage, and the off-level voltage can be a low level voltage. When the scanning transistor SCT is p-type, the on-level voltage can be a low level voltage, and the off-level voltage can be a high level voltage.

[0258] The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2 of the driving transistor DRT. The storage capacitor Cst can maintain the image data voltage VDATA, which corresponds to the image signal voltage, or its corresponding voltage for one frame.

[0259] The storage capacitor Cst is not a parasitic capacitor (e.g., Cgs, Cgd), which is an internal capacitor existing between the first node N1 and the second node N2 of the driving transistor DRT. The storage capacitor Cst can be an external capacitor intentionally designed to be outside the driving transistor DRT.

[0260] Each of the driving transistor DRT and the scanning transistor SCT can be an n-type transistor or a p-type transistor. Both the driving transistor DRT and the scanning transistor SCT can be n-type transistors or p-type transistors. At least one of the driving transistor DRT and the scanning transistor SCT can be an n-type transistor (or a p-type transistor), and the other can be a p-type transistor (or an n-type transistor).

[0261] Figure 19 The equivalent circuit of the sub-pixel SP shown is for illustrative purposes only and may include one or more transistors or one or more capacitors in some cases. Alternatively, each of the multiple sub-pixel SPs may have the same structure, or some of the multiple sub-pixel SPs may have different structures.

[0262] Reference Figure 19 The gate drive circuit 1930 may include multiple gate drive units GDU to output scan signals SCAN to multiple gate lines GL.

[0263] Each of the multiple gate drive units (GDUs) may include a pull-up transistor (Tu), a pull-down transistor (Td), and a control logic unit (LOGIC).

[0264] Pull-up transistor Tu and pull-down transistor Td can be connected in series between the node to which the clock signal CLK is input and the node to which the gate-base voltage GVSS is input.

[0265] The pull-up transistor Tu and the pull-down transistor Td are connected to the output point Nout of their output scan signal SCAN and to the gate line GL.

[0266] During the timing when the pull-up transistor Tu is turned on and the pull-down transistor Td is turned off, a high-level gate voltage corresponding to the clock signal CLK is applied to the output point Nout through the pull-up transistor Tu, so that the high-level gate voltage can be output to the gate line GL connected to the output point Nout. Here, the high-level gate voltage corresponds to the on-level voltage of the scan signal SCAN.

[0267] During the timing when the pull-up transistor Tu is turned off and the pull-down transistor Td is turned on, a low-level gate voltage corresponding to the gate-base voltage GVSS is applied to the output point Nout through the pull-down transistor Td, so that the low-level gate voltage can be output to the gate line GL connected to the output point Nout. Here, the low-level gate voltage corresponds to the turn-off level voltage of the scan signal SCAN.

[0268] The control logic unit LOGIC receives a start signal VST and a reset signal RST. It controls the voltage of node Q, which acts as the gate node of pull-up transistor Tu, and the voltage of node QB, which acts as the gate node of pull-down transistor Td. The voltages at node Q and node QB are opposite to each other. If the voltage at node Q is high, the voltage at node QB is low; conversely, if the voltage at node Q is low, the voltage at node QB is high.

[0269] The above reference Figures 10 to 18 The structures of the thin-film transistor array substrate 100 and the thin-film transistor TFT described may include heteroconductive structures, hydrogen conductive structures, gate insulator layer etch-free structures, and structures using functional insulating layers 150.

[0270] The above reference Figures 10 to 18 The structures of the thin-film transistor array substrate 100 and the thin-film transistor TFT described herein can be applied to the driving transistor DRT and / or scanning transistor SCT in the sub-pixel SP, or to the pull-up transistor Tu and pull-down transistor Td included in the gate driving unit GDU, or to the transistors in the control logic unit LOGIC of the gate driving unit GDU.

[0271] Reference Figure 19 The display panel 1910 of the display device according to embodiments of the present disclosure may include a thin-film transistor array substrate 100, on which a plurality of thin-film transistor TFTs are disposed. At least one of the plurality of thin-film transistor TFTs may include a semiconductor layer 120, a gate insulating layer 130, a main source electrode 141, a main drain electrode 142, a main gate electrode 143, and a functional insulating layer 150.

[0272] The semiconductor layer 120 may include a channel portion 123, a first conductive portion 121 located on one side of the channel portion 123, and a second conductive portion 122 located on the other side of the channel portion 123. The first conductive portion 121 may include a first main conductive portion 121M and a first sub-conductive portion 121A. The second conductive portion 122 may include a second main conductive portion 122M and a second sub-conductive portion 122A.

[0273] The gate insulating layer 130 may be located on the semiconductor layer 120 and may include a first contact hole CNT1 that exposes a portion of the first main conductive portion 121M and a second contact hole CNT2 that exposes a portion of the second main conductive portion 122M.

[0274] The main source electrode 141 may be located on the gate insulating layer 130 and may be electrically connected to the first main conductive portion 121M through the first contact hole CNT1. The main drain electrode 142 may be located on the gate insulating layer 130 and may be electrically connected to the second main conductive portion 122M through the second contact hole CNT2. The main gate electrode 143 may be located on the gate insulating layer 130 and may overlap with the channel portion 123.

[0275] The functional insulating layer 150 can be disposed on the main source electrode 141, the main gate electrode 143 and the main drain electrode 142.

[0276] The first sub-conductive portion 121A may be located between the first main conductive portion 121M and the channel portion 123. The first sub-conductive portion 121A may not overlap with the main source electrode 141 and the main gate electrode 143.

[0277] The second sub-conductive portion 122A may be located between the second main conductive portion 122M and the channel portion 123. The second sub-conductive portion 122A may not overlap with the main drain electrode 142 and the main gate electrode 143.

[0278] The first sub-conductive portion 121A and the functional insulating layer 150 can be separated by the gate insulating layer 130. The second sub-conductive portion 122A and the functional insulating layer 150 can be separated by the gate insulating layer 130.

[0279] The first sub-conductive portion 121A may have a conductivity different from that of the first main conductive portion 121M. The second sub-conductive portion 122A may have a conductivity different from that of the second main conductive portion 122M.

[0280] The embodiments of the present disclosure described above relate to a thin-film transistor array substrate 100 and a display device, wherein the semiconductor layer 120 has different types of conductive portions with different conductivity (auxiliary source / second conductive portions 121A, 122A and main source / second conductive portions 121M and 122M). Furthermore, it has a structure (no etched gate insulator layer structure) where the gate insulator layer 130 is not etched to expose the semiconductor layer 120 between the source electrode portion (main source electrode 141) and the gate electrode portion (main gate electrode 143) and between the drain electrode portion (main drain electrode 142) and the gate electrode portion (main gate electrode 143), thereby preventing loss, damage, or breakage of the semiconductor layer 120.

[0281] Furthermore, according to embodiments of this disclosure, since a gate insulating layer 130 is formed after the second auxiliary source electrode 1210 and the second auxiliary drain electrode 1220 are formed on the first main conductive portion 121M and the second main conductive portion 122M respectively, and then the gate insulating layer 130 is etched to form the first contact hole CNT1 and the second contact hole CNT2, the risk of damage, loss or disconnection of the first main conductive portion 121M and the second main conductive portion 122M can be prevented or minimized.

[0282] Furthermore, according to embodiments of this disclosure, a thin-film transistor array substrate 100 including a thin-film transistor TFT and a display device can be provided. The thin-film transistor TFT has a structure that can simultaneously provide excellent electrical characteristics (e.g., current characteristics, mobility, etc.) while eliminating or minimizing the possibility of damage to the semiconductor layer 120.

[0283] According to embodiments of the present disclosure, a thin-film transistor array substrate 100 including a thin-film transistor TFT and a display device can be provided. The thin-film transistor TFT has the following structure: a second auxiliary source electrode 1210 and a second auxiliary drain electrode 1220 are configured to simultaneously contact each of a first main conductive portion 121M and a second main conductive portion 122M, thereby preventing the formation of parasitic capacitance.

[0284] According to embodiments of the present disclosure, by having a structure capable of forming a capacitor CAP with a thin thickness, a thin-film transistor array substrate 100 and a display device capable of increasing the aperture ratio can be provided.

[0285] The foregoing description has been provided to enable any person skilled in the art to implement and use the technical concepts of the present invention, and has been provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the invention. The foregoing description and drawings provide examples of the technical concepts of the invention for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of the invention. Therefore, the scope of the invention is not limited to the embodiments shown, but is consistent with the widest scope consistent with the claims. The scope of protection of the invention should be interpreted based on the appended claims, and all technical concepts within their equivalents should be interpreted as being included within the scope of the invention.

Claims

1. A thin-film transistor array substrate, comprising: A semiconductor layer, the semiconductor layer including a channel portion, a first conductive portion located on one side of the channel portion and a second conductive portion located on the other side of the channel portion, the first conductive portion including a first main conductive portion and a first sub-conductive portion, and the second conductive portion including a second main conductive portion and a second sub-conductive portion; A gate insulating layer is disposed on the channel portion, the first main conductive portion, the first sub-conductive portion, the second main conductive portion, and the second sub-conductive portion, and has a first contact hole that exposes a portion of the first main conductive portion and a second contact hole that exposes a portion of the second main conductive portion. The main source electrode is disposed on the gate insulator layer and electrically connected to the first main conductive portion through the first contact hole in the gate insulator layer; The main drain electrode is disposed on the gate insulator layer and electrically connected to the second main conductive portion through the second contact hole in the gate insulator layer; A main gate electrode, wherein the main gate electrode is disposed on the gate insulating layer and overlaps with the channel portion; as well as As a functional insulating layer containing hydrogen, and the functional insulating layer is disposed on the main source electrode, the main gate electrode, and the main drain electrode, The first sub-conductive portion is located between the first main conductive portion and the channel portion. The first sub-conductive portion does not overlap with the main source electrode and the main gate electrode, and the first sub-conductive portion has a conductivity different from that of the first main conductive portion. The second sub-conductive portion is located between the second main conductive portion and the channel portion. The second sub-conductive portion does not overlap with the main drain electrode and the main gate electrode, and the second sub-conductive portion has a conductivity different from that of the second main conductive portion. The first sub-conductive portion and the functional insulating layer are separated by the gate insulating layer, and the second sub-conductive portion and the functional insulating layer are separated by the gate insulating layer.

2. The thin-film transistor array substrate according to claim 1, wherein, Among the first main conductive portion, the first sub-conductive portion, and the channel portion, the first main conductive portion has the highest conductivity, and the channel portion has the lowest conductivity. Among the second main conductive portion, the second sub-conductive portion, and the channel portion, the second main conductive portion has the highest conductivity, and the channel portion has the lowest conductivity.

3. The thin-film transistor array substrate according to claim 1, wherein, The vertical separation distance between the first sub-conductive portion and the functional insulating layer is less than or equal to the vertical separation distance between the first main conductive portion and the functional insulating layer, and the vertical separation distance between the second sub-conductive portion and the functional insulating layer is less than or equal to the vertical separation distance between the second main conductive portion and the functional insulating layer.

4. The thin-film transistor array substrate according to claim 1, wherein, The main gate electrode and the main source electrode are spaced apart by a first horizontal separation distance, such that the first upper surface of the gate insulator layer is exposed between the main gate electrode and the main source electrode. The main gate electrode and the main drain electrode are spaced apart by a second horizontal separation distance, such that the second upper surface of the gate insulator layer is exposed between the main gate electrode and the main drain electrode. Wherein, the first horizontal separation distance corresponds to the length of the first sub-conductive portion, and the second horizontal separation distance corresponds to the length of the second sub-conductive portion.

5. The thin-film transistor array substrate according to claim 4, wherein, The functional insulating layer is in contact with the first upper surface of the gate insulating layer and with the second upper surface of the gate insulating layer.

6. The thin-film transistor array substrate according to claim 1, further comprising: A passivation layer is disposed on the main source electrode, the main gate electrode and the main drain electrode and has a third contact hole that exposes a portion of the main source electrode or the main drain electrode; as well as A pixel electrode is disposed on the passivation layer and is in electrical contact with the main source electrode or the main drain electrode through the third contact hole.

7. The thin-film transistor array substrate according to claim 6, wherein, The functional insulating layer is disposed below the passivation layer.

8. The thin-film transistor array substrate according to claim 6, wherein, The functional insulating layer is disposed on the passivation layer.

9. The thin-film transistor array substrate according to claim 6, wherein, The passivation layer includes a plurality of sub-passivation layers, and the functional insulating layer is disposed between the plurality of sub-passivation layers.

10. The thin-film transistor array substrate according to claim 1, wherein, The functional insulating layer diffuses hydrogen into the first sub-conductive portion and the second sub-conductive portion.

11. The thin-film transistor array substrate according to claim 10, wherein, The hydrogen concentration of the functional insulating layer is higher than that of the first sub-conductive portion and the second sub-conductive portion.

12. The thin-film transistor array substrate according to claim 10, wherein, The functional insulating layer includes at least one of silicon nitride (SiNx), silicon oxynitride (SiON), or silicon oxide (SiOx).

13. The thin-film transistor array substrate of claim 10, further comprising a hydrogen diffusion barrier layer between the functional insulating layer and the channel portion, the hydrogen diffusion barrier layer blocking the diffusion of hydrogen from the functional insulating layer to the channel portion, and the hydrogen diffusion barrier layer including the main gate electrode.

14. The thin-film transistor array substrate according to claim 1, further comprising: A first auxiliary source electrode is located between the main source electrode and the first main conductive portion, and the first auxiliary source electrode electrically connects the main source electrode to the first main conductive portion through the first contact hole; A first auxiliary drain electrode is located between the main drain electrode and the second main conductive portion, and the first auxiliary drain electrode electrically connects the main drain electrode to the second main conductive portion through the second contact hole; as well as An auxiliary gate electrode is provided between the gate insulating layer and the main gate electrode, and is electrically connected to the main gate electrode and overlaps with the channel portion.

15. The thin-film transistor array substrate according to claim 14, wherein, The first auxiliary source electrode is in contact with the surface of the first main conductive portion, and the first auxiliary drain electrode is in contact with the surface of the second main conductive portion.

16. The thin-film transistor array substrate according to claim 14, wherein, The first auxiliary source electrode and the first auxiliary drain electrode are made of the same material as the auxiliary gate electrode and are located on the same layer of the thin-film transistor array substrate, and the main source electrode and the main drain electrode are made of the same material as the main gate electrode and are located on the same layer of the thin-film transistor array substrate.

17. The thin-film transistor array substrate according to claim 14, further comprising: A buffer layer beneath the semiconductor layer; as well as The light-shielding layer beneath the buffer layer, The first auxiliary source electrode or the first auxiliary drain electrode is electrically connected to the light-shielding layer through a fourth contact hole passing through the gate insulator layer and the buffer layer.

18. The thin-film transistor array substrate of claim 17, further comprising a plurality of sub-pixels, each sub-pixel comprising a thin-film transistor and a capacitor, wherein, The thin-film transistor includes the semiconductor layer, the main source electrode, the main drain electrode, and the main gate electrode. The capacitor includes a first plate, a second plate on the first plate, and a third plate on the second plate. The first plate is the light-shielding layer or a metal layer disposed on the same layer as the light-shielding layer. The second plate is another semiconductor layer located on the same layer as the semiconductor layer and in a conductive state. The third plate is the main gate electrode and the auxiliary gate electrode, or a metal located on the same layer as the main gate electrode and the auxiliary gate electrode.

19. The thin-film transistor array substrate according to claim 14, further comprising: The second auxiliary source electrode is in contact with the upper surface of the first main conductive portion, and the second auxiliary source electrode electrically connects the first auxiliary source electrode to the first main conductive portion. as well as The second auxiliary drain electrode is in contact with the upper surface of the second main conductive portion, and the second auxiliary drain electrode electrically connects the first auxiliary drain electrode to the second main conductive portion. Wherein, the second auxiliary source electrode does not overlap with the auxiliary gate electrode and the first sub-conductive portion, and the second auxiliary drain electrode does not overlap with the auxiliary gate electrode and the second sub-conductive portion.

20. The thin-film transistor array substrate according to claim 1, wherein, The gate insulating layer is configured such that the semiconductor layer is not exposed between the main source electrode and the main gate electrode, and between the main drain electrode and the main gate electrode.

21. A display device, the display device comprising a thin-film transistor array substrate, wherein a plurality of thin-film transistors are disposed on the thin-film transistor array substrate. in, At least one of the plurality of thin-film transistors includes: A semiconductor layer, the semiconductor layer including a channel portion, a first conductive portion located on one side of the channel portion and a second conductive portion located on the other side of the channel portion, the first conductive portion including a first main conductive portion and a first sub-conductive portion, and the second conductive portion including a second main conductive portion and a second sub-conductive portion; A gate insulating layer is disposed on the channel portion, the first main conductive portion, the first sub-conductive portion, the second main conductive portion and the second sub-conductive portion and has a first contact hole that exposes a portion of the first main conductive portion and a second contact hole that exposes a portion of the second main conductive portion. The main source electrode is disposed on the gate insulator layer and electrically connected to the first main conductive portion through the first contact hole in the gate insulator layer; The main drain electrode is disposed on the gate insulator layer and electrically connected to the second main conductive portion through the second contact hole in the gate insulator layer; The main gate electrode is disposed on the gate insulating layer and overlaps with the channel portion; and As a functional insulating layer containing hydrogen, and the functional insulating layer is disposed on the main source electrode, the main gate electrode, and the main drain electrode, The first sub-conductive portion is located between the first main conductive portion and the channel portion. The first sub-conductive portion does not overlap with the main source electrode and the main gate electrode, and the first sub-conductive portion has a conductivity different from that of the first main conductive portion. The second sub-conductive portion is located between the second main conductive portion and the channel portion. The second sub-conductive portion does not overlap with the main drain electrode and the main gate electrode, and the second sub-conductive portion has a conductivity different from that of the second main conductive portion. The first sub-conductive portion and the functional insulating layer are separated by the gate insulating layer, and the second sub-conductive portion and the functional insulating layer are separated by the gate insulating layer.

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