MEMORY CIRCUIT AND METHOD FOR OPERATING THE SAME

Abstract

Memory circuit (100) comprising: a first memory cell array (102) on a first layer (F); a second memory cell array on a second layer (F) that is distinct from the first layer (F); a first selection transistor array (104) on a third layer (F) that is distinct from the first layer (F) and the second layer (F); a second selection transistor array (106) on a fourth layer (F) that is distinct from the first layer (F), the second layer (F), and the third layer (F); a first set of bit lines (BL) extending in a first direction (Z) that are coupled to the first memory cell array (102), the second memory cell array, and the first selection transistor array (104); a second set of bit lines (BL) extending in the first direction (Z) and connected to the first memory cell array (102) and the second memory cell array through the first selection transistor array (104) are coupled;a first set of source lines (SL) extending in the first direction (Z) coupled to the first memory cell array (102), the second memory cell array, and the second select transistor array (106), and separated from the first set of bit lines (BL) in a second direction (X) that differs from the first direction (Z); and a second set of source lines (SL) extending in the first direction (Z) and coupled to the first memory cell array (102) and the second memory cell array through the second select transistor array (106), wherein the first select transistor array (104) has: a first select line (SG) extending in the second direction (X);and a first selection transistor (212) comprising a first gate, a first drain and a first source, wherein the first gate is coupled to the first selection line (SG), the first drain is coupled to a first bit line (BL) of the first set of bit lines (BL) and the first source is coupled to a first bit line (BL) of the second set of bit lines (BL), wherein the first memory cell array (102) comprises: a first word line (WL) extending in the second direction (X);and a first n-transistor having a second gate, a second drain and a second source, the second gate being coupled to the first word line (WL), the second drain being coupled to the first drain by the first bit line (BL) of the first set of bit lines (BL) and the second source being coupled to a first source line (SL) of the first set of source lines (SL), and wherein the second memory cell array has: a second word line (WL) extending in the second direction and separated from the first word line in the first direction;and a second n-transistor having a third gate, a third drain and a third source, wherein the third gate is coupled to the second word line (WL), the third drain is coupled to the first drain and the second drain by the first bit line (BL) of the first set of bit lines (BL) and the third source is coupled to the second source by the first source line (SL) of the first set of source lines (SL), and wherein the second select transistor array (106) has: a second select line (SG) extending in the second direction (X) and separated from the first select line (SG) in the first direction (Z);and a second selection transistor (214) having a fourth gate, a fourth drain and a fourth source, wherein the fourth gate is coupled to the second selection line (SG), the fourth drain is coupled to a first source line (SL) of the second set of source lines (SL) and the fourth source is coupled to the second source and the third source by the first source line (SL) of the first set of source lines (SL), wherein the first layer (F) is above the second layer (F), the second layer (F) is above the third layer (F) and the third layer (F) is above the fourth layer (F).

Description

PRIOR ARTThe semiconductor IC industry has created a wide variety of digital devices to address problems in a number of different areas. Some of these digital devices, such as memory macros, are configured to store data. As ICs have become smaller and more complex, the resistance of conductive lines within these digital devices has also changed, affecting the operating voltages of these digital devices and overall IC performance.WO 2019 / 152 226 A1 describes a memory structure having active columns of polysilicon formed over a semiconductor substrate, each active column including one or more vertical NOR strings, each NOR string comprising thin film memory transistors sharing a local source line and a local bit line, the local bit line being connected by a segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.Further prior art is known from U.S. Pat. No. 6,380,636 B1.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure may best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be appreciated that, in accordance with practice in the industry, various features are not drawn to scale. Indeed, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased. FIG. 1 is a perspective view of a memory circuit in accordance with some embodiments. FIG. 2A is a circuit diagram of a memory circuit in accordance with some embodiments. FIGS. 2B-2C are corresponding circuit diagrams of corresponding portions of the memory circuit of FIG. 2A, which are simplified for ease of illustration. FIG. 3A is a circuit diagram of a memory circuit in accordance with some embodiments. FIG. 3B is a timing diagram of waveforms of a memory circuit in accordance with some embodiments. FIG. 4 is a circuit diagram of a memory circuit in accordance with some embodiments. FIG. 5A is a circuit diagram of a memory circuit in accordance with some embodiments. FIG. 5B is a corresponding circuit diagram of a corresponding portion of the memory circuit of FIG. 5A, which is simplified for ease of illustration. FIG. 6A is a circuit diagram of a memory circuit in accordance with some embodiments. FIG. 6B is a corresponding circuit diagram of a corresponding portion of the memory circuit of FIG. 6A, which is simplified for ease of illustration. FIG. 7A is a circuit diagram of a memory circuit in accordance with some embodiments. FIG. 7B is a corresponding circuit diagram of corresponding portions of a memory circuit, which is simplified for ease of illustration. FIG. 8 is a diagram of a memory cell device in accordance with some embodiments. FIG. 9 is a diagram of a memory cell device in accordance with some embodiments. FIG. 10 is a flow diagram of a method of operating a circuit in accordance with some embodiments.DETAILED DESCRIPTIONThe following disclosure provides various embodiments, or examples, for implementing various features of the invention. Specific examples of components, materials, values, steps, arrangements, and the like are described below to simplify the present disclosure. These are, of course, merely examples and are not limiting. Other components, materials, values, steps, arrangements, or the like are contemplated. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for purposes of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Further, spatially relative terms such as "underlying", "below", "below", "overlying", "above", and the like may be used herein for ease of description to describe the relationship of an element or feature to (another) element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptive terms used herein may also be construed accordingly.In accordance with some embodiments, a memory circuit includes a first memory cell on a first layer, a second memory cell on a second layer, a first selection transistor on a third layer, a second selection transistor on a fourth layer, a local bit line, a global bit line, a local source line, and a global source line.In some embodiments, the local bit line is coupled to the first memory cell, the second memory cell, and the first selection transistor. In some embodiments, the global bit line is coupled to the first selection transistor.In some embodiments, the local source line is coupled to the first memory cell, the second memory cell, and the second selection transistor. In some embodiments, the global source line is coupled to the second selection transistor.In some embodiments, the global bit line is coupled to the local bit line, the first memory cell, and the second memory cell through the first selection transistor. In some embodiments, the global source line is coupled to the local source line, the first memory cell, and the second memory cell through the second selection transistor.In some embodiments, the first and second selection transistors are enabled for read operation and other selection transistors in other rows of the memory circuit are disabled for read operation.In some embodiments, by enabling the first and second select transistors for read operation and disabling other select transistors in other rows of the memory circuit for read operation, the local bit line / source line load of the disabled transistors is reduced compared to other approaches. In some embodiments, by decreasing the local bitline / source line load, the total bitline / source line load and capacitance of the memory circuit is decreased, thereby causing the precharge and sensing speed of the memory circuit to improve compared to other approaches.MEMORY CIRCUITFIG. 1 is a perspective view of a memory circuit 100, in accordance with some embodiments. In the embodiment of FIG. 1, memory circuit 100 is a memory macro.Memory circuit 100 includes a memory cell array 102, a select gate array 104, and a select gate array 106.Memory cell array 102 is connected to select gate array 104 and select gate array 106. Memory cell array 102 is via select gate array 104. Select gate array 106 is over memory cell array 102. Memory cell array 102 is separated from select gate array 104 and select gate array 106 by isolation region 120. In some embodiments, select gate array 104 is on a first layer of memory circuit 100. In some embodiments, memory cell array 102 is on a second layer of memory circuit 100 over the first layer. In some embodiments, memory cell array 102 is on a third layer of memory circuit 100 over the first layer and the second layer.Each memory cell in the memory cell array 102 is electrically connected to a corresponding select gate of the select gate array 104 and a corresponding select gate of the select gate array 106.Memory cell array 102 includes a three-dimensional (3D) array of memory cells that includes M rows and C columns and is configured on F layers of memory circuit 100, where M, C, and F are positive integers.The columns C of memory cells (collectively referred to as "memory cells MC") in memory cell array 102 are arranged in a first direction Y. The rows R of memory cells MC in memory cell array 102 are arranged in a second direction X. The layers F of memory cells MC in memory cell array 102 are arranged in a third direction Z.At least one of the first direction Y, the second direction X, or the third direction Z is different from another one of at least the first direction Y, the second direction X, or the third direction Z. In some embodiments, at least one of the first direction Y, the second direction X, or the third direction Z is perpendicular to another one of at least the first direction Y, the second direction X, or the third direction Z.Memory cell array 102 includes memory cell arrays 102[0],..., 102[F-1] arranged on a corresponding layer 0,..., F-1 of layers F of memory cell array 102. For example, each memory cell array 102[0],..., 102[F-1] has an array of memory cells MC arranged on a corresponding layer 0,..., F-1 of layers F. Memory cell arrays 102 are referred to herein by 102[layer or level number].Each memory cell array 102[ 0],..., 102[F- 1] of memory cell array 102 is separated from another memory cell array 102[ 0],..., 102[F- 1] of memory cell array 102 in the third direction Z by isolation region 120.Each memory cell array 102[ 0],..., 102[F- 1] of memory cell array 102 includes an array of memory cells MC[o, o, layer], MC[1, o, layer],..., MC[C- 1, 0, layer],..., MC[o, M- 1, layer], MC[1, M- 1, layer],..., MC[C- 1, M- 1, layer], which includes M rows and C columns on a corresponding layer 0,.., F- 1 of layers F. Memory cells MC are referred to herein by MC[column number, row number, layer or level number]. For example, memory cell array 102[0] includes an array of memory cells MC[0,0,0], MC[1,0,0],..., MC[C-1,0,0],..., MC[0,M-1,0], MC[1,M-1,0],..., MC[C-1,M-1,0] on corresponding layer 0.The rows of memory cells MC in each memory cell array 102[0],..., 102[F-1] are arranged in the second direction X. The columns of cells in each memory cell array 102[0],..., 102[F-1] are arranged in the first direction Y. In some embodiments, each memory cell MC in memory cell array 102 is configured to store a corresponding bit of data.In some embodiments, at least one memory cell array 102[ 0],..., 102[F- 1] of memory cell array 102 is the same as at least one other memory cell array 102[ 0],..., 102[F- 1] of memory cell array 102. In some embodiments, at least one memory cell array 102[ 0],..., 102[F- 1] of memory cell array 102 is different from at least one other memory cell array 102[ 0],..., 102[F- 1] of memory cell array 102.In some embodiments, memory cell array 102 is a non-volatile random access memory (NVRAM) array. In some embodiments, each memory cell in memory cell array 102 corresponds to a thin film transistor (TFT). In some embodiments, each memory cell in memory cell array 102 corresponds to a ferroelectric resistive random access memory (FeRAM) cell. In some embodiments, each memory cell in memory cell array 102 corresponds to a ferroelectric field effect transistor (FeFET) memory cell. In some embodiments, each memory cell in memory cell array 102 corresponds to a magneto-resistive random access memory (MRAM) cell. In some embodiments, each memory cell in memory cell array 102 corresponds to a resistive random access memory (RRAM) cell. Various types of memory cells in memory cell array 102 are within the contemplated scope of the present disclosure. For example, in some embodiments, each memory cell in memory cell array 102 is a static random access memory (SRAM). In some embodiments, each memory cell in memory cell array 102 corresponds to a dynamic random access memory (DRAM) cell. In some embodiments, each memory cell in memory cell array 102 corresponds to a phase change memory cell. In some embodiments, each memory cell in memory cell array 102 corresponds to a charge-based memory cell. Other configurations of memory cell array 102 are within the scope of the present disclosure.Each memory cell array in each respective layer of memory cell array 102 further includes M word lines (collectively referred to as "word lines WL") extending in the second direction X. Word lines WL are denoted herein by WL[Reihenzahl]_FL[Ebenenzahl]. Within each layer of memory cell array 102, M word lines are coupled to a corresponding row of memory cells of memory cell array 102[0],...,102[F-1]. For example, memory cell array 102[0] further includes M word lines WL[o]_FL[o], WL[1]_FL[o],..., WL[1]_FL[0] coupled to a corresponding row of memory cells in layer 0 of memory cell array 102. Similarly, memory cell array 102[F-1] further includes M word lines WL[o]_FL[F-1], WL[1]_FL[F-1],..., WL[M-1]_FL[F-1] coupled to a corresponding row of memory cells in layer F-1 of memory cell array 102. Memory cell array 102 has F*M word lines WL.Each row of memory cells in memory cell array 102[0] is associated with a corresponding word line of word lines WL[o]_FL[o], WL[1]_FL[o],..., WL[M-1]_FL[o] in layer 0 of memory cell array 102. Similarly, each row of memory cells in memory cell array 102[F-1] is associated with a corresponding word line of word lines WL[o]_FL[F-1], WL[1]_FL[F-1],..., WL[M-1]_FL[F-1] in layer F-1 of memory cell array 102. Other configurations of word lines WL are within the scope of the present disclosure.Memory cell array 102 further includes bit lines BL[0,0], BL[1,0],..., BL[C-1,0],..., BL[0,M-1], BL[1,M-1],..., BL[C-1,M-1] (collectively referred to as "bit lines BL") coupled to a corresponding column and row of memory cells in memory cell array 102. Bit lines BL are referred to herein by BL[column number, row number]. For ease of illustration, some of the bit lines in memory cell array 102 are not shown in FIG. 1. Memory cell array 102 has C*M bit lines BL. In some embodiments, bit lines BL are also referred to as local bit lines.Each column and row in memory cell array 102 is associated with a corresponding bit line. Each bit line BL extends in the third direction Z.Bit lines BL electrically couple respective memory cells lying on different layers of memory cell array 102 to each other and to a respective select gate of select gate array 104. For example, each memory cell in row 0 and column 0 of memory cell array 102 is electrically coupled together by bit line BL[0,0] and further coupled to a corresponding select gate SG[0,0] of select gate array 104. Similarly, each memory cell in row M- 1 and column C- 1 of memory cell array 102 is electrically coupled together by bit line BL[C- 1, M- 1] and further coupled to a corresponding select gate SG[C- 1, M- 1] of select gate array 104. Other configurations of bit lines BL are within the scope of the present disclosure.Memory cell array 102 further includes source lines SL[0,0], SL[1,0],.--, SL[C-1,0],--, SL[0,M-1], SL[1,M-1],--, SL[C-1,M-1] (collectively referred to as "source lines SL") coupled to a corresponding column and row of memory cells in memory cell array 102. Source lines SL are referred to herein by SL[column number, row number]. For ease of illustration, some of the source lines in memory cell array 102 are not shown in FIG. 1. Memory cell array 102 has C*M source lines SL. In some embodiments, source lines SL are also referred to as local source lines.Each column and row in memory cell array 102 is associated with a corresponding source line. Each source line SL extends in the third direction Z.Source lines SL electrically couple respective memory cells residing on different layers of memory cell array 102 to each other and to a respective select gate of select gate array 106. For example, each memory cell in row 0 and column 0 of memory cell array 102 is electrically coupled together by source line SL[ 0,0] and further coupled to a corresponding select gate SG**[0,0] of select gate array 106. Similarly, each memory cell in row M- 1 and column C- 1 of memory cell array 102 is electrically coupled together by source line SL[C- 1, M- 1] and further coupled to a corresponding select gate SG*[C- 1, M- 1] of select gate array 106. Other configurations of source lines SL are within the scope of the present disclosure.Select gate array 104 includes an array of select gates SG[0,0], SG[1,0],..., SG[C-1,0],..., SG[0,M-1], SG[1,M-1],..., SG[C-1,M-1] (collectively referred to as "select gates SG") having M rows and V columns, where M and C are positive integers. Select gates SG are referred to herein by SG[column number, row number].The columns C of selection gates SG in selection gate array 104 are arranged in the first direction Y. The rows R of select gates SG in select gate array 104 are arranged in the second direction X. In some embodiments, select gate array 104 is arranged on the first layer of memory circuit 100. For ease of illustration, some of the select gates in select gate array 104 are not marked in FIG. 1. Select gate array 104 has C*M select gates SG.In some embodiments, each select gate SG in select gate array 104 is similar to a corresponding memory cell in memory cell array 102, and a similar detailed description is omitted. In some embodiments, each selection gate SG includes a selection transistor. In some embodiments, each selection gate SG includes an n-transistor, a p-transistor, or a transfer gate.Each select gate SG in select gate array 104 is electrically coupled by respective bit lines BL to respective memory cells MC located on different layers of memory cell array 102. For example, select gate SG[0,0] of select gate array 104 is electrically coupled to each memory cell MC in row 0 and column 0 of memory cell array 102 through bit line BL[o,0]. For example, select gate SG[C-1, M-1] of select gate array 104 is electrically coupled to each memory cell MC in row M-1 and column C-1 of memory cell array 102 through bit line BL[C-1, M-1].Select gate array 104 further includes M select lines SG[ 0], SG[ 1],..., SG[M- 1] (collectively referred to as "select line SGL") coupled to a corresponding row of select gates in select gate array 104. Select lines SGL are referred to herein by SG[row number].Each row in select gate array 104 is associated with a corresponding select line. Each select line is configured to control the corresponding row of select gates in select gate array 104. Each select line SGL extends in the second direction X. For ease of illustration, some of the select lines in select gate array 104 are not marked in FIG. 1. Select gate array 104 includes M select lines SGL.In some embodiments, each select line in select gate array 104 is similar to a corresponding word line WL in memory cell array 102, and a similar detailed description is omitted. Other configurations of select gate array 104 or select lines SGL are within the scope of the present disclosure.Select gate array 106 includes an array of select gates SG*[o,0], SG*[1,0],..., SG*[C-1,0],..., SG*[0,M-1], SG*[1,M-1],..., SG*[C-1,M-1] (collectively referred to as "select gates SG*") having M rows C columns. Select gates SG* are referred to herein by SG*[column number, row number].The columns C of selection gates SG* in selection gate array 106 are arranged in the first direction Y. The rows R of select gates SG* in select gate array 106 are arranged in the second direction X. In some embodiments, select gate array 106 is arranged on the third layer of memory circuit 100. For ease of illustration, some of the select gates in select gate array 106 are not marked in FIG. 1. Select gate array 106 includes C*M select gates SG*.In some embodiments, each select gate SG* in select gate array 106 is similar to a corresponding memory cell in memory cell array 102 or a corresponding select gate in select gate array 104, and a similar detailed description is omitted. In some embodiments, each selection gate SG* includes a selection transistor. In some embodiments, each selection gate SG* includes an n-transistor, a p-transistor, or a transfer gate.Each select gate SG* in select gate array 106 is electrically coupled by respective source lines SL to respective memory cells MC that are on different layers of memory cell array 102. For example, select gate SG*[0,0] of select gate array 106 is electrically coupled to each memory cell MC in row 0 and column 0 of memory cell array 102 by source lines SL[0,0]. For example, select gate SG*[C-1,M-1] of select gate array 106 is electrically coupled to each memory cell MC in row M-1 and column C-1 of memory cell array 102 through source line SL[C-1,M-1].Select gate array 106 further includes M select lines SG*[0], SG*[1],..., SG*[M-1] (collectively referred to as "select line SGL*") coupled to a corresponding row of select gates in select gate array 106. Select lines SGL* are referred to herein by SG*[row number].Each row in select gate array 106 is associated with a corresponding select line. Each select line is configured to control the corresponding row of select gates in select gate array 106. Each select line SGL* extends in the second direction X. For ease of illustration, some of the select lines in select gate array 106 are not marked in FIG. 1. Select gate array 106 includes M select lines SGL*.In some embodiments, each selection line SGL* in selection gate array 106 is similar to a corresponding word line WL in memory cell array 102 or a corresponding selection line SGL, and a similar detailed description is omitted. Other configurations of select gate arrays 106 or select lines SGL* are within the scope of the present disclosure.Memory cell array 102 further includes C global bitlines GBL[o], GBL[1],..., GBL[C-1] (collectively referred to as "global bitlines GBL") coupled to a corresponding column of select gates in select gate array 104. Global bitlines GBL are referred to herein by GBL[column number]. Each column in select gate array 104 is associated with a corresponding global bit line.Global bit line GBL[o] is electrically coupled to column 0 of select gates of select gate array 104. In other words, rows 0 through M- 1 of select gate array 104 are coupled together in column 0 of select gate array 104 by global bit line GBL[o].Similarly, global bit line GBL[C-1] is electrically coupled to column C-1 of select gates of select gate array 104. In other words, rows 0 through M- 1 of select gate array 104 in column C- 1 of select gate array 104 are coupled together by global bit line GBL[C- 1].Each column of select gates of select gate array 104 is configured to selectively couple the corresponding global bit line and the corresponding column of local bit lines. For example, column o of select gates SG[0,0], SG[1,0],..., SG[C-1,0] of select gate array 104 is configured to selectively couple the corresponding global bit line GBL[o] and the corresponding column of local bit lines BL[0,0], BL[0,1],..., BL[0,M-1].Similarly, column C- 1 of select gates SG[C- 1,0], SG[C- 1,1],..., SG[C- 1,M- 1] of select gate array 104 is configured to selectively couple between the corresponding global bit line GBL[C- 1] and the corresponding column of local bit lines BL[C- 1,0], BL[C- 1,1],..., BL[C- 1,M- 1].Each global bit line GBL includes a conductive portion 130 extending in at least the first direction Y and M conductive portions 132[ 0], 132[ 1],..., 132[M- 1] extending in the third direction Z and coupled to corresponding select gates of select gate array 104 and conductive portion 130. For example, global bit line GBL[C- 1] includes a conductive portion 130 extending in at least the first direction Y, and conductive portions 132[ 0], 132[ 1],..., 132[M- 1] (referred to herein as a "set of conductive portions 132") extending in the third direction Z coupled to corresponding select gates SG[C- 1, 0], SG[C- 1, 1],..., SG[C- 1, M- 1] of select gate array 104 and conductive portion 130. For ease of illustration, some of the conductive portions 130 and conductive portions 132[ 0], 132[ 1],..., 132[M- 1] in global bitlines GBL are not shown in FIG. 1.Other configurations of at least one of the global bit line GBL, the conductive portion 130, and the set of conductive portions 132 are within the scope of the present disclosure.Memory cell array 102 further includes C global source lines GSL[o], GSL[1],..., GSL[C-1] (collectively referred to as "global source lines GSL") coupled to a corresponding column of select gates in select gate array 106. Global source lines GSL are referred to herein by GSL[column number]. Each column in select gate array 106 is associated with a corresponding global source line.Global source line GSL[o] is electrically coupled to column 0 of select gates of select gate array 106. In other words, rows 0 through M- 1 of select gate array 106 in column 0 of select gate array 106 are coupled together by global source line GSL[0].Similarly, global source line GSL[C- 1] is electrically coupled to column C- 1 of select gates of select gate array 106. In other words, rows 0 through M- 1 of select gate array 106 in column C- 1 of select gate array 106 are coupled together by global source line GSL[C- 1].Each column of select gates of select gate array 106 is configured to selectively couple the corresponding global source line and the corresponding column of local source lines. For example, column 0 of select gates SG[o,0], SG[1,0],..., SG[C-1,0] of select gate array 106 is configured to selectively couple the corresponding global source line GSL[0] and the corresponding column of local source lines SL[0,0], SL[0,1],..., SL[0,M-1].Similarly, column C- 1 of select gates SG[C- 1, 0], SG[C- 1, 1],..., SG[C- 1, M- 1] of select gate array 106 is configured to selectively couple the corresponding global source line GSL[C- 1] and the corresponding column of local source lines SL[C- 1, 0], SL[C- 1, 1],..., SL[C- 1, M- 1].Each global source line GSL includes a conductive portion 140 extending in at least the first direction Y, and M conductive portions 142[ 0], 142[ 1],..., 142[M- 1] extending in the third direction Z and coupled to corresponding select gates of select gate array 106 and the conductive portion 140. For example, global source line GSL[C- 1] includes a conductive portion 140 extending in at least the first direction Y, and conductive portions 142[ 0], 142[ 1],..., 142[M- 1] (hereinafter referred to as a "set of conductive portions 142") extending in the third direction Z are coupled to corresponding select gates SG*[C- 1, 0], SG*[C- 1, 1],..., SG*[C- 1, M- 1] of select gate array 106 and conductive portion 140. For ease of illustration, some of the conductive portions 140 and conductive portions 142[ 0], 142[ 1],..., 142[M- 1] in global source lines GSL are not shown in FIG. 1.Other configurations of at least one of the global source line GSL, the conductive portion 140, and the set of conductive portions 142 are within the scope of the present disclosure.Other configurations of memory circuit 100 are within the scope of the present disclosure. In some embodiments, select gate array 104 or 106 is not included in memory circuit 100. In some embodiments, select gate array 104 or 106 is between one or more layers F of memory cell array 102.FIG. 2A is a circuit diagram of a memory circuit 200 in accordance with some embodiments. FIGS. 2B-2C are corresponding circuit diagrams of corresponding portions 200B-200C of memory circuit 200, which are simplified for ease of illustration. Portion 200B includes one or more features of memory circuit 200 of FIG. 2A for column 0 and row 0-2 of memory circuit 200, and portion 200C includes one or more features of memory circuit 200 of FIG. 2A for columns 0-2 and row 0 of memory circuit 200.Memory circuit 200 is an embodiment of memory circuit 100 of FIG. 1, expressed in a schematic diagram, and a similar detailed description is therefore omitted.Memory circuit 200 refers to memory circuit 100 of FIG. 1. components that are the same or similar to those in one or more of FIGS. 1-10 (shown below) are given the same reference numerals and a detailed description is therefore omitted. For ease of illustration, some of the labeled elements of FIGS. 2A-2C are not labeled in each of FIGS. 2A-2C. In some embodiments, FIGS. 2A-2C include additional elements not shown in FIGS. 2A-2C.Memory circuit 200 includes a memory cell array 202, a select gate array 204, and a select gate array 206.Memory cell array 202 is an embodiment of memory cell array 102 of FIG. 1, select gate array 204 is an embodiment of select gate array 104 of FIG. 1, select gate array 206 is an embodiment of select gate array 106 of FIG. 1, and a similar detailed description is therefore omitted.Memory cell array 202 includes memory cell arrays 202[0],..., 202[F-1] arranged on a corresponding layer 0,..., F-1 of layers F of memory cell array 202. Memory cell arrays 202[0],..., 202[F-1] are embodiments of memory cell arrays 102[0],..., 102[F-1] of FIG. 1, and a similar detailed description is therefore omitted.Each memory cell array 202[0],..., 202[F-1] of memory cell array 202 includes an array of memory cells MC[o,o,layer], MC[1,o,Schicht],..., MC[C-1,0,layer],..., MC[0,M-1,layer], MC[1,M-1,layer],..., MC[C-1,M-1,layer], which include M rows and C columns on a corresponding layer 0,.., F-1 of layers F.Each memory cell MC includes a corresponding transistor (collectively referred to as "transistors 210"). Transistors 210 are referred to herein by 210 [column number, row number, layer or level number]. For example, memory cell array 202[0] includes an array of transistors 210[0,0,0], 210[1,0,0],..., 210[C-1,0,0],..., 210[0,M-1,0], 210[1,M-1,0],..., 210[C-1,M-1,0] on corresponding layer 0. For ease of illustration, some transistors 210 of memory cell array 202 are not marked in FIG. 2A.All transistors 210 are n-transistors. In some embodiments, all transistors 210 are N-metal oxide semiconductor (NMOS) transistors. Other types of transistors are within the scope of the present disclosure. In some embodiments, all transistors 210 are p-transistors. In some embodiments, all transistors 210 are P-metal oxide semiconductor (PMOS) transistors.Each transistor 210 has a gate coupled to a corresponding word line WL, a source coupled to at least one corresponding source line SL, and a drain coupled to at least one corresponding bit line BL. Other transistor terminals are within the scope of the present disclosure. For example, in the present disclosure, reference to the drains and sources of a same transistor may be changed to a source and a drain of the same transistor.For each layer of memory cell array 202, each transistor 210 has a gate coupled to a word line within the corresponding layer. For example, in layer 0, each transistor 210 has a corresponding gate coupled to a word line within layer 0. In other words, word lines WL[o]_FL[o], WL[1]_FL[0],..., WL[M-1]_FL[o] are coupled to a corresponding row of transistors (e.g., memory cells) in layer 0 of memory cell array 102 through each gate of the corresponding transistor. Each gate is configured to receive a corresponding wordline signal (not marked) on the corresponding wordline WL.A column includes memory cells in each layer of memory cell array 202 within a specific row and column, a select gate of select gate array 204 within the same specific row and column, and a select gate of select gate array 206 within the same specific row and column. For example, column 250 (FIG. 2B ) in row 0 and column 0 of memory circuit 200 corresponds to memory cells 210[0,0,0], 210[0,0,1],..., 210[0,0 F-1] in row 0 and column 0 of each layer of memory cell array 202, select transistor 212[0,0] in row 0 and column 0, and select transistor 214[0,0] in row 0 and column 0.Within each pillar, a drain of each corresponding memory cell on each layer of memory cell array 202 is coupled together by a local bit line in the pillar and is further coupled to a / a corresponding drain / source of a select gate of select gate array 204 in the pillar. For example, a drain of corresponding memory cells 210[0,0,0], 210[0,0,1],..., 210[0,0,F-1] are coupled together in row 0 and column 0 of each layer of memory cell array 202 by bit line BL[0,0] and further coupled to a / a drain / source of select transistor 212[0,0] in column 250 (FIG. 2B ).Within each pillar, a source of each corresponding memory cell on each layer of memory cell array 202 is coupled together by a local source line in the pillar and further coupled to a / a corresponding drain / source of a select gate of select gate array 204 in the pillar. For example, a source of corresponding memory cells 210[0,0,0], 210[0,0,1],..., 210[0,0,F-1] are coupled together in row 0 and column 0 of each layer of memory cell array 202 by source line SL[0,0] and further coupled together with a / a drain / source of select transistor 214[0,0] in column 250 (FIG. 2B ).Select gate array 204 includes an array of select gates SG[0,0], SG[1,0],..., SG[C-1,0],..., SG[0,M-1], SG[1,M-1],..., SG[C-1,M-1] described in FIG. 1.Each select gate SG[0,0], SG[1,0],..., SG[C-1,0],..., SG[0,M-1], SG[1,M-1],..., SG[C-1,M-1] of select gate array 204 includes a corresponding select transistor 212[0,0], 212[1,0],..., 212[C-1,0],..., 212[0,M-1], 212[1,M-1],..., 212[C-1,M-1] (collectively referred to as "select transistors 212"). Selection transistors 212 are referred to herein by 212 [column number, row number]. For ease of illustration, some selection transistors 212 of memory circuit 200 are not marked in FIG. 2A.Each column of selection transistors 212 is configured to selectively couple the corresponding global bit line and the corresponding column of local bit lines together. For example, column o of selection transistors 212[0,0], 212[0,1],..., 212[0,M-1] is configured to selectively couple the corresponding global bit line GBL[o] and the corresponding column of local bit lines BL[0,0], BL[0,1],..., BL[0,M-1].All selection transistors 212 are n-transistors. In some embodiments, all selection transistors 212 are NMOS transistors. Other types of transistors are within the scope of the present disclosure. In some embodiments, all selection transistors 212 are p-transistors. In some embodiments, all selection transistors 212 are PMOS transistors.Each selection transistor 212 has a gate coupled to a corresponding selection line SGL, a drain / source(s) coupled to at least one corresponding global bit line GBL, and a source / drain(s) coupled to at least one corresponding bit line BL.Each gate of a corresponding row of selection transistors 212 is electrically coupled to a corresponding selection line SG[ 0], SG[ 1],..., SG[M- 1] and is configured to receive a corresponding selection line signal SLS[ 0], SLS[1],..., SLS[M- 1]. Each selection transistor of selection transistors 212 is activated or deactivated in response to the corresponding selection line signal SLS[0], SLS[1],..., SLS[M-1] received on the corresponding selection line SG[0], SG[1],..., SG[M-1].If activated, a select transistor of select transistors 212 electrically couples the corresponding global bit line and the corresponding column of local bit lines. If disabled, the selection transistor of selection transistors 212 electrically decouples the corresponding global bit line and the corresponding column of local bit lines. In some embodiments, one row of selection transistors 212 is enabled for a period of time (between time T 1-T 2 in FIG. 3C ) and the other rows of selection transistors 212 are disabled for the same period of time (between time T 1-T 2 in FIG. 3C ).Within each pillar, a drain / source(s) of each respective selection transistor 212 is coupled to a respective global bit line GBL in the pillar. For example, one(s) drain / source of the corresponding select transistor 212[0,0] is coupled in row 0 and column 0 to global bit line GBL[o] in column 250 (FIGS. 2B-2C ).Within each column, a global bit line GBL is electrically coupled to each / each drain / source of each respective selection transistor 212 within the column. For example, in column 0, global bit line GBL[o] is electrically coupled to each / each drain / source of select transistors 212[0,0], 212[0,1],..., 212[0,M-1] in column 0. Therefore, each selection transistor 212 within a corresponding column is configured to share the corresponding global bit line GBL.Within each pillar, a source / drain(s) of each respective selection transistor 212 is coupled to a respective local bitline BL in the pillar. For example, one(s) source / drain of the corresponding select transistor 212[0,0] in row 0 and column 0 is coupled to local bit line BL[0,0] in column 250 (FIGS. 2B-2C ).Within each pillar, the / source / drain of each respective selection transistor 212 is coupled to the drains of each respective memory cell on each layer of the memory cell array 202 in the pillar through the respective local bit line BL. For example, the / source / drain of the corresponding select transistor 212[0,0] in row 0 and column 0 is coupled to the drains of memory cells 210[0,0,0], 210[0,0,1],..., 210[0,0,F-1] in row 0 and column 0 of each layer of memory cell array 202 in column 250 by local bit line BL[0,0] (FIGS. 2B-2C ).Select gate array 206 includes an array of select gates SG*[0,0], SG*[1,0],.--, SG*[C-1,0],--, SG*[0,M-1], SG*[1,M-1],--, SG*[C-1,M-1] described in FIG. 1.Each select gate SG*[0,0], SG*[1,0],..., SG*[C-1,0],..., SG*[0,M-1], SG*[1,M-1],..., SG*[C-1,M-1] of select gate array 206 includes a corresponding select transistor 214[0,0], 214[1,0];..., 214[C-1,0],..., 214[0,M-1], 214[1,M-1],..., 214[C-1,M-1] (collectively referred to as "select transistors 214"). Select transistors 214 are referred to herein by 214 [column number, row number]. For ease of illustration, some selection transistors 214 of memory circuit 200 are not marked in FIG. 2A.Each column of selection transistors 214 is configured to selectively couple the corresponding global source line and the corresponding column of local source lines together. For example, column o of selection transistors 214[0,0], 214[0,1],..., 214[0,M-1] is configured to selectively couple the corresponding global source line GSL[o] and the corresponding column of local source lines SL[o,o],SL[o,1],..., SL[0,M-1].All selection transistors 214 are n-transistors. In some embodiments, all selection transistors 14 are NMOS transistors. Other types of transistors are within the scope of the present disclosure. In some embodiments, all selection transistors 214 are p-transistors. In some embodiments, all selection transistors 214 are PMOS transistors.In some embodiments, at least one selection transistor of selection transistors 212 or 214 has multiple transistors (e.g., multiple cells) coupled in parallel, thereby improving the driving current capacity of the corresponding selection gate SG.In some embodiments, at least one selection transistor of selection transistors 212 or 214 has a same transistor size as at least one transistor 210 in a corresponding memory cell of memory cell array 202 or another selection transistor of selection transistors 212 or 214. In some embodiments, transistor size comprises one or more of a number of fins, a channel length, or a channel width. In some embodiments, at least one selection transistor of selection transistors 212 or 214 has a different transistor size than at least one transistor 210 in a corresponding memory cell of memory cell array 202 or another selection transistor of selection transistors 212 or 214.Each selection transistor 214 includes a gate coupled to a corresponding selection line SGL*, a drain / source(s) coupled to at least one corresponding global source line GSL, and a source / drain(s) coupled to at least one corresponding source line SL.Each gate of a corresponding row of selection transistors 214 is electrically coupled to a corresponding selection line SG*[0], SG*[1],..., SG*[M-1] and is configured to receive a corresponding selection line signal SLS*[0], SLS*[1],..., SLS*[M-1]. Each selection transistor of selection transistors 214 is activated or deactivated in response to the corresponding selection line signal SLS*[0], SLS*[1],..., SLS*[M-1] received on the corresponding selection line SG*[0], SG*[1],..., SG*[M-1]. In some embodiments, at least select line signal SLS*[0], SLS*[1],..., SLS*[M-2], or SLS*[M-1] is at least equal to corresponding select line signal SLS[0], SLS[1],..., SLS[M-2], or SLS[M-1].If activated, a select transistor of select transistors 214 electrically couples the corresponding global source line and the corresponding column of local source lines. If disabled, the selection transistor of selection transistors 214 electrically decouples the corresponding global source line and the corresponding column of local source lines. In some embodiments, one row of selection transistors 214 is enabled for a period of time (between time T 1-T 2 in FIG. 3C ) and the other rows of selection transistors 214 are disabled for the same period of time (between time T 1-T 2 in FIG. 3C ).In some embodiments, the timing of enabling or disabling selection transistors 212 is synchronized with the timing of enabling or disabling selection transistors 214.Within each pillar, a drain / source(s) of each respective selection transistor 214 is coupled to a respective global source line GSLin the pillar. For example, one(s) drain / source of the corresponding select transistor 214[0,0] in row 0 and column 0 is coupled to global source line GSL[o] in column 250 (FIGS. 2B-2C ).Within each column, a global source line GSL is electrically coupled to a / a drain / source of each respective selection transistor 214 within the column. For example, in column 0, global source line GSL[o] is electrically coupled to each / each drain / source of selection transistors 214[0,0], 214[0,1],..., 214[0,M-1] in column 0. Therefore, each selection transistor 214 within a corresponding column is configured to share the corresponding global source line GSL.Within each pillar, a source / drain(s) of each respective selection transistor 214 is coupled to a respective local source line SL in the pillar. For example, one(s) source / drain of the corresponding select transistor 214[0,0] in row 0 and column 0 is coupled to local source line SL[0,0] in column 250 (FIGS. 2B-2C ).Within each pillar, the source / drain of each respective selection transistor 214 is coupled to the sources of each respective memory cell on each layer of the memory cell array 202 in the pillar through the respective local source line SL. For example, the / source / drain of the corresponding select transistor 214[0,0] in row 0 and column 0 is coupled to the sources of memory cells 210[0,0,0], 210[0,0,1],..., 210[0,0,F-1] in row 0 and column 0 of each layer of memory cell array 202 in column 250 by local source line SL[0,0] (FIGS. 2B-2C ).In some embodiments, by enabling one row of selection transistors 214 for a time duration and disabling the other rows of selection transistors 214 in the same column for the same time duration, the global source line GSL in the same column is capable of being shared.In some embodiments, by enabling one row of selection transistors 212 for a period of time and disabling the other rows of selection transistors 212 in the same column for the same period of time, the local bit line BL that loads the disabled selection transistors 212 is reduced compared to other approaches. Similarly, in some embodiments, by enabling one row of selection transistors 214 for a duration and disabling the other rows of selection transistors 214 in the same column for the same duration, the local source line SL that loads the disabled selection transistors 214 is reduced compared to other approaches. In some embodiments, by reducing local BL / SL loading, the overall BL / SL loading and capacity of memory circuit 200 is reduced, thereby reducing the precharge and scan speed of memory circuit 200 to improve it compared to other approaches.FIG. 3A is a circuit diagram of a memory circuit 300A, in accordance with some embodiments.Memory circuit 300A is a portion of memory circuit 200 of FIGS. 2A-2C. For example, memory circuit 300A corresponds to rows 0 and 1 of portion 200B of memory circuit 200 of FIG. 2B.FIG. 3B is a timing diagram 300B of waveforms of a memory circuit, such as portion 300A of memory circuit 200 in FIGS. 2A-2C, in accordance with some embodiments.Memory circuit 300A and timing diagram 300B are an example of enabling one row (e.g., row 0) of selection transistors 212 and 214 and disabling the other rows (e.g., rows 1 through M- 1) of selection transistors 212 and 214 in the same column (column 0).In some embodiments, FIG. 3B is a timing diagram 300B of waveforms of at least circuit 100- 200 of FIGS. 1 and 2A- 2C or memory circuits 400- 800 of FIGS. 4-8, in accordance with some embodiments.At time T 0, each of select power signal SLS[ 0], select line signal SLS**[ 0], select line signal SLS[ 1], select line signal SLS**[ 1] thereby causes the corresponding select transistor 212[ 0, 0], 214[ 0, 0], 212[ 0, 1], 214[ 0, 1] to be turned off. By turning off select transistor 212[0,0], bit line BL[0,0] is not coupled to global bit line GBL[o], and by turning off select transistor 214[0,0], source line SL[0,0] is not coupled to global source line GSL[o]. By turning off selection transistor 212[0,1], bit line BL[o,1] is not coupled to global bit line GBL[o], and by turning off selection transistor 214[0,1], source line SL[o,1] is not coupled to global source line GSL[o].At time T0, all of wordline signal WL[0]_FL[0]* of wordline WL[o]_FL[o]* and wordline signals WL[1]_FL[o]* of wordline WL[1]_FL[o] - wordline signals WL[1]_FL[F-1]* of wordline WL[1]_FL[F-1] are logic low.At time T1, select line signal SLS[ 0] and select line signal SLS**[ 0] transition from logic low to logic high. In response to select line signal SLS[ 0] and select line signal SLS**[ 0] being logic high, select transistors 212[ 0, 0] and 214[ 0, 0] are caused to be activated or turned on. By turning on select transistor 212[0,0], bit line BL[0,0] is coupled to global bit line GBL[o], and by turning on select transistor 214[0,0], source line SL[0,0] is coupled to global source line GSL[o]. Thus, a current path IBL from the bit line BL[0,0] is closed with the global source line GBL[0], and a current path ISL from the source line SL[0,0] to the global source line GBL[o] is closed. However, since selection transistor 212[ 0, 1] is turned off, a current path from bit line BL[o, 1] to global bit line GBL[ 0] is opened, and since selection transistor 214[ 0, 1] is turned off, a current path from source line SL[o, 1] to global source line GBL[o] is opened. Thus, one row (e.g., row 0) of select transistors 212[0,0] and 214[0,0] is selected and the other rows (e.g., rows 1 through M-1) of select transistors 212[0,1] and 214[0,1] in the same column (column 0) are not selected or disabled.At time T1, wordline signal WL[0]_FL[0]* from a selected memory cell (e.g., transistor 210[0,0,0]) also transitions from logic low to logic high. In other words, a selected memory cell MC[0,0,0] in memory cell array 202[0] is activated and data can be read from the selected memory cell. In response to wordline signal WL[o]_FL[o]* being logic high, transistor 210[0,0,0] is caused to be activated or turned on. By turning on transistor 210[0,0,0], bit line BL[0,0] and source line SL[0,0] are coupled together, allowing global bit line GBL[o] and global source line GSL[o] to be coupled together.In some embodiments, one or more memory cells of other layers of memory cell array 202 within the same pillar are unselected as memory cell 210[0,0,0]. In some embodiments, unselected memory cells of row 0 and column 0 of memory cell array 202 include corresponding logic low wordline signals of corresponding wordlines WL[o]_FL[1]-WL[o]_FL[F-1].In some embodiments, memory cells in other rows of memory cell array 202 are unselected. In some embodiments, unselected memory cells in other rows of memory cell array 202 have corresponding wordline signals WL[1]_FL[o]* through WL[ 1]_FL[F- 1]* that are logic low.At time T2, select line signals SLS[ 0] and select line signals SLS**[ 0] transition from logic high to logic low. In response to select line signal SLS[ 0] and select line signal SLS**[ 0] being logic low, select transistors 212[ 0, 0] and 214[ 0, 0] are caused to be disabled or turned off. By turning off select transistor 212[0,0], bit line BL[0,0] is decoupled from global bit line GBL[o], and by turning off select transistor 214[0,0], source line SL[0,0] is decoupled from global source line GSL[o]. Therefore, the current path IBL from the bit line BL[0,0] to the global bit line GBL[0] is opened, and the current path ISL from the source line SL[0,0] to the global source line GBL[o] is opened. Thus, row 0 of selected transistors 212[0,0] and 214[0,0] is deselected.At time T2, wordline signal WL[o]_FL[o]* of transistor 210[0,0,0] transitions from logic high to logic low. In other words, selected memory cell MC[0,0,0] in memory cell array 202[0] is disabled or deselected and data can no longer be read from the unselected memory cell. In response to wordline signal WL[o]_FL[o]* being logic low, transistor 210[0,0,0] causes to be disabled or turned off. Turning off transistor 210[0,0,0], bit line BL[0,0] and source line SL[0,0] are disconnected.FIG. 4 is a circuit diagram of a memory circuit 400 in accordance with some embodiments.Memory circuit 400 is an embodiment of memory circuit 100 of FIG. 1 expressed in a schematic diagram and a similar detailed description is therefore omitted.Memory circuit 400 is a variation of memory circuit 200 of FIGS. 2A-2C. Memory circuit 400 corresponds to a portion of memory circuit 200. For example, memory circuit 400 corresponds to column 0 and rows 0-3 of memory circuit 200.Compared to memory circuit 200, memory circuit 400 further includes predecoder circuits 402, select line driver circuits 404, predecoder circuits 410, and wordline driver circuits 412.Predecoder circuits 402 include predecoder circuits 402[0],..., 402[3]. In some embodiments, predecoder circuits 402 are configured to predecode portions of addresses in select gate arrays 204 or 206 that identify a series of select gates in select gate arrays 204 and 206. In some embodiments, predecoder circuits 402 include row decoder circuits (not shown).Select line driver circuits 404 include select line driver circuits 404[0],..., 404[3]. In some embodiments, select line driver circuits 404 are configured to generate select line signals SLS[0],..., SLS[3]. Each predecoder circuit 402[0],..., 402[3] is coupled to a corresponding select line driver circuit 404[0],..., 404[3].Each select line driver circuit is coupled to a pair of select gates within each corresponding row of memory circuit 400. Each select line driver circuit 404[ 0],..., 404[ 3] is coupled to a corresponding select gate (e.g., select transistor 212[0,0],..., 212[ 0, 3]) of select gate array 204 through a corresponding select line SG[ 0],..., SG[ 3] and to a corresponding select gate (e.g., select transistor 214[0,0],..., 214[ 0, 3]) of select gate array 206 through a corresponding select line SG*[0],..., SG**[ 3]. In some embodiments, each select gate [e.g., select transistor 212[0,0],..., 212[0,3]) of select gate array 204 has a same select line signal (e.g., SLS[0],..., SLS[3]) as a corresponding select gate (e.g., select transistor 214[0,0],..., 214[0,3]) of select gate array 206 in the same row of memory circuit 400.Predecoder circuits 410 include predecoder circuits 410[0],..., 410[3]. In some embodiments, predecoder circuits 410 are configured to predecode portions of addresses in memory cell array 202 that identify a row of memory cells in memory cell array 202. In some embodiments, predecoder circuits 410 include row decoder circuits.Word line driver circuits 412 include word line driver circuits 412[0],..., 412[3]. Each predecoder circuit 410[0],..., 410[3] is coupled to a corresponding wordline driver circuit 412[0],..., 412[3]. In some embodiments, wordline driver circuits 412 are configured to generate wordline signals on corresponding wordlines. For example, wordline driver circuit 412[0] is configured to generate wordline signals on wordlines WL[o]_FL[o],..., WL[3]_FL[o], and wordline driver circuit 412[1] is configured to generate wordline signals on wordlines WL[o]_FL[F-1],..., WL[3]_FL[F-1].Each wordline driver circuit is coupled to each wordline within each corresponding row and layer of memory circuit 400. For example, wordline driver circuit 412[0] is coupled to wordlines WL[o]_FL[o],..., WL[3]_FL[0] on layer 0 of memory cell array 202. Similarly, wordline driver circuit 412[3] is coupled to wordlines WL[o]_FL[F-1],..., WL[3]_FL[F-1] on layer F-1 of memory cell array 202. In other words, wordline driver circuits 412 are shared by each row of memory cells in the same layer of memory cell array 202.In some embodiments, using at least predecoder circuits 402, select line driver circuits 404, predecoder circuits 410, or wordline driver circuits 412 as configured, a memory circuit has fewer driver circuits (e.g., select line driver circuits 404 and wordline driver circuits 412) than other approaches. In some embodiments, by reducing the number of driver circuits, memory circuit 400 occupies less area than other approaches. In some embodiments, the number of driver circuits reduced by memory circuit 400 is at least 70%.While FIG. 4 has been described with respect to 1 column (e.g., column 0) and 4 rows (e.g., rows 0-3) of memory circuit 200, the features of memory circuit 400 are applicable to each of the rows of columns of memory circuit 200 and are omitted for brevity.FIG. 5A is a circuit diagram of a memory circuit 500, in accordance with some embodiments. FIG. 5B is a corresponding circuit diagram of a corresponding portion 500B of memory circuit 500 that is simplified for ease of illustration. Portion 500B includes one or more features of memory circuit 500 of FIG. 5A for column 0 and row 0 of memory circuit 500, and a similar detailed description is omitted. Portion 500B corresponds to a column 550.Memory circuit 500 is a variation of memory circuit 200 of FIGS. 2A-2C. For example, memory circuit 500 corresponds to memory circuit 200 without select gate array 204.Memory circuit 500 is an embodiment of memory circuit 100 of FIG. 1 expressed in a schematic diagram and a similar detailed description is therefore omitted.Memory circuit 500 is a variation of memory circuit 200 of FIGS. 2A-2C. Compared to memory circuit 200 of FIGS. 2A-2C, memory circuit 500 does not include select gate array 204, select transistors 212, and select lines SG.By not including select gate array 204, select transistors 212 and select lines SG, each column of global bit lines GBL is directly coupled to columns of local bit lines BL. For example, global bit line GBL[0] within column 0 is directly coupled to each of local bit lines BL[0,0], BL[0,1],..., BL[0,M-1] within column 0 of memory circuit 500.By not including select gate array 204, select transistors 212 and select lines SG, all bit lines BL within a corresponding column of memory circuit 500 are coupled together. For example, all local bit lines BL[0,0], BL[o,1],..., BL[0,M-1] within column o of memory circuit 500 are coupled together by global bit line GBL[o].Within each pillar, the drains of each corresponding memory cell on each layer of memory cell array 202 within the pillar are coupled to the corresponding global bit line GBL through the corresponding local bit line BL. For example, the drains of respective memory cells 210[0,0,0], 210[0,0,1],..., 210[0,0,F-1] in row o and column 0 of each layer of memory cell array 202 in column 550 (shown in FIG. 5B ) are coupled to the respective global bit line GBL[o] in column 0 through the respective local bit line BL[0,0].In some embodiments, by designating select gate array 206, select transistors 214, and select lines SG* in memory circuit 500, one row of select transistors 214 in memory circuit 500 is activated for one time duration and other rows of select transistors 214 in the same column are deactivated for the same time duration, thereby reducing loading of the deactivated select transistors 124 by the local source line SL compared to other approaches. In some embodiments, by reducing loading by the local SL, the overall loading by the SL and capacitance of memory circuit 500 is reduced, thereby causing the precharge and scan speed of memory circuit 500 to improve compared to other approaches.FIG. 6A is a circuit diagram of a memory circuit 600 in accordance with some embodiments. FIG. 6B is a corresponding circuit diagram of a corresponding portion 600B of memory circuit 600 that is simplified for ease of illustration. Portion 600B includes one or more features of memory circuit 600 of FIG. 6A for column 0 and row 0 of memory circuit 600, and a similar detailed description is omitted. Portion 600B corresponds to a pillar 650.Memory circuit 600 is a variation of memory circuit 200 of FIGS. 2A-2C. For example, memory circuit 600 corresponds to memory circuit 200 without select gate array 206.Memory circuit 600 is an embodiment of memory circuit 100 of FIG. 1 expressed in a schematic diagram and a similar detailed description is therefore omitted.Memory circuit 600 is a variation of memory circuit 200 of FIGS. 2A-2C. Compared to memory circuit 200 of FIGS. 2A-2C, memory circuit 600 does not include select gate array 206, select transistors 214, and select lines SG*.By not including select gate array 206, select transistors 214, and select lines SG*, each column of global source lines GSL is directly coupled to columns of local source lines SL. For example, global source line GSL[0] within column 0 is directly coupled to each of local source lines SL[0,0], SL[0,1],..., SL[0,M-1] within column 0 of memory circuit 600.By not including select gate array 206, select transistors 214, and select lines SG*, all source lines SL within a corresponding column of memory circuit 600 are coupled together. For example, all local source lines SL[0,0], SL[0,1],..., SL[0,M-1] within column 0 of memory circuit 600 are coupled together by global source line GSL[o].Within each pillar, the drains of each corresponding memory cell on each layer of memory cell array 202 within the pillar are coupled to the corresponding global source line GSL through the corresponding local source line SL. For example, the drains of respective memory cells 210[0,0,0], 210[0,0,1],..., 210[0,0,F-1] in row 0 and column 0 of each layer of memory cell array 202 in column 650 (shown in FIG. 6B ) are coupled to the respective global source line GSL[o] in column 0 through the respective local source line SL[0,0].In some embodiments, by including select gate array 204, select transistors 212, and select lines SG in memory circuit 600, a row of select transistors 212 in memory circuit 600 is enabled for a period of time and other rows of select transistors 212 in the same column are disabled for the same period of time, thereby reducing loading by the local bit line BL of the disabled select transistors 212 compared to other approaches. In some embodiments, by reducing loading by the local BL, loading is reduced by the entire BL and capacitance of memory circuit 600, thereby causing the precharge and scan speed of memory circuit 600 to improve compared to other approaches.FIG. 7A is a circuit diagram of a memory circuit 700 in accordance with some embodiments. FIG. 7B is a corresponding circuit diagram of a corresponding portion 700B of memory circuit 700 that is simplified for ease of illustration. Portion 700B includes one or more features of memory circuit 700 of FIG. 7A for column 0 and row 0 of memory circuit 700, and a similar detailed description is omitted. Portion 700B corresponds to a column 750.Memory circuit 700 is a variation of memory circuit 200 of FIGS. 2A-2C. For example, memory circuit 700 corresponds to memory circuit 200 without select gate array 206 and select gate array 204 is positioned between two previously adjacent layers of memory cell array 202.Memory circuit 700 is an embodiment of memory circuit 100 of FIG. 1 expressed in a schematic diagram and a similar detailed description is therefore omitted.Memory circuit 700 is a variation of memory circuit 200 of FIGS. 2A-2C. Compared to memory circuit 200 of FIGS. 2A-2C, memory circuit 700 does not include select gate array 206, select transistors 214, and select lines SG*, and select gate array 204 is positioned between two layers of memory cell array 202 that were adjacent in FIG. 2A. In some embodiments, two elements are adjacent to each other if they are directly adjacent to each other.Memory cell array 202 includes F layers (e.g., layers 0, 1, 2,..., F-1) of memory cells. In FIGS. 7A-7B, select gate array 204 is positioned between layer 1 and layer 2 of memory cell array 202. Other layer configurations of memory circuit 700 or select gate array 204 are within the scope of the present disclosure. Select gate array 204 may be positioned between other layers of memory cell array 202 and is within the scope of the present disclosure. For example, in some embodiments, select gate array 204 is positioned between layer F- 1 and layer F- 2 of memory cell array 202.Memory cell array 202 is divided into memory cell array 702a (memory cell array 202[0], 202[1]) positioned below select gate array 204 and memory cell array 702b (memory cell array 202[2], 202[F-1]) positioned above select gate array 204.By positioning select gate array 204 between layer 1 and layer 2 of memory cell array 202, each column of global bit lines GBL is directly coupled to drains / sources of corresponding transistors 210 (memory cells MC) that are positioned on layers of memory cell array 202 below select gate array 204 within the column of memory cells. For example, global bit line GBL[0] within column 0 is directly coupled to each / each drain / source of transistors 210[0,0,0] and 210[0,0,1] within column 0 of memory cell array 202.By positioning select gate array 204 between layer 1 and layer 2 of memory cell array 202, each column of local bit lines BL is directly coupled to sources / drains of corresponding transistors 210 (memory cells MC) that are positioned on layers of memory cell array 202 below select gate array 204 within the column of memory cells. For example, a local bit line BL[o] within column 0 is directly coupled to each / each source / drain of transistors 210[0,0,0] and 210[0,0,1] within column 0 of memory cell array 202.Within each column, the source / drain of each respective selection transistor 212 is coupled through the respective local bit line BL to sources / drains of each respective memory cell positioned on layers of memory cell array 202 below selection transistor 212. For example, as shown in FIG. 7B, in row 0 and column 0, the source / drain of corresponding select transistor 212[0,0] positioned over layers 0 and 1 of memory cell array 202 is coupled to the source / drains of memory cells 210[0,0,0] and 210[0,0,1] of corresponding layers 0 and 1 of memory cell array 202 in column 750 (in FIG. 7B ) by local bit line BL[0,0].By positioning select gate array 204 between layer 1 and layer 2 of memory cell array 202, each select transistor 212 of SG array 204 electrically couples the corresponding local bit line BL and the corresponding local source line SL to each other. For example, select transistor 212[0,0] of row 0 and column 0 of memory circuit 700 electrically couples local bit line BL[0] and local source line SL[0] to each other.By positioning select gate array 204 between layer 1 and layer 2 of memory cell array 202, each column of global source lines GSL is directly coupled to source / drains of corresponding transistors 210 (memory cells MC) positioned on layers of memory cell array 202 via select gate array 204 within the column of memory cells. For example, as shown in FIG. 7B, global source line GSL[o] within column 0 is directly coupled to each / each source / drain of transistors 210[0,0,F-2] and 210[0,0,F-1] within column 0 of memory cell array 202.By positioning select gate array 204 between layer 1 and layer 2 of memory cell array 202, each column of local source lines SL is directly coupled to drains / sources of corresponding transistors 210 (memory cells MC) that are positioned on layers of memory cell array 202 via select gate array 204 within the column of memory cells. For example, as shown in FIG. 7B, local source line SL[o] within column 0 is directly coupled to each / each drain / source of transistors 210[0,0,F-2] and 210[0,0,F-1] within column 0 of memory cell array 202.Within each pillar, the drain / source of each respective selection transistor 212 is coupled to drains / sources of each respective memory cell positioned on layers of memory cell array 202 via selection transistor 212 through the respective local source line SL. For example, as shown in FIG. 7B, in row 0 and column 0, the drain / source of the corresponding selection transistor 212[0,0] positioned under layers F-2 and F-1 of memory cell array 202 is coupled to the drain / sources of memory cells 210[0,0,F-2] and 210[0,0,F-1] of corresponding layers F-2 and F-1 of memory cell array 202 in column 750 (shown in FIG. 7B ) through local source line SL[0,0].By including select gate array 204 in memory circuit 700, memory circuit 700 may reduce loading by local bitline BL / local source line SL of disabled select transistors, resulting in the advantages discussed above with respect to memory circuit 200.FIG. 8 is a diagram of a memory cell device 800 in accordance with some embodiments.Memory circuit 800 is a variation of memory circuit 200 of FIGS. 2A-2C. For example, select gate arrays SG[0,0] and SG*[0,0] of FIG. 2B have been replaced with corresponding transfer gates TG[0,0] and TG*[0,0] in FIG. 8.Memory circuit 800 corresponds to an embodiment of pillar 250 of memory circuit 200, and a similar detailed description will be omitted. Memory circuit 800 includes pillar 850, which is simplified for ease of illustration. Column 850 is a variation of column 250 of FIGS. 2B-2C. While FIG. 8 shows a single column of memory circuit 800, the features of memory circuit 800 are applicable to each column in memory circuit 100- 700 and are not shown for brevity. For example, transfer gate TG[0,0] replaces each select gate in select gate array 104 or 204 and transfer gate TG*[o,o] replaces each select gate in select gate array 106 or 206, and a similar detailed description is omitted. In other words, transfer gate TG[0,0] is part of a first transfer gate array 802, the select gate array 104 or 204 is replaced, and transfer gate TG*[0,0] is part of a second transfer gate array 804, the select gate array 106 or 206 is replaced, and a similar detailed description is omitted. Each transfer gate of the first transfer gate array 802 is configured to selectively couple the corresponding global bit line and the corresponding column of local bit lines together. Each transmission gate of the second transmission gate array 804 is configured to selectively couple the corresponding global source line and the corresponding column of local source lines together.Column 850 includes one or more features of memory circuit 200 of FIG. 2A for column 0 and row 0 of memory circuit 200, and a similar detailed description is omitted.Transfer gate TG[0,0] includes select transistor 212[0,0] and select transistor 812[0,0]. Selection transistor 812[0,0] is similar to selection transistor 212[0,0], and a similar detailed description is omitted.Each transfer gate TG[0,0], TG[1,0],..., TG[C-1,0],..., TG[0,M-1], SG[1,M-1],..., TG[C-1,M-1] from the first transfer gate array 802 includes a corresponding selection transistor 212[0,0], 212[1,0],..., 212[C-1,0],..., 212[0,M-1], 212[1,M-1],..., 212[C-1,M-1] and a corresponding selection transistor 812[0,0], 812[1,0],..., 812[C-1,0],..., 812[0,M-1], 212[1,M-1],...., 812[C-1, M-1] (collectively referred to as "selection transistors 812"). Selection transistors 812 are referred to herein by 8128[column number, row number]. For ease of illustration, memory circuit 800 includes a column of selection transistors 812.Each column of selection transistors 212 and 812 is configured to selectively couple the corresponding global bit line and the corresponding column of local bit lines together. Column 0 of selection transistors 212[0,0], 212[0,1],..., 212[0,M-1] and selection transistors 812[0,0], 812[0,1],..., 812[0,M-1] (not shown) are configured to selectively couple the corresponding global bit line GBL[o] and the corresponding column of local bit lines BL[0,0], BL[0,1],..., BL[0,M-1] to each other.All selection transistors 812 are p-transistors. In some embodiments, all selection transistors 812 are PMOS transistors. Other types of transistors are within the scope of the present disclosure. In some embodiments, all selection transistors 812 are n-transistors. In some embodiments, all selection transistors 812 are NMOS transistors.Each selection transistor 812 has a gate coupled to a corresponding selection line SGB, a drain / source(s) coupled to at least one corresponding global bit line GBL and a / one corresponding drain / source of selection transistor 212, and a source / drain(s) coupled to at least one corresponding bit line BL and a / one corresponding source / drain of selection transistor 212.In column 850, the / source / drain of the corresponding select transistor 212[0,0] and the / source / drain of the corresponding select transistor 812[0,0] are coupled together in row 0 and column 0 and are further coupled to the drains of memory cells 210[0,0,0], 210[0,0,1],..., 210[0,0,F-1] in row 0 and column 0 of each layer of memory cell array 202 in column 250 by local bit line BL[0,0].In column 850, the drain / source of the corresponding select transistor 212[0,0] and the drain / source of the corresponding select transistor 812[0,0] are coupled together in row 0 and column o and further coupled to the global bit line GBL[o].Each gate of a corresponding row of selection transistors 812 is electrically coupled to a corresponding selection line SGB[0], SGB[1],..., SGB[M-1] (collectively referred to as "selection lines SGB"] and is configured to receive a corresponding selection line signal SLSB[0], SLSB[1],..., SLSB[M-1] (collectively referred to as "selection line signal SLSB"). Each selection transistor of selection transistors 812 is activated or deactivated in response to the corresponding selection line signal SLSB[0], SLSB[1],..., SLSB[M-1] received on the corresponding selection line SGB[0], SGB[1],..., SGB[M-1]. In some embodiments, select line signals SLSB are reversed from select line signals SLS and vice versa.If enabled, select transistors 212[0,0] and 812[0,0] electrically couple the corresponding global bit line and the corresponding column of local bit lines. If disabled, select transistors 212[0,0] and 812[0,0] electrically decouple the corresponding global bit line and corresponding column of local bit lines. In some embodiments, one row of selection transistors 212 and 812 is enabled for a period of time (between time T 1-T 2 in FIG. 3C ) and the other rows of selection transistors 212 and 812 are disabled for the same period of time (between time T 1-T 2 in FIG. 3C ).Transfer gate TG*[o,o] includes select transistor 214[0,0] and select transistor 814[0,0]. Select transistor 814[0,0] is similar to select transistor 214[0,0] and a similar detailed description is omitted.Each transfer gate TG*[0,0], TG*[1,0],..., TG*[C-1,0],..., TG*[0,M-1], SG[1,M-1],..., TG*[C-1,M-1] from the second transfer gate array 804 includes a corresponding selection transistor 214[0,0], 214[1,0],..., 214[C-1,0],..., 214[0,M-1], 214[1,M-1],..., 214[C-1,M-1] and a corresponding selection transistor 814[0,0], 814[1,0],..., 814[C-1,0],..., 814[0,M-1], 214[1,M-1],..., 814[C-1,M-1] (collectively referred to as "selection transistors 814"). Select transistors 813 are referred to herein by 814 [column number, row number]. For ease of illustration, memory circuit 800 includes a column of selection transistors 814.Each column of selection transistors 214 and 814 is configured to couple the corresponding global source line and the corresponding column of local source lines together. Column 0 of selection transistors 214[0,0], 214[0,1],..., 214[0,M-1] and selection transistors 814[0,0], 814[0,1],..., 814[0,M-1] (not shown) are configured to selectively couple the corresponding global source line GSL[0] and the corresponding column of local source lines SL[0,0], SL[0,1],..., SL[0,M-1].All selection transistors 814 are p-transistors. In some embodiments, all selection transistors 814 are PMOS transistors. Other types of transistors are within the scope of the present disclosure. In some embodiments, all selection transistors 814 are n-transistors. In some embodiments, all selection transistors 814 are NMOS transistors.Each selection transistor 814 has a gate coupled to a corresponding selection line SGB, a drain / source(s) coupled to at least one corresponding global source line GSL and a / one corresponding drain / source of selection transistor 214, and a source / drain(s) coupled to at least one corresponding source line SL and a / one corresponding source / drain of selection transistor 214.In column 850, the / source / drain of the corresponding select transistor 214[0,0] and the / source / drain of the corresponding select transistor 814[0,0] are coupled together in row 0 and column 0 and are further coupled to the sources of memory cells 210[0,0,0], 210[0,0,1],..., 210[0,0,F-1] in row 0 and column 0 of each layer of memory cell array 202 in column 250 by local source line SL[0,0].In column 850, the drain / source of the corresponding select transistor 214[0,0] and the drain / source of the corresponding select transistor 814[0,0] are coupled together in row 0 and column o and are further coupled to the global source line GSL[0].Each gate of a respective row of selection transistors 814 is electrically coupled to a respective selection line SGB[0], SGB[1],..., SGB[M-1] of selection lines SGB and is configured to receive a respective selection line signal SLSB[0], SLSB[1],..., SLSB[M-1] of selection line signals SLSB. Each selection transistor of selection transistors 814 is activated or deactivated in response to the corresponding selection line signal SLSB[0], SLSB[1],..., SLSB[M-1] received on the corresponding selection line SGB[0], SGB[1],..., SGB[M-1]. In some embodiments, select line signals SLSB received from transmission gates 814 are different from the select line signals received from transmission gates 812.When activated, select transistors 214[0,0] and 814[0,0] electrically couple the corresponding global source line and the corresponding column of local source lines. If disabled, select transistors 14[0,0] and 814[0,0] electrically decouple the corresponding global source line and column of local source lines. In some embodiments, one row of selection transistors 214 and 814 is enabled for a period of time (between time T 1-T 2 in FIG. 3C ) and the other rows of selection transistors 214 and 814 are disabled for the same period of time (between time T 1-T 2 in FIG. 3C ).FIG. 9 is a diagram of a memory cell device 900 in accordance with some embodiments. Memory cell device 900 is usable as part or all of one or more memory cells of memory cell array 102 or 202, as discussed above with respect to FIGS. 1 or 2A-2C.In some embodiments, the memory cell device is a dual gate thin film transistor (DG TFT). Other types of transistors are within the scope of the present disclosure.In some embodiments, memory cell device 900 is usable as memory cell MC[0,0,0] in layer 0 of memory cell array 202 and memory cell MC[0,0,1] in layer 1 of memory cell array 202. In some embodiments, memory cell device 900 includes a first gate (e.g., gate layer 902) corresponding to the gate of transistor 210[0,0,0] in layer 0 of memory cell array 202, and a second gate (e.g., gate layer 918) corresponding to the gate of transistor 210[0,0,1] in layer 1 of memory cell array 202. Memory cell device 900 may be usable as other memory cells that are adjacent layers of memory cell array 202.Memory cell device 900 includes a gate layer 902. In some embodiments, gate layer 902 includes a conductive material. In some embodiments, gate layer 902 includes polysilicon, LTPS, a-Si TFT, IGZO, or semiconductor material, or combinations thereof, or the like. In some embodiments, gate layer 902 corresponds to wordline WL. In some embodiments, word line WL includes polysilicon, LTPS, a-Si TFT, IGZO, or semiconductor material, or combinations thereof, or the like.Memory cell device 900 further includes an insulating layer 904 over gate layer 902 and a gate layer 918 over insulating layer 916. In some embodiments, insulating layer 904 includes a ferroelectric base layer 906a and insulating layer 916 includes a ferroelectric base layer 916a. In some embodiments, at least one insulating layer 904 or 916 includes SiO, SiO 2 high-k oxide, or combinations thereof, or the like. In some embodiments, at least one of insulating layers 904 and 916 includes a gate oxide or the like.The ferroelectric base layer 904a is under a channel layer 906a. The ferroelectric base layer 916a is over the channel layer 914a. In some embodiments, at least ferroelectric base layer 904 aor 916 aincludes perovskite, SBT, PZT, HfZrO, HfO, or combinations thereof, or the like. In some embodiments, at least one ferroelectric base layer 904a or 916a is a layer having ferroelectric properties. In some embodiments, at least one of insulating layer 904 and 916 is a charge trapping base layer having charge trapping properties.Memory cell device 900 further includes a source 908 and a drain 910 on ferroelectric base layer 904 a. The source 908 and the drain 910 are under ferroelectric base layer 916 a. In some embodiments, at least one of source 908 and drain 910 includes a conductive material. In some embodiments, a conductive material includes doped polysilicon, TiN, W, Cu, Co, Ru, or combinations thereof, or the like.In some embodiments, source 908 corresponds to the source of transistor 210[0,0,0] in layer 0 of memory cell array 202 and the source of transistor 210[0,0,1] in layer 1 of memory cell array 202. In some embodiments, drain 910 corresponds to the drain of transistor 210[0,0,0] in layer 0 of memory cell array 202 and the drain of transistor 210[0,0,1] in layer 1 of memory cell array 202. In some embodiments, bit line BL is coupled to drain 910 and source line SL is coupled to source 908. In some embodiments, bit line BL or source line SL includes doped polysilicon, TiN, W, Cu, Co, Ru, or combinations thereof, or the like.Memory cell device 900 further includes a channel 906 and a channel 914. In some embodiments, at least one channel 906 or 914 extends between the source 908 and the drain 910. In some embodiments, at least one of channels 906 and 914 includes a conductive material. In some embodiments, at least one channel 906 or 914 includes polysilicon, LTPS, a-Si TFT, IGZO, or semiconductor material, or combinations thereof, or the like. In some embodiments, insulating layer 904 is on gate 902, channel 906 is on insulating layer 904, source 908 and drain 910 are on channel 906, channel 914 is on source 908 and drain 910, insulating layer 916 is on channel 914, and gate 918 is on insulating layer 916.Memory cell device 900 further includes an insulating layer 912 between source 908 and drain 910. In some embodiments, memory cell device 900 is a 2-bit memory cell having a common source and drain. In some embodiments, insulating layer 912 includes SiO, SiO 2 or combinations thereof, or the like.In some embodiments, gate layer 918 is over insulating layer 916. In some embodiments, gate layer 918 includes a conductive material. In some embodiments, gate layer 918 includes polysilicon, LTPS, a-Si TFT, IGZO, or semiconductor material, or combinations thereof, or the like. In some embodiments, gate layer 918 corresponds to wordline WL. In some embodiments, one or more layers of memory cell device 900 are not included. In some embodiments, one or more layers of memory cell device 900 are divided into multiple layers.By included in memory circuit 100- 800 discussed above with respect to FIGS. 1-8, memory cell device 900 operates to achieve the advantages discussed above with respect to memory circuit 100- 800.METHODSFIG. 10 is a flow diagram of a method of operating a circuit in accordance with some embodiments.In some embodiments, FIG. 10 is a flow diagram of a method of operating the memory circuit of FIGS. 1-9. It is understood that additional operations may be performed before, during, and / or after the method 1000 depicted in FIG. 10, and that some other operations may be described only briefly herein. It is understood that method 1000 utilizes features of one or more of circuits 100, 200, 300A, 400, 500, 600, 700, 800, or 900 or waveform 300B of FIG. 3B.In operation 1002 of method 1000, a first row of selection transistors is activated. In some embodiments, operation 1002 includes at least receiving, by a first selection transistor in the first row of selection transistors, a first selection line signal and turning on the first selection transistor in response to the first selection line signal, thereby electrically coupling a first local bit line and a global bit line together.In some embodiments, the first row of selection transistors of method 1000 includes row 0. In some embodiments, the first select transistor of method 1000 includes select transistor 212[0,0]. In some embodiments, the first select line signal of method 1000 includes select line signal SLS[0]. In some embodiments, the first local bit line of method 1000 includes bit line BL[0,0]. In some embodiments, the global bitline of method 1000 includes global bitline BL[0].In operation 1004 of method 1000, a second row of selection transistors is activated. In some embodiments, operation 1004 includes at least receiving, by a second selection transistor in the second row of selection transistors, a second selection line signal and turning on the second selection transistor in response to the second selection line signal, thereby electrically coupling a first local source line and a global source line together.In some embodiments, the second row of selection transistors of method 1000 includes the row of selection transistors 214 in row 0. In some embodiments, the second select transistor of method 1000 includes select transistor 214[0,0]. In some embodiments, the second select line signal of method 1000 includes select line signal SLS*[0]. In some embodiments, the first local source line of method 1000 includes source line SL[0,0]. In some embodiments, the global source line of method 1000 includes global source line SL[0].In operation 1006 of method 1000, a third row of selection transistors is disabled. In some embodiments, operation 1006 includes at least receiving, by a third selection transistor in the third row of selection transistors, a third selection line signal and turning off the third selection transistor in response to the third selection line signal, thereby electrically decoupling a second local bit line and the global bit line from each other.In some embodiments, the third row of selection transistors of method 1000 includes row 1. In some embodiments, the third selection transistor of method 1000 includes selection transistor 212[ 0, 1]. In some embodiments, the third select line signal of method 1000 includes select line signal SLS[ 1]. In some embodiments, the second local bit line of method 1000 includes bit line BL[o,1].In operation 1008 of method 1000, a fourth row of selection transistors is deactivated. In some embodiments, operation 1008 includes at least receiving, by a fourth selection transistor in the fourth row of selection transistors, a fourth selection line signal and turning off the fourth selection transistor in response to the fourth selection line signal, thereby electrically decoupling a second local source line and the global source line from each other.In some embodiments, the fourth row of selection transistors of method 1000 includes the row of selection transistors 214 in row 1. In some embodiments, the fourth selection transistor of method 1000 includes selection transistor 214[ 0, 1]. In some embodiments, the fourth select line signal of method 1000 includes select line signal SLS*[ 1]. In some embodiments, the second local source line of method 1000 includes source line SL[o,1].In operation 1010 of method 1000, a first row of memory cells is activated in response to a first wordline signal. In some embodiments, operation 1010 includes at least receiving, by a first memory cell in the first row of memory cells, the first wordline signal and turning on the first memory cell in response to the first wordline signal.In some embodiments, the first row of memory cells of method 1000 includes memory cells in row 0. In some embodiments, the first memory cell of method 1000 includes memory cell 210[0,0,0]. In some embodiments, the first wordline signal of method 1000 includes wordline signal WL[ 0]_FL[ 0].In operation 1012 of method 1000, a second row of memory cells is disabled in response to a second wordline signal. In some embodiments, operation 1012 includes at least receiving, by a second memory cell n of the second row of memory cells, the second wordline signal and turning off the second memory cell in response to the second wordline signal.In some embodiments, the second row of memory cells of method 1000 includes memory cells in row 1. In some embodiments, the second memory cell of method 1000 includes at least memory cell 210[0,1,0]. In some embodiments, the second wordline signal of method 1000 includes wordline signal WL[ 1]_FL[o].In operation 1014 of method 1000, the first row of selection transistors is deactivated. In some embodiments, operation 1014 includes turning off the first selection transistor in response to the first selection line signal, thereby electrically decoupling the first local bit line and the global bit line from each other.In operation 1016 of method 1000, the second row of selection transistors is disabled. In some embodiments, operation 1016 includes turning off the second selection transistor in response to the second selection line signal, thereby electrically decoupling the first local source line and the global source line from each other.In operation 1018 of method 1000, the first row of memory cells is deactivated in response to the first wordline signal.Operating method 1000, the memory circuit operates to achieve the advantages discussed above with respect to memory circuit 100- 800 and memory cell 900. While method 1000 has been discussed above with respect to FIGS. 1, 2A-2C, and 3A-3B, it is understood that method 1000 utilizes the features of one or more of FIGS. 4A-7B, 8, and 9.While method 1000 has been described above with respect to rows 0-1, column o, and layers 0 and 1 of memory cell array 202, it is understood that method 1000 applies to each row, column, and layer of memory cell array 202.In some embodiments, one or more of the operations of methods 1000 are not performed. Moreover, the different PMOS or NMOS transistors shown in FIGS. 2A-0 are doped with a particular doping (e.g., N or P) for illustrative purposes. Embodiments of the disclosure are limited to a particular transistor type and one or more of the PMOS or NMOS transistors shown in FIGS. 2A-9 may be replaced with a corresponding transistor of a different transistor / dopant type. Similarly, the low or high logic value of different signals used in the description above is illustrative. Embodiments of the disclosure are not limited to a particular logic value when a signal is enabled and / or disabled. Different logical values are to be selected within the scope of different embodiments. Different numbers of transistors in FIGS. 2A-10 are to be selected within the scope of the different embodiments.One skilled in the art will readily appreciate that one or more of the disclosed embodiments may satisfy one or more of the advantages provided. Having read the foregoing description, one skilled in the art will be able to effect various changes, substitutions of equivalents, and various other embodiments as broadly discussed herein.One aspect of this description relates to a memory circuit. The memory circuit includes a first memory cell on a first layer, a second memory cell on a second layer different from the first layer, a first selection transistor on a third layer different from the first layer and the second layer, a first bit line, a second bit line, and a first source line. The first bit line extends in a first direction and is coupled to the first memory cell, the second memory cell, and the first selection transistor. The second bit line extends in the first direction and is coupled to the first selection transistor. The first source line extends in the first direction, is coupled to the first memory cell and the second memory cell, and is separated from the first bit line in a second direction different from the first direction. In some embodiments, the memory circuit further includes a first selection line extending in the second direction and coupled to the first selection transistor. In some embodiments, the memory circuit further includes a first word line extending in the second direction, separated from the first select line in the first direction, and coupled to the first memory cell. In some embodiments, the memory circuit further includes a second word line extending in the second direction, separated from the first word line in the first direction, and coupled to the second memory cell. In some embodiments, the first selection transistor includes a first gate, a first drain, and a first source, the first gate coupled to the first selection line, the first drain coupled to the first bit line, and the first source coupled to the second bit line. In some embodiments, the first memory cell includes a first transistor having a second gate, a second drain, and a second source, the second gate coupled to the first word line, the second drain coupled to the first drain through the first bit line, and the second source coupled to the first source line. In some embodiments, the second memory cell includes a second transistor having a third gate, a third drain, and a third source, the third gate coupled to the second word line, the third drain coupled to the first drain and the second drain through the first bit line, and the third source coupled to the second source through the first source line. In some embodiments, the memory circuit further includes a second selection transistor on a fourth layer different from the first layer, the second layer, and the third layer, wherein the first source line is further coupled to the second selection transistor. In some embodiments, the memory circuit further includes a second selection line extending in the second direction and coupled to the second selection transistor. In some embodiments, the memory circuit further includes a second source line extending in the first direction and coupled to the second selection transistor. In some embodiments, the second selection transistor includes a fourth gate, a fourth drain, and a fourth source, the fourth gate being coupled to the second selection line, the fourth drain being coupled to the second source line, and the fourth source being coupled to the second source and the third source through the first source line. In some embodiments, the memory circuit further includes a second selection transistor on a fourth layer different from the first layer, the second layer, and the third layer, wherein the first source line is further coupled to the second selection transistor. In some embodiments, the memory circuit further includes a second source line extending in the first direction and coupled to the second selection transistor. In some embodiments, the memory circuit further includes a third memory cell on the first layer and is separated from the first memory cell in a third direction different from the first direction and the second direction. In some embodiments, the memory circuit further includes a fourth memory cell on the second layer and is separated from the second memory cell in the third direction. In some embodiments, the memory circuit further includes a third selection transistor on the third layer, is separated from the first selection transistor in the third direction, and is coupled to the second bit line. In some embodiments, the memory circuit further includes a fourth selection transistor on the fourth layer and separated from the second selection transistor in the third direction and coupled to the second source line. In some embodiments, the memory circuit further includes a third bit line extending in the first direction, coupled to the third memory cell, the fourth memory cell, and the third selection transistor, and separated from the first bit line in the third direction. In some embodiments, the memory circuit further includes a third source line extending in the first direction, coupled to the third memory cell, the fourth memory cell, and the fourth selection transistor, and separated from the first source line in the third direction.Another aspect of this description relates to a memory circuit. The memory circuit includes a first memory cell array on a first layer, a second memory cell array on a second layer different from the first layer, a first selection transistor array on a third layer different from the first layer and the second layer, a second selection transistor array on a fourth layer different from the first layer, the second layer, and the third layer, a first set of bit lines, a second set of bit lines, a first set of source lines, and a second set of source lines. In some embodiments, the first set of bit lines extending in a first direction are coupled to the first memory cell array, the second memory cell array, and the first selection transistor array. In some embodiments, the second set of bit lines extends in the first direction and is coupled to the first memory cell array and the second memory cell array through the first select transistor array. In some embodiments, the first set of source lines extends in the first direction, is coupled to the first memory cell array, the second memory cell array, and the second selection transistor array, and is separated from the first set of bit lines in a second direction different from the first direction. In some embodiments, the second set of source lines extends in the first direction and is coupled to the first memory cell array and the second memory cell array through the second selection transistor array. In some embodiments, the first selection transistor array includes a first selection line extending in the second direction and a first selection transistor including a first gate, a first drain, and a first source, the first gate coupled to the first selection line, the first drain coupled to a first bit line of the first set of bit lines, and the first source coupled to a first bit line of the second set of bit lines. In some embodiments, the first memory cell array includes a first word line extending in the second direction and a first n-transistor including a second gate, a second drain, and a second source, the second gate coupled to the first word line, the second drain coupled to the first drain through the first bit line of the first set of bit lines, and the second source coupled to a first source line of the first set of source lines. In some embodiments, the second memory cell array includes a second word line extending in the second direction and separated from the first word line in the first direction. In some embodiments, the second memory cell array includes a second n-transistor having a third gate, a third drain, and a third source, the third gate coupled to the second word line, the third drain coupled to the first drain and the second drain through the first bit line of the first set of bit lines, and the third source coupled to the second source through the first source line of the first set of source lines. In some embodiments, the second selection transistor array includes a second selection line extending in the second direction and separated from the first selection line in the first direction. In some embodiments, the second selection transistor array further includes a second selection transistor having a fourth gate, a fourth drain, and a fourth source, the fourth gate coupled to the second selection line, the fourth drain coupled to a first source line of the second set of source lines, and the fourth source coupled to the second source and the third source through the first source line of the first set of source lines. In some embodiments, the memory circuit further includes a first select line driver coupled to the first select line and the second select line. In some embodiments, the memory circuit further includes a first word line extending in the second direction and coupled to a first row of memory cells in the first memory cell array. In some embodiments, the memory circuit further includes a second word line extending in the second direction and coupled to a second row of memory cells in the first memory cell array. In some embodiments, the memory circuit further includes a third word line extending in the second direction and coupled to a third row of memory cells in the second memory cell array. In some embodiments, the memory circuit further includes a fourth word line extending in the second direction and coupled to a fourth row of memory cells in the second memory cell array. In some embodiments, the memory circuit further includes a first word driver coupled to the first word line and the second word line. In some embodiments, the memory circuit further includes a second word driver coupled to the third word line and the fourth word line. In some embodiments, the first layer is over the second layer, the second layer is over the third layer, and the third layer is over the fourth layer.Yet another aspect of the description relates to a method of operating a memory circuit. The method includes activating a first row of selection transistors, deactivating a second row of selection transistors, activating a first row of memory cells in response to a first wordline signal, and deactivating a second row of memory cells in response to a second wordline signal. In some embodiments, activating the first row of selection transistors includes turning on a first selection transistor in the first row of selection transistors in response to a first selection line signal, thereby electrically coupling a first local bit line and a global bit line together. In some embodiments, disabling the second row of selection transistors includes turning off a second selection transistor in the second row of selection transistors in response to a second selection line signal, thereby electrically decoupling a second local bit line and the global bit line from each other. In some embodiments, the method further comprises activating a third row of selection transistors, wherein activating the third row of selection transistors comprises turning on a third selection transistor in the third row of selection transistors in response to a third selection line signal, thereby electrically coupling a first local source line and a global source line together. In some embodiments, the method further comprises activating a fourth row of selection transistors, wherein deactivating the fourth row of selection transistors comprises turning off a fourth selection transistor in the fourth row of selection transistors in response to a fourth selection line signal, thereby electrically decoupling a second local source line and the global source line from each other. In some embodiments, the method further comprises disabling the first row of selection transistors, wherein disabling the first row of selection transistors comprises turning off the first selection transistor in response to the first selection line signal, thereby electrically decoupling the first local bit line and the global bit line from each other. In some embodiments, the method further comprises disabling the third row of selection transistors, wherein disabling the third row of selection transistors comprises turning off the third selection transistor in response to the third selection line signal, thereby electrically decoupling the first local source line and the global source line from each other.

Claims

A memory circuit (100) comprising: a first memory cell array (102) on a first layer (F); a second memory cell array on a second layer (F) different from the first layer (F); a first selection transistor array (104) on a third layer (F) different from the first layer (F) and the second layer (F); a second selection transistor array (106) on a fourth layer (F) different from the first layer (F), the second layer (F) and the third layer (F); a first set of bit lines (BL) extending in a first direction (Z) coupled to the first memory cell array (102), the second memory cell array and the first selection transistor array (104); a second set of bit lines (BL) extending in the first direction (Z) and coupled to the first memory cell array (102) and the second memory cell array through the first selection transistor array (104); a first set of source lines (SL) extending in the first direction (Z) coupled to the first memory cell array (102), the second memory cell array, and the second selection transistor array (106) and separated from the first set of bit lines (BL) in a second direction (X) different from the first direction (Z); and a second set of source lines (SL) extending in the first direction (Z) and coupled to the first memory cell array (102) and the second memory cell array through the second selection transistor array (106), the first selection transistor array (104) comprising: a first selection line (SG) extending in the second direction (X); and a first selection transistor (212) having a first gate, a first drain, and a first source, the first gate coupled to the first selection line (SG), the first drain coupled to a first bit line (BL) of the first set of bit lines (BL), and the first source coupled to a first bit line (BL) of the second set of bit lines (BL), the first memory cell array (102) comprising: a first word line (WL) extending in the second direction (X); and a first n-type transistor having a second gate, a second drain, and a second source, the second gate coupled to the first word line (WL), the second drain coupled to the first drain through the first bit line (BL) of the first set of bit lines (BL), and the second source coupled to a first source line (SL) of the first set of source lines (SL), and wherein the second memory cell array includes: a second word line (WL) extending in the second direction and separated from the first word line in the first direction; and a second n-type transistor having a third gate, a third drain, and a third source, wherein the third gate is coupled to the second word line (WL), the third drain is coupled to the first drain and the second drain through the first bit line (BL) of the first set of bit lines (BL), and the third source is coupled to the second source through the first source line (SL) of the first set of source lines (SL), and wherein the second selection transistor array (106) comprises: a second selection line (SG) extending in the second direction (X) and separated from the first selection line (SG) in the first direction (Z); and a second selection transistor (214) having a fourth gate, a fourth drain and a fourth source, the fourth gate being coupled to the second selection line (SG), the fourth drain being coupled to a first source line (SL) of the second set of source lines (SL) and the fourth source being coupled to the second source and the third source through the first source line (SL) of the first set of source lines (SL), the first layer (F) being over the second layer (F), the second layer (F) being over the third layer (F) and the third layer (F) being over the fourth layer (F).The memory circuit (100) of claim 1, further comprising: a first select line driver (404) coupled to the first select line (SG) and the second select line (SG).The memory circuit (100) of claim 1 or 2, further comprising: a first word line (WL) extending in the second direction (X) and coupled to a first row of memory cells (MC) in the first memory cell array (102); a second word line (WL) extending in the second direction (X) and coupled to a second row of memory cells (MC) in the first memory cell array (102); a third word line (WL) extending in the second direction (X) and coupled to a third row of memory cells (ML) in the second memory cell array; a fourth word line (WL) extending in the second direction (X) and coupled to a fourth row of memory cells (MC) in the second memory cell array; a first word line driver coupled to the first word line (WL) and the second word line (WL); and a second word line driver coupled to the third word line (WL) and the fourth word line (WL).The memory circuit (100) according to claim 1 or claim 2 combined with claim 3, comprising a plurality of selection line drivers (404), wherein the respective selection line driver (404) is configured to generate a selection line signal (SLS).The memory circuit (100) of claim 4, wherein each select line driver (404) is coupled to a pair of select gates within each corresponding row of the memory circuit (100).The memory circuit (100) of claim 4 or 5, comprising at least one predecoder circuit (410) coupled to a select line driver (404).The memory circuit (100) of claim 6, wherein the respective predecoder circuit (410) is configured to predecode portions of addresses in the memory cell array (102) identifying a row of memory cells in the memory cell array (102).The memory circuit (100) of claim 7, comprising at least one wordline driver circuit (412), wherein the respective wordline driver circuit (412) is coupled to a predecoder circuit (410).The memory circuit (100) of claim 8, wherein the respective wordline driver circuit (412) is configured to generate wordline signals on corresponding wordlines (WL).The memory circuit (100) of claim 8 or 9, wherein wordline driver circuits (412) of each row of memory cells in the same layer are shared by the memory cell array (102).

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