Transistor arrays and their manufacturing methods, memory and their manufacturing methods

Abstract

This invention provides a transistor array and its manufacturing method. The transistor array includes: a plurality of U-shaped active pillars with two branches arranged along a first direction and a second direction, respectively; each U-shaped active pillar includes: a channel region; a source at a first end of the channel region; a drain at a second end of the channel region, wherein the first end and the second end are opposite ends of the channel region in a third direction, the third direction being perpendicular to the surface of the substrate used to form the transistor array; the plane formed by the first direction and the second direction is perpendicular to the third direction; a plurality of gate structures, each gate structure being located between two adjacent U-shaped active pillars arranged along the first direction; and a plurality of electrically insulated connection portions, each connection portion electrically connecting two adjacent branches of two U-shaped active pillars that are physically in contact with the corresponding gate structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and to, but is not limited to, a transistor array and its manufacturing method, and a memory and its manufacturing method. Background Technology

[0002] Transistors in semiconductor structures are widely used as switching devices or driving devices in electronic devices. For example, transistors can be used in Dynamic Random Access Memory (DRAM) to control each memory cell (storage capacitor).

[0003] In related technologies, the architecture of transistors in semiconductor structures mainly includes planar transistors and buried-channel transistors. However, regardless of whether it is a planar transistor or a buried-channel transistor, its source (S) and drain (D) are located on opposite sides of the gate (G). In this structure, the source and drain occupy different positions, resulting in a larger transistor area. Furthermore, in memory devices, the source and drain of the transistor are connected to different structures after formation. When the source and drain are located on opposite sides of the gate, it easily leads to complex internal circuit wiring in the semiconductor device and increased manufacturing difficulty. Summary of the Invention

[0004] To address the related technical problems, embodiments of the present invention propose a transistor array and its manufacturing method, as well as a memory and its manufacturing method.

[0005] This invention provides a transistor array, comprising:

[0006] A plurality of U-shaped active posts, each having two branches, are arranged along a first direction and a second direction respectively; wherein each of the U-shaped active posts includes:

[0007] Channel area;

[0008] The source electrode is located at the first end of the channel region;

[0009] The drain is located at the second end of the channel region, wherein the first end and the second end are the two opposite ends of the channel region in a third direction, which is perpendicular to the surface of the substrate used to form the transistor array; the plane formed by the first direction and the second direction is perpendicular to the third direction.

[0010] Multiple gate structures, each gate structure being located between two adjacent U-shaped active pillars arranged along a first direction; and,

[0011] Multiple electrically insulated connection portions, each of which electrically connects two adjacent branches of two U-shaped active pillars that are in physical contact with the corresponding gate structure.

[0012] In the above scheme, each of the gate structures includes: a gate oxide layer, a gate, and a first isolation layer; wherein,

[0013] The gate oxide layer at least covers the two sidewalls of two adjacent U-shaped active pillars arranged along the first direction and disposed opposite each other.

[0014] The gate is located between the gate oxide layers of two adjacent U-shaped active pillars arranged along the first direction; the gates of each row of U-shaped active pillars arranged along the second direction are physically connected to each other.

[0015] The first isolation layer is located between the gate and the connection portion.

[0016] In the above scheme, each of the gate structures further includes a second isolation layer, which is located at the other end of the gate structure opposite to the first isolation layer in a third direction.

[0017] In the above scheme, the angle between the first direction and the second direction ranges from 0 to 90 degrees.

[0018] This invention also provides a memory, comprising:

[0019] In any of the above solutions, the transistor array has multiple gates arranged in parallel along a first direction for receiving word line voltage and controlling the transistors to be turned on or off by the word line voltage;

[0020] Multiple memory cells, each of which is connected to the source or drain of a transistor in the transistor array; and

[0021] Multiple bit lines are arranged side by side along a second direction. Each bit line is connected to the drain or source of a row of transistors arranged along a first direction in the transistor array. The bit lines are used to perform read or write operations on the memory cell when the transistors are turned on. The memory cell and the bit lines are connected to different electrodes.

[0022] In the above scheme, the memory includes: dynamic random access memory, ferroelectric memory, phase change memory, magnetic change memory, or resistive change memory.

[0023] In the above scheme, the memory includes dynamic random access memory, and the memory cell includes a storage capacitor;

[0024] One end of the storage capacitor is connected to the source of a transistor in the transistor array, and the other end of the storage capacitor is grounded. The storage capacitor is used to store the written data.

[0025] In the above scheme, multiple storage capacitors are arranged in a square or hexagonal pattern.

[0026] In the above scheme, the storage capacitor includes cup-shaped, cylindrical, or pillar-shaped capacitors.

[0027] In the above scheme, the memory includes a resistive random access memory (RRAM), and the memory cell includes an adjustable resistor.

[0028] The adjustable resistor is connected between the bit line and the source of a transistor in the transistor array; or, the adjustable resistor is connected between the bit line and the drain of a transistor in the transistor array, and the adjustable resistor is used to adjust the state of the stored data by the bit line voltage provided by the bit line.

[0029] This invention also provides a method for manufacturing a transistor array, comprising:

[0030] Provide substrate;

[0031] Along the first surface of the substrate, a plurality of spaced insulating strips and active strips are formed in the substrate, and the insulating strips and active strips extend along a first direction; the first direction is parallel to the first surface;

[0032] Along the first surface of the substrate, a plurality of spaced-apart gate isolation structures and gate structures are formed in the substrate, both extending along a second direction; the dimension of the gate isolation structure along a third direction is smaller than the dimension of the active strip along the third direction; the dimension of the gate structure along the third direction is equal to the dimension of the active strip along the third direction; the second direction is parallel to the first surface; the third direction is perpendicular to both the first and second directions; the gate isolation structures and gate structures divide each active strip into a plurality of U-shaped active pillars; each active pillar has two branches;

[0033] The source of each transistor is formed at the first end of each of the active pillars;

[0034] The drain of each transistor is formed at the second end of each active pillar, wherein the first end and the second end are opposite ends of the active pillar in a third direction; the active pillar between the source and the drain constitutes the channel region of each transistor.

[0035] Multiple electrically insulated connection portions are formed on the active pillars, and each connection portion electrically connects two adjacent branches of two active pillars that are physically in contact with the corresponding gate structure.

[0036] In the above scheme, forming multiple gate structures in the substrate includes:

[0037] Multiple gate trenches are formed in the substrate; each of the active pillars has an exposed sidewall in the corresponding gate trench;

[0038] A gate oxide layer is formed on at least the exposed sidewall of each of the active pillars;

[0039] A gate is formed in each of the gate trenches in which the gate oxide layer is formed;

[0040] A first isolation layer is formed in each of the gate trenches where the gate oxide layer and the gate are formed, to obtain the gate structure, wherein the surface of the first isolation layer is flush with the surface of the active pillar.

[0041] In the above scheme, forming a gate oxide layer on at least the exposed sidewall of each of the active pillars includes:

[0042] A gate oxide layer is formed on at least the exposed sidewall of each of the U-shaped active pillars by in-situ oxidation.

[0043] The method in the above scheme further includes:

[0044] Prior to forming the gate oxide layer, an isolation material is deposited in each of the gate trenches to form a second isolation layer.

[0045] In the above scheme, forming multiple electrically insulated connection portions on the active post includes:

[0046] A mask layer with multiple openings is formed at one end of each active pillar near the U-shaped opening, each opening exposing two adjacent branches of the two active pillars in physical contact with the corresponding gate structure, as well as the region between the two adjacent branches along a first direction.

[0047] The plurality of connecting portions are formed using the mask layer;

[0048] The method further includes:

[0049] Insulating material is filled between multiple joints.

[0050] In the above scheme, forming the source of each transistor at the first end of each active pillar includes:

[0051] Ion implantation is performed on the end of each active post near the U-shaped opening to form the source of each transistor.

[0052] In the above scheme, forming the drain of each transistor at the second end of each active pillar includes:

[0053] The substrate is thinned from its second surface and along a third direction to expose the second end of the active pillar away from the first surface of the substrate; wherein the second surface is the opposite side to the first surface;

[0054] Ion implantation is performed on the end of each active post away from the U-shaped opening to form the drain of each transistor.

[0055] This invention also provides a method for manufacturing a memory, comprising:

[0056] A transistor array is formed; the transistor array is manufactured by the manufacturing method of the transistor array provided by any one of claims 11 to 17; the transistor array has a plurality of gates arranged in parallel along a first direction for receiving word line voltages and controlling the transistors to be turned on or off by the word line voltages;

[0057] Multiple memory cells are formed, and each memory cell is connected to the source or drain of a transistor in the transistor array.

[0058] Multiple bit lines are formed and arranged in parallel along the second direction. Each bit line is connected to the source or drain of a row of transistors arranged along the first direction in the transistor array. The bit lines are used to perform read or write operations on the memory cell when the transistors are turned on.

[0059] This invention provides a transistor array and a method for manufacturing the same, as well as a memory and a method for manufacturing the same. The transistor array includes: a plurality of U-shaped active pillars, each having two branches, arranged along a first direction and a second direction respectively; each U-shaped active pillar includes: a channel region; a source at a first end of the channel region; and a drain at a second end of the channel region, wherein the first end and the second end are opposite ends of the channel region in a third direction, which is perpendicular to the surface of the substrate used to form the transistor array; a plane formed by the first direction and the second direction is perpendicular to the third direction; a plurality of gate structures, each gate structure located between two adjacent U-shaped active pillars arranged along the first direction; and a plurality of electrically insulated connection portions, each connection portion electrically connecting two adjacent branches of two U-shaped active pillars that are physically in contact with the corresponding gate structure. In various embodiments of the present invention, the source and drain of the transistor extend along the substrate thickness direction, thereby reducing the area occupied by a single transistor in the horizontal direction and increasing the number of transistors that can be placed per unit area, thus improving the transistor density in the transistor array. Simultaneously, the two U-shaped active pillars share a common gate, which can further increase the transistor density in the transistor array. Furthermore, the transistor array provided in this disclosure can be used to form a memory. Since the drain and source of the transistor are located on different sides of the wafer, the different structures connected to the source and drain in the memory can be designed on two separate sides of the wafer, i.e., on two opposite sides of the wafer, thereby simplifying the internal circuit layout of the memory and reducing the manufacturing process difficulty of the memory. Attached Figure Description

[0060] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0061] Figures 1a-1b This is a schematic diagram of the circuit connection of a DRAM transistor in the related technology;

[0062] Figures 1c-1d This is a three-dimensional perspective diagram of the structure of a DRAM transistor in related technologies;

[0063] Figures 1e-1h This is a top-view schematic diagram of the structural formation process of a DRAM transistor in related technologies;

[0064] Figure 2a This is a three-dimensional structural diagram of a transistor array provided in an embodiment of this application;

[0065] Figure 2bA three-dimensional structural diagram of a transistor unit in a transistor array provided for an embodiment of this application;

[0066] Figure 3 A schematic diagram illustrating the implementation flow of a transistor array manufacturing method provided in this application embodiment;

[0067] Figures 4a-4r A cross-sectional schematic diagram of the manufacturing process of a transistor array provided in an embodiment of this application;

[0068] Figures 5a to 5f A schematic diagram of various optional types of longitudinal cross-sections for each transistor provided in embodiments of this application;

[0069] Figures 6a to 6f Cross-sectional schematic diagrams of various optional types of each transistor provided for embodiments of this application;

[0070] Figure 7a A three-dimensional structural diagram of a memory provided in an embodiment of this application;

[0071] Figure 7b A three-dimensional structural diagram of a cell structure in a memory provided in an embodiment of this application;

[0072] Figure 7c This is a three-dimensional structural diagram of another cell structure in a memory provided in an embodiment of this application;

[0073] Figures 8a to 8b A schematic diagram illustrating several different arrangements of storage capacitors provided in the embodiments of this application;

[0074] Figures 9a to 9c Schematic diagrams of several different structural forms of storage capacitors provided in the embodiments of this application;

[0075] Figure 10 A schematic diagram illustrating the implementation flow of a memory manufacturing method provided in an embodiment of this application;

[0076] Figure 11a A top view schematic diagram of a storage capacitor after its formation, provided in an embodiment of this application;

[0077] Figure 11b A cross-sectional view of a storage capacitor after its formation, provided in an embodiment of this application;

[0078] Figure 12a This is a top view schematic diagram of a bit line after its formation, provided as an embodiment of this application;

[0079] Figure 12b This is a cross-sectional schematic diagram of a bit line after its formation, provided as an embodiment of this application.

[0080] Explanation of reference numerals in the attached figures

[0081] SUB - Substrate; 100 - Pad layer; 101 - Insulating layer; 102 - Active strip; 103 - Insulating strip; 104 - Gate isolation structure; 105 - Insulating material; 106 - First dielectric layer; 107 - Second dielectric layer; 108 - Third dielectric layer; 109 - Fourth dielectric layer; GS - Gate structure; 20 - Transistor array; 200 - Transistor cell / transistor; 201 - Channel region; 202 - Source; 203 - Drain; 204 - Gate; 205 - Gate oxide layer; 206 - Connector; 207 - Second isolation layer; 208 - First isolation layer; 30 - Memory; 301 - Memory cell contact; 302 - Memory cell / storage capacitor; 3021 - Bottom electrode; 30 22 - Dielectric layer; 3023 - Top electrode; CUP - Cup capacitor; CYL - Cylindrical capacitor; PIL - Pillar capacitor; 401 - Bit line contact; 402 - Bit line; 403 - Word line; 102 - Active bar; AP - Active pillar; AP1 - First active pillar; AP2 - Second active pillar; APA - Active pillar array; 2021 - First sub-source; 2022 - Second sub-source; S1 - First surface; S2 - Second surface; S3 - Third surface; S4 - Fourth surface; S5 - Fifth surface; H0 - Initial thickness; H1 - First thickness; H2 - Second thickness; H3 - Third thickness; H4 - Fourth thickness; H5 - Fifth thickness; H6 - Sixth thickness; H7 - Seventh thickness. Detailed Implementation

[0082] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the specific technical solutions of the invention will be further described in detail below with reference to the accompanying drawings of the embodiments of this application. The following embodiments are used to illustrate this application, but are not intended to limit the scope of this application.

[0083] In the following description, the use of suffixes such as "module" or "unit" to denote elements is solely for the purpose of illustration and has no specific meaning in itself. Therefore, "module" or "unit" may be used interchangeably.

[0084] In related technologies, the transistors of mainstream memory include planar transistors and buried channel array transistors (BCAT). However, regardless of whether it is a planar transistor or a buried channel array transistor, the source and drain are located on the horizontal sides of the gate in terms of their structure.

[0085] Furthermore, since transistors can be fabricated on silicon substrates, they can be used in various types of memory, such as DRAM. Typically, DRAM consists of multiple memory cell structures, each of which mainly comprises a transistor and a memory cell (storage capacitor) controlled by the transistor. That is, DRAM includes an architecture of 1T1C (Transistor T and Capacitor C).

[0086] Figure 1a This is a schematic diagram of a control circuit using a 1T1C architecture in related technologies, such as... Figure 1a As shown, the drain of transistor T is electrically connected to the bit line BL, the source of transistor T is electrically connected to one of the electrode plates of capacitor C, the other electrode plate of capacitor C is grounded through the ground terminal GND, and the gate of transistor T is connected to the word line WL. The voltage applied through the word line WL controls the transistor T to be turned on or off. The bit line BL is used to perform read or write operations on transistor T when it is turned on.

[0087] Figure 1b This is a schematic diagram of the control circuit for a memory cell array using a 1T1C architecture in related technologies, such as... Figure 1b As shown, the drains of multiple transistors T are electrically connected to the row address strobe (RAS), the sources of transistors T are electrically connected to one of the electrode plates of capacitor C, and the other electrode plate of capacitor C is grounded through ground terminal GND. The gates of the multiple transistors T are connected to the column address strobe (CAS). The voltage applied by the row address strobe (RAS) controls the transistors T to turn on or off, and the column address strobe (CAS) is used to perform read or write operations on transistor T when it is turned on. The address associated with RAS is a row address, and the address associated with CAS is a column address. In DRAM, a data bit is stored in the cell at the intersection of the column address and the row address, and CAS makes the column address valid.

[0088] Figure 1c This is a schematic diagram of the structure of a DRAM transistor formed using planar transistors in related technologies. Figure 1d This is a schematic diagram of the structure of a DRAM transistor formed using a buried channel transistor in related technologies. Figure 1c The transistors in the relevant technologies are planar transistors. Figure 1d The transistor in the relevant technology is a schematic diagram of a buried channel transistor, as shown in the figure. Figure 1c and 1dAs shown, in the related technology, the source 1101 or 1103 and the drain 1103 or 1101 of the transistor are located on both sides of the gate 1105. In this structure, the source and drain occupy different positions, resulting in a larger area for both planar transistors and buried channel transistors.

[0089] like Figure 1c and 1d As shown, in a DRAM transistor, the source (or drain) 1101 is connected to the bit line 1102, and the drain (or source) 1103 is connected to the capacitor 1104. For chips formed using BCAT (Block Component Assembly), chip-on-board (COB) packaging is typically used to form the memory. Since the source and drain of planar transistors and buried channel transistors are located on opposite sides of the gate, the bit lines and capacitors in a DRAM transistor are also located on the same side of the gate. Furthermore, subsequent processes require connections between bit lines, transistors, and capacitors, as well as connections between word lines (WL) and transistors. This results in complex circuit routing and a more difficult manufacturing process in the DRAM memory's storage array area.

[0090] Figure 1e-1h This is a top view of a plane perpendicular to the substrate thickness direction (the XY plane in the attached figure) during the structural process of a DRAM transistor formed in the related technology. Figure 1h for Figure 1f An enlarged view of a unit memory cell in region P. The X direction represents the word line direction, the Y direction represents the bit line direction, and the DT direction represents the transistor direction.

[0091] like Figure 1e As shown, the direction of transistor T intersects the bit line at an angle of 18–20°; Figure 1f , 1g As shown, word lines WL and bit lines BL intersect perpendicularly, and each transistor T intersects with two word lines WL and one bit line BL. Figure 1g As shown, a single bit line BL can be used to read and erase two adjacent capacitors C individually via the switches of the two word lines WL. Figure 1h As shown, viewed from the XY plane, the two unit memory cells correspond to transistors T1 and T2 in the diagram. Therefore, the unit memory cell is the area of ​​a 6-cell array, which is 6F. 2 The structure occupies a large area.

[0092] Furthermore, as memory integration density continues to increase, transistor size is becoming smaller and smaller. Due to the limitations of channel size in planar transistors and buried transistors, transistor arrays in related technologies cannot withstand high currents.

[0093] Based on at least one of the aforementioned problems existing in related technologies, embodiments of this application provide a transistor array and a method for manufacturing the same, as well as a memory and a method for manufacturing the same.

[0094] Figure 2a This is a three-dimensional structural diagram of a transistor array provided in an embodiment of this application, as shown below. Figure 2a As shown, the transistor array 20 includes a plurality of U-shaped active pillars AP with two branches arranged along a first direction and a second direction, respectively.

[0095] In this embodiment, the first direction intersects the second direction, and the angle between the first direction and the second direction can be any angle between 0 and 90 degrees; see below for details. Figures 6a to 6f Description of the relevant parts. For example, the first direction may be perpendicular to the second direction.

[0096] In this and hereinafter, for ease of description, the first direction and the second direction in the embodiments of the present invention refer to two orthogonal directions in the substrate plane, that is, two transversely extending surfaces in the substrate plane; the third direction is a direction perpendicular to the substrate plane, that is, the thickness direction of the active pillar. The first direction is represented by the X direction in the figures; the second direction is represented by the Y direction in the figures; and the third direction is represented by the Z direction in the figures.

[0097] In this embodiment, the shape of the sidewall of the active column along the third direction in the plane containing the first direction and the third direction is at least one of a straight line, an oblique line, and an arc; see below for details. Figures 5a to 5f Description of relevant parts. For example, the active column has a straight sidewall along the third direction. Here, for ease of description, the active column in this embodiment of the invention has a straight sidewall along the third direction that is parallel to the third direction.

[0098] In some embodiments, such as Figure 2a As shown, transistor array 20 includes:

[0099] A plurality of U-shaped active pillar APs, each having two branches, are arranged along a first direction and a second direction respectively; wherein each of the U-shaped active pillar APs includes:

[0100] Ditch area 201;

[0101] Source 202 is located at the first end of the channel region 201;

[0102] Drain 203 is located at the second end of the channel region 201, wherein the first end and the second end are the two opposite ends of the channel region in a third direction, and the third direction is perpendicular to the surface of the substrate used to form the transistor array 20; the plane formed by the first direction and the second direction is perpendicular to the third direction.

[0103] Multiple gate structures GS, each gate structure GS being located between two adjacent U-shaped active pillars AP1 and AP2 arranged along a first direction; and,

[0104] Multiple electrically insulated connection portions 206, each of which electrically connects two adjacent branches 2021, 2022 of two U-shaped active pillars AP1, AP2 that are in physical contact with the corresponding gate structure GS.

[0105] Figure 2b This application provides a three-dimensional structural diagram of a transistor unit 200 in a transistor array, as shown in the embodiment. Figure 2b As shown, the U-shaped active pillar AP in the transistor unit 200 includes: a channel region 201, a source 202, and a drain 203.

[0106] In some embodiments, such as Figure 2b As shown, transistor unit 200 includes:

[0107] Two U-shaped active pillar APs with two branches are arranged along a first direction; wherein each of the U-shaped active pillar APs includes:

[0108] Ditch area 201;

[0109] Source 202 is located at the first end of the channel region 201;

[0110] Drain 203 is located at the second end of the channel region 201, wherein the first end and the second end are the two opposite ends of the channel region in a third direction, the third direction being perpendicular to the surface of the substrate used to form the transistor unit 200; the plane formed by the first direction and the second direction is perpendicular to the third direction.

[0111] A gate structure GS, the gate structure GS being located between two adjacent U-shaped active pillars AP1 and AP2 arranged along a first direction; and,

[0112] A mutually electrically insulated connection portion 206 electrically connects two adjacent branches 2021 and 2022 of two U-shaped active pillars AP1 and AP2 that are in physical contact with the corresponding gate structure GS.

[0113] Please continue reading Figure 2aIn some embodiments, each of the gate structures GS includes at least: a gate oxide layer 205, a gate 204, and a first isolation layer 208; wherein,

[0114] The gate oxide layer 205 at least covers the two sidewalls of two adjacent U-shaped active pillars AP arranged along the first direction and disposed opposite each other.

[0115] The gate 204 is located between the gate oxide layers 205 of two adjacent U-shaped active pillar APs arranged along the first direction; the gates 204 of each row of U-shaped active pillar APs arranged along the second direction are physically connected to each other.

[0116] The first isolation layer 208 is located between the gate 204 and the connection portion 206.

[0117] In some embodiments, each of the gate structures GS further includes a second isolation layer 207, which is located at the other end of the gate structure GS opposite to the first isolation layer 208 in the third direction.

[0118] like Figure 2a As shown in the embodiments of this application, the transistor array 20 includes an even number of U-shaped active pillars arranged along the X-axis direction. For example, the transistor array 20 includes two or four U-shaped active pillars arranged along the X-axis direction. Each U-shaped active pillar array includes at least one U-shaped active pillar AP arranged along the Y-axis direction. Figure 2b As shown, every two adjacent U-shaped active pillars AP1, AP2 along the first direction are used to form a transistor unit 200, and the insulating strip 103 (see below) Figure 4i and 4j The gate structure GS is used to isolate any two adjacent U-shaped active pillars AP during the formation of the transistor unit 200; at the same time, the gate isolation structure 104 forms the transistor AP into a U-shape.

[0119] For example, the transistor array 20 includes three U-shaped active pillar columns APA arranged along a first direction. The first and second U-shaped active pillar columns are defined as a single U-shaped active pillar unit column. The first active pillar AP1 and the second active pillar AP2 can define a transistor unit 200. The transistor unit 200 also includes a gate structure GS and a connection portion 206 between the first active pillar AP1 and the second active pillar AP2. For details on the transistor unit 200, please refer to... Figure 2b The structure shown.

[0120] In some embodiments, the positions of the source 202 and the drain 203 can be interchanged (see below). Figure 7b and 7cThe source electrode 202 is located at the first end of the channel region 201; the drain electrode 203 is located at the second end of the channel region 201. The first end can be the end closer to the branch portions 2021 and 2022, or the end farther away from the branch portions 2021 and 2022. The first end and the second end are two interchangeable ends of the channel region in a third direction.

[0121] It should be noted that, as Figure 2a and 2b As shown in the view, apart from the second isolation layer 207 and the first isolation layer 208 in the gate structure GS, the other dielectric layers are not shown. In fact, the gate structure GS is filled between adjacent active pillars along the first direction, and the insulating strip 103 is also filled between adjacent active pillars arranged along the second direction in each row of active pillars (see below). Figure 4i and 4j Each active pillar has a gate isolation structure 104 (see below) between its two sub-sources along the first direction. Figure 4i and 4j ).

[0122] In this embodiment, the source and drain of the transistor extend along the substrate thickness direction, thereby reducing the area occupied by a single transistor in the horizontal direction and increasing the number of transistors that can be placed per unit area, thus improving the transistor density in the transistor array. Simultaneously, the two U-shaped transistors share a gate, which further increases the transistor density in the transistor array. Furthermore, the transistor array provided in this disclosure can be used to form a memory. Since the drain and source of the transistor are located on different sides of the wafer, the different structures connected to the source and drain in the memory can be designed on two separate sides of the wafer, i.e., on two opposite sides of the wafer, thereby simplifying the internal circuit layout of the memory and reducing the manufacturing process difficulty.

[0123] The transistor array provided in this application embodiment can be formed by the transistor array manufacturing method provided in the following embodiment.

[0124] Figure 3 This is a schematic diagram illustrating the implementation flow of a transistor array manufacturing method provided in an embodiment of this application, as shown below. Figure 3 As shown, the method for manufacturing the transistor array includes the following steps:

[0125] Step S301, provide a substrate;

[0126] Step S302: Along the first surface of the substrate, a plurality of spaced insulating strips and active strips are formed in the substrate, wherein the insulating strips and active strips extend along a first direction; the first direction is parallel to the first surface.

[0127] Step S303: Along the first surface of the substrate, a plurality of spaced gate isolation structures and gate structures are formed in the substrate, both extending along a second direction; the dimension of the gate isolation structure along a third direction is smaller than the dimension of the active strip along the third direction; the dimension of the gate structure along the third direction is equal to the dimension of the active strip along the third direction; the second direction is parallel to the first surface; the third direction is perpendicular to both the first and second directions; the gate isolation structures and gate structures divide each active strip into a plurality of U-shaped active pillars; each active pillar has two branches;

[0128] Step S304: Form the source of each transistor at the first end of each active pillar.

[0129] Step S305: Form the drain of each transistor at the second end of each active pillar, wherein the first end and the second end are the two opposite ends of the active pillar in a third direction; the active pillar between the source and the drain constitutes the channel region of each transistor.

[0130] Step S306: A plurality of electrically insulated connection portions are formed on the active pillars, and each connection portion electrically connects two adjacent branches of two active pillars that are physically in contact with the corresponding gate structure.

[0131] Figures 4a-4r This is a cross-sectional schematic diagram illustrating the manufacturing process of a transistor array, as provided in an embodiment of this application. It should be understood that... Figure 3 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 3 The steps shown can be rearranged in order according to actual needs. The following section combines... Figure 3 , Figures 4a-4r The manufacturing method of the transistor array provided in the embodiments of this application will be described in detail.

[0132] First, please refer to Figure 4a and 4b , Figure 4a This is a top view. Figure 4b for Figure 4a A cross-sectional view along section AA; performing steps S301 and S302 to provide a substrate; forming a plurality of spaced insulating strips and active strips along a first surface of the substrate, the insulating strips and active strips extending along a first direction; the first direction being parallel to the first surface.

[0133] like Figure 4a and 4bAs shown, the substrate SUB includes a pad layer 100, an insulating layer 101 and an active layer (not shown), and active strips 102 arranged along a second direction are formed on the substrate, each active strip 102 extending along the X-axis direction; each of the active strips 102 is spaced apart by an insulating strip 103.

[0134] In some embodiments, the substrate SUB can be selected according to the actual needs of the device. The substrate SUB includes an insulating layer 101 and an active layer (not shown) sequentially stacked on the pad layer 100 along a third direction (Z direction in the figures). The material of the pad layer 100 may include silicon (Si), germanium (Ge), silicon germanide (SiGe) substrates, etc.; the material of the insulating layer 101 may include, but is not limited to, silicon oxide. In practical applications, the insulating layer 101 and the active layer (not shown) on the substrate 100 can be formed using processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).

[0135] In this embodiment, the substrate SUB can also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI). The substrate is doped with certain impurity ions as needed. The impurity ions can be N-type impurity ions or P-type impurity ions. In one embodiment, the doping includes well region doping and source / drain region doping, and an active layer (not shown) is formed in the substrate SUB.

[0136] In some embodiments, the plurality of spaced insulating strips 103 and active strips 102 are formed by the following steps: forming an insulating layer 101 on a pad layer 100, forming an active layer (not shown) on the insulating layer 101 or directly providing SOI or GOI, using a shallow trench isolation (STI) process, etching a shallow trench (not shown) in the active layer along a third direction to form a trench penetrating the active layer, the bottom of the shallow trench (not shown) extending to the insulating layer 101 in the substrate, depositing an insulating material in the shallow trench (not shown), performing chemical mechanical polishing (CMP) on the insulating strip material so that the surface of the insulating material is flush with the surface of the active layer (not shown), forming the insulating strip 103; the plurality of insulating strips 103 divide the active layer (not shown) into a plurality of active strips 102, forming a plurality of spaced insulating strips 103 and active strips 102 in the substrate.

[0137] In this embodiment of the application, the material of the insulating strip 103 may be silicon dioxide or other insulating materials.

[0138] Please refer to Figure 4c and 4d , Figure 4e and 4f ; Execute step S303, along the first surface S1 of the substrate, form multiple spaced gate isolation structures 104 and gate structures GS in the substrate, wherein the gate isolation structures 104 and gate structures GS (refer to the following) Figure 4i and 4j All extend along the second direction; the dimension of the gate isolation structure 104 along the third direction is smaller than the dimension of the active strip along the third direction; the gate structure GS (refer to the following) Figure 4i and 4j The dimension along the third direction is equal to the dimension of the active strip along the third direction; the second direction is parallel to the first surface S1; the third direction is perpendicular to both the first and second directions; the gate isolation structure 104 and the gate structure GS (see below) Figure 4i and 4j Each active bar is divided into several U-shaped active columns; each active column has two branches.

[0139] In some embodiments, refer to the following Figure 4i and 4jMultiple gate isolation structures 104 and gate structures GS are formed in the substrate at intervals, including: the gate isolation structure 104 can be formed first and then the gate structure GS can be formed, or the gate structure GS can be formed first and then the gate isolation structure 104 can be formed; the gate isolation structure 104 can also be formed at the same time as the gate structure GS.

[0140] In this embodiment, the gate isolation structure 104 is formed first, and then the gate structure GS is formed (see below). Figure 4i and 4j The process will be explained.

[0141] refer to Figure 4c and 4d , Figure 4c This is a top view. Figure 4d for Figure 4c A sectional view along section BB; as shown Figure 4c and 4d As shown, the gate isolation structure 104 is arranged along the X-axis and Y-axis directions; as Figure 4d As shown, each of the gate isolation structures 104 has a first thickness H1 in the Z-axis direction, which is less than the initial thickness H0 of the active strip 102 in the Z-axis direction.

[0142] A gate isolation trench (GIT) that does not penetrate the active bar 102 is formed by etching along a third direction in the active bar 102. An insulating material is deposited in the gate isolation trench GIT. The insulating material is then subjected to chemical mechanical polishing (CMP) treatment so that the surface of the insulating material is flush with the surface of the active bar 102, thereby forming the gate isolation structure 104.

[0143] Here, a dry etching process can be used to etch the active strip 102, such as plasma etching or reactive ion etching. It should be noted that, in this embodiment, the etching of the active strip 102 is a partial etching in the thickness direction of the active strip 102, that is, the etching process will not etch through the active strip 102.

[0144] In this embodiment, the gate isolation structure 104 can be deposited by any suitable deposition process. The material of the gate isolation structure 104 includes any insulating material, such as silicon nitride, silicon oxynitride, silicon carbide, or silicon dioxide.

[0145] Please refer to Figure 4e and 4f , Figure 4g and 4h , Figure 4i and 4j In some embodiments, forming multiple gate structures GS in the substrate includes:

[0146] Step S3031: Form multiple gate trenches GT in the substrate; each active pillar has an exposed sidewall in the corresponding gate trench GT;

[0147] Step S3032: Form a gate oxide layer 205 on at least the exposed sidewall of each of the active pillars AP;

[0148] Step S3033: Form a gate 204 in each of the gate trenches GT in which the gate oxide layer 205 is formed;

[0149] Step S3034: A first isolation layer 208 is formed in each of the gate trenches GT in which the gate oxide layer 205 and the gate 204 are formed, to obtain the gate structure GS. The surface of the first isolation layer 208 is adjacent to the active pillar AP (attached below). Figures 4e to 4n In this example, the active pillar AP is shown as having a surface flush with the first source pillar AP1 and the second source pillar AP2.

[0150] refer to Figure 4e and 4f , Figure 4e This is a top view. Figure 4f for Figure 4e A cross-sectional view along section BB; performing S3031, forming multiple gate trenches in the substrate; each of the active pillars has an exposed sidewall in the corresponding gate trench.

[0151] like Figure 4e As shown, the gate trenches GT are arranged along the X-axis and Y-axis directions; as Figure 4f As shown, the gate trench GT penetrates the active strip 102 to expose the insulating layer 101, and each of the gate trenches GT has an initial thickness H0 in the Z-axis direction that is equal to that of the active strip 102 in the Z-axis direction.

[0152] A gate trench GT is etched along a third direction in the active strip 102 and extends through the active strip 102. The gate trench GT and the insulating strip 103 described in step 301 divide each active strip 102 into several discrete active pillars AP. Each active pillar AP has an exposed sidewall in the gate trench GT. Simultaneously, the gate isolation structure 104 divides one end of each active pillar AP into two spaced sub-ends, and the end of the active pillar furthest from the two spaced sub-ends has one end. Therefore, the formed active pillar AP appears U-shaped in the XZ plane.

[0153] In some embodiments, the shape of the active column along the sidewall of the third direction in the plane containing the first direction and the third direction is at least one of a straight line, an oblique line, and an arc. See below for details. Figures 5a to 5f , Figures 5a to 5f This is a schematic diagram of various optional longitudinal cross-sections for each transistor provided in the embodiments of this application. Figure 5a The sidewall of the active column described herein is straight. Figure 5b The sidewall of the active column described in the text is a diagonal line. Figure 5c The sidewall of the active column described in the text is curved; Figure 5d , 5e The sidewall of the active column described in section 5f has a shape that is a combination of at least one of straight lines, oblique lines, and arcs. Figure 5a , 5b 5c and Figure 5d , 5e The difference between 5f and 5 is that the gate trench formation process is the same as or different from the gate isolation trench formation process, so the sidewall morphology of the active pillar in the gate trench is the same as or different from the sidewall morphology of the active pillar in the gate isolation trench.

[0154] Here, a dry etching process can be used to etch the active strip 102, such as plasma etching or reactive ion etching. It should be noted that in this embodiment, the etching of the active strip 102 is a through-etching process performed in the thickness direction of the active strip 102, etching through the active strip 102. That is, the depth of the gate trench GT in the Z-axis direction is equal to the initial thickness H0 of the active strip 102 in the Z-axis direction.

[0155] Please refer to Figure 4g and 4h , Figure 4g This is a top view. Figure 4h for Figure 4g A cross-sectional view along section BB; performing S3032, forming a gate oxide layer on at least the exposed sidewall of each of the active pillars.

[0156] In some embodiments, forming a gate oxide layer on at least the exposed sidewall of each of the active pillars includes:

[0157] By in-situ oxidation of the active pillars to expose the sidewalls in the corresponding gate trenches, a gate oxide layer is formed on at least the exposed sidewalls of each of the U-shaped active pillars.

[0158] Here, heating or pressurization can be used to heat or pressurize two adjacent active columns AP (such as...) arranged along the X-axis. Figure 4hIn the schematic diagram, the first active pillar AP1 and the second active pillar AP2 have an exposed sidewall in the gate trench GT that is oxidized in situ to form a gate oxide layer of silicon dioxide.

[0159] In some embodiments, the gate oxide layer 205 also covers the bottom of the gate trench GT.

[0160] In some embodiments, prior to forming the gate oxide layer 205, an isolation material is deposited in each of the gate trenches GT to form a second isolation layer 207.

[0161] In some embodiments, before forming the gate oxide 205 layer, an isolation material is deposited in each of the gate trenches GT to form a second isolation layer 207; or after forming the gate oxide 205 layer, an isolation material is deposited in each of the gate trenches GT to form a second isolation layer 207.

[0162] like Figure 4g and 4h As shown in this embodiment, before forming the gate oxide 205 layer, a second isolation layer 207 is formed in each gate trench GT. The second isolation layer 207 has a dimension of a second thickness H2 in the Z direction. The second thickness H2 can be substantially equal to the initial thickness H0 minus the first thickness H1.

[0163] Please refer to Figure 4i and 4j , Figure 4i This is a top view. Figure 4j for Figure 4i A cross-sectional view along section BB; performing step S3033, forming a gate in each of the gate trenches where the gate oxide layer is formed.

[0164] Gate material is deposited in each of the gate trenches GT in which the gate oxide layer 205 is formed to form the gate 204.

[0165] Here, gate material can be deposited in the gate trench after the gate oxide layer has been formed using processes such as PVD, CVD, or ALD. Then, an etch-back process is used to make the distance between the gate and the surface of the active pillar reach a fourth thickness, thus forming the gate. In the embodiments of this application, the gate material can be any metal material or semiconductor conductive material, such as copper, cobalt, tungsten, doped silicon, polysilicon, or any combination thereof.

[0166] like Figure 4i and 4jAs shown, gate material is deposited in the gate trench GT where the gate oxide layer 205 is deposited. Then, through an etch-back process, the distance between the gate 204 and the surface of the active pillar 102 is a fourth thickness H4, forming the gate 204. The dimension of the gate 204 in the Z-axis direction is a third thickness H3. The third thickness H3 is less than the initial dimension H0 of the gate trench GT in the Z-axis direction or less than the value of the initial thickness H0 minus the dimension H4 of the first isolation layer 208 in the Z-axis direction (H0-H4).

[0167] Continue to refer to Figure 4i and 4j , Figure 4i This is a top view. Figure 4j for Figure 4i A cross-sectional view along section BB; Step S3034 is performed to form a first isolation layer in each of the gate trenches where the gate oxide layer and the gate are formed, thereby obtaining the gate structure, wherein the surface of the first isolation layer is flush with the surface of the active pillar.

[0168] Test Figure 4i and 4j In this embodiment, an isolation material is deposited in each gate trench GT where the gate oxide layer 205 and the gate 204 are formed to form a first isolation layer 208. The first isolation layer 208 has a fourth thickness H4 in the Z direction. The fourth thickness H4 can be substantially equal to the value of the second thickness H2; the sum of the second thickness H2, the third thickness H3, and the fourth thickness H4 can be substantially equal to the value of the initial thickness H0. That is, the second isolation layer 207, the gate 204, and the first isolation layer 208 fill the gate trench GT in the Z direction.

[0169] In this embodiment, the first isolation layer 208 can be deposited by any suitable deposition process. The material of the first isolation layer 208 includes any insulating material, such as silicon nitride, silicon oxynitride, silicon carbide, or silicon dioxide.

[0170] Please refer to Figure 4k and 4l , Figure 4k This is a top view. Figure 4l for Figure 4k A cross-sectional view along section BB; perform step S304 to form the source of each transistor at the first end of each of the active pillars.

[0171] like Figure 4k and 4l As shown, in some embodiments, forming the source 202 of each transistor at the first end S1 of each active pillar AP includes: performing ion implantation on the end of each active pillar AP near the U-shaped opening to form the source 202 of each transistor.

[0172] like Figure 4l In the above, the source electrode 202 has a fifth thickness H5 in the Z-axis direction. The size of the source electrode 202 in the Z-axis direction is greater than the size of the first isolation layer 208 in the Z-axis direction, that is, the fifth thickness H5 is greater than the fourth thickness H4. In other words, there is an overlapping area between the source electrode, the gate oxide layer and the gate.

[0173] In some embodiments, in the XY plane, i.e., the top view plane, the shape of the source electrode 202 includes any of the following: square, semi-circular, triangular, or arbitrary polygon. It is understood that the shape of the source electrode 202 is inherited from the shape of the end of the active post AP near the U-shaped opening, and the shape of the source electrode 202 can be formed according to the aforementioned steps S301 to S303.

[0174] It should be noted that the positions of the source 202 and the drain 203 can be interchanged. The end of the branch 2021, 2022 closer to the active pillar AP can form either the source or the drain. The end of the branch 2021, 2022 farther away from the active pillar AP can form either the drain or the source.

[0175] In some embodiments, a drain may be formed at one end of the branch 2021, 2022 near the active post AP, that is, step S304 is executed first, then step S305, and then step S306 is executed.

[0176] In other embodiments, in a scheme where the source is formed at one end of the branch 2021, 2022 near the active post AP, step S304 is executed first, followed by step S306, and then step S305, as described below.

[0177] Please refer to Figure 4m and 4n , Figure 4m This is a top view. Figure 4n for Figure 4m A cross-sectional view along section BB; Step S306 is performed to form a plurality of electrically insulated connection portions 206 on the active pillars, each of the connection portions 206 electrically connecting two adjacent branches of two active pillars AP that are physically in contact with the corresponding gate structures.

[0178] In some embodiments, forming a plurality of electrically insulated connection portions 206 on the active post AP includes:

[0179] A mask layer with multiple openings is formed at one end of each active pillar AP near the U-shaped opening, each opening exposing two adjacent branches of the two active pillars in physical contact with the corresponding gate structure, as well as the region between the two adjacent branches along a first direction.

[0180] The plurality of connecting portions 206 are formed using the mask layer;

[0181] The method further includes:

[0182] Insulating material 105 is filled between multiple joints.

[0183] It should be noted that, as Figure 4n As shown, since the two sub-sources controlled by each gate 204 are located in the first active pillar AP1 and the second active pillar AP2 respectively, and the source 202 in the first active pillar AP1 and the second active pillar AP2 is isolated into two independent parts by the gate isolation structure 104, after forming the source 202, a connection portion 206 needs to be formed on the first sub-source 2021 and the second sub-source 2022, the connection portion 206 electrically connecting the first sub-source 2021 in the first active pillar AP1 and the second sub-source 2022 in the second active pillar AP2; and as Figure 4m As shown, each of the connecting portions 206 is electrically insulated from each other.

[0184] A connection portion 206 is formed between the two sub-source electrodes to connect the two independent source electrodes and form a complete source electrode. Here, the material of the connection portion 206 is composed of any suitable conductive material.

[0185] In this embodiment of the application, the insulating material 105 can be deposited by any suitable deposition process. The insulating material 105 includes any kind of insulating material, such as silicon nitride, silicon oxynitride, silicon carbide or silicon dioxide.

[0186] Please refer to Figure 4o and 4p , Figure 4o This is a top view. Figure 4p for Figure 4o A cross-sectional view along section BB; Execute step S305 to form the drain of each transistor at the second end of each active pillar AP, wherein the first end and the second end are the two opposite ends of the active pillar in the third direction; the active pillar between the source and the drain constitutes the channel region of each transistor.

[0187] In some embodiments, forming the drain of each transistor at the second end of each active pillar AP includes:

[0188] Step S3051: Thin the substrate from the second surface of the substrate and along a third direction to expose the second end of the active pillar away from the first surface of the substrate; wherein the second surface is the opposite side of the first surface;

[0189] Step S3052: Ion implantation is performed on the end of each active pillar away from the U-shaped opening to form the drain of each transistor.

[0190] In practical applications, such as Figure 4o and 4p As shown, in step S3051, the substrate containing the transistor array 20 is flipped, and the transistor array 20 is moved from the second surface S2 of the substrate (referring to the upper surface). Figure 4m and 4n The transistor array 20 is thinned to remove part of the substrate SUB, with the insulating layer 101 serving as the thinning stop layer and having a fourth thickness H4.

[0191] The insulating layer 101 is removed upwards by the third party, exposing the fourth surface S4 (attached) at one end of the active post AP. Figure 4r The fourth surface S4) and the second isolation layer 207 are the sides of the drain formation region and the second isolation layer 207. The third surface S3 at the other end of the active pillar is the side opposite to the fourth surface S4 at one end of the active pillar; the first surface S1 of the substrate is the same as the third surface S3 at the other end of the active pillar.

[0192] In practical applications, such as Figure 4q and 4r As shown, in step S3051, ion implantation is performed at a preset depth on the first end of the active pillar AP, and the drain formation region has the sixth thickness H6 in the third direction, thereby forming the drain 203. Figure 4r In this context, the drain 203 has a sixth thickness H6 in the Z-axis direction. The size of the drain 203 in the Z-axis direction is greater than the size of the second isolation layer 207 in the Z-axis direction, that is, the sixth thickness H6 is greater than the second thickness H2. In other words, there is an overlap region between the drain, the gate oxide layer, and the gate.

[0193] In some embodiments, in the XY plane, i.e., the top view plane, the shape of the drain 203 includes any of the following: square, semi-circular, triangular, or arbitrary polygon. It is understood that the shape of the drain 203 is inherited from the active post AP, and the shape of the drain 203 can be formed according to the aforementioned steps S401 to S403.

[0194] In some embodiments, on the second surface S2 of the substrate (referring to the above) Figure 4nBefore thinning, the fifth surface S5 at one end of the transistor array needs to be fixed to a support structure to prevent damage to the already formed transistor array during the thinning of the fifth surface S5 at one end of the transistor array 20. The sixth surface (not shown) at the other end of the transistor array is connected to the second surface S2 of the substrate (refer to the above). Figure 4n () are on the same side.

[0195] In this embodiment, the region located between the source and the drain forms the channel region 201 of each transistor in the transistor array.

[0196] like Figure 4r In the Z-axis direction, the channel region 201 has a thickness of H7. The projection of the channel region 201 on the XY section covers the projection of the gate 204 on the XY section, that is, there is an overlapping area between the source, drain, gate oxide layer and gate.

[0197] In some embodiments, the positions of the source and drain can be interchanged, meaning the source can be formed first or the drain can be formed first. The positions of source 202 and drain 203 can be interchanged. Specifically, source 202 is located at the first end of the channel region 201; drain 203 is located at the second end of the channel region 201, and the positions of the first and second ends can be interchanged. The first and second ends are respectively two interchangeable positions of the channel region in a third direction.

[0198] In some embodiments, the horizontal cross-section of the second end of the channel region is two rectangles (squares), a semicircle, a triangle, or a polygon; the horizontal cross-section of the first end of the channel region can be of any shape.

[0199] In some embodiments, the cross-sectional shape of each transistor in the transistor array along a direction perpendicular to the third direction and passing through the channel region 201 can be square, elliptical, or rhomboid. See details. Figures 6a to 6f , Figures 6a to 6f Cross-sectional schematic diagrams of various optional types of each transistor provided in embodiments of this application. Figure 6a Figure 6d The cross-section of the transistor is rectangular; Figure 6b and Figure 6e The cross-section of the transistor is elliptical. Figure 6c and Figure 6f The cross-section of the transistor is rhomboid. Among them, Figure 6a , 6b 6c and Figure 6d , 6eThe difference between 6f and 6 is that the gate extends in different directions, that is, the second direction in which each transistor in the transistor array is arranged is different; that is, the angle between the first direction and the second direction can be any angle between 0 and 90 degrees.

[0200] The manufacturing method of the transistor array provided in this application embodiment is similar to that of the transistor array in the above embodiment. For technical features not disclosed in detail in this application embodiment, please refer to the above embodiment for understanding. Here, they will not be repeated.

[0201] The transistor array formed by the manufacturing method of the transistor array provided in this application embodiment greatly reduces the area of ​​the transistor because the source and drain of each transistor are located at opposite ends of the channel region along the thickness direction of the active pillar. Furthermore, each transistor in the transistor array provided in this application embodiment has dual vertical channels, thereby increasing the drive current intensity of each transistor in the transistor array.

[0202] This application provides a memory. Figure 7a This is a three-dimensional structural diagram of a memory provided in an embodiment of this application. Figure 7b A three-dimensional structural diagram of a cell structure in a memory provided in an embodiment of this application;

[0203] In some embodiments, such as Figure 7a As shown, the memory 30 includes:

[0204] The transistor array 20 described in any of the above embodiments and the transistor array 20 formed by the manufacturing method of the transistor array in the above embodiments; the transistor array 20 (refer to the above) Figure 2a The transistor 200 has multiple gates 204 arranged in parallel along a first direction for receiving the voltage of the word line 403 and controlling the transistor 200 by the voltage of the word line 403 (refer to the above). Figure 2b ) On or off;

[0205] Multiple memory cells 302, each of which is connected to the source 202 or drain 203 of a transistor 200 in the transistor array 20; and

[0206] Multiple bit lines 402 are arranged in parallel along the second direction. Each bit line 402 is connected to the drain 203 or source 202 of a row of transistors arranged along the first direction in the transistor array 20. The bit lines 402 are used to perform read or write operations on the memory cell 302 when the transistor 200 is turned on. The memory cell 302 and the bit lines 402 are connected to different electrodes.

[0207] In some embodiments, such as Figure 7b As shown, the memory 30 includes:

[0208] The transistor unit 200 formed by the manufacturing method of the transistor array in the above embodiments; the transistor unit 200 (refer to the above) Figure 2b It has a gate 204 extending along a second direction for receiving the voltage of word line 403 and controlling the transistor 200 to be turned on or off by the voltage of word line 403;

[0209] A memory cell 302, the memory cell 302 being connected to the source 202 of the transistor cell 200; and

[0210] A bit line 402 extends along a first direction and is connected to the drain 203 of the U-shaped active pillars arranged along the first direction in the transistor unit 200. The bit line 402 is used to perform read or write operations on the memory unit 302 when the transistor unit 200 is turned on. The memory unit 302 and the bit line 402 are connected to different electrodes.

[0211] In some embodiments, such as Figure 7c As shown, the memory 30' includes:

[0212] The transistor unit 200 formed by the manufacturing method of the transistor array in the above embodiments; the transistor unit 200 (refer to the above) Figure 2b It has a gate 204 extending along a second direction for receiving the voltage of word line 403 and controlling the transistor 200 to be turned on or off by the voltage of word line 403;

[0213] Two memory cells 302' are connected to the source 202' of the transistor cell 200; and

[0214] A bit line 402' extends along a first direction, and the bit line 402' is connected to the drain 203' of the U-shaped active pillars arranged along the first direction in the transistor unit 200. The bit line 402' is used to perform read or write operations on the memory unit 302' when the transistor unit 200 is turned on. The memory unit 302 and the bit line 402' are connected to different electrodes.

[0215] In some embodiments, the positions of the source 202 and the drain 203 can be interchanged; Reference Figure 7b and Figure 7c As shown. Figure 7bAs shown, in the memory 30, the memory cell 302 is connected to the connection portion 206 and the source 202 via the memory cell contact 301, and the bit line 402 is connected to the drain 203 via the bit line contact 401. (Reference) Figure 7c for Figure 7b A schematic diagram after the source and drain are interchanged, as shown below. Figure 7c As shown, in the memory 30', the memory cell 302' is connected to the source 202' through the memory cell contact 301', and the bit line 402' is connected to the connection portion 206 and the drain 203' through the bit line contact 401'.

[0216] like Figure 7a As shown in the embodiment of this application, the memory 30 includes: transistors 200, word lines 403, and bit lines 402; the transistors 200 include at least an active pillar array (APA) and a gate structure GS; the active pillar array (APA) includes a plurality of U-shaped active pillars AP arranged along a first direction and a second direction respectively; wherein each transistor 200 includes at least: a gate 204, a source 202, and a drain 203. The gate structure GS includes a gate 204, a gate oxide layer 205, a second isolation layer 207, and a first isolation layer 208, and the gate structure GS includes a plurality of pins arranged along the first direction and the second direction respectively.

[0217] It should be noted that, as Figure 7a , 7b As shown in Figure 7c, apart from the second isolation layer 207 and the first isolation layer 208 in the gate structure GS, the other dielectric layers are not shown in the view. In fact, the gate structure GS is filled between adjacent active pillars along the first direction, and the insulating strip 103 is also filled between adjacent active pillars arranged along the second direction in each row of active pillars (refer to the above). Figure 4i and 4j Each active pillar has a gate isolation structure 104 between its two sub-sources along the first direction (see above). Figure 4i and 4j ).

[0218] Please continue reading Figure 7a The word line 403 extending along the Y-axis direction and each of the transistor arrays 20 (refer to the above) Figure 2a The gate 204 of each active pillar is connected to the word line 403, which provides a word line voltage and controls the conduction or cutoff of the channel region in each active pillar. The bit line 402, extending along the X-axis, is connected to each transistor array 20 (refer to the above). Figure 2a The drain 203 of the transistor 200AP is connected, and the bit line 402 is used to perform a read or write operation on the memory cell 302 when each of the transistors 200AP is turned on.

[0219] In this embodiment, the materials of the word lines and the bit lines include, but are not limited to, tungsten, cobalt, copper, aluminum, polycrystalline silicon, doped silicon, silicides, or any combination thereof.

[0220] In some embodiments, the memory provided in this application includes various types of memory. For example, NAND flash memory, Nor flash memory, DRAM, static random access memory (SRAM), phase-change memory (PCM), ferroelectric memory, magnetic variable memory, or resistive variable memory.

[0221] See Figure 7b In some embodiments, the memory includes dynamic random access memory (DRAM), and the memory cell includes a storage capacitor 302.

[0222] One end of the storage capacitor 302 is connected to the source 202 of a transistor in the transistor array, and the other end of the storage capacitor 302 is grounded. The storage capacitor 302 is used to store the written data.

[0223] In practical applications, the multiple storage capacitors can be arranged in various shapes.

[0224] In some embodiments, the plurality of storage capacitors are arranged in a square or in a hexagonal arrangement.

[0225] For example, such as Figure 8a In the XY top view plane, the array layout of the storage capacitors 302 can be arranged in a square. For example, as... Figure 8b In the XY top view plane, the array layout of the storage capacitors 302 can be arranged in a hexagonal shape.

[0226] In practical applications, the storage capacitor can take on various structures.

[0227] In some embodiments, the storage capacitor includes a cup-shaped, cylindrical, or pillar-shaped capacitor.

[0228] For example, such as Figure 9a As shown, the storage capacitor 302 may include a cup-shaped capacitor CUP; for example, as Figure 9b As shown, the storage capacitor 302 may include a cylindrical capacitor CYL; for example, as Figure 9cAs shown, the storage capacitor 302 may include a pillar-shaped capacitor PIL. The cup-shaped capacitor CUP, cylindrical capacitor CYL, and pillar-shaped capacitor PIL all include a bottom electrode 3021, a top electrode 3023, and a dielectric layer 3022 located between the bottom electrode 3021 and the top electrode 3023. It should be noted that the bottom electrode 3021 is connected to the source 202 of a transistor in the transistor array AP, and the top electrode 3023 of the cup-shaped capacitor CUP is grounded. The cup-shaped capacitor CUP is used to store the written data.

[0229] It should be noted that, when the areas of the bottom electrode 3021 in the cup-shaped capacitor (CUP), cylindrical capacitor (CYL), and pillar-shaped capacitor (PIL) are equal, the top electrode 3023 of the cylindrical capacitor (CYL) has the largest area, followed by the top electrode 3023 of the cylindrical capacitor (CYL) and pillar-shaped capacitor (PIL). Therefore, in practical applications, the cylindrical capacitor (CYL) can be used as the storage unit of a memory, which is beneficial for achieving extremely high memory integration.

[0230] In some embodiments, the memory includes a resistive random access memory (RRAM), and the memory cell includes an adjustable resistor connected to the bit line 402 and the transistor array 20 (refer to the above). Figure 2a One transistor 200 (refer to the above) Figure 2b The adjustable resistor is connected between the source 202 of the transistor array 20 and the drain 203 of the transistor 200 in the transistor array 20. The adjustable resistor is used to adjust the state of the stored data by the bit line voltage provided by the bit line 402.

[0231] In this application, some common memories are merely exemplified and listed. The scope of protection of this application is not limited to these. Any memory that includes the transistor array provided in the embodiments of this application is within the scope of protection of this application.

[0232] The transistor array in the memory provided in this application embodiment is formed by the manufacturing method of the transistor array provided in the above embodiment. For technical features not disclosed in detail in this application embodiment, please refer to the above embodiment for understanding. Here, they will not be repeated.

[0233] The memory provided in this application includes at least a transistor array. Since the source and drain of each active pillar in the transistor array are located at the first end and the second end in the thickness direction of the active pillar, respectively, the area of ​​the transistor array is greatly reduced, thereby making the formed memory more miniaturized. In addition, since each active pillar in the transistor array has dual vertical channels, the driving current intensity of each active pillar in the transistor array is increased, thus improving the electrical performance of the memory.

[0234] In addition, embodiments of this application also provide a method for manufacturing a memory, including:

[0235] Step S701: Forming a transistor array; the transistor array is manufactured by a transistor array manufacturing method provided by any of the above methods; the transistor array has multiple gates arranged in parallel along a first direction for receiving word line voltages and controlling the transistors to be turned on or off by the word line voltages;

[0236] Step S702: Form a plurality of memory cells, each of which is connected to the source or drain of a transistor in the transistor array.

[0237] Step S703: Form multiple bit lines arranged in parallel along the second direction. Each bit line is connected to the source or drain of a row of transistors arranged along the first direction in the transistor array. The bit lines are used to perform read or write operations on the memory cell when the transistors are turned on.

[0238] Figure 10 This is a schematic diagram illustrating the implementation flow of a memory manufacturing method provided in an embodiment of this application, as shown below. Figure 10 As shown, the method includes the following steps:

[0239] Step S701, please refer to the above for details. Figure 4q and Figure 4r A transistor array is formed; the transistor array is manufactured by a transistor array manufacturing method provided by any of the above methods; the transistor array has multiple gates arranged in parallel along a first direction for receiving word line voltages and controlling the transistors to be turned on or off by the word line voltages.

[0240] A word line is formed, which is connected to the gate of each of the active pillars. The word line is used to provide a word line voltage and to control the conduction or cutoff of each of the active pillars through the word line voltage.

[0241] In some embodiments, the word lines can be formed through the following steps:

[0242] In the second direction, the gates of each active pillar in the active pillar array are interconnected to form the word line. For specific details in this embodiment, please refer to the above description. Figure 4q and Figure 4r The transistor array and word lines are formed by the manufacturing method of the transistor array and gate structure in the above embodiments.

[0243] Step S702, for details please refer to Figure 11a and Figure 11bMultiple memory cells are formed, each of which is connected to the source or drain of a transistor in the transistor array. The memory cells can be formed through the following steps:

[0244] Step S7021: A first dielectric layer is formed on the surface of the connection portion on the source region of the active post.

[0245] Step S7022: Etch the first dielectric layer to expose the connection portion on the source region of the active pillar, forming a memory cell contact hole.

[0246] Step S7023: Fill the storage cell contact hole with metal material to form the storage cell contact 301.

[0247] Step S7024: A second dielectric layer is formed on the surface of the first dielectric layer and the contact 301 of the storage cell.

[0248] Step S7025: Etch the second dielectric layer to expose the memory cell contact 301 and form a memory cell hole.

[0249] Step S7026: Form the memory cell 302 in the memory cell hole, for example, form a memory capacitor.

[0250] Step S703, for details please refer to Figure 12a and Figure 12b Multiple bit lines are formed in parallel along the second direction. Each bit line is connected to the source or drain of a row of transistors arranged along the first direction in the transistor array. The bit lines are used to perform read or write operations on the memory cell when the transistor is turned on.

[0251] In some embodiments, the drain region of the active pillar forms a bit line, which is formed by the following steps:

[0252] Step S7031: A third dielectric layer is formed on the surface of the drain of the active pillar array and the second isolation layer.

[0253] Step S7032: Etch the third dielectric layer to expose the drain electrode and form a bit line contact hole.

[0254] Step S7033: Fill the bit line contact hole with metal material to form the bit line contact 401.

[0255] Step S7034: A fourth dielectric layer is formed on the surface of the third dielectric layer and the bit line contact 401.

[0256] Step S7035: Etch the fourth dielectric layer to expose the bit line contact 401 and form a bit line trench.

[0257] Step S7036: Fill the bit line groove with metal material to form the bit line 402.

[0258] in, Figure 11a and 11b These are top and cross-sectional schematic diagrams, respectively, of a storage capacitor formed according to an embodiment of this application, wherein... Figure 11a This is a top view. Figure 11b For example, a cross-sectional view. Figure 11a and 11b As shown, a memory cell contact 301 and a plurality of memory capacitors 302 are formed on the surface of the connection portion 206 on the source electrode 202.

[0259] in, Figure 12a and 12b These are top and cross-sectional schematic diagrams, respectively, of a bit line formed according to an embodiment of this application, wherein... Figure 12a This is a top view. Figure 12b For example, a cross-sectional view. Figure 12a and 12b As shown, multiple bit line contacts 401 and multiple bit lines 402 are formed on the surface of the drain 203.

[0260] The method for manufacturing the memory provided in this application is similar to that of the memory in the above embodiments. For technical features not disclosed in detail in this application, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0261] The source and drain of the transistor extend along the thickness direction of the substrate, thereby reducing the area occupied by a single transistor in the horizontal direction and increasing the number of transistors that can be placed per unit area, thus improving the transistor density in the transistor array. Simultaneously, the two U-shaped active pillars share a gate, which can further increase the transistor density in the transistor array. Furthermore, the transistor array provided in this disclosure can be used to form a memory. Since the drain and source of the transistor are located on different sides of the wafer, the different structures connected to the source and drain in the memory can be designed on two separate sides of the wafer, i.e., on two opposite sides of the wafer, thereby simplifying the internal circuit layout of the memory and reducing the process difficulty of memory manufacturing.

[0262] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.

[0263] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0264] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0265] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A transistor array, comprising: The transistor array comprises: a plurality of U-shaped active pillars with two branch parts arranged along a first direction and a second direction respectively; wherein each of the U-shaped active pillars comprises: a channel region; a source located at a first end of the channel region; a drain located at a second end of the channel region, wherein the first end and the second end are two opposite ends of the channel region in a third direction, the third direction is perpendicular to a surface of a substrate used for forming the transistor array, and the first direction and the second direction form a plane which is perpendicular to the third direction; a plurality of gate structures, each of the gate structures being located between two adjacent U-shaped active pillars arranged along the first direction; and a plurality of connection parts which are electrically insulated from each other, each of the connection parts electrically connecting two adjacent branch parts of two active pillars arranged along the first direction which are in physical contact with a corresponding gate structure, to form a complete source or drain.

2. The transistor array of claim 1, wherein, Each of the gate structures comprises: a gate oxide layer, a gate, and a first isolation layer; wherein the gate oxide layer covers at least two side walls of two adjacent U-shaped active pillars arranged along the first direction which are oppositely arranged; the gate is located between the gate oxide layers of two adjacent U-shaped active pillars arranged along the first direction; the gates of each row of U-shaped active pillars arranged along the second direction are physically connected to each other; the first isolation layer is located between the gate and the connection part.

3. The transistor array of claim 2, wherein, Each of the gate structures further comprises: a second isolation layer located at the other end of the gate structure opposite to the first isolation layer in the third direction.

4. The transistor array of claim 1, wherein, The included angle between the first direction and the second direction ranges from 0 to 90 degrees.

5. A memory, comprising: The transistor array comprises: any one of claims 1 to 4; the transistor array has a plurality of gates arranged along a first direction in parallel, used for receiving a word line voltage and controlling the transistor to be turned on or turned off through the word line voltage; a plurality of storage units, each of the storage units being connected to the source or drain of a transistor in the transistor array; and a plurality of bit lines arranged along a second direction in parallel, each of the bit lines being connected to the drain or source of a row of transistors arranged along the first direction in the transistor array, the bit line being used for performing a read or write operation on the storage unit when the transistor is turned on; the storage unit and the bit line are connected to different electrodes.

6. The memory of claim 5, wherein, The memory comprises: a dynamic random access memory, a ferroelectric memory, a phase change memory, a magnetic variable memory, or a resistive variable memory.

7. The memory of claim 6, wherein, The memory comprises a dynamic random access memory, and the storage unit comprises a storage capacitor; one end of the storage capacitor is connected to the source of a transistor in the transistor array, and the other end of the storage capacitor is grounded, and the storage capacitor is used for storing written data.

8. The memory of claim 7, wherein, The plurality of storage capacitors are arranged in a square or a hexagon.

9. The memory of claim 7, wherein, The storage capacitor comprises a cup-shaped, cylindrical or pillar-shaped capacitor.

10. The memory of claim 6, wherein, The memory comprises a resistive variable memory, and the storage unit comprises an adjustable resistor, The adjustable resistance is connected between the bit line and a source of a transistor in the transistor array, or the adjustable resistance is connected between the bit line and a drain of a transistor in the transistor array, and the adjustable resistance is used to adjust a state of stored data by a bit line voltage provided by the bit line.

11. A method of fabricating an array of transistors, characterized by, The method comprises: providing a substrate; forming a plurality of spaced insulating strips and active strips in the substrate along a first surface of the substrate, the insulating strips and active strips each extending along a first direction; the first direction being parallel to the first surface; forming a plurality of gate isolation structures and gate structures in the substrate along the first surface of the substrate, the gate isolation structures and gate structures each extending along a second direction; a dimension of the gate isolation structures along a third direction being less than a dimension of the active strips along the third direction; a dimension of the gate structures along the third direction being equal to the dimension of the active strips along the third direction; the second direction being parallel to the first surface; the third direction being perpendicular to both the first direction and the second direction; the gate isolation structures and gate structures dividing each of the active strips into a plurality of U-shaped active pillars; each of the active pillars having two branch portions; forming a source of each of the transistors at a first end of each of the active pillars; forming a drain of each of the transistors at a second end of each of the active pillars, wherein the first end and the second end are opposite ends of the active pillars along the third direction; the active pillar between the source and the drain constituting a channel region of each of the transistors; forming a plurality of connection portions on the active pillars, each of the connection portions electrically connecting two adjacent branch portions of two active pillars in physical contact with a corresponding gate structure.

12. The method of claim 11, wherein, The forming a plurality of gate structures in the substrate comprises: forming a plurality of gate trenches in the substrate; each of the active pillars having an exposed sidewall in a corresponding gate trench; forming a gate oxide layer on at least the exposed sidewall of each of the active pillars; forming a gate in each of the gate trenches having the gate oxide layer formed thereon; forming a first isolation layer in each of the gate trenches having the gate oxide layer and the gate formed thereon, the surface of the first isolation layer being flush with the surface of the active pillars, to obtain the gate structure.

13. The method of claim 12, wherein, The forming a gate oxide layer on at least the exposed sidewall of each of the active pillars comprises: forming a gate oxide layer on at least the exposed sidewall of each of the U-shaped active pillars by in-situ oxidation.

14. The method of claim 12, wherein, The method further comprises: depositing an isolation material in each of the gate trenches before forming the gate oxide layer, to form a second isolation layer.

15. The method of claim 11, wherein, The forming a plurality of connection portions on the active pillars comprises: forming a mask layer having a plurality of openings at one end of each of the active pillars close to the opening of the U-shape, each of the openings exposing two adjacent branch portions of two active pillars in physical contact with a corresponding gate structure, and a region between the two adjacent branch portions along the first direction; forming a plurality of connection portions using the mask layer; The method further comprises: filling an insulating material between the plurality of connection portions.

16. The method of claim 11, wherein, The source of each transistor is formed at a first end of each of the active pillars, comprising: Ion implantation is performed on an end of each of the active pillars close to the U-shaped opening to form the source of each of the transistors.

17. The method of claim 11, wherein, The drain of each of the transistors is formed at a second end of each of the active pillars, comprising: A thinning process is performed on the substrate from a second surface of the substrate and along a third direction to expose the second end of the active pillars away from the first surface of the substrate; wherein the second surface is the opposite surface of the first surface; Ion implantation is performed on an end of each of the active pillars away from the U-shaped opening to form the drain of each of the transistors.

18. A method of manufacturing a memory, characterized by, The method comprises: forming a transistor array; the transistor array is manufactured by the transistor array manufacturing method provided in any one of claims 11 to 17; the transistor array has a plurality of gates arranged side by side along a first direction, used to receive a word line voltage and control the transistor to be turned on or turned off through the word line voltage; forming a plurality of storage units, each of the storage units is connected to the source or drain of a transistor in the transistor array; forming a plurality of bit lines arranged side by side along a second direction, each of the bit lines is connected to the source or drain of a row of transistors arranged along the first direction in the transistor array, and the bit line is used to perform read or write operation on the storage unit when the transistor is turned on.

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