Semiconductor element and manufacturing method thereof

Abstract

The present invention discloses a semiconductor device and a method for fabricating the same. The method includes forming a magnetic tunneling junction (MTJ) stack structure on a substrate, performing an etching process to remove a portion of the MTJ stack structure to form an MTJ, performing a deposition process to form a polymer on the MTJ sidewalls, and then removing the polymer to form a roughened surface on the MTJ sidewalls. The MTJ includes a pinned layer disposed on the substrate, a barrier layer disposed on the pinned layer, and a free layer disposed on the barrier layer. The roughened surface can be provided on the pinned layer, the barrier layer, and / or the free layer sidewalls.

Description

Technical Field

[0001] The present invention relates to a semiconductor element and a manufacturing method thereof, and in particular to a magnetoresistive random access memory (MRAM) and a manufacturing method thereof. Background Art

[0002] The magnetoresistance (MR) effect is known to occur when a material's electrical resistance changes with an applied magnetic field. Its physical quantity is defined as the difference in resistance in the presence and absence of a magnetic field divided by the original resistance, representing the rate of change of resistance. Currently, the magnetoresistance effect has been successfully applied to hard drive production and holds significant commercial value. Furthermore, by exploiting the characteristic of giant magnetoresistance materials exhibiting varying resistance values under different magnetization states, magnetic random access memory (MRAM) can be fabricated, which has the advantage of retaining stored data even when power is off.

[0003] The magnetoresistance effect is also used in the field of magnetic field sensing. For example, the electronic compass components of the global positioning system (GPS) in mobile phones are used to provide information such as the user's movement direction. Currently, there are various magnetic field sensing technologies on the market, such as anisotropic magnetoresistance (AMR) sensing elements, giant magnetoresistance (GMR) sensing elements, magnetic tunneling junction (MTJ) sensing elements, etc. However, the disadvantages of the above-mentioned existing technologies generally include: larger chip area, more expensive manufacturing process, higher power consumption, insufficient sensitivity, and susceptibility to temperature changes, etc., and further improvement is necessary. Summary of the Invention

[0004] One embodiment of the present invention discloses a method for fabricating a semiconductor device. The method includes first forming a magnetic tunneling junction (MTJ) stack structure on a substrate, then performing an etching process to remove a portion of the MTJ stack structure to form an MTJ, performing a deposition process to form a polymer on the MTJ sidewalls, and then removing the polymer to form a roughened surface on the MTJ sidewalls. The MTJ includes a pinned layer disposed on the substrate, a barrier layer disposed on the pinned layer, and a free layer disposed on the barrier layer. The roughened surface may be provided on the pinned layer, the barrier layer, and / or the free layer sidewalls.

[0005] Another embodiment of the present invention discloses a semiconductor device comprising a magnetic tunneling junction (MTJ) disposed on a substrate, wherein the MTJ sidewalls include a roughened surface. More specifically, the MTJ includes a pinned layer disposed on the substrate, a barrier layer disposed on the pinned layer, and a free layer disposed on the barrier layer. The roughened surface may be disposed on the pinned layer, the barrier layer, and / or the free layer sidewalls. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1 to 4 A schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0007] Figures 5 to 10 Schematic diagrams of the structures of semiconductor devices according to different embodiments of the present invention.

[0008] Description of main component symbols

[0009] 12: Base

[0010] 14: MRAM area

[0011] 16: Interlayer dielectric layer

[0012] 18: Metal interconnect structure

[0013] 20: Metal interconnect structure

[0014] 22: Intermetallic dielectric layer

[0015] 24: Metal interconnects

[0016] 26: Stop layer

[0017] 28: Intermetallic dielectric layer

[0018] 30:Metal interconnect

[0019] 32: Metal interconnects

[0020] 34: Barrier layer

[0021] 36:Metal layer

[0022] 38: Lower electrode

[0023] 40: Fixed layer

[0024] 42: Barrier layer

[0025] 44: Free layer

[0026] 46:MTJ stacking structure

[0027] 48: Upper electrode

[0028] 50: Patterned mask

[0029] 52:MTJ

[0030] 54:MTJ

[0031] 56:Polymer

[0032] 58: Rough surface

[0033] 60: Covering layer

[0034] 62: Intermetallic dielectric layer

[0035] 64:Metal interconnect

[0036] 66: Stop layer DETAILED DESCRIPTION

[0037] Please refer to Figures 1 to 4 , Figures 1 to 4 Schematic diagram of a method for manufacturing a semiconductor device, or more specifically, an MRAM cell, according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, for example, a substrate 12 made of a semiconductor material, wherein the semiconductor material can be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and an MRAM region 14 and a logic region (not shown) are preferably defined on the substrate 12.

[0038] The substrate 12 may include active devices such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers, and dielectric layers such as an interlayer dielectric (ILD) 16 covering the substrate 12. More specifically, the substrate 12 may include planar or non-planar MOS transistors (e.g., fin-structured transistors), wherein the MOS transistors may include a gate structure (e.g., a metal gate) and transistor components such as source / drain regions, spacers, epitaxial layers, and contact etch stop layers. The ILD 16 may be disposed on the substrate 12 and cover the MOS transistors. The ILD 16 may include a plurality of contact plugs electrically connected to the gate and / or source / drain regions of the MOS transistors. The fabrication processes for planar or non-planar transistors and ILDs are well known in the art and are not further described herein.

[0039] Then, metal interconnect structures 18 and 20 are sequentially formed on the interlayer dielectric layer 16 to electrically connect the aforementioned contact plugs, wherein the metal interconnect structure 18 includes an intermetallic dielectric layer 22 and a metal interconnect 24 embedded in the intermetallic dielectric layer 22, and the metal interconnect structure 20 includes a stop layer 26, an intermetallic dielectric layer 28, and a plurality of metal interconnects 30 and 32 embedded in the stop layer 26 and the intermetallic dielectric layer 28.

[0040] In this embodiment, each metal interconnect 24 in the metal interconnect structure 18 preferably comprises a trench conductor, and each metal interconnect 30, 32 in the metal interconnect structure 20 preferably comprises a via conductor. Furthermore, each metal interconnect 24, 30, 32 in each metal interconnect structure 18, 20 may be inlaid in the intermetal dielectric layers 22, 28 and / or the stop layer 26 using a single damascene process or a dual damascene process and electrically connected to each other. For example, each metal interconnect 24, 30, 32 may further include a barrier layer 34 and a metal layer 36. Barrier layer 34 may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while metal layer 36 may be selected from the group consisting of, but not limited to, tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. Single damascene or dual damascene fabrication processes are well known in the art and are not further described herein. Furthermore, in this embodiment, the metal layer 36 in the metal interconnect 24 preferably comprises copper, the metal layer 36 in the metal interconnects 30 and 32 preferably comprises tungsten, the intermetallic dielectric layers 22 and 28 preferably comprise silicon oxide or an ultra-low-k dielectric layer, and the stop layer 26 comprises nitrogen-doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN), but is not limited thereto.

[0041] Next, a lower electrode 38 may be formed on the surface of the intermetal dielectric layer 28, an MTJ stack structure 46 consisting of a pinned layer 40, a barrier layer 42, and a free layer 44 may be formed on the lower electrode 38, an upper electrode 48 may be formed on the MTJ stack structure 46, and a patterned mask 50, such as a patterned photoresist, may be formed on the surface of the upper electrode 48. The free layer 44 may optionally include a first free layer (not shown) disposed on the barrier layer 42, a stop layer (not shown) disposed on the first free layer, and a second free layer (not shown) disposed on the stop layer.

[0042] In this embodiment, the lower electrode layer 38 and the upper electrode 48 preferably include a conductive material, such as but not limited to tantalum (Ta), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), or a combination thereof. The fixed layer 40 may include a ferromagnetic material such as but not limited to cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), iron (Fe), cobalt (Co), etc., to fix or limit the magnetic moment direction of the adjacent layer. The barrier layer 42 may be composed of an insulating material including an oxide, such as aluminum oxide (AlO). x ) or magnesium oxide (MgO), but are not limited thereto. The free layer 44, including the first and second free layers, can be made of a ferromagnetic material, such as iron, cobalt, nickel, or alloys thereof, such as cobalt-iron-boron (CoFeB) or nickel-iron (NiFe), but are not limited thereto. The magnetization direction of the free layer 44 is "freely" altered by an external magnetic field.

[0043] like Figure 2 As shown, an etching process is then performed using a patterned mask 50 to remove a portion of the upper electrode 48, a portion of the MTJ stack structure 46, and a portion of the lower electrode 38 to form a plurality of MTJs 52 and 54. A deposition process is then performed to form a polymer 56 on the sidewalls of each MTJ 52 and 54. The etching process and the deposition process are then repeated. In detail, in the etching process and the deposition process repeated and alternating at this stage, the etching process preferably uses hydrochloric acid and / or chlorine gas to remove or pattern a portion of the upper electrode 48, a portion of the MTJ stack structure 46, and a portion of the lower electrode 38 to form the MTJs 52 and 54, and the deposition process includes introducing methyl chloride to form a polymer 56 on the sidewalls of each MTJ 52 and 54. The formed polymer 56 preferably includes a carbon-bonded and / or hydrogen-bonded polymer.

[0044] Then as Figure 3 As shown, another etching process is then performed using sulfuric acid (H2SO4) and / or hydrofluoric acid (HF) to completely remove the polymer 56 accumulated through the aforementioned etching process and deposition process. It should be noted that in this embodiment, during the aforementioned repeated etching process and deposition process, a rough surface 58 is preferably formed on the sidewalls of each MTJ 52, 54, and the rough surface 58 is exposed after the polymer 56 is removed. The so-called rough surface 58 may vary depending on the recipe or parameters used in the etching process, for example, it may include a more detailed profile such as a jagged surface or a wavy surface.

[0045] It is worth noting that, when the MTJ stack structure 46 is currently patterned to form the MTJs 52 and 54 by reactive ion etching (RIE) and / or ion beam etching (IBE) processes, not only will the metal sputtering rebound to the sidewalls of the MTJs 52 and 54 affect the magnetic performance of the MTJs 52 and 54, but the characteristics of the IBE etching may also easily cause the top surface of the intermetallic dielectric layer 28 on both sides of the MTJs 52 and 54 to have excessive curvature, so the present embodiment preferably repeats the aforementioned etching process using hydrochloric acid and / or chlorine as the main etching components and the methyl chloride deposition process while omitting the aforementioned reactive ion etching and / or ion beam etching processes. While patterning the MTJ stack structure 46 to form the MTJs 52 and 54, a polymer 56 is formed on the sidewalls of the MTJs 52 and 54, thereby protecting the sidewalls of the MTJs 52 and 54 from being damaged by the impact of metal atoms.

[0046] Then as Figure 4 As shown, a capping layer 60 is formed on the MTJs 52 and 54 and covers the surface of the IMD layer 28. An IMD layer 62 is formed on the capping layer 60. One or more photolithography and etching processes are then performed to remove portions of the IMD layer 62 and the capping layer 60 to form contact holes (not shown). Conductive material is then filled into each contact hole and a planarization process, such as CMP, is performed to form metal interconnects 64 connected to the upper electrode 48 below. Finally, another stop layer 66 is formed on the IMD layer 62 and covers the metal interconnects 64.

[0047] In this embodiment, cap layer 60 preferably comprises silicon nitride, but other dielectric materials may be selected depending on process requirements, such as silicon oxide, silicon oxynitride, or silicon carbide nitride. Stop layer 66 may be selected from the group consisting of nitrogen-doped carbide (NDC), silicon nitride, and silicon carbon nitride (SiCN), and preferably comprises silicon carbide nitride. As with the metal interconnects formed above, each metal interconnect 64 within IMD layer 62 may be inlaid within the IMD layer using either a single damascene process or a dual damascene process. For example, each metal interconnect 64 may further include a barrier layer and a metal layer, wherein the barrier layer may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer may be selected from the group consisting of, but not limited to, tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. Since single-damascene or dual-damascene fabrication processes are well known in the art, they will not be further described here. This completes the fabrication of a semiconductor device according to one embodiment of the present invention.

[0048] Please continue to refer to Figures 5 to 7 , Figures 5 to 7 Schematic diagram of the structure of semiconductor components according to different embodiments of the present invention. Figures 5 to 7 As shown, each MTJ, such as MTJ 52, is disposed on substrate 12, lower electrode 38 is disposed below MTJ 52, and upper electrode 48 is disposed above MTJ 52, wherein MTJ 52 includes a fixed layer 40 disposed on metal interconnect 30, a barrier layer 42 disposed on fixed layer 40, and a free layer 44 disposed on barrier layer 42, and the sidewall of MTJ 52 includes a rough surface 58. More specifically, the present invention can adjust the etching parameters when patterning MTJ 52 so that the rough surface 58 appears only on a portion of the sidewall of MTJ 52, for example, as shown in FIG. Figure 5 As shown, it only appears on the sidewall of the fixed layer 40 of the MTJ 52. Figure 6 As shown, it only appears on the sidewalls of the barrier layer 42 of the MTJ 52, or as shown in FIG. Figure 7 Only the sidewalls of the free layer 44 of the MTJ 52 are shown, and these are all within the scope of the present invention.

[0049] Please also refer to Figures 8 to 10 , Figures 8 to 10 Schematic diagram of the structure of semiconductor components according to different embodiments of the present invention. Figures 8 to 10As shown, compared to the aforementioned embodiment in which the rough surface 58 only appears on one of the fixed layer 40, the barrier layer 42, or the free layer 44, according to other embodiments of the present invention, the etching parameters relative to each material layer can be adjusted when patterning the MTJ 52 so that the rough surface 58 appears on part of the sidewalls of the fixed layer 40, the barrier layer 42, and / or the free layer 44. For example, Figure 8 As shown, a rough surface 58 is formed on the sidewalls of the fixed layer 40 and the free layer 44, but the sidewalls of the barrier layer 42 are still flat. Figure 9 As shown, a rough surface 58 is formed on the sidewalls of the fixed layer 40 and the barrier layer 42, but the sidewall of the free layer 44 is still a flat surface, or as shown in FIG. Figure 10 As shown, rough surfaces 58 are formed on the sidewalls of the barrier layer 42 and the free layer 44 , but the sidewalls of the pinned layer 40 remain flat, which are all within the scope of the present invention.

[0050] In addition, according to another embodiment of the present invention, compared with the aforementioned embodiment in which the rough surface 58 only appears on the side walls of each MTJ 52, 54, the present invention can adjust the parameters of the etching process when patterning the MTJs 52, 54 so that the rough surface can be provided not only on the side walls of each MTJ 52, 54, but also on the side walls of the lower electrode 38 and / or the upper electrode 48. These variations are all within the scope of the present invention.

[0051] In summary, when the MTJ stack structure 46 is currently patterned using reactive ion etching (RIE) and / or ion beam etching (IBE) processes to form MTJs 52 and 54, not only will the metal sputtering rebound to the sidewalls of the MTJs 52 and 54 affect the magnetic performance of the MTJs 52 and 54, but the characteristics of IBE etching may also easily cause the top surface of the intermetallic dielectric layer 28 on both sides of the MTJs 52 and 54 to have excessive curvature. Therefore, the present invention preferably repeats the aforementioned etching process using hydrochloric acid and / or chlorine as the main etching components and the deposition process including methyl chloride to replace the current reactive ion etching and / or ion beam etching, so as to form polymer 56 on the sidewalls of the MTJs 52 and 54 while patterning the MTJ stack structure 46 to form the MTJs 52 and 54, thereby protecting the sidewalls of the MTJs 52 and 54 from being damaged by the bombardment of metal atoms during the patterning process.

[0052] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: Include: forming a magnetic tunneling junction (MTJ) stack structure on a substrate; forming a bottom electrode below the magnetic tunnel junction; forming a top electrode above the magnetic tunnel junction; (a) performing an etching process to remove a portion of the upper electrode, a portion of the magnetic tunnel junction stack structure, and a portion of the lower electrode to form a magnetic tunnel junction; as well as (b) performing a deposition process to form a polymer on the sidewalls of the magnetic tunnel junction, wherein the polymer exposes the sidewalls of the upper electrode and the sidewalls of the lower electrode.

2. The method of claim 1, further comprising repeating steps (a) and (b).

3. The method of claim 1, wherein the etching process comprises hydrochloric acid or chlorine gas. The method of claim 1 , wherein the deposition process comprises methyl chloride. The method of claim 1 , further comprising removing the polymer to form a rough surface on the magnetic tunnel junction sidewall.

6. The method of claim 5, further comprising removing the polymer using sulfuric acid and hydrofluoric acid. The method of claim 5 , wherein the rough surface comprises a wavy surface. The method according to claim 5 , wherein the sidewall of the bottom electrode comprises the rough surface.

9. A semiconductor device manufactured by the method according to claim 1, characterized in that Include: A magnetic tunneling junction (MTJ) is provided on a substrate, wherein a sidewall of the MTJ comprises a rough surface.

10. The semiconductor device according to claim 9, further comprising: a lower electrode disposed below the magnetic tunnel junction; and The upper electrode is disposed above the magnetic tunnel junction.

11. The semiconductor device as claimed in claim 10, wherein the sidewall of the bottom electrode comprises the rough surface.

12. The semiconductor device according to claim 9, wherein the magnetic tunnel junction comprises: a fixed layer disposed on the substrate; a barrier layer disposed on the fixed layer; and The free layer is disposed on the barrier layer. 13 . The semiconductor device as claimed in claim 12 , wherein the sidewall of the fixed layer comprises the rough surface. The semiconductor device as claimed in claim 12 , wherein the barrier layer sidewall comprises the rough surface. The semiconductor device as claimed in claim 12 , wherein the free layer sidewall comprises the rough surface. 16 . The semiconductor device as claimed in claim 12 , wherein the fixed layer sidewall and the free layer sidewall comprise the rough surface. The semiconductor device as claimed in claim 9 , wherein the rough surface comprises a wavy surface.

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