Semiconductor element and method for manufacturing the same

Abstract

The present invention discloses a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device comprises the following steps: first forming an intermetallic dielectric layer on a substrate, then forming a groove in the intermetallic dielectric layer, forming a synthetic antiferromagnetic layer in the groove, forming a metal layer on the synthetic antiferromagnetic layer, planarizing the metal layer and the synthetic antiferromagnetic layer to form a metal interconnect, and finally forming a magnetic tunneling junction (MTJ) on the metal interconnect.

Description

Technical Field

[0001] The present invention relates to a semiconductor element and a manufacturing method thereof, and in particular to a magnetoresistive random access memory (MRAM) and a manufacturing method thereof. Background Art

[0002] The magnetoresistance (MR) effect is known to occur when a material's electrical resistance changes with an applied magnetic field. Its physical quantity is defined as the difference in resistance in the presence and absence of a magnetic field divided by the original resistance, representing the rate of change of resistance. Currently, the magnetoresistance effect has been successfully applied to hard drive production and holds significant commercial value. Furthermore, by exploiting the characteristic of giant magnetoresistance materials exhibiting varying resistance values under different magnetization states, magnetic random access memory (MRAM) can be fabricated, which has the advantage of retaining stored data even when power is off.

[0003] The magnetoresistance effect is also used in the field of magnetic field sensing. For example, the electronic compass components of the global positioning system (GPS) in mobile phones are used to provide information such as the user's movement direction. Currently, there are various magnetic field sensing technologies on the market, such as anisotropic magnetoresistance (AMR) sensing elements, giant magnetoresistance (GMR) sensing elements, magnetic tunneling junction (MTJ) sensing elements, etc. However, the disadvantages of the above-mentioned existing technologies generally include: larger chip area, more expensive manufacturing process, higher power consumption, insufficient sensitivity, and susceptibility to temperature changes, etc., and further improvement is necessary. Summary of the Invention

[0004] One embodiment of the present invention discloses a method for fabricating a semiconductor device. The method includes first forming an intermetallic dielectric (IMD) layer on a substrate, then forming a recess in the IMD layer, forming a synthetic antiferromagnetic (SAM) layer in the recess, forming a metal layer on the SAM layer, planarizing the metal layer and SAM layer to form a metal interconnect, and finally forming a magnetic tunneling junction (MTJ) on the metal interconnect.

[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a metal interconnect disposed on a substrate and a magnetic tunneling junction (MTJ) disposed on the metal interconnect, wherein the metal interconnect further includes a first barrier layer disposed on the substrate, a synthetic antiferromagnetic layer disposed on the first barrier layer, a second barrier layer disposed on the synthetic antiferromagnetic layer, and a metal layer disposed on the second barrier layer.

[0006] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a metal interconnect disposed on a substrate and a magnetic tunneling junction (MTJ) disposed on the metal interconnect, wherein the metal interconnect includes a metal layer, a first synthetic antiferromagnetic layer disposed on one side of the metal layer, and a second synthetic antiferromagnetic layer disposed on the other side of the metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1 to 3 A schematic diagram of a method for manufacturing an MRAM cell according to an embodiment of the present invention;

[0008] Figures 4 to 9 FIG. 1 is a schematic diagram of a method for fabricating an MRAM cell according to an embodiment of the present invention.

[0009] Description of main component symbols

[0010] 12: Base

[0011] 14: MRAM area

[0012] 16: Interlayer dielectric layer

[0013] 18: Metal interconnect structure

[0014] 20: Intermetallic dielectric layer

[0015] 22: Metal interconnects

[0016] 24: Barrier layer

[0017] 26:Metal layer

[0018] 28: Stop layer

[0019] 30: Intermetallic dielectric layer

[0020] 32: Groove

[0021] 34: Barrier layer

[0022] 36: Synthetic Antiferromagnetic Layer

[0023] 38: Barrier layer

[0024] 40:Metal layer

[0025] 42: Metal interconnects

[0026] 44: First ferromagnetic layer

[0027] 46: Spacer layer

[0028] 48: Second ferromagnetic layer

[0029] 50: lower electrode

[0030] 52: Fixed layer

[0031] 54: Spacer layer

[0032] 56: Reference layer

[0033] 58: Barrier layer

[0034] 60: Free layer

[0035] 62:MTJ stacking structure

[0036] 64: Upper electrode

[0037] 66:MTJ

[0038] 68: Covering layer

[0039] 70: Intermetallic dielectric layer

[0040] 72:Metal interconnect

[0041] 74: Stop layer

[0042] 82: Groove

[0043] 84: First synthetic antiferromagnetic layer

[0044] 86: Second synthetic antiferromagnetic layer DETAILED DESCRIPTION

[0045] Please refer to Figures 1 to 3 , Figures 1 to 3 Schematic diagram of a method for manufacturing a semiconductor device, or more specifically, an MRAM cell, according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, for example, a substrate 12 made of a semiconductor material, wherein the semiconductor material can be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and an MRAM region 14 and a logic region (not shown) are preferably defined on the substrate 12.

[0046] The substrate 12 may include active devices such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers, and dielectric layers such as an interlayer dielectric (ILD) 16 covering the substrate 12. More specifically, the substrate 12 may include planar or non-planar MOS transistors (e.g., fin-structured transistors), wherein the MOS transistors may include a gate structure (e.g., a metal gate) and transistor components such as source / drain regions, spacers, epitaxial layers, and contact etch stop layers. The ILD 16 may be disposed on the substrate 12 and cover the MOS transistors. The ILD 16 may include a plurality of contact plugs electrically connected to the gate and / or source / drain regions of the MOS transistors. The fabrication processes for planar or non-planar transistors and ILDs are well known in the art and are not further described herein.

[0047] Then, a metal interconnect structure 18 is formed on the interlayer dielectric layer 16 to electrically connect to the aforementioned contact plugs, wherein the metal interconnect structure 18 includes an intermetallic dielectric layer 20 and metal interconnects 22 embedded in the intermetallic dielectric layer 20. In the present embodiment, the metal interconnects 22 in the metal interconnect structure 18 preferably include a trench conductor, and the metal interconnects 22 in the metal interconnect structure 18 can be embedded in the intermetallic dielectric layer 20 according to a single damascene process or a dual damascene process and electrically connected to each other. For example, each metal interconnect 22 may further include a barrier layer 24 and a metal layer 26. The barrier layer 24 may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer 26 may be selected from the group consisting of, but not limited to, tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), and the like. Single-damascene or dual-damascene fabrication processes are well known in the art and will not be further described herein. Furthermore, in this embodiment, the metal layer 26 of the metal interconnect 18 preferably comprises copper, and the intermetallic dielectric layer 20 preferably comprises silicon oxide or an ultra-low-k dielectric layer, but is not limited thereto.

[0048] A stop layer 28 and another IMD layer 30 are then sequentially formed on the IMD layer 20. A photolithography and etching process is then performed to remove a portion of the IMD layer 30 to form at least one recess 32 in the IMD layer 30. A barrier layer 34, a synthetic antiferromagnetic (SAF) layer 36, another barrier layer 38, and a metal layer 40 are then sequentially formed in the recess 32 to fill the recess 32. A planarization process, such as chemical mechanical polishing (CMP), is then performed to remove a portion of the metal layer 40, a portion of the barrier layer 38, a portion of the SAF layer 36, and a portion of the barrier layer 34 to form a metal interconnect 42 or a contact plug in the recess 32.

[0049] In this embodiment, the synthetic antiferromagnetic layer 36 preferably includes a composite structure that can generate a reverse magnetic field, for example, further comprising a first ferromagnetic layer 44, a spacer 46 disposed on the first ferromagnetic layer 44, and a second ferromagnetic layer 48 disposed on the spacer 46, wherein the first ferromagnetic layer 44 and the second ferromagnetic layer 48 preferably include ferromagnetic materials such as cobalt-iron-boron (CoFeB) and the spacer 46 includes a non-magnetic layer composed of a non-magnetic material.

[0050] Generally, as the thickness of the barrier layer in the metal interconnect directly below a magnetic tunneling junction (MTJ) increases, the exchange coupling between the reference layer and the pinned layer in the upper MTJ decreases, affecting the MTJ's performance. To improve this phenomenon, the present invention preferably forms a synthetic antiferromagnetic layer 36 between the two barrier layers 34 and 38. The reverse magnetic field generated by the synthetic antiferromagnetic layer 36 balances the stray field of the subsequent MTJ, preventing the exchange coupling between the reference layer and the pinned layer from decreasing and impacting the MTJ's performance.

[0051] Like metal interconnect 22, metal interconnect 42 formed in this stage can be inlaid in the intermetallic dielectric layer using a single damascene process or a dual damascene process. The lower barrier layer 34 preferably comprises a metal such as titanium, the upper barrier layer 38 preferably comprises a metal nitride such as titanium nitride, and the metal layer 40 preferably comprises tungsten, but the materials are not limited thereto. According to other embodiments of the present invention, barrier layers 34 and 38 can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer 40 can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. In addition, the stop layer 28 may include a nitrogen doped carbide layer (NDC), silicon nitride, or silicon carbon nitride (SiCN), and the intermetallic dielectric layer 30 may include silicon oxide or an ultra-low-k dielectric layer.

[0052] Next, a lower electrode 50 may be formed on the surface of the intermetal dielectric layer 30 and the metal interconnect 42. An MTJ stack structure 62 consisting of a pinned layer 52, a spacer layer 54, a reference layer 56, a barrier layer 58, and a free layer 60 may be formed on the lower electrode 50. An upper electrode 64 may also be formed on the MTJ stack structure 62. The free layer 60 may optionally include a first free layer (not shown) disposed on the barrier layer 58, a stop layer (not shown) disposed on the first free layer, and a second free layer (not shown) disposed on the stop layer.

[0053] In this embodiment, the lower electrode layer 50 and the upper electrode 64 preferably include conductive materials, such as but not limited to tantalum (Ta), platinum (Pt), copper (Cu), gold (Au), aluminum (Al) or a combination thereof. The fixed layer 52 may include ferromagnetic materials such as but not limited to cobalt iron boron (CoFeB), cobalt iron (CoFe), iron (Fe), cobalt (Co), etc., to fix or limit the direction of the magnetic moment of the adjacent layer. The spacer layer 54 may include a metal such as but not limited to tantalum. The reference layer 56 is preferably provided between the spacer layer 54 and the barrier layer 58, which may include a ferromagnetic material such as iron, cobalt, nickel or an alloy thereof such as cobalt iron boron (CoFeB), but not limited thereto. The barrier layer 58 may be composed of an insulating material including an oxide, such as aluminum oxide (AlO). x) or magnesium oxide (MgO), but are not limited thereto. The free layer 60, including the first and second free layers, can be made of a ferromagnetic material, such as iron, cobalt, nickel, or alloys thereof, such as cobalt-iron-boron (CoFeB) or nickel-iron (NiFe), but are not limited thereto. The magnetization direction of the free layer 60 is "free" to change in response to an external magnetic field.

[0054] Then as Figure 2 As shown, one or more etching processes are performed using a patterned mask (not shown) as a mask to remove a portion of the upper electrode 64, a portion of the MTJ stack structure 62, a portion of the lower electrode 50, and a portion of the intermetallic dielectric layer 30 to form an MTJ 66 on the metal interconnect 42. It is worth noting that the etching process performed in patterning the MTJ stack structure 62 and the intermetallic dielectric layer 30 in this embodiment may include a reactive ion etching process (RIE) and / or an ion beam etching process (IBE). Due to the characteristics of the ion beam etching process, the top surface of the remaining intermetallic dielectric layer 30 is preferably slightly lower than the top surface of the metal interconnect 42, and the top surface of the intermetallic dielectric layer 30 preferably has a curved or arc-shaped surface.

[0055] Then Figure 3 As shown, a capping layer 68 is formed on the MTJ 66 and covers the surface of the IMD layer 30. An IMD layer 70 is formed on the capping layer 68. One or more photolithography and etching processes are then performed to remove portions of the IMD layer 70 and the capping layer 68 to form contact holes (not shown). Conductive material is then filled into each contact hole and a planarization process such as CMP is performed to form metal interconnects 72 connected to the upper electrode 64 below. Finally, another stop layer 74 is formed on the IMD layer 70 and covers the metal interconnects 72.

[0056] In this embodiment, cap layer 68 preferably comprises silicon nitride, but other dielectric materials may be selected depending on process requirements, such as silicon oxide, silicon oxynitride, or silicon carbide nitride. Stop layer 74 may be selected from the group consisting of nitrogen doped carbide (NDC), silicon nitride, and silicon carbon nitride (SiCN), and preferably comprises silicon carbide nitride. Similar to the metal interconnects 22 formed above, each metal interconnect 72 disposed within IMD layer 70 may be inlaid within the IMD layer using either a single damascene process or a dual damascene process. For example, each metal interconnect 72 may further include a barrier layer and a metal layer, wherein the barrier layer may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer may be selected from the group consisting of, but not limited to, tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. Since single-damascene or dual-damascene fabrication processes are well known in the art, they will not be further described here. This completes the fabrication of a semiconductor device according to one embodiment of the present invention.

[0057] Please continue to refer to Figures 4 to 9 , Figures 4 to 9 FIG1 is a schematic diagram of a method for manufacturing an MRAM cell according to an embodiment of the present invention, wherein for the sake of simplicity, the same components disclosed in this embodiment and the previous embodiment preferably use the same reference numerals. Figure 4 As shown, a substrate 12 is first provided, for example, a substrate 12 made of a semiconductor material, wherein the semiconductor material can be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and an MRAM region 14 and a logic region (not shown) are preferably defined on the substrate 12.

[0058] The substrate 12 may include active devices such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers, and dielectric layers such as an interlayer dielectric (ILD) 16 covering the substrate 12. More specifically, the substrate 12 may include planar or non-planar MOS transistors (e.g., fin-structured transistors). The MOS transistors may include a gate structure (e.g., a metal gate) and transistor components such as source / drain regions, spacers, epitaxial layers, and contact etch stop layers. The ILD 16 may be disposed on the substrate 12 and cover the MOS transistors. The ILD 16 may include a plurality of contact plugs electrically connected to the gate and / or source / drain regions of the MOS transistors. The fabrication processes for planar or non-planar transistors and ILDs are well known in the art and are not further described herein.

[0059] Then, a metal interconnect structure 18 is formed on the interlayer dielectric layer 16 to electrically connect to the aforementioned contact plugs, wherein the metal interconnect structure 18 includes an intermetallic dielectric layer 20 and metal interconnects 22 embedded in the intermetallic dielectric layer 20. In the present embodiment, the metal interconnects 22 in the metal interconnect structure 18 preferably include a trench conductor, and the metal interconnects 22 in the metal interconnect structure 18 can be embedded in the intermetallic dielectric layer 20 according to a single damascene process or a dual damascene process and electrically connected to each other. For example, each metal interconnect 22 may further include a barrier layer 24 and a metal layer 26. The barrier layer 24 may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer 26 may be selected from the group consisting of, but not limited to, tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), and the like. Single-damascene or dual-damascene fabrication processes are well known in the art and will not be further described herein. Furthermore, in this embodiment, the metal layer 26 of the metal interconnect 18 preferably comprises copper, and the intermetallic dielectric layer 20 preferably comprises silicon oxide or an ultra-low-k dielectric layer, but is not limited thereto.

[0060] A stop layer 28 and another IMD layer 30 are then sequentially formed on the IMD layer 20. A photolithography and etching process is then performed to remove portions of the IMD layer 30 and the stop layer 28 to form at least one recess 32 in the IMD layer 30. A barrier layer 34 and a metal layer 40 are then sequentially formed in the recess 32 to fill the recess 32. A planarization process, such as chemical mechanical polishing (CMP), is then performed to remove portions of the metal layer 40 and the barrier layer 34 to form a metal interconnect 42 or a contact plug in the recess 32.

[0061] Like metal interconnect 22, metal interconnect 42 formed in this stage can be inlaid in IMD layer 30 using a single damascene process or a dual damascene process. Barrier layer 34 can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). Metal layer 40 preferably includes tungsten (W), but can also be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. Stop layer 28 can include nitrogen doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN). IMD layer 30 can include silicon oxide or an ultra-low-k dielectric layer.

[0062] like Figure 5 As shown, an etching process is then performed, for example, without forming a patterned mask, by utilizing the selectivity between the metal layer 40 and the barrier layer 32 to remove a portion of the barrier layer 32 to form grooves 82 on both sides of the metal layer 40 .

[0063] like Figure 6As shown, a synthetic antiferromagnetic (SAF) layer 36 is then formed on the surfaces of the intermetal dielectric layer 30 and the metal layer 40 and fills the groove 82 but does not completely fill the groove 82. As in the previous embodiment, the synthetic antiferromagnetic layer 36 preferably includes a composite structure capable of generating a reverse magnetic field, for example, including a first ferromagnetic layer 44, a spacer 46 disposed on the first ferromagnetic layer 44, and a second ferromagnetic layer 48 disposed on the spacer 46. The first ferromagnetic layer 44 and the second ferromagnetic layer 48 preferably include ferromagnetic materials such as cobalt-iron-boron (CoFeB), and the spacer 46 includes a non-magnetic layer made of a non-magnetic material.

[0064] like Figure 7 As shown, a planarization process is then performed, such as using a chemical mechanical polishing (CMP) process to remove a portion of the synthetic antiferromagnetic layer 36, a portion of the metal layer 40, and a portion of the intermetallic dielectric layer 30 to form a first synthetic antiferromagnetic layer 84 on one side of the metal layer 40 and a second synthetic antiferromagnetic layer 86 on the other side of the metal layer 40. Structurally, the first ferromagnetic layer 44 and the spacer layer 46 in the first synthetic antiferromagnetic layer 84 and the second synthetic antiferromagnetic layer 86 preferably have a substantially L-shaped cross-section after the planarization process, while the second ferromagnetic layer 48 maintains a horizontal shape. The tops of the first ferromagnetic layer 44, the spacer layer 46, and the second ferromagnetic layer 48 are preferably flush with the tops of the intermetallic dielectric layer 30 and the metal layer 40. It should also be noted that although the first synthetic antiferromagnetic layer 84 and the second synthetic antiferromagnetic layer 86 are respectively arranged on the left and right sides of the metal layer 40 from a cross-sectional view, if viewed from above, the first synthetic antiferromagnetic layer 84 and the second synthetic antiferromagnetic layer 86 are preferably a single structure in the form of a ring and surround the entire metal layer 40.

[0065] Subsequently, an MTJ can be formed on the metal interconnect 42, the first synthetic antiferromagnetic layer 84, the second synthetic antiferromagnetic layer 86, and the metal layer 40, similar to the above-described embodiments. For example, a lower electrode 50 can be formed on the surfaces of the intermetal dielectric layer 30 and the metal interconnect 42. An MTJ stack structure 62 consisting of a pinned layer 52, a spacer layer 54, a reference layer 56, a barrier layer 58, and a free layer 60 can be formed on the lower electrode 50. A top electrode 64 can also be formed on the MTJ stack structure 62. The free layer 60 can optionally include a first free layer (not shown) disposed on the barrier layer 58, a stop layer (not shown) disposed on the first free layer, and a second free layer (not shown) disposed on the stop layer.

[0066] In this embodiment, the bottom electrode layer 50 and the top electrode 64 preferably comprise a conductive material, such as, but not limited to, tantalum (Ta), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), or a combination thereof. The pinned layer 52 may comprise a ferromagnetic material, such as, but not limited to, cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), iron (Fe), or cobalt (Co), to pin or constrain the magnetic moment direction of adjacent layers. The spacer layer 54 may comprise a metal, such as, but not limited to, tantalum. The reference layer 56 is preferably disposed between the spacer layer 54 and the barrier layer 58 and may comprise a ferromagnetic material, such as, but not limited to, iron, cobalt, nickel, or alloys thereof, such as, but not limited to, cobalt-iron-boron (CoFeB). The barrier layer 58 may be comprised of an insulating material comprising an oxide, such as, but not limited to, aluminum oxide (AlOx) or magnesium oxide (MgO). The free layer 60, including the first free layer and the second free layer, can be made of a ferromagnetic material, such as, but not limited to, iron, cobalt, nickel, or alloys thereof, such as cobalt-iron-boron (CoFeB) and nickel-iron (NiFe). The magnetization direction of the free layer 60 is "free" to change in response to an external magnetic field.

[0067] Then as Figure 8As shown, one or more etching processes are performed using a patterned mask (not shown) as a mask to remove a portion of the upper electrode 64, a portion of the MTJ stack structure 62, a portion of the lower electrode 50, and a portion of the intermetallic dielectric layer 30 to form an MTJ 66 on the metal interconnect 42. As in the previous embodiment, the etching process performed in patterning the MTJ stack structure 62 and the intermetallic dielectric layer 30 in this embodiment may include a reactive ion etching process (RIE) and / or an ion beam etching process (IBE). Due to the characteristics of the ion beam etching process, the top surface of the remaining intermetallic dielectric layer 30 is preferably slightly lower than the top surface of the metal interconnect 42, and the top surface of the intermetallic dielectric layer 30 preferably has a curved or arcuate shape.

[0068] Then as Figure 9 As shown, a capping layer 68 is formed on the MTJ 66 and covers the surface of the IMD layer 30. An IMD layer 70 is formed on the capping layer 68. One or more photolithography and etching processes are then performed to remove portions of the IMD layer 70 and the capping layer 68 to form contact holes (not shown). Conductive material is then filled into each contact hole and a planarization process such as CMP is performed to form metal interconnects 72 connected to the upper electrode 64 below. Finally, another stop layer 74 is formed on the IMD layer 70 and covers the metal interconnects 72.

[0069] In this embodiment, cap layer 68 preferably comprises silicon nitride, but other dielectric materials may be selected depending on process requirements, such as silicon oxide, silicon oxynitride, or silicon carbide nitride. Stop layer 74 may be selected from the group consisting of nitrogen doped carbide (NDC), silicon nitride, and silicon carbon nitride (SiCN), and preferably comprises silicon carbide nitride. Similar to the metal interconnects 22 formed above, each metal interconnect 72 disposed within IMD layer 70 may be inlaid within the IMD layer using either a single damascene process or a dual damascene process. For example, each metal interconnect 72 may further include a barrier layer and a metal layer, wherein the barrier layer may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer may be selected from the group consisting of, but not limited to, tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. Since single-damascene or dual-damascene fabrication processes are well known in the art, they will not be further described here. This completes the fabrication of a semiconductor device according to one embodiment of the present invention.

[0070] In summary, as the thickness of the barrier layer in the metal interconnect directly below the magnetic tunneling junction (MTJ) increases, the exchange coupling between the reference layer and the pinned layer in the upper magnetic tunneling junction decreases, affecting the performance of the magnetic tunneling junction. To improve this phenomenon, the present invention can provide at least one synthetic antiferromagnetic layer between the MTJ and the metal interconnect directly below, such as Figures 1 to 3 In the embodiment, a synthetic antiferromagnetic layer 36 having a roughly U-shaped cross section is formed between the two barrier layers 34 and 38, or as Figures 4 to 9 In the embodiment, a first synthetic antiferromagnetic layer 84 and a second synthetic antiferromagnetic layer 86 are formed on both sides of the metal layer 40, respectively, and the stray field of the upper magnetic tunnel junction is balanced by the reverse magnetic field generated by the synthetic antiferromagnetic layer, so that the exchange coupling value between the reference layer and the fixed layer is not reduced and affects the performance of the magnetic tunnel junction.

[0071] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: Include: forming an intermetallic dielectric layer on the substrate; forming a groove in the intermetal dielectric layer; forming a synthetic antiferromagnetic layer in the groove; forming a metal layer on the synthetic antiferromagnetic layer; as well as planarizing the metal layer and the synthetic antiferromagnetic layer to form metal interconnects on the substrate; as well as A magnetic tunneling junction (MTJ) is formed on the metal interconnect.

2. The method according to claim 1, further comprising: forming a first barrier layer in the groove; forming the synthetic antiferromagnetic layer on the first barrier layer; and A second barrier layer is formed on the synthetic antiferromagnetic layer. The method of claim 2 , wherein the first barrier layer comprises titanium. The method of claim 2 , wherein the second barrier layer comprises titanium nitride.

5. The method of claim 1 , wherein the synthetic antiferromagnetic layer comprises: a first ferromagnetic layer; a spacer layer disposed on the first ferromagnetic layer; and The second ferromagnetic layer is disposed on the spacer layer. 6 . The method of claim 5 , wherein the first ferromagnetic layer and the second ferromagnetic layer comprise cobalt-iron-boron (CoFeB). The method of claim 5 , wherein the spacer layer comprises a non-magnetic layer.

8. A semiconductor device, characterized in that: Include: A metal interconnect disposed on the substrate, wherein the metal interconnect comprises a synthetic antiferromagnetic layer; A magnetic tunneling junction (MTJ) is provided on the metal interconnect; and An intermetallic dielectric layer surrounds the metal interconnect, wherein a bottom surface of the magnetic tunnel junction is higher than a top surface of the intermetallic dielectric layer.

9. The semiconductor device as claimed in claim 8, wherein the metal interconnect further comprises: A first barrier layer is disposed on the substrate; The synthetic antiferromagnetic layer is disposed on the first barrier layer; a second barrier layer disposed on the synthetic antiferromagnetic layer; and The metal layer is disposed on the second barrier layer. 10 . The semiconductor device as claimed in claim 9 , wherein the first barrier layer comprises titanium. The semiconductor device as claimed in claim 9 , wherein the second barrier layer comprises titanium nitride.

12. The semiconductor device according to claim 9, wherein the synthetic antiferromagnetic layer comprises: a first ferromagnetic layer; a spacer layer disposed on the first ferromagnetic layer; and The second ferromagnetic layer is disposed on the spacer layer. 13 . The semiconductor device of claim 12 , wherein the first ferromagnetic layer and the second ferromagnetic layer comprise cobalt-iron-boron (CoFeB). The semiconductor device as claimed in claim 12 , wherein the spacer layer comprises a non-magnetic layer.

15. A semiconductor device, characterized in that: Include: A metal interconnect is provided on the substrate, wherein the metal interconnect comprises: Metal layer; a first synthetic antiferromagnetic layer disposed on one side of the metal layer; and a second synthetic antiferromagnetic layer disposed on the other side of the metal layer; and A magnetic tunneling junction (MTJ) is provided on the metal interconnect, wherein top surfaces of the metal layer, the first synthetic antiferromagnetic layer and the second synthetic antiferromagnetic layer are coplanar.

16. The semiconductor device according to claim 15, further comprising: a barrier layer surrounding the metal layer; The first synthetic antiferromagnetic layer is disposed on the barrier layer on one side of the metal layer; and The second synthetic antiferromagnetic layer is disposed on the barrier layer at the other side of the metal layer.

17. The semiconductor device of claim 15, wherein each of the first synthetic antiferromagnetic layer and the second synthetic antiferromagnetic layer comprises: a first ferromagnetic layer; a spacer layer disposed on the first ferromagnetic layer; and The second ferromagnetic layer is disposed on the spacer layer. 18 . The semiconductor device of claim 17 , wherein the first ferromagnetic layer and the second ferromagnetic layer comprise cobalt-iron-boron (CoFeB). The semiconductor device as claimed in claim 17 , wherein the spacer layer comprises a non-magnetic layer.

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