Semiconductor devices and methods for manufacturing semiconductor devices

Abstract

Semiconductor devices and methods for manufacturing semiconductor devices are disclosed. In an embodiment, the semiconductor device includes: a substrate; a group III nitride-based transistor disposed on a front surface of the substrate; and a conductive through-substrate via. The conductive through-substrate via includes a via extending from the front surface of the substrate to a rear surface and a conductive material extending from the front surface of the substrate to the rear surface. The via tapers from the front surface of the substrate to the rear surface.

Description

Background Technology

[0001] To this day, transistors used in power electronics applications are typically fabricated using silicon (Si) semiconductor materials. Common transistor devices used in power applications include silicon. Silicon power MOSFETs and silicon insulated gate bipolar transistors (IGBTs) are being considered. Silicon carbide (SiC) power devices have recently been explored. Group III nitride-based semiconductor devices, such as gallium nitride (GaN) devices, are now emerging as attractive candidates for carrying high current densities, withstanding high breakdown voltages, and providing very low on-resistance, ultrafast switching times, and improved power efficiency.

[0002] In some lateral transistor devices, such as gallium nitride-based high electron mobility transistors (HEMTs), the source is coupled to the back side of a substrate on which the transistor structure is formed. The source can be coupled to the back surface of the substrate via a conductive through-substrate via (TSV).

[0003] Further improvements to the connection between the source and the rear surface of the substrate are desirable. Summary of the Invention

[0004] In one embodiment, the semiconductor device includes: a substrate; a group III nitride-based transistor disposed on a front surface of the substrate; and a conductive through-substrate via. The conductive through-substrate via includes a via extending from the front surface of the substrate to a rear surface and a conductive material extending from the front surface of the substrate to the rear surface. The via tapers from the front surface of the substrate to the rear surface.

[0005] In one embodiment, the semiconductor device includes: a substrate; a group III nitride-based transistor disposed on a front surface of the substrate; and a conductive through-substrate via. The conductive through-substrate via includes: a via extending from a front surface of the substrate to a rear surface; a conductive plug filling a first portion of the via; and a conductive pad layer lining the sidewalls of a second portion of the via and electrically coupled to the conductive plug.

[0006] In one embodiment, the semiconductor device includes: a substrate; a group III nitride-based transistor disposed on a front surface of the substrate; and a conductive through-substrate via. The conductive through-substrate via includes: a via extending from the front surface of the substrate to a rear surface; and a conductive material extending from the front surface of the substrate to the rear surface and extending to a first surface of the substrate adjacent to the via.

[0007] In one embodiment, the method includes: forming an opening in a front surface of a substrate, the substrate including at least one group III nitride-based transistor on a first surface; inserting a conductive material into the opening; and using the conductive material to couple a source electrode of the group III nitride-based transistor to a rear surface of the substrate.

[0008] Those skilled in the art will recognize the additional features and advantages when reading the following detailed description and when viewing the accompanying drawings. Attached Figure Description

[0009] The elements in the accompanying drawings are not necessarily to scale with respect to each other. The same reference numerals indicate corresponding similar parts. Features of the various illustrated embodiments can be combined unless they are mutually exclusive. Exemplary embodiments are depicted in the drawings and described in detail below.

[0010] Figure 1 The illustration shows a cross-sectional view of a semiconductor device including a group III nitride-based transistor and a conductive through-substrate via (TSV).

[0011] Figure 2a The illustration shows a cross-sectional view of a semiconductor device including a group III nitride-based transistor and a conductive through-substrate via (TSV).

[0012] Figure 2b The illustration shows a cross-sectional view of a semiconductor device including a group III nitride-based transistor and a conductive through-substrate via (TSV).

[0013] Figure 3a The illustration shows a cross-sectional view of a semiconductor device including a group III nitride-based transistor and a conductive through-substrate via (TSV).

[0014] Figure 3b The illustration shows a cross-sectional view of a semiconductor device including a group III nitride-based transistor and a conductive through-substrate via (TSV).

[0015] Figure 4a Illustration Figure 3b The plan view of the semiconductor device and the connection between the conductive through-substrate via and the group III nitride-based transistor;

[0016] Figure 4b The diagram shows along Figure 4a A cross-sectional view of line AA, and the connection between the conductive through-substrate via and the group III nitride-based transistor;

[0017] Figure 4c The diagram shows a cross-sectional view of the connection between a conductive through-substrate via and a group III nitride-based transistor.

[0018] Figure 5a Illustration Figure 2b and Figure 3b A cross-sectional view of a conductive through-substrate via;

[0019] Figure 5b Illustration Figure 2b and Figure 3b A cross-sectional view of a conductive through-substrate via;

[0020] Figure 6 The diagram illustrates a flowchart of a method for fabricating conductive through-substrate vias.

[0021] Figure 7 The illustration shows a flowchart of a method for fabricating a group III nitride-based transistor device with conductive through-substrate vias;

[0022] Figure 8 The figure shows a cross-sectional view of the initial semiconductor substrate;

[0023] Figure 9 The diagram shows a device with a blind hole. Figure 8 A cross-sectional view of the initial semiconductor substrate;

[0024] Figure 10 The illustration is in Figure 9 A cross-sectional view of the conductive plug at the bottom of the blind hole;

[0025] Figure 11 Illustration Figure 10 An enlarged view of the upper part of the blind hole;

[0026] Figure 12 The figure shows a cross-sectional view of the conductive layer arranged on the conductive plug and surrounding the covered gap.

[0027] Figure 13 The figure shows a cross-sectional view of the cavity formed in the blind hole above the conductive plug;

[0028] Figure 14 The illustration shows cross-sectional views after metallization is formed on a group III nitride-based transistor and after the back surface is processed to form conductive through-substrate vias.

[0029] Figure 15 The illustration shows a cross-sectional view of a semiconductor device with a group III nitride-based transistor coupled to a conductive through-substrate via that is substantially filled using a dual damascene technique.

[0030] Figure 16 The figure shows a cross-sectional view of a semiconductor device with a group III nitride-based transistor coupled to a conductive through-substrate via formed by a single damascene technique.

[0031] Figure 17The figure shows a cross-sectional view of a semiconductor device with a group III nitride-based transistor coupled to a conductive through-substrate via formed by a single damascene technique.

[0032] Figure 18 The figure shows a cross-sectional view of a semiconductor device having a group III nitride-based transistor and conductive through-substrate vias formed in multiple epitaxial group III nitride layers using a dual damascene technique.

[0033] Figure 19 Illustration Figure 18 A plan view of a semiconductor device;

[0034] Figure 20 The figure shows a cross-sectional view of a semiconductor device having a group III nitride-based transistor and conductive through-substrate vias formed in multiple epitaxial group III nitride layers by a single damascene technique.

[0035] Figure 21 The figure shows a cross-sectional view of a semiconductor device having a group III nitride-based transistor and conductive through-substrate vias formed in multiple epitaxial group III nitride layers using a single damascene technique. Detailed Implementation

[0036] In the following detailed description, reference is made to the accompanying drawings, which form part of this document and illustrate by way of illustration specific embodiments in which the invention may be practiced. In this regard, the orientation of the figures(s) being described uses directional terms such as “top,” “bottom,” “front,” “rear,” “forward,” “tailward,” etc. Because components of the embodiments can be positioned in many different orientations, the directional terms are used for illustrative purposes and are by no means limiting. It is to be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the invention. The following detailed description is not to be taken in a limiting sense, and the scope of the invention is defined by the appended claims.

[0037] Many exemplary embodiments will be explained below. In this context, the same structural features are identified by the same or similar reference numerals in the figures. In the context of this description, “lateral” or “lateral direction” should be understood to mean a direction or limit generally parallel to the lateral limits of the semiconductor material or semiconductor carrier. Thus, the lateral direction generally extends parallel to these surfaces or sides. In contrast, the term “vertical” or “vertical direction” should be understood to mean a direction generally perpendicular to these surfaces or sides and therefore perpendicular to the lateral direction. Thus, the vertical direction travels in the thickness direction of the semiconductor material or semiconductor carrier.

[0038] As used in this specification, when an element such as a layer, region, or substrate is referred to as being "on" or "extending" to another element, it may be directly on or directly extending to the other element, or there may be an intermediate element present. In contrast, when an element is referred to as being "directly on" or "directly extending to" another element, there is no intermediate element present.

[0039] As used in this specification, when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0040] Depletion-type devices, such as high-voltage depletion-type transistors, have a negative threshold voltage, meaning they can conduct current at zero gate voltage. These devices are typically on. Enhancement-type devices, such as low-voltage enhancement-type transistors, have a positive threshold voltage, meaning they cannot conduct current at zero gate voltage and are typically off. Enhancement-type devices are not limited to low-voltage devices and can also be high-voltage devices.

[0041] As used herein, a "high-voltage device," such as a high-voltage depletion-mode transistor, is an electronic device optimized for high-voltage switching applications. That is, when the transistor is off, it can block high voltages such as approximately 300V or higher, approximately 600V or higher, or approximately 1200V or higher, and when the transistor is on, it has a sufficiently low on-resistance (RON) for the application in which it is used, i.e., it experiences sufficiently low conduction losses when a substantial current passes through the device. A high-voltage device can block at least a voltage equal to the high-voltage supply or the maximum voltage in the circuit in which it is used. A high-voltage device may be able to block 300V, 600V, 1200V, or other suitable blocking voltages required by the application.

[0042] As used herein, the phrase "Group III nitride" refers to a compound semiconductor comprising nitrogen (N) and at least one Group III element including aluminum (Al), gallium (Ga), indium (In), and boron (B), and including, but not limited to, any alloys thereof, such as, for example, aluminum gallium nitride (Al). x Ga (1-x) N), Indium gallium nitride (In y Ga (1-y) N), aluminum indium gallium nitride (Al) x In y Ga (1-x-y) gallium arsenide phosphide (GaAs) a P bN (1-a-b) ) and aluminum arsenide indium gallium phosphide (Al x In y Ga (1-x-y) As a P b N (1-a-b) AlGaN and AlGaN refer to aluminum gallium nitride (AlGaN) produced by the formula AlGaN. x Ga (1-x) N describes the alloy, where 0 <x<1。

[0043] Figure 1 The illustration includes a substrate 31 and a semiconductor device 30 comprising a group III nitride-based transistor 32 (such as a high electron mobility transistor (HEMT)) disposed on a front surface 33 of the substrate 31. The semiconductor device 30 also includes at least one conductive through-substrate via (TSV) 34.

[0044] The conductive through-substrate via 34 includes: a via or through-hole 35 extending from the front surface 33 of the substrate 31 to the rear surface 41; and a conductive material 36 also extending from the front surface 33 to the rear surface 41.

[0045] The conductive material 36 can be electrically coupled to the group III nitride-based transistor 32, for example, to the source electrode of the group III nitride-based transistor 32, so that the group III nitride-based transistor is electrically coupled to the rear surface 41 of the substrate 31. A conductive through-substrate via 34 is formed by introducing a via 35 into the front surface 33 of the substrate 31 adjacent to the group III nitride-based transistor 32. Introducing the via 35 from the front surface 33 allows the via 35 to be formed by processing one side of the substrate 31 on which the group III nitride-based transistor 32 is disposed. This can be used to assist in better positioning of the via 35 with respect to the group III nitride-based transistor 32 and to assist in the electrical coupling of the conductive material 36 to the group III nitride-based transistor 32.

[0046] The substrate 31 includes a front surface 33 capable of supporting the epitaxial growth of at least one group III nitride layer. The substrate 31 may include, for example,... <100> silicon wafers or <111> A semiconductor wafer made of silicon, silicon carbide, or sapphire. A group III nitride-based transistor 32 may include multiple group III nitride layers epitaxially grown on a front surface 33.

[0047] The group III nitride-based transistor 32 can have different structures. In some embodiments, the group III nitride-based transistor 32 is provided by a mesa 37 or a discrete region comprising multiple group III nitride layers providing a single switching device. At least the sides of the mesa 37 can be embedded in an insulating layer such as a SiO2 layer.

[0048] At the wafer level, substrate 31 may include a plurality of mesa 37, each providing a group III nitride-based transistor device 32, the mesa being spaced apart from each other on a front surface 33. Mesa 37 may have sides embedded in a common insulating layer. In some embodiments, conductive through-substrate vias 34 are arranged adjacent to the mesa 37 comprising the group III nitride-based transistor and spaced apart from the mesa 37 comprising the group III nitride-based transistor by a portion of substrate 31 and the insulating layer.

[0049] In other embodiments, a group III nitride-based transistor and a conductive through-substrate via are formed in a plurality of epitaxial group III nitride layers extending across the front surface of the substrate. The group III nitride-based transistor may be one of a plurality of transistor cells coupled in parallel. The conductive through-substrate via may be disposed within the cell domain.

[0050] The conductive through-substrate via 34 can take various forms. For example, the conductive material 36 can substantially fill, partially fill, or pad the via 35. The conductive through-substrate via 34 can have different lateral shapes. For example, the conductive through-substrate via can have a laterally elongated shape, such as a substantially rectangular shape, or it can have a square, circular, or hexagonal lateral shape.

[0051] Figure 2a The illustrated semiconductor device 50 includes a substrate 31, a group III nitride-based transistor 32 formed in a mesa 37 on the front surface 33 of the substrate 31, and a conductive through-substrate via 34.

[0052] In some embodiments, such as in Figure 2a In the illustrated embodiment, the via 35 tapers from the front surface 33 of the substrate 31 to the rear surface 41, such that the lateral area of ​​the via 35 is larger at the front surface 33 of the substrate 31 than at the rear surface 41.

[0053] The sidewall 51 of the conductive through-substrate via 34 can be tilted at an angle between 86° and 89° relative to the front surface 33 of the substrate 31 to form a tapered shape. The tapered shape can be formed as a result of a via 35 introduced from the front surface 33 into the substrate 31. The via 35 can be formed by etching (such as plasma etching).

[0054] In some embodiments, the via 35 is substantially filled with a conductive material 36, such as, for example, in Figure 2a As illustrated in the figure. In these embodiments, the conductive material has a larger lateral area at the front surface 33 of the substrate 31 compared to the rear surface 41 of the substrate 31.

[0055] The conductive material 36 and thus the conductive through-substrate vias 34 can be electrically coupled to the source electrode 38 of the group-III nitride-based transistor 32, as schematically indicated by the line 53 in Figure 2a .

[0056] The group-III nitride-based transistor 32 and mesa 37 can include a semiconductor structure that includes a plurality of epitaxial group-III nitride-based layers. The mesa 37 can include: a buffer structure 54 that includes one or more epitaxial group-III nitride-based layers; a channel layer 55 disposed on the buffer structure 54; and a barrier layer 56 disposed on the channel layer 55. The channel layer 55 can include gallium nitride (GaN), and the barrier layer 56 can include aluminum gallium nitride (Al x Ga (1-x) N ， (where 0 < x < 1) to form a heterojunction at the interface 57 between the channel layer 55 and the barrier layer 56, which is capable of supporting a two-dimensional charge gas, such as a two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG), as indicated by the dashed line 58. The group-III nitride-based transistor 32 includes a source electrode 38, a drain electrode 39, and a gate electrode 40 disposed on the barrier layer 56. The gate electrode 40 is disposed transversely between the source electrode 38 and the drain electrode 39.

[0057] A two-dimensional charge gas, such as a two-dimensional electron gas (2DEG), can be formed by piezoelectric and spontaneous polarization at the interface between the channel layer 55 and the barrier layer 56. The group-III nitride-based transistor 32 can be a high electron mobility transistor (HEMT) and can have a breakdown voltage of at least 200V. <第18行开始缺失原文行号标签

[0058] A conductive layer 59 is disposed on the rear surface 41 of the substrate 31 and can have a solderable surface or include solder so that the semiconductor substrate 31 can be mounted on a package die pad or a ground plane and electrically coupled to the package die pad or the ground plane. The conductive layer 59 can include two or more sub-layers, such as a metal layer and a solderable layer.

[0059] Figure 2b Illustrated is a semiconductor device 60 that includes a group-III nitride-based transistor 32 and at least one conductive through-substrate via 34 formed in a mesa 37 disposed on the front surface 33 of a substrate 31. (这里原文似乎缺失了部分内容,请检查原文是否完整)

[0060] The conductive through-substrate vias 34 are in contact with Figure 2aThe difference in the conductive through-substrate via illustrated in the middle lies in the arrangement of the conductive material 36 within the via 35. In this embodiment, a first portion of the via 35 adjacent to the rear surface 41 of the substrate 31 includes a conductive plug 61, which substantially fills the bottom of the via 35. A conductive pad layer 62 is also provided, which pads the sidewalls 51 of the via 35 in a second portion adjacent to the front surface 33 of the substrate 31. The conductive pad layer 62 surrounds a gap 63 in the upper portion of the via 35. The conductive pad layer 62 is disposed on at least the outer peripheral region of the conductive plug 61 such that the conductive plug 61 and the conductive pad layer 62 provide a conductive path from the front surface 33 of the substrate 31 to the rear surface 41.

[0061] The guide hole 35 may also taper from the front surface 33 to the rear surface 41 such that the narrower bottom of the guide hole 35 is substantially filled with conductive material and that the wider area of ​​the guide hole 35 adjacent to the front surface 33 includes the gap 63 defined by the upper surfaces of the conductive pad layer 62 and the conductive plug 61.

[0062] The substrate 31 may have a height h1 and the first conductive portion 61 may have a height h2, where h2 ≤ 2h1 / 3. As an example, 20 μm ≤ h1 ≤ 100 μm and 5 μm ≤ h2 ≤ 70 μm.

[0063] The second conductive portion 62 may have a thickness t, for example 0.5μm≤t≤3μm, and the first conductive portion 61 may have a height h2, for example 5μm≤h2≤70μm.

[0064] A multilayer pad structure can be provided between the conductive material 36 and the sidewalls of the through-substrate via 35. The multilayer pad structure can be in direct contact with the substrate 31 and provide adhesion and / or barrier functions.

[0065] In some embodiments, a portion of the front surface 33 of the substrate 31 is also removed in the region adjacent to the mesa 37 so that the mesa 37 is positioned on the raised region of the substrate 41.

[0066] Mesa 37 may have a height in the range of 1 μm to 10 μm and lateral dimensions suitable for forming active regions of semiconductor devices (such as HEMTs) or semiconductor devices.

[0067] In the illustrated embodiment, the mesa 37 has the form of discrete protrusions having sides that can be embedded in an insulating layer. However, in other embodiments, the protrusion structure providing the mesa for a semiconductor device can be connected to adjacent protrusion regions by a portion comprising one or more group III nitride layers.

[0068] Forming discrete mesa 37 on the front surface can help reduce wafer bending and simplify manufacturing. One or more group III nitrides epitaxially grown across the entire surface of a wafer (such as a single-crystal silicon wafer) can cause wafer bending—due to the highly compressed or stretched individual epitaxial group III nitride layers and because of high in-plane lattice mismatch and the difference in the coefficient of thermal expansion between the group III nitride layer and the substrate. For a 200mm wafer, a wafer bending value of up to 200μm may occur at the center. As a result, these wafers may exhibit fragility during processing in the semiconductor production line.

[0069] However, if the majority of the material disposed on the upper surface of the semiconductor wafer comprises insulating material rather than an epitaxially deposited group III nitride layer, the total area occupied by group III nitride covering the region on the upper surface of the wafer can be between 10% and 90% of the total wafer area. Therefore, this arrangement can be used to reduce any bending of the semiconductor wafer to assist in the automated handling of the semiconductor wafer in subsequent processing steps.

[0070] The wafer can have a wafer bending depth b of less than 200 μm, where: 100*t*b / d 2 ≤15

[0071] Where d is the wafer diameter, t is the thickness of the epitaxially deposited group III nitride layer, and b is the wafer curvature at the center of the wafer.

[0072] The diameter d can be 200 mm, and the thickness t can be from 1 μm to 10 μm. A wafer with a diameter of 200 mm can have a thickness of approximately 725 μm. With a wafer diameter of 200 mm (and for mesas with a height of 0.5 μm to 10 μm), the mesas 37 can have a surface flatness variation of less than ±10% of the mesas height.

[0073] In some embodiments, group III nitride-based transistors and conductive through-substrate vias can be formed in a continuous semiconductor structure comprising a plurality of epitaxial group III nitride layers. In these embodiments, conductive through-substrate vias are disposed in each epitaxial group III nitride layer in which the transistor structure is formed and can be in direct contact with each epitaxial group III nitride layer.

[0074] Figure 3aCross-sectional view of the illustrated semiconductor device 70, the semiconductor device 70 including a substrate 71 having a front surface 72 that is capable of supporting epitaxial growth of one or more group III nitrides. The substrate 71 may include a semiconductor substrate, such as a semiconductor wafer such as a <100> or <111> silicon wafer, silicon carbide, or sapphire. A plurality of group III layers are epitaxially grown on the front surface 72 to form a semiconductor structure 73. The semiconductor structure 73 may include: a buffer or transition structure 74 disposed on the front surface 72; a channel layer 75 including gallium nitride disposed on the buffer structure; and a barrier layer 76 including aluminum gallium nitride (Al x Ga (1-x) N, where 0 < x < 1), so as to form a heterojunction at an interface 77 between the barrier layer 76 and the channel layer 75, which is capable of supporting a two-dimensional charge gas indicated by a dashed line 78 in Figure 3a such as a two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG).

[0075] A group III nitride-based transistor is formed in a portion of the semiconductor structure 73 by: a source electrode 79, a drain electrode 80, and a gate electrode 81 being disposed on the barrier layer 76 such that the gate electrode 81 is disposed transversely between the source electrode 79 and the drain electrode 80. The electrodes 79, 80, 81 may form a transistor cell or segment 88 that is one of a plurality of transistor cells that are electrically coupled in parallel to form a single switching device. The source electrode 79, the drain electrode 80, and the gate electrode 91 may have a shape similar to an elongated bar, each having a length extending into the plane of the drawing. The source electrode 79, the drain electrode 80, and the gate electrode 91 may include one or more metals.

[0076] The semiconductor device 70 further includes at least one conductive through-substrate via 82 that extends through the semiconductor structure 73 including the epitaxial group III nitride layers and extends through the substrate 71 such that it extends from an upper surface 83 of the outermost surface of the semiconductor structure 73 (which is provided by the barrier layer 76 in this embodiment) to a rear surface 84 of the substrate 71. The conductive through-substrate via 82 includes: a via 85 that extends from the upper surface 83 to the rear surface 84; and a conductive material 86 that extends from the upper surface 83 to the rear surface 84. A conductive layer 87 is disposed on the rear surface 84 and is electrically coupled to the conductive material 86 within the conductive through-substrate via 82.

[0077] The conductive through-substrate via 82 may be coupled to an electrode of the group III nitride-based transistor 88, as in Figure 3aAs schematically indicated by line 89. In particular, the conductive through-substrate via 82 can be electrically coupled to the source electrode 79 of the transistor 88. In some embodiments, the conductive through-substrate via 82 is electrically coupled on the front surface 72 to two adjacent transistor cells 88 arranged on opposite sides of the conductive through-substrate via 82.

[0078] The conductive through-substrate via 82 can also take different forms. Figure 3a In the illustrated embodiment, the via 85 has a tapered shape such that the sidewall 90 is inclined at an angle of approximately 86° to 89° relative to the upper surface 83. The lateral area of ​​the via 85 at the upper surface 83 is greater than the lateral area of ​​the via 85 at the rear surface 84. The via 85 may be substantially filled with a conductive material 86, such as... Figure 3a As illustrated. In other embodiments, the conductive through-substrate via 85 includes gaps or unfilled areas in at least a portion of the via 85. In some embodiments, the sidewalls 90 are padded with a conductive material such that the gap extends from the upper surface 83 to the rear surface 84.

[0079] In some embodiments, such as in Figure 3b In the illustrated embodiment, the bottom of the via 85 is substantially filled with a conductive material forming a conductive plug 91, while the upper portion of the via 85 includes a conductive pad layer 92 that pads the sidewalls 90 of the via 85, leaving a gap 93 at the center of the via 85. In embodiments where the via 85 is partially filled with conductive material 86, the via 85 may also taper from the upper surface 83 to the rear surface 84, thereby giving the via a larger lateral area at the upper surface 83 compared to the rear surface 84.

[0080] A multilayer pad structure can be provided between the conductive material 86 and the sidewall of the through-substrate via 85.

[0081] The conductive through-substrate vias according to the embodiments described herein can have different lateral shapes. For example, the conductive through-substrate via 82 can have an elongated lateral region, such as a rectangle, or can have a square, circular, or hexagonal lateral shape.

[0082] Multiple conductive through-substrate vias can be arranged in a row or an array, substantially parallel to the source electrode 79 of the group III nitride-based transistor 88. Two or more conductive through-substrate vias can also be sensibly coupled to the common electrode of the group III nitride-based transistor.

[0083] However, the group III nitride-based transistors 32 and 88 are not limited to the illustrated arrangement and may have other arrangements. For example, a cap layer comprising gallium nitride (GaN) may be disposed on the barrier layer. One or more insulating and / or passivation layers may be disposed on the barrier layer. The gate may include a gate recess structure and / or a p-doped group III nitride layer may be disposed below the gate electrode. The source and / or drain contacts may include recess structures to, for example, minimize ohmic contact resistance.

[0084] The group III nitride-based transistors 32 and 88 can be HEMTs and can be depletion-mode devices that are typically on. The metal gate forms a Schottky barrier contact, and the source and drain form an ohmic metal contact. The group III nitride-based transistors 32 and 88 can also be enhancement-mode devices that are typically off. The group III nitride-based transistors 32 and 88 can be high-voltage devices, for example, having a blocking voltage capability of at least 600V.

[0085] Conductive through-substrate vias can be coupled to the source electrode of a group III nitride-based transistor in various ways—for example, through one or more bonding wirings or through a portion of a metallization structure disposed on the front surface of the substrate.

[0086] Figure 4a The diagram shows the floor plan and Figure 4b The figure shows a cross-sectional view along line A-A of semiconductor device 70 and two adjacent transistor cells 88, 88'. Figure 4a and Figure 4b An embodiment of the electrical connection between the source electrode 79 and the conductive through-substrate via 82 is also illustrated.

[0087] The group III nitride-based transistor 70 includes multiple transistor cells or segments 88 coupled in parallel with each other. Figure 4a and Figure 4b The diagram illustrates two transistor cells 88, 88', arranged symmetrically about a center line 94, whereby the common drain electrode 80 for both transistor cells 88, 88' is arranged symmetrically about the center line 94. Each transistor cell 88, 88' includes a source electrode 79 and a gate electrode 81, the gate electrode 81 being laterally arranged between the source electrode 79 and the drain electrode 80. The source electrode 79, gate electrode 81, and drain electrode 80 of each transistor cell 88, 88' have an elongated, strip-like shape and extend substantially parallel to each other.

[0088] At least one conductive through-substrate via 82, 82' is arranged laterally adjacent to each other and spaced apart from the source electrode 79 of each transistor cell 88, 88'. A plurality of conductive through-substrate vias 82, 82' may be provided for a single conductive connection between the source electrodes 79, 79' and the rear surface 84 of the substrate 71. The through-substrate vias 82, 82' may be arranged in a row, extending substantially parallel to the source electrodes 79, 79' and laterally outside the source electrodes 79, 79' relative to the centerline 94.

[0089] Conductive through-substrate vias 82 and 82' are formed by providing conductive paths from the upper surface 83 to the rear surface 84 through conductive materials 86 and 86' disposed in the through-substrate vias 82 and 82'. The conductive paths within the through-substrate vias 82 and 82' can be as follows: Figure 3a As shown in the diagram, it is provided through a conductive part, or as... Figure 3b As shown in the diagram, it is provided by two conductive parts 91 and 92 of different shapes.

[0090] Conductive layers 95, 95' are disposed on the upper surface 83 and provide lateral redistribution of source connections between the source electrodes 79, 79' and the conductive through-substrate vias 82, 82'. Conductive layer 95 may be part of the first layer of the back end of the pad metallization.

[0091] In some embodiments, the conductive material 86, 86' within the vias 82, 82' may extend onto the upper surface 83 in the region adjacent to the vias 82, 82' to form a conductive layer 95, 95, which extends onto and is electrically coupled to the source electrodes 79, 79'. The conductive layers 95, 95' and the conductive material 86, 86' may comprise high-purity copper, which may be deposited by electroplating. Because a single element provides both vertical and lateral electrical paths, such an arrangement may be referred to as a dual damascene.

[0092] In some embodiments, conductive layers 95, 95' are deposited separately from conductive materials 86, 86' within vias 82. Such an arrangement may be referred to as mono-mosaic.

[0093] Figure 4cThe illustration shows a cross-sectional view of a semiconductor device 30 comprising a group III nitride-based transistor 32 disposed in a mesa 37. The sides of the mesa 37 are embedded in an insulating layer 96, which, together with the upper surface of the group III nitride transistor 32, forms a substantially flat surface 97. A via 35 extends through the insulating layer 96 and into the substrate 31 to reach the rear surface 41 of the substrate 31. A conductive layer 95 extends from a conductive material 36 within the via 35 to the upper surface 97 of the insulating layer 96 and to the source electrode 38, electrically coupling the source electrode 38 to a layer 59 disposed on the rear surface 41 of the substrate 31 via a conductive through-substrate via 34. The conductive layer 95 may be integrated with the conductive material 36 or may be provided as a separately deposited conductive layer.

[0094] exist Figure 5a and Figure 5b The diagram below illustrates in more detail various structures for partially filled conductive through-substrate vias. Each structure is based on... Figure 2b The conductive through-substrate via 34 is illustrated in the figure. However, the structures are not limited to use in the semiconductor device 30. For example, they can be used in… Figure 3b The conductive via 82 of the semiconductor device 70 shown in the figure.

[0095] Figure 5a The illustration shows an embodiment of a structure 100 including a conductive pad layer 62 and a conductive plug 61, with the conductive pad layer 62 positioned directly on the upper surface of the conductive plug 61, forming a substantially horizontal interface 101 between the conductive plug 61 and the conductive pad layer 62. The conductive pad layer 62 may surround a gap 63 within a via 35, which is open at a first surface 33 of the semiconductor substrate 31.

[0096] The structure 100 includes an interface 101 between the upper surface of the conductive plug 61 and the lower surface of the bottom of the U-shaped conductive pad layer 62, and may be formed after the conductive pad layer 62 is deposited on the conductive plug 61.

[0097] The conductive pad layer 62 and the conductive plug 61 can have different microstructures. For example, the conductive plug 61 can include a larger grain size than the conductive pad layer 62. Different microstructures may arise from different conditions used for depositing the conductive plug 61 and the conductive pad layer 62 in the via 34.

[0098] In the embodiments, different electrochemical processing baths, including different chemical additive systems, were used to deposit the conductive plug 61 and the conductive liner layer 62. The chemical additive systems can be identified in the final product using analytical techniques such as TOF-SIMS (Time-Of-Flight Secondary Ion Mass Spectrometry).

[0099] The conductive pad layer 62 and the conductive plug 61 may comprise the same material, such as the same metal. In some embodiments, the conductive pad layer 62 and the conductive plug 61 comprise high-purity copper.

[0100] The conductive plug 61 has a height h2, which is greater than the thickness t of the conductive liner layer 62, for example, h2 ≥ 3t. In some embodiments, 0.5 μm ≤ t ≤ 3 μm and

[0101] The conductive through-substrate via 34 may have a height h1, and the conductive plug 61 may have a height h2, wherein h2 may be less than or equal to 2 / 3h1, i.e., h2 ≤ 2h1 / 3. In some embodiments, 20 μm ≤ h1 ≤ 100 μm and 5 μm ≤ h2 ≤ 70 μm.

[0102] One or more further layers, diffusion barriers and / or seed layers that provide adhesion promotion may be disposed between the material of the substrate 31 defining the sidewall 51 of the via 35, the conductive plug 61 and the conductive pad layer 62.

[0103] The conductive through-substrate via 34 can be considered as being anisotropically filled by the conductive plug 61 filling the lateral region of the via 35 while the conductive pad layer 62 surrounds the center of the via 35 to form a gap 63 or an open area. Anisotropic filling can be used to provide stress relief and simpler handling of the substrate at the wafer level and at the device level after wafer monomerization.

[0104] For example, positioning the gap 63 within the via 35 can be used to prevent bending of the substrate 31, particularly at the wafer level, during the fabrication of the array of conductive through-substrate vias 34, and can be used for stress compensation. Because the conductive material of the conductive plug 61 and the conductive pad layer 62 can expand into the gap 63, the conductive through-substrate vias 34 can have improved thermal performance during thermal cycling. Furthermore, the use of a filled bottom for the conductive through-substrate vias 34 prevents solder from entering the vias during die attachment—for example, when the rear surface 25 is soldered to the die pads or ground plane.

[0105] The gap 63, positioned within the upper portion of the via 35, may be open at the front surface 33. In some embodiments, the upper end 102 of the conductive via 34 is sealed at the front surface 33 to create a cavity within the upper portion of the conductive through-substrate via 34 and within the conductive pad layer 62. The lateral area of ​​the conductive through-substrate via 34 formed by the gap 63 or the cavity—if present—may be approximately 4% of the total surface area of ​​the substrate 31.

[0106] Figure 5b The illustrated structure 103 can be formed, for example, during subsequent processing of a device having an arrangement including an interface 101 between the upper surface of a conductive plug 61 and the bottom of a U-shaped conductive pad layer 62—if the semiconductor substrate 31 has undergone annealing. This subsequent annealing process can cause grain growth of the materials of the conductive plug 61 and the conductive pad layer 62 so that the interface is no longer distinguishable, and the conductive pad layer 62 is formed on the sidewall 51 of the via 34 and on the outer periphery of the upper surface of the conductive plug 61, which has a different microstructure than the conductive plug 61—for example, a smaller grain size. In this embodiment, the middle portion of the upper surface of the conductive plug 61 forms the bottom of the gap 63.

[0107] Figure 6 The illustration shows a flowchart 110 of a method for fabricating conductive vias (such as conductive through-substrate vias 34, 82) in a substrate comprising a group III nitride-based transistor on its front surface. In block 111, an opening is formed in the front surface of the substrate comprising the group III nitride-based transistor disposed on the front surface. In block 112, a conductive material is inserted into the opening. In block 113, the source electrode of the group III nitride-based transistor is coupled to a rear surface of the substrate, the rear surface being opposite the front surface.

[0108] An opening is arranged in the front surface of the substrate such that it is spaced apart from the group III nitride-based transistor after the group III nitride-based transistor is formed and is located at a certain lateral distance from the group III nitride-based transistor.

[0109] In some embodiments, the method further includes: epitaxially depositing a first group III nitride layer having a first bandgap on a front surface of a substrate; epitaxially depositing a second group III nitride layer having a second bandgap different from the first bandgap on the front surface of the substrate and forming a heterojunction therebetween; forming a metallization structure on the second group III nitride layer to form a transistor structure; and inserting an opening through the first and second group III nitride layers and into the front surface of the substrate. The heterojunction can support a two-dimensional charge gas formed by piezoelectricity and spontaneous polarization. The metallization structure can include strip-like metal electrodes that extend substantially parallel to each other to form a gate electrode disposed between a source electrode and a drain electrode. The opening is spaced apart from the metallization structure forming the transistor structure by regions of the first and second group III nitride layers.

[0110] In some embodiments, a group III nitride-based transistor is formed in a mesa disposed on the front surface of a substrate. The mesa includes a first epitaxial group III nitride layer having a first bandgap and a second epitaxial group III nitride layer having a second bandgap different from the first bandgap, thereby forming a heterojunction therebetween. A plurality of mesas spaced apart from each other can be disposed on the front surface. In some embodiments, at least the sidewalls of the mesa are embedded in an insulating layer disposed on the front surface of the substrate. Openings can be formed through the insulating layer and into the front surface of the substrate such that the openings are spaced apart from the group III nitride layers of the mesa by portions of the insulating layer and the substrate.

[0111] In some embodiments, the method further includes applying a conductive material to the front surface of a substrate such that it extends from the sidewall of the opening onto the front surface and onto the source electrode of a group III nitride-based transistor.

[0112] In some embodiments, a further conductive layer is applied to the conductive material within the opening and to the front surface of the substrate such that it electrically couples the source electrode of the group III nitride-based transistor to the conductive material. The further conductive layer may be disposed above the plane of the group III nitride-based transistor and electrically coupled to the source electrode via one or more conductive vias extending between the source electrode and the further conductive layer.

[0113] In some embodiments, the opening is substantially filled with a conductive material. The conductive material may be applied, for example, by electroplating.

[0114] In some embodiments, the opening is partially filled with a conductive material. The opening may be partially filled by using electroplating to create two portions of different shapes within the opening.

[0115] In some embodiments, the conductive material is inserted into the opening using first deposition parameters such that a first conductive layer fills the opening in the first portion. A second conductive layer is formed on the first conductive layer in a second portion of the opening using second deposition parameters such that the second conductive layer surrounds a gap in the second portion.

[0116] The first and second conductive layers can be formed by electrodeposition. The first conductive layer can form a conductive plug and the second conductive layer can form a conductive pad. The second conductive layer can be formed directly on the first conductive layer, forming a substantially horizontal interface between them. In some embodiments, the second conductive layer can extend from the outer periphery of the first conductive layer on the sidewall of the opening. The first and second conductive layers can be distinguished by their respective microstructures. For example, the first conductive layer can have a larger average grain size compared to the second conductive layer.

[0117] A first deposition parameter can be selected to facilitate the growth of the first conductive layer in the vertical direction relative to the main surface of the substrate, and a second deposition parameter can be selected to facilitate the growth of the second conductive layer in the lateral direction relative to the main surface of the substrate. The first and second deposition parameters can be selected such that the first conductive layer has the form of a conductive plug (having a height h1), and the second conductive layer has a thickness t, where h1 ≥ 3t.

[0118] In some embodiments, the substrate undergoes annealing during subsequent processing after arrangement. This subsequent annealing can cause grain growth of the materials of the first and second conductive layers, making the interface no longer distinguishable. However, portions of the second conductive layer formed on the opening sidewalls and at the outer periphery of the first conductive layer may have a different microstructure (e.g., smaller grain size) than the first conductive layer, thus making the two conductive layers distinguishable.

[0119] In some embodiments, the opening is in the form of a blind via or an end-closed via, and a first conductive layer is applied to the bottom of the blind via such that the bottom portion of the blind via is filled with the first conductive layer. In some embodiments, the blind via is filled to a depth of 10% to 70% of its total depth. A second layer may be positioned directly on the first layer to form an interface and extend along the sidewalls to the opening end of the via at the first surface. In some embodiments, the second layer further extends to the first surface of the semiconductor substrate and is electrically coupled to a group III nitride-based transistor. To provide a conductive path between the front and rear surfaces of the final substrate, the rear surface adjacent to the blind via may be processed to remove material until a portion of the conductive plug is exposed, and the substrate has the desired thickness.

[0120] In some embodiments, the gap in the second portion of the opening is covered after the application of the second conductive layer. The gap can be covered by forming a first insulating layer surrounding the second conductive layer and forming a second insulating layer over the gap, thereby forming a closed and sealed cavity or opening within the opening.

[0121] After the second conductive layer is applied and before the metallization structure is applied to the first surface, the gap in the second part of the opening can be temporarily covered, for example, by inserting a resist plug, the front surface is planarized, for example, by chemical mechanical polishing (CMP), and the resist plug is removed.

[0122] Figure 7 The illustration shows a flowchart of a method 120 for fabricating a group III nitride-based transistor device. In block 121, a group III nitride-based transistor is formed on the front surface of a semiconductor substrate. In block 122, a blind via is inserted into the front surface, and conductive material is inserted into the blind via. In block 123, a metallization structure is applied to the front surface, the metallization structure having: at least one conductive portion between the conductive material electrically coupled in the blind via and the source electrode of the group III nitride-based transistor; and at least one conductive portion coupled to each of the gate electrode and drain electrode of the group III nitride-based transistor. In block 124, a second surface of the substrate opposite the first surface and the metallization structure is processed to expose the surface of the conductive material disposed at the bottom of the via.

[0123] After forming a group III nitride-based transistor on the first surface of the substrate and before depositing a metallization structure on the front surface, a conductive through-substrate via is formed. The front surface includes a composite and / or crystal orientation that supports the epitaxial growth of the group III nitride.

[0124] A group III nitride-based transistor can be provided as a discrete mesa disposed on the front surface of a substrate or in a portion of a stack of epitaxial group III nitride layers extending substantially over the entire front surface. If the group III nitride-based transistor is provided in a mesa, openings can be spaced apart and located at a distance from the sides of the mesa and laterally separated from the group III nitride-based material by a portion of the substrate. The openings can be defined by the substrate material and the material of the insulating layer. If the group III nitride-based transistor is formed in a portion of a stack of group III nitride layers, openings can be formed in the stack of group III nitride layers such that the stack of group III nitride layers defines a portion of the opening, wherein the substrate material defines the remainder of the opening.

[0125] During the insertion of vias into the substrate and the fabrication of conductive vias, group III nitride-based transistors can be covered by one or more insulating layers.

[0126] The volume of a conductive through-substrate via can be filled or partially filled with a conductive material. The volume of the through-substrate via can be filled with a conductive material isotropically or homogeneously. Alternatively, the volume of the through-substrate via can be filled with a conductive material anisotropically or heterogeneously.

[0127] In embodiments where the volume of a conductive through-substrate via is partially filled with conductive material, the opening can be a blind via, and the bottom of the blind via can be filled to a predetermined depth using conductive material. A conductive pad layer can be formed in the via above the conductive material surrounding the gap. The conductive pad layer can extend from the conductive material to the source electrode of the group III nitride-based transistor and electrically couple the conductive material to the source electrode of the group III nitride-based transistor. The via can be described as anisotropically filled.

[0128] In embodiments where the conductive material includes a conductive plug and a conductive pad layer, the conductive pad layer may be further formed on a first surface of the substrate surrounding the opening and electrically coupled to the source electrode of a group III nitride-based transistor.

[0129] In some embodiments, the gap within the guide hole, surrounded by a conductive pad layer, is covered or sealed. The enclosed cavity or opening can be entirely defined by an insulating material such as a dielectric.

[0130] Now refer to Figures 8 to 14 This describes a method for fabricating transistor devices based on group III nitrides.

[0131] Figure 8 The figure illustrates an initial substrate 130 having a front surface 131. The substrate 130 may, for example, include... <100> or <111> A silicon wafer, silicon carbide wafer, or sapphire wafer, with an initial thickness t greater than the final thickness of the substrate for a transistor device. i .

[0132] Multiple mesa 132 are formed on the front surface 131. Each mesa 132 is spaced apart by a region 136 in which conductive through-substrate vias (TSVs) are formed. Each region 136 may be referred to as a passive region because they do not contribute to the switching function of the transistor device. The mesa 132 includes multiple epitaxial group III nitride layers and forms the transistor device. The mesa 132 may, for example, have the structure illustrated in Figures 2 and 3 and have sides embedded in an insulating layer 133. The mesa 132 in the front surface 131 is separated by a first oxide layer 134 (e.g., SiO2, which covers the source, gate, and drain metal contacts or electrodes) and a nitride layer 135 (e.g., SiN) on the first oxide layer 134. x The first oxide layer (e.g., SiO2) covers the nitride layer 135 and a second oxide layer 137 on top of it. In region 136, the first oxide layer can be omitted and SiN... X Layer 135 and second oxide layer 137 are disposed on insulating layer 133.

[0133] like Figure 9 As illustrated in the diagram, a blind via 140 is inserted into the front surface 131 of the substrate 130 in the passive region 136, where the passive region 136 is positioned between the mesa 132 or the active region 138 in which the transistor is formed.

[0134] The blind via 140 has a bottom 141 formed by a portion of the material of the semiconductor substrate 130 and has a depth t b Depth t b The initial thickness t is less than that of the substrate 130. i And approximates the desired final thickness t of the substrate in a group III nitride-based transistor device. f The bottom 141 is substantially circular in shape. The upper portion of the blind via 140 is defined by the insulating layer 133. The blind via 140 can be inserted into the front surface 131 by reactive ion etching. The blind via 140 is spaced from the mesa 132 by a portion of the substrate 131 and the insulating layer 133. The second oxide layer 137 and the nitride layer 135 can then be removed from the front surface 131 in the passive region 136.

[0135] In the plan view, the blind via 140 may have an elongated shape and may, for example, be substantially rectangular in the elongation direction. The blind via 140 may be one of a plurality of blind vias arranged in a row extending into the plane of the drawing (substantially parallel to the source electrode extension of the group III nitride-based transistor) or arranged in a regular array between two active regions 138 or mesas 132, each of which includes a group III nitride-based transistor. The sidewalls 142 of the blind via 140 may be substantially perpendicular to the front surface 131 or may be slightly inclined such that the blind via 140 tapers toward the bottom 141. As an example, the blind via 140 may have a lateral dimension of approximately 8 μm by 50 μm and a depth of approximately 60 μm at the front surface 131.

[0136] Figure 10 The diagram illustrates the deposition of a barrier layer structure 143 on the sidewall 142 of the blind via 140 and on the front surface 131 of the substrate 130, particularly on the insulating layer 133. Figure 11 The barrier layer structure 143 is illustrated in more detail. The barrier layer structure 143 may be deposited using physical vapor deposition (PVD) techniques (e.g., sputtering) and / or chemical vapor deposition (CVD) techniques.

[0137] The barrier layer 143 extends on the sidewalls 142 and bottom 141 of the blind via 140, on the insulating layer 133 on the front surface 131 of the substrate 130 in the passive region 136, and on the second oxide layer 137 in the active region 138.

[0138] The barrier layer 143 may have various structures, such as a layer of Ta, or a Ta / TaN or Ta / Ta or Ti / TiN deposited by PVD, or a Ti / TiN deposited by PVD and a W layer deposited by CVD or PVD, or a Ti / TiN deposited by PVD and a W / Ta / TaN deposited by CVD or PVD, or a Ti / TiN deposited by PVD and a W / TaN / Ta layer deposited by CVD or PVD—and optionally further include at least one of the following: for example, pre-cleaning, wet chemical HF-holding, sputtering pre-cleaning, or hydrogen reduction after W deposition by CVD and before sputtering, performing W etch-back to remove W from the planar portion of the wafer—and a further copper seed layer deposited by sputtering for copper plating.

[0139] In some embodiments, such as those that can be Figure 11As seen in the magnified view, portion 144 of the barrier layer 143 disposed on the front surface 131 of the substrate 130 has a different number of layers than portions 145 disposed on the sidewalls 142 and bottom 141 of the blind via 140. In this embodiment, portion 144 includes a structure starting from the insulating layer 133, comprising layers of Ti, TiN, TaN, and Ta, and a Cu seed layer. The second portion 145 includes a structure starting from the cleaned surface of the semiconductor substrate 131 forming the sidewalls 142 and bottom 141 of the blind via 140, comprising layers of Ti, TiN, W, TaN, and Ta, and a Cu seed layer.

[0140] After depositing the barrier layer 143, which includes the outermost seed layer, a conductive material is inserted into the blind via 140, for example by electroplating. In some embodiments (such as in...), Figure 15 In the embodiment shown in the figure, the blind hole 140 is filled with a conductive material.

[0141] In some embodiments (such as in Figures 10 to 13 In the embodiments illustrated in the figure, the conductive material is inserted into the blind via using a two-stage process to produce a blind via 140 that is partially and anisotropically filled.

[0142] Figure 10 The diagram illustrates the substrate after the first stage of a two-stage process. In the first stage, conductive material is inserted into the bottom 141 of a blind via 140 to form a first conductive layer 146 that fills the volume of the blind via 140 adjacent to the bottom 141. The first layer 146 may be deposited using an electroplating technique and may be deposited under conditions that favor vertical growth of the layer 146 relative to the first main surface 131 while suppressing lateral or front-side growth of the substrate, such that the volume of the blind via 140 is filled with the first layer 146. The first conductive layer 146 may be referred to as a conductive plug.

[0143] Figure 12 The illustration shows the substrate 130 after a second conductive layer 147 has been deposited within the blind via 140. The second conductive layer 147 liner the barrier layer 143 on the sidewall 142 of the blind via 140, the upper surface of the first layer 146 within the blind via 140, and extends over the front surface 131 of the substrate 130 and the insulating layer 133. The second conductive layer 147 surrounds a gap 149 within the upper portion 150 of the blind via 140.

[0144] The second conductive layer 147 may be deposited by electroplating technology, and may be deposited using conditions favorable to the conformal deposition and growth of the second conductive layer 147, such that the second conductive layer 147 pads the upper portion 150 of the blind via 140, leaving a gap 149 at the center of the blind via 140. The second conductive layer 147 may be referred to as a conductive pad layer. The first conductive layer 146 and the second conductive layer 147 may comprise high-purity copper.

[0145] After deposition, an interface 148 is formed between the first conductive layer 146 and the second conductive layer 147. The interface 148 is distinguishable because the first conductive layer 146 and the second conductive layer 147 are deposited in two deposition steps and can have different microstructures.

[0146] In embodiments where the substrate undergoes subsequent heat treatment, interface 148 may no longer be distinguishable. However, the second conductive layer 147 and the first conductive layer 146 disposed on the sidewall 142 of the blind via 140 may have different microstructures, such as different grain sizes, and are distinguishable.

[0147] The gap 149 within the blind via 140 can be temporarily sealed using a further material such as resist 151. A planarization process can be performed on the front surface, wherein the resist layer 151 prevents material from entering the gap 149 within the blind via 140. The resist layer 151 can then be removed.

[0148] The second conductive layer 147 may extend onto the front surface 131 of the substrate 130 and may be electrically coupled to an electrode (such as a source electrode) of a Group III nitride transistor. At least a portion of the second conductive layer 147 may extend onto and be in direct contact with the source electrode. Because the second layer 147 provides a vertical conductive path within the blind via 140 and a horizontal conductive path on the front surface 131, and because the conductive material providing these two paths is substantially constructed using a common chemical mechanical polishing (CMP) process step, this method may be referred to as dual damascene.

[0149] In some embodiments, the second conductive layer 147 may extend from the first conductive layer to the outermost surface of the insulating layer 133 and be contained within a via. This approach may be referred to as a single damascene method. The second conductive layer may be electrically coupled to the group III nitride-based transistor (e.g., the source electrode) via a via extending laterally from the via to the conductive layer above the group III nitride-based transistor and vertically from the source electrode to the conductive layer.

[0150] Figure 13The diagram illustrates an opening or closed cavity 152 formed within the upper portion 150 of a blind via 140. The opening or closed cavity 152 may be defined by a dielectric material. The opening can be formed by first depositing a silicon nitride layer 153 that pads and passivates a second conductive layer 147 within the blind via 140 and on the front surface 131. The silicon nitride layer 153 may be conformally deposited. A second dielectric layer, such as oxide 154, may be deposited onto the uppermost portion of the blind via 140 such that the oxide layer 154 seals the opening of the blind via 140 and forms a cavity or opening 152 within the blind via 140 together with the silicon nitride layer 153. The oxide layer 154 may also extend over a group III nitride-based transistor 131 and form an interlayer dielectric for a metallization structure subsequently deposited on the front surface 131. The oxide layer 154 may also partially cover the silicon nitride layer 153.

[0151] At least a first level of BeoL (Back end of line) metallization is formed. A via 160 is formed through the arranged dielectric layer to expose a portion of the source electrode 161, gate electrode 162, and drain electrode 163. The via 160 may be filled with one or more metals, such as tungsten, using one or more barrier layers and / or adhesive layers.

[0152] Figure 14 The illustration shows an example of a metallization structure 170, which can be formed on the front surface 131 to electrically couple the metal contacts of a group III nitride-based transistor to external contact pads 171. The metallization structure is a multilayer metallization structure.

[0153] After forming the metallization structure 170 of the front surface 131, the rear surface 172 of the initial substrate 130 can be processed to remove material and reduce the thickness of the substrate 130 from the initial thickness t. i Reduced to the final thickness t f The surface 173 of the first conductive layer 146, exposed at the bottom 141 of the blind via 140, is exposed to a new rear surface 172 of the substrate 130. The rear surface can be processed by grinding, dry polishing, chemical mechanical polishing, or a combination thereof.

[0154] One or more conductive layers 174, including, for example, solder layers, can be deposited onto the final rear surface 172. The one or more conductive layers 174 enable group III nitride-based transistor devices to be mounted on and electrically coupled to the further surface, such as flanges, which provide a ground plane and can also serve as heat sinks for group III nitride-based transistor devices.

[0155] The combination of a first conductive layer 146 exposed in the rear surface 172 of substrate 130 and a second conductive layer 147 extending onto the front surface 131 and electrically coupled to the source electrode 161 of a group III nitride-based transistor, and particularly a group III nitride-based transistor, provides a conductive through-substrate via 175 for the group III nitride-based transistor. The conductive through-substrate via 175 allows the source electrode 161 to be coupled to a surface on the opposite side of substrate 130.

[0156] The conductive through-substrate via 175 is partially filled because it includes a dielectric-defined cavity 152 in its upper portion. The conductive through-substrate via 175 includes a bottom-closed metal plane provided by a first conductive layer 146 and a top plane partially formed by the dielectric layer of the sealed cavity 152. The bottom-closed metal plane prevents contamination of the via 175 during processing of the rear surface 172, and the cavity 152 provides expansion volume to compensate for thermal stress.

[0157] Figure 14 The figure also shows a cross-sectional view of the substrate 130, which illustrates the lateral connection between the conductive material within the via 140 and the source electrode 161 of the group III nitride-based transistor.

[0158] A conductive through-substrate via 175 extends through an insulating layer 133, which is disposed adjacent to a passive region 136 of the group III nitride-based transistor. The insulating layer 133 is substantially coplanar with the upper surface of the group III nitride-based transistor. A second conductive layer 147 disposed on the sidewall of the via 140 extends to the upper surface of the insulating layer 133 and to at least a portion of the source electrode 161 to electrically couple the source electrode 161 to the rear surface of the substrate 130.

[0159] The metallization structure 170 may include multiple dielectric and conductive layers to provide a conductive redistribution structure to the outermost surface of the metallization structure 170 for each of the gate electrode 162, drain electrode 163, and optional ground source electrode 161.

[0160] Figure 15 The figure shows a cross-sectional view of a semiconductor device 180, which includes a substrate 130, a group III nitride-based transistor on a front surface 131, and at least one conductive through-substrate via 175' extending from the front surface 131 to a rear surface 172. The semiconductor device 180 also includes a metallization structure 170 disposed on the front surface 131, as shown in... Figure 14 As illustrated in the embodiment shown in the figure. Semiconductor device 180 and Figure 14 The difference in the device illustrated in the middle lies in the arrangement of the conductive material 181 within the via 140. Figure 15In the embodiment illustrated, the conductive through-substrate via 175' is substantially filled with a conductive material, such as high-purity copper. (As shown in...) Figure 14 As illustrated in the embodiment, the conductive material 181 extends laterally onto the front surface 131 of the substrate 130 to form layer 182, and particularly extends onto the insulating layer 133 in the passive region 136. The conductive material 181 extends to and is electrically coupled to the source electrode 161 of the group III nitride-based transistor.

[0161] Figure 16 The diagram illustrates an alternative structure for a conductive through-substrate via 175” that can be described as a single damascene process. A conductive material is contained within the blind via 140 and provides only a vertical conductive path. In this embodiment, the blind via is filled with conductive material. In this embodiment, the blind via 140 is formed not only through an insulating layer 133—which is disposed on the front surface 131 of the substrate 130 and has an upper surface substantially coplanar with the upper surface of the group III nitride-based transistor—but also through a further insulating layer—which is disposed on the insulating layer 133 and on the upper surface of the group III nitride-based transistor. The further insulating layer covers the source electrode 161, the gate electrode 162, and the drain electrode 163.

[0162] exist Figure 16 In the embodiment illustrated, the conductive through-substrate via 175" is partially filled such that a gap 152 is provided in the upper portion of the conductive through-substrate via 175" and the conductive through-substrate via 175" is covered by a further insulating layer extending above the conductive through-substrate via 175" and the group III nitride-based transistor to form an opening or cavity 152 within the via 175" . In this embodiment, the conductive through-substrate via 175" provides only a vertical conductive path. The electrical connection between the conductive through-substrate via 175" and the group III nitride-based transistor (e.g., source electrode 161) can be achieved by... Figure 16 Further conductive layers, not visible in the cross-sectional view, are provided via vias through the insulating layer above the source electrode 161. These further conductive layers and vias may be provided by a portion of the metallization structure 170.

[0163] Figure 17 The illustration shows a semiconductor device 180 with an alternative arrangement of conductive material 181 in a blind via 140 fabricated using a single damascene technique. The through-substrate via 175”' is substantially filled with conductive material 181, which extends through the insulating layer 133 and is contained within the blind via 140.

[0164] In some embodiments, the conductive through-substrate via is partially defined by a group III nitride layer forming the transistor device. The conductive through-substrate via may be formed within a cell domain of the transistor device.

[0165] Figure 18 The illustration shows a cross-sectional view of a semiconductor device 190 including a substrate 191 having a front surface 192, on which multiple epitaxial group III nitride layers 193 are deposited. The multiple group III nitride layers 193 include a barrier layer and a channel layer forming a heterojunction capable of supporting a two-dimensional charge gas.

[0166] Transistor structure 194 is formed in a portion 195 of multiple group III nitride layers 193 by means of a source electrode 196, a drain electrode 197, and a gate electrode 198 disposed on multiple epitaxial group III nitride layers 193. The gate electrode 198 is laterally disposed between the source electrode 196 and the drain electrode 197. Transistor structure 194 may be one of multiple transistor cells coupled in parallel. Semiconductor device 190 also includes a conductive through-substrate via 200, which is laterally disposed adjacent to the source electrode 196 and spaced apart from the source electrode 196 through a region of substrate 191. The uppermost surface of the multiple group III nitride layers 193 may include one or more passivation layers and / or insulating layers 199. The conductive through-substrate via 200 extends through the insulating layer 199, through the multiple group III nitride layers 193 into the substrate 191, and extends to the rear surface 201.

[0167] The conductive through-substrate via 200 can take different forms. Figure 18 In the embodiment illustrated, the conductive through-substrate via 200 includes a via 202 partially filled with a conductive material (e.g., high-purity copper). The bottom of the via 202 is substantially filled with conductive material to form a conductive plug 203, while the upper portion of the via 202 is padded with a conductive pad layer 204 that surrounds and defines a gap 205. The conductive pad layer 204 extends through the upper portion of the via defined by a plurality of group III nitride layers 193 and extends to the upper surface of the adjacent via 202 of the plurality of group III nitride layers 193. Thus, the conductive through-substrate via 200 includes a vertical conductive path from the bottom of the via 202 to the upper surface of the plurality of group III nitride layers 193 and a lateral conductive path substantially perpendicular to the via 202 in the direction of the group III nitride-based transistor 194. The gap 205 can be sealed by the insulating layer 208 to form a closed cavity within the conductive through-substrate via 200.

[0168] The semiconductor device 190 also includes a multilayer metallization structure 206 disposed on a passivation layer 199 and providing a conductive redistribution structure from the electrodes of the group III nitride-based transistor 194 (such as drain electrode 197 and gate electrode 198 and optional ground source electrode 196) to the outermost contact pad 207 disposed on the front surface 192.

[0169] A conductive through-substrate via 200 can be laterally positioned between two adjacent group III nitride-based transistors. In some embodiments, the group III nitride-based transistor 194 is one of a plurality of transistor cells coupled in parallel to create a single switching device. Electrodes 196, 197, and 198 can have a similar strip shape and extend substantially parallel to each other into the plane of the figures. Regions of the plurality of group III nitride layers disposed between the source electrodes 196 of adjacent transistor cells can be referred to as passive regions because they do not contribute to the volume of the group III nitride-based layer 193 providing switching functionality. The conductive through-substrate via 200 can be one of a plurality of conductive through-substrate vias arranged in a row or array substantially parallel to the source electrodes 196 extending into the plane of the figures. One or more conductive through-substrate vias 200 can be coupled to a common source electrode 196. In some embodiments, one or more conductive through-substrate vias 200 are electrically coupled to the source electrodes of two adjacent transistor cells disposed on opposite sides of the conductive through-substrate vias 200.

[0170] Figure 19 The diagram illustrates a plan view of semiconductor device 190. Source electrode 196, drain electrode 197, and gate electrode 197 have a strip-like shape and extend substantially parallel to each other. Conductive through-substrate vias 200 are arranged substantially parallel to the rows extending from the source electrodes of adjacent transistor structures 194. The conductive through-substrate vias 200 are electrically coupled to each other and to the source electrode 196 through a region of conductive layer 204 disposed on the front surface 193.

[0171] Figure 20 The diagram illustrates an alternative structure for a through-substrate via 200' used for conductivity. The via 202 extends through an insulating layer 209 disposed on a plurality of group III nitride layers 193 and through the plurality of group III nitride layers 193 and the substrate 191, as shown in... Figure 18 As illustrated in the embodiment, in this embodiment, the conductive pad layer 204 is integrally arranged within the via 202 and provides only vertical conductive paths. The conductive through-substrate via 200' can be electrically coupled to a group III nitride-based transistor 194 via, for example, one or more portions of the metallization structure 206.

[0172] In some embodiments, the conductive through-substrate via 200" may also be substantially filled with a conductive material, such as in Figure 21 As shown in the diagram.

[0173] For ease of description, spatially relative terms such as "below," "below," "lower part," "above," and "upper part" are used to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device, in addition to differing from those depicted in the figures. Furthermore, terms such as "first" and "second" are also used to describe various elements, regions, sections, etc., without limitation. Similar terms are used throughout the description to refer to similar elements.

[0174] As used herein, the terms “having,” “containing,” “including,” “comprising,” etc., are open-ended terms that indicate the presence of the stated element or feature but do not exclude additional elements or features. The quantifiers and pronouns “a,” “an,” and “this” are intended to include both plural and singular forms unless the context clearly indicates otherwise. It is to be understood that features of the various embodiments described herein may be combined with each other unless specifically indicated otherwise.

[0175] While specific embodiments have been described and illustrated herein, those skilled in the art will appreciate that various alternatives and / or equivalent implementations may be made in place of the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that the invention be limited only by the claims and their equivalents.

Claims

1. A semiconductor device, comprising: Substrate; A group III nitride-based transistor is disposed on the front surface of the substrate; Conductive through-substrate vias; and One or more mesa on the front surface of the substrate. The conductive through-substrate via includes: A via, extending from the front surface of the substrate to the rear surface; and Conductive material, extending from the front surface to the rear surface of the semiconductor substrate. The via gradually tapers from the front surface of the substrate to the rear surface. The group III nitride-based transistor is formed in one or more mesa, and the one or more mesa are laterally spaced from the conductive through-substrate vias on the substrate. The conductive material includes a conductive plug filling a first portion of the via, and a conductive pad layer lining the sidewalls of a second portion of the via and electrically coupled to the conductive plug, wherein the conductive plug has a grain size larger than the grain size of the conductive pad layer.

2. The semiconductor device according to claim 1, wherein, The sidewall of the guide hole is inclined at an angle of 86° to 89° relative to the front surface.

3. The semiconductor device of claim 1, wherein the one or more mesa comprises a plurality of epitaxial group III nitride layers and is spaced apart from the conductive through-substrate vias by at least one insulating layer.

4. A semiconductor device, comprising: Substrate; A group III nitride-based transistor is disposed on the front surface of the substrate; Conductive through-substrate vias; and One or more mesa on the front surface of the substrate. The conductive through-substrate via includes: A via extends from the front surface of the substrate to the rear surface; Conductive plug, filling the first part of the guide hole; and A conductive liner layer lining the sidewall of the second part of the guide hole and electrically coupled to the conductive plug. The group III nitride-based transistor is formed in one or more mesa, and the one or more mesa are laterally spaced from the conductive through-substrate vias on the substrate. The conductive plug has a grain size larger than the grain size of the conductive liner layer.

5. The semiconductor device according to claim 4, wherein, The conductive pad layer surrounds the gap within the guide hole.

6. The semiconductor device according to claim 4, wherein, The conductive through-substrate via electrically couples the source electrode of the group III nitride-based transistor disposed on the front surface of the substrate to a conductive layer disposed on the rear surface of the substrate.

7. The semiconductor device of claim 4, further comprising a dielectric material covering the via and defining a cavity within a second portion of the via.

8. The semiconductor device according to claim 7, wherein, The dielectric material includes a first layer disposed on the conductive pad layer and a second layer covering the via to define the cavity.

9. The semiconductor device according to claim 4, wherein, The one or more mesa comprises a plurality of epitaxial group III nitride layers and is spaced apart from the conductive through-substrate vias by at least one insulating layer.

10. A semiconductor device, comprising: Substrate; A group III nitride-based transistor is disposed on the front surface of the substrate; Conductive through-substrate vias; and One or more mesa on the front surface of the substrate. The conductive through-substrate via includes: A via, extending from the front surface of the substrate to the rear surface; and A conductive material extends from the front surface of the substrate to the rear surface and then to the front surface of the substrate adjacent to the via. The group III nitride-based transistor is formed in one or more mesa, and the one or more mesa are laterally spaced from the conductive through-substrate vias on the substrate, wherein the vias taper from a front surface to a rear surface of the substrate. The conductive material includes a conductive plug filling a first portion of the via, and a conductive pad layer lining the sidewalls of a second portion of the via and electrically coupled to the conductive plug, wherein the conductive plug has a grain size larger than the grain size of the conductive pad layer.

11. The semiconductor device according to claim 10, wherein, The one or more mesa comprises a plurality of epitaxial group III nitride layers and is spaced apart from the conductive through-substrate vias by at least one insulating layer.

12. The semiconductor device of claim 10, further comprising a lateral conductive layer extending on the front surface of the substrate between the conductive material and the source electrode of the group III nitride transistor, wherein, The conductive material is disposed on a portion of the transverse conductive layer.

13. A method for manufacturing a semiconductor device, comprising: An opening is formed in the front surface of a substrate, the substrate including at least one group III nitride-based transistor on the front surface; Insert the conductive material into the opening; and The source electrode of a group III nitride-based transistor is coupled to the back surface of a substrate using a conductive material. In this embodiment, a group III nitride-based transistor is formed in a mesa disposed on the front surface of a substrate, and the mesa is laterally spaced from an opening on the substrate, wherein vias taper from the front surface of the substrate to the rear surface. Inserting the conductive material into the opening includes: A first conductive layer is formed in a first portion of an opening in a substrate using first deposition parameters such that the first conductive layer fills the opening in the first portion; and Using second deposition parameters, a second conductive layer is formed on the first conductive layer in the second portion of the opening such that the second conductive layer lining the sidewalls of the second portion and defining a gap in the second portion. The first conductive layer has a grain size larger than that of the second conductive layer.

14. The method of claim 13, wherein the opening is a blind via, the conductive material is inserted into the blind via, and the material is removed from the rear surface of the substrate to expose the surface of the conductive material and create a conductive through-substrate via.

15. The method of claim 13, wherein the mesa comprises a first epitaxial group III nitride layer having a first bandgap and a second epitaxial group III nitride layer having a second bandgap different from the first bandgap, wherein a heterojunction exists between the first epitaxial group III nitride layer and the second epitaxial group III nitride layer, and the mesa is embedded in an insulating layer disposed on a front surface of a substrate, wherein an opening is inserted through the insulating layer and into the front surface of the substrate.

16. The method of claim 13, further comprising: Apply the metallization structure to the front surface of the substrate; Remove material from the back surface of the substrate to expose the surface of the conductive material; as well as Apply a conductive layer to the rear surface.

17. The method of claim 13, further comprising forming a conductive material on the front surface of the substrate adjacent to the opening.

18. The method of claim 17, further comprising forming a conductive material on a conductive layer disposed on the front surface and electrically coupled to the source electrode of a group III nitride-based transistor.

19. The method of claim 13, wherein a first deposition parameter is selected to facilitate the growth of the first conductive layer relative to the main surface of the substrate in the vertical direction and a second deposition parameter is selected to facilitate the growth of the second conductive layer relative to the main surface of the substrate in the transverse direction.

20. The method of claim 13, wherein the first conductive layer and the second conductive layer are formed by electroplating.

21. The method of claim 13, wherein the opening is a blind hole, a first conductive layer is applied to the bottom of the blind hole, and the bottom of the blind hole is filled with the first conductive layer.

22. The method of claim 21, wherein the first conductive layer fills the blind via to a depth of 10% to 70% of the total depth of the blind via.

23. The method of claim 13, further comprising: After applying the second conductive layer, the gap in the second part of the opening is covered.

24. The method of claim 13, further comprising forming a first insulating layer over a second conductive layer surrounding the gap and forming a second insulating layer over the gap to form a closed cavity within the opening.

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