Surface acoustic wave chip scale package and method of manufacturing the same

Abstract

A surface acoustic wave (SAW) wafer-level package is disclosed, comprising: a substrate; an interdigitated transducer (IDT) formed on the substrate; a sidewall formed on the substrate along the periphery of the IDT; a cover formed on the sidewall and above the IDT to form a hollow portion with the sidewall above the IDT; a connecting electrode formed on the substrate, electrically connected to the IDT and extending outward from the periphery of the sidewall; a connecting terminal electrically connected to the portion of the connecting electrode extending outward from the periphery of the sidewall, formed as an outer surface covering the sidewall and a surface and a portion of the top surface of the cover, and having a top surface formed above the top surface of the cover; and an organic solderable corrosion protectant (OSP) coating formed at least on the top surface of the connecting terminal.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0082868, filed on July 6, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This invention relates to surface acoustic wave (SAW) devices, and more specifically, to a SAW wafer-level package and a method for manufacturing the same. Background Technology

[0004] Surface acoustic waves (SAWs) are sound waves that propagate along the surface of an elastic substrate. As a result of the piezoelectric effect, sound waves are generated by electrical signals. The electric field of the sound wave can be concentrated around the substrate surface and can interact with the conductive electrons of another semiconductor directly disposed on the surface. The medium through which the sound waves propagate is a piezoelectric material with high electromechanical coupling efficiency and low sound wave energy loss, and semiconductors offer optimal efficiency due to the high mobility of conductive electrons, optimal specific resistivity, and low DC power consumption. The electronic circuitry that replaces the SAW with an electromechanical device utilizing the interaction between the conductive electrons of the SAW and the semiconductor is called an SAW device.

[0005] Because the wave energy of SAW (Super-Action Wave) propagates concentrated on a solid surface, the signal is easily controlled and devices can be miniaturized. Furthermore, the advent of high-quality piezoelectric materials such as LiNbO3, LiTaO3, quartz, and PZT has enabled the easy and efficient generation, detection, and control of SAW signals by mounting interdigital transducers (IDTs) on the surface. Therefore, the research and development of various high-performance electronic devices for processing radio frequency signals using SAW is accelerating rapidly.

[0006] SAW devices are configured with input and output electrodes, each with a thin metal film at both ends, mounted on a dielectric surface. This allows high frequencies to enter the SAW, and the output electrode detects radio wave characteristics to return an electrical signal. Examples of its applications include delay line devices, amplifiers, mode converters, beam deflectors, and optical switches.

[0007] In the manufacture of such SAW devices and semiconductor devices, recently, unlike existing methods that include wafer fabrication, chip dicing, and packaging, a manufacturing method utilizing wafer-level package (WLP) has become widely used. In this method, packaging processes and testing are performed at the wafer level, and the complete product is simply manufactured by dicing the chip.

[0008] WLP (Wafer Packaging) allows for the manufacture of complete product packages at the wafer level, meaning without separating individual chips from the wafer. Furthermore, existing wafer manufacturing equipment and processes can be reused for packaging. Because the packaging process in WLP is performed at the wafer level, hundreds or thousands of packages can be manufactured in a single process compared to existing methods of packaging individual chips, significantly reducing manufacturing and investment costs.

[0009] Figure 1 The cross-sectional structure of a conventional SAW wafer-level package is shown. As shown, the SAW wafer-level package includes a substrate 10, an IDT 20, a connection electrode 30 formed on the substrate 10 and electrically connected to the IDT 20, a sidewall 40 formed on the substrate 10 along the periphery of the IDT 20, a cover 50 formed on the sidewall 40 and above the IDT 20 to form a hollow portion 45 with the sidewall 40 above the IDT 20, a connection terminal 60 electrically connected to the connection electrode 30 and protruding above the cover 50, and a tin plating layer 70. The connection terminal 60 is typically formed of copper. Here, the tin plating layer 70 is formed on the top surface of the connection terminal 60 to improve solderability when the SAW wafer-level package is mounted on another substrate, etc. Summary of the Invention

[0010] Existing surface acoustic wave (SAW) wafer-level packages have a structure in which connection terminals 60 pass vertically through sidewalls 40 and cover 50. Therefore, due to the limited area of ​​the hollow portion 45 where the IDT 20 is located, there are limitations to increasing the size or number of such IDT 20s.

[0011] In addition, under the existing SAW wafer-level packaging, complex processes are required, including applying photoresist, electroplating, and removing photoresist, to form a tin plating layer 70 on the top surface of the connection terminal 60. This process requires expensive equipment and a long processing time.

[0012] In addition, since a tin plating layer 70 with a certain thickness (e.g., about 1-2 μm) needs to be formed, a process is required to measure the thickness of the tin plating layer 70 of each manufactured product and to check whether the product has good quality. This process further increases the product delivery time.

[0013] The present invention aims to provide a surface acoustic wave (SAW) wafer-level package in which the area of ​​the hollow portion serving as the space where interdigitated transducers (IDTs) are arranged can be increased, thereby increasing the size or number of such IDTs, and provides a method for manufacturing the SAW wafer-level package.

[0014] The present invention also aims to provide a SAW wafer-level package that uses shortened process and delivery times and does not require expensive equipment, as well as a method for manufacturing the SAW wafer-level package.

[0015] It should be noted that the technical objectives of the present invention are not limited to the above objectives, and other objectives of the present invention will be obvious to those skilled in the art from the following description.

[0016] According to one aspect of the present invention, a SAW wafer-level package is provided, comprising: a substrate; an IDT formed on the substrate; a sidewall formed on the substrate along the periphery of the IDT; a cap formed above the sidewall and the IDT to form a hollow portion with the sidewall above the IDT; a connection electrode formed on the substrate, electrically connected to the IDT, and extending outward from the periphery of the sidewall; a connection terminal electrically connected to a portion of the connection electrode extending outward from the periphery of the sidewall, formed covering an outer surface of the sidewall and a surface and a portion of a top surface of the cap, and having a top surface formed above the top surface of the cap; and an organic solderability preservative (OSP) coating formed at least on the top surface of the connection terminal.

[0017] The OSP coating can be formed on the top and side surfaces of the connection terminal.

[0018] According to another aspect of the present invention, a method for manufacturing a SAW wafer-level package is provided. The method includes: forming a base device comprising: a substrate; an IDT formed on the substrate; a sidewall formed on the substrate along the periphery of the IDT; a cap formed above the sidewall and the IDT to form a hollow portion with the sidewall above the IDT; a connection electrode formed on the substrate, electrically connected to the IDT, and extending outward from the periphery of the sidewall; and a connection terminal electrically connected to a portion of the connection electrode extending outward from the periphery of the sidewall, formed covering an outer surface of the sidewall and a surface and a portion of a top surface of the cap, and having a top surface formed above the top surface of the cap; and forming an OSP coating, the OSP coating being formed at least on the top surface of the connection terminal.

[0019] The formation of the OSP coating may include forming the OSP coating on the top and side surfaces of the connection terminal.

[0020] The formation of the OSP coating may include forming the OSP coating by dipping, spraying or spin coating.

[0021] According to another aspect of the present invention, a SAW wafer-level package is provided, comprising: a substrate; an IDT formed on the substrate; a sidewall formed on the substrate along the periphery of the IDT; a cover formed above the sidewall and the IDT to form a hollow portion with the sidewall above the IDT; a connection electrode formed on the substrate, electrically connected to the IDT, and extending outward from the periphery of the sidewall; a connection terminal electrically connected to a portion of the connection electrode extending outward from the periphery of the sidewall, formed covering an outer surface of the sidewall and a surface and a portion of the top surface of the cover, and having a top surface formed above the top surface of the cover; a cover protection layer formed around the side surface of the connection terminal and the top and side surfaces of the cover, while at least exposing the top surface of the connection terminal; and an OSP coating formed at least on the top surface of the connection terminal.

[0022] The top surface of the connecting terminal and the top surface of the cover protective layer can be substantially in the same plane.

[0023] The connection terminal may be formed to protrude above the top surface of the cover protective layer, and the OSP coating is formed on the top surface of the connection terminal and its side surface protruding above the top surface of the cover protective layer.

[0024] According to another aspect of the present invention, a method for manufacturing SAW wafer-level packages is provided. The method includes: forming a first base device comprising: a substrate; an IDT formed on the substrate; a sidewall formed on the substrate along the periphery of the IDT; a cover formed above the sidewall and the IDT to form a hollow portion with the sidewall above the IDT; a connecting electrode formed on the substrate, electrically connected to the IDT, and extending outward from the periphery of the sidewall; and a connecting terminal electrically connected to a portion of the connecting electrode extending outward from the periphery of the sidewall, formed to extend over an outer surface of the sidewall and a surface and a portion of the top surface of the cover, and having a top surface formed above the top surface of the cover; forming a second base device by forming a cover protective layer that surrounds the side surface of the connecting terminal and the top and side surfaces of the cover while simultaneously covering the connecting terminal; forming a third base device by planarizing the top surface of the cover protective layer to at least expose the top surface of the connecting terminal and making the top surface of the connecting terminal and the top surface of the cover protective layer substantially in the same plane; and forming an OSP coating, the OSP coating being formed at least on the top surface of the connecting terminal.

[0025] The formation of the OSP coating may include forming the OSP coating by dipping, spraying or spin coating.

[0026] The method may further include: after forming the third base device, forming a fourth base device by etching the top surface of the cover protective layer to make the connection terminal protrude above the top surface of the cover protective layer.

[0027] The formation of the OSP coating may include forming the OSP coating on the top surface of the connection terminal and on its side surface exposed above the top surface of the cover protective layer. Attached Figure Description

[0028] The above and other objects, features, and advantages of the present invention will become more apparent to those skilled in the art from the detailed description of exemplary embodiments of the invention with reference to the accompanying drawings, wherein:

[0029] Figure 1 The cross-sectional structure of an existing surface acoustic wave (SAW) wafer-level package is shown;

[0030] Figure 2 The cross-sectional structure of a SAW wafer-level package according to a first embodiment of the present invention is shown;

[0031] Figure 3 The manufacturing process of SAW wafer-level packaging according to a first embodiment of the present invention is shown;

[0032] Figure 4 The cross-sectional structure of a SAW wafer-level package according to a second embodiment of the present invention is shown.

[0033] Figure 5A and 5B The manufacturing process of SAW wafer-level packaging according to a second embodiment of the present invention is illustrated;

[0034] Figure 6 The cross-sectional structure of a SAW wafer-level package according to a third embodiment of the present invention is shown; and

[0035] Figure 7A and 7B The manufacturing process of SAW wafer-level packaging according to a third embodiment of the present invention is shown. Detailed Implementation

[0036] In the following description, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Throughout the following description and drawings, substantially identical elements will be labeled with the same reference numerals, and repeated descriptions will be omitted. Furthermore, in the description of embodiments of the present invention, detailed descriptions of well-known functions or components of the prior art that are deemed to obscure the understanding of the embodiments of the present invention will be omitted.

[0037] Figure 2 The cross-sectional structure of a surface acoustic wave (SAW) wafer-level package 1 according to a first embodiment of the present invention is shown.

[0038] According to this embodiment, the SAW wafer-level package 1 includes a substrate 10, an interdigital transducer (IDT) 20, a connecting electrode 31, a sidewall 41, a cover 51, a connecting terminal 61, and an organic solderable corrosion protectant (OSP) coating 80.

[0039] The substrate 10 performs the function of generating a piezoelectric effect and supporting the device, and can be a piezoelectric substrate. For example, a piezoelectric substrate including LiTa2O3, LiNbO3, etc. can be used.

[0040] The IDT 20 is formed on the substrate 10. The SAW device functions as a filter or the like through the mechanical vibration of the IDT 20.

[0041] Sidewall 41 is formed on substrate 10 around IDT 20 along its periphery. Sidewall 41 may include a material such as photoresist.

[0042] A cover 51 is formed above the sidewall 41 and the IDT 20 to form a hollow portion 46 above the IDT 20. The cover 51 may include a material such as a photoresist.

[0043] A connection electrode 31 is formed on the substrate 10 to be electrically connected to the IDT 20, thereby performing a dielectric function that electrically connects the IDT 20 to an external source. For example, signals input from external terminals are transmitted to the IDT 20 via the connection electrode 31, and signals generated by the IDT 20 are transmitted to external terminals via the connection electrode 31. In this embodiment of the invention, the connection electrode 31 is formed to extend from the inside of the sidewall 41 to the periphery of the sidewall 41.

[0044] The connection terminal 61 is electrically connected to the portion of the connection electrode 31 extending outward from the periphery of the sidewall 41 and is formed covering an outer surface of the sidewall 41, a surface of the cover 51, and a top surface. Furthermore, the top surface of the connection terminal 61 is formed to be higher than the top surface of the cover 51. The connection terminal 61 may include materials such as Ti, Cu, Sn, Ni, Au, etc.

[0045] and Figure 1 The structure shown differs from that of the connecting terminal 60, which vertically passes through the side wall 40 and the cover 50. This embodiment of the invention has... Figure 2 The structure shown includes a connecting terminal 61 formed covering an outer surface of the sidewall 41, a surface of the cover 51, and a top surface. Therefore, the inner surface of the sidewall 41 can be configured to be larger than... Figure 1 The sidewall 40 is positioned further outward, thus forming a hollow portion 46 with a larger area. Therefore, the area used to house the IDT 20 is increased, thereby allowing for an increase in the size or number of such IDT 20.

[0046] OSP coating 80 is formed on the top and side surfaces of the connection terminal 61 and provides improved solderability. OSP coating 80 can be formed to have a thickness of less than approximately 5 μm. Since OSP coating 80 is formed not only on the top surface of the connection terminal 61 but also on the side surfaces of the connection terminal 61, soldering can be applied to the side surfaces of OSP coating 80, thereby further improving solderability.

[0047] OSP uses organic compounds such as alkylbenzimidazole and diphenylimidazole to form a thin and uniform film on the surface of copper or similar materials. The film formed as described above protects the copper surface from external air and moisture, and prevents surface oxidation even in high-humidity environments (such as reflow and adhesive curing), thus providing a clean surface during soldering. Furthermore, in the case of OSP, the film is easily formed through simple processes such as spraying and spin coating, and the copper and solder bond to each other at atomic distances, resulting in excellent adhesion.

[0048] Since the OSP coating 80 can be formed using simple processes such as dipping, spraying, and spin coating, the complex processes involving applying photoresist, electroplating, and removing photoresist to form the tin plating 70 can be omitted. Therefore, in this invention, expensive equipment for forming the tin plating is not required, and the process time is shortened. Furthermore, since the OSP coating 80 is formed with a specific thickness of less than 5 μm, the process of checking the product's quality by measuring, for example, the thickness of the tin plating 70 can be omitted. The reduction in process time and the omission of the quality check process significantly shorten the product's delivery time.

[0049] Figure 3 The process for manufacturing SAW wafer-level packages according to a first embodiment of the present invention is shown.

[0050] As shown in the figure, a basic device 1a is formed, including a substrate 10, an IDT 20, a connecting electrode 31, a sidewall 41, a cover 51, and a connecting terminal 61.

[0051] When the top and side surfaces of the connection terminals 61 of the base device 1a are coated with an OSP solution, the SAW wafer-level package 1 according to the first embodiment is completed, wherein the OSP coating 80 is formed on the top and side surfaces of the connection terminals 61. OSP coating can be performed by immersing a portion or all of the base device 1a in the OSP solution or by using processes such as spraying or spin coating.

[0052] Figure 4 The cross-sectional structure of the SAW wafer-level package 2 according to the second embodiment of the present invention is shown.

[0053] According to this embodiment, the SAW wafer-level package 2 includes a substrate 10, an IDT 20, a connection electrode 31, a sidewall 41, a cover 51, a connection terminal 62, a cover protective layer 90, and an OSP coating 81.

[0054] Since the substrate 10, IDT 20, connecting electrode 31, sidewall 41 and cover 51 are substantially the same as those in the first embodiment, detailed descriptions will be omitted.

[0055] The portion of the connecting terminal 62 protruding above the cover 51 may have a relatively higher height than in the first embodiment to correspond to the thickness d1 of the cover protective layer 90 above the top surface of the cover 51, which will be described below.

[0056] The cover protective layer 90 can be formed around the side surface of the connecting terminal 62 and the top and side surfaces of the cover 51, while exposing the top surface of the connecting terminal 62. Furthermore, the top surface of the connecting terminal 62 and the top surface of the cover protective layer 90 can be substantially in the same plane. In this case, the thickness d1 of the cover protective layer 90 above the top surface of the cover 51 is substantially equal to the height of the portion of the connecting terminal 62 protruding above the cover 51.

[0057] The protective layer 90 may comprise a solid, liquid, or film-like material such as epoxy resin or photoresist. The protective layer 90 protects the cover 51 from external pressure caused by processes such as transfer molding. Therefore, the thickness d1 of the protective layer 90 above the top surface of the cover 51 can be formed to be 20 μm or more. However, when it is necessary to protect the cover 51 from externally applied pressure, the thickness d1 of the protective layer 90 above the top surface of the cover 51 can be formed to be less than 20 μm.

[0058] OSP coating 81 is formed on the top surface of the connection terminal 61 and provides improved solderability.

[0059] Figure 5A and 5B The process for manufacturing SAW wafer-level package 2 according to a second embodiment of the present invention is shown.

[0060] As shown in the figure, a first base device 2a is formed, including a substrate 10, an IDT 20, a connecting electrode 31, a sidewall 41, a cover 51, and a connecting terminal 62'. Here, the portion of the connecting terminal 62' protruding above the cover 51 has a height d1' that is higher than the height d1 of the portion of the connecting terminal 62 to be formed protruding above the cover 51.

[0061] Subsequently, a second base device 2b is formed by forming a cover protective layer 90' surrounding the side surface of the connection terminal 62' and the top and side surfaces of the cover 51, while simultaneously covering the connection terminal 62'. The thickness of the cover protective layer 90' above the top surface of the cover 51 is formed to be greater than the height d1'.

[0062] Subsequently, the top surface of the cover protective layer 90' and the top surface of the connection terminal 62' are planarized to form a third base device 2c, wherein the top surface of the connection terminal 62 is exposed and the top surface of the connection terminal 62 and the top surface of the cover protective layer 90 are substantially in the same plane. Through planarization, the thickness of the cover protective layer 90 above the top surface of the cover 51 is formed to be d1. Planarization can be performed, for example, by grinding.

[0063] When the top surface of the connection terminal 62 of the third base device 2c is coated with an OSP solution, the SAW wafer-level package 2 according to the second embodiment is completed, wherein an OSP coating 81 is formed on the top surface of the connection terminal 62. OSP coating can be performed by immersing part or all of the third base device 2c in the OSP solution or by using processes such as spraying or spin coating.

[0064] Figure 6 The cross-sectional structure of the SAW wafer-level package 3 according to a third embodiment of the present invention is shown.

[0065] According to this embodiment, the SAW wafer-level package 3 includes a substrate 10, an IDT 20, a connecting electrode 31, a sidewall 41, a cover 51, a connecting terminal 63, a cover protective layer 90, and an OSP coating 82.

[0066] Since the substrate 10, IDT 20, connecting electrode 31, sidewall 41 and cover 51 are substantially the same as those in the second embodiment, detailed descriptions will be omitted.

[0067] In the second embodiment, the top surface of the connecting terminal 62 and the top surface of the cover protective layer 90 are substantially in the same plane. However, in this embodiment, the connecting terminal 63 is formed to protrude above the top surface of the cover protective layer 90. For example, the top surface of the connecting terminal 63 may be positioned higher than the top surface of the cover protective layer 90 by d2, and the cover protective layer 90 may be formed to surround the side surface of the connecting terminal 63 and the top and side surfaces of the cover 51, while exposing the portion of the top and side surfaces of the connecting terminal 63 adjacent to the top surface. The height d2 of the connecting terminal 63 protruding above the top surface of the cover protective layer 90 may be approximately 10 μm or less.

[0068] OSP coating 82 is formed on the top surface of the connection terminal 63 and on its side surface protruding above the top surface of the cover protection layer 90, providing improved solderability. Since OSP coating 82 is also formed on the side surface of the connection terminal 63, the side surface of OSP coating 82 can also be soldered, thereby further improving solderability.

[0069] Figure 7A and 7BThe process for manufacturing SAW wafer-level package 3 according to a third embodiment of the present invention is shown.

[0070] As shown in the figure, a first basic device 3a is formed, including a substrate 10, an IDT 20, a connecting electrode 31, a sidewall 41, a cover 51, and a connecting terminal 63'. Here, the height d3 of the portion of the connecting terminal 63' protruding above the cover 51 is higher than the height d1+d2 of the portion of the connecting terminal 63 to be formed protruding above the cover 51.

[0071] Subsequently, a second base device 3b is formed by forming a cover protective layer 90' that simultaneously covers the side surface of the connection terminal 63' and the top and side surfaces of the cover 51. The thickness of the cover protective layer 90' above the top surface of the cover 51 is formed to be greater than the height d3.

[0072] Subsequently, the top surface of the cover protective layer 90' is planarized, and the top surface of the connection terminal 63' is also planarized to form a third base device 3c, wherein the top surface of the connection terminal 63 is exposed and the top surface of the connection terminal 63 and the top surface of the cover protective layer 90' are substantially in the same plane. Through planarization, the thickness of the cover protective layer 90' above the top surface of the cover 51 is formed to be d1+d2. Planarization can be performed, for example, by grinding.

[0073] Subsequently, the top surface of the cover protective layer 90” is etched so that the connection terminal 63 protrudes further beyond the top surface of the cover protective layer 90. The fourth base device 3d is formed by etching, wherein a portion corresponding to thickness d2 is removed from the top surface of the cover protective layer 90”. Etching can be performed, for example, by vapor phase etching.

[0074] When the top surface of the connection terminal 63 of the fourth base device 3d and its side surface exposed above the cover protection layer 90 are coated with an OSP solution, the SAW wafer-level package 3 according to the third embodiment is completed, wherein an OSP coating 82 is formed on the top surface of the connection terminal 63 and the side surface exposed above the cover protection layer 90. OSP coating can be performed by immersing part or all of the fourth base device 3d in an OSP solution or by using processes such as spraying or spin coating.

[0075] According to the present invention, in SAW wafer-level packaging and its manufacturing method, the area of ​​the hollow portion serving as the space for arranging IDTs can be increased, thereby increasing the size or number of such IDTs.

[0076] Furthermore, since an OSP coating is formed on the top surface of the connection terminal, expensive equipment for forming a tin plating layer is not required, and process time can be shortened. In addition, since there is no need to measure the OSP coating thickness, delivery time is further reduced.

[0077] The effects of the present invention are not limited to those described above, and those skilled in the art will understand other unstated effects of the present invention from the above disclosure.

[0078] Exemplary embodiments of the present invention have been described above. Those skilled in the art will understand that modifications can be made to the invention without departing from its essential characteristics. Therefore, the disclosed embodiments should not be considered limiting but descriptive. The scope of the invention is defined in the claims rather than in the foregoing description, and all differences within their equivalents should be understood to be included within the scope of the invention.

Claims

1. A surface acoustic wave (SAW) wafer-level package, comprising: substrate; An interdigitated transducer (IDT) is formed on the substrate; Sidewalls are formed on the substrate along the periphery of the IDT; A cover is formed above the sidewalls and the IDT to form a hollow portion with the sidewalls above the IDT; A connecting electrode is formed on the substrate, electrically connected to the IDT, and extends outward from the periphery of the sidewall; A connection terminal, electrically connected to a portion of the connection electrode extending outward from the periphery of the sidewall, is formed covering an outer surface of the sidewall, an outer surface of the cover, and a portion of the top surface of the cover, and has a top surface formed above the top surface of the cover; as well as An organic solderable corrosion-resistant OSP coating is formed on the top and side surfaces of the connection terminals. The OSP coating is formed along the side surface of the connection terminal and directly contacts the portion of the connection electrode extending outward from the periphery of the sidewall.

2. A method for manufacturing SAW wafer-level packages, the method comprising: A base device is formed, comprising: a substrate; an individual thermal detachment (IDT) formed on the substrate; a sidewall formed on the substrate along the periphery of the IDT; a cover formed above the sidewall and the IDT to form a hollow portion with the sidewall above the IDT; a connecting electrode formed on the substrate, electrically connected to the IDT, and extending outward from the periphery of the sidewall; and a connecting terminal electrically connected to the portion of the connecting electrode extending outward from the periphery of the sidewall, formed covering an outer surface of the sidewall and an outer surface of the cover and a portion of the top surface of the cover, and having a top surface formed above the top surface of the cover; and An OSP coating is formed on the top and side surfaces of the connection terminals. The OSP coating is formed along the side surface of the connection terminal and directly contacts the portion of the connection electrode extending outward from the periphery of the sidewall.

3. The method of claim 2, wherein forming the OSP coating comprises forming the OSP coating by dip coating, spray coating or spin coating.

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