A delay circuit

Abstract

A delay circuit includes a current source, an input and initialization module, a capacitor C0, a current mirror module and a judgment output module; the first current loop of the current mirror module is from a voltage terminal Vcp to a voltage terminal Vss, and the second current loop of the current mirror module is from a voltage terminal Vcn to a voltage terminal Vss; when the input voltage IN of the input and initialization module is a first control level, the ratio of the current I2 of the first current loop to the current I4 of the second current loop is m:1; once the voltage of the voltage terminal Vcp is greater than the reference voltage Vref, the judgment output module outputs a second control level, the second control level has the same phase as the first control level, and the delay time Tdelay is the time difference between the start point of the first control level and the start point of the second control level. Therefore, the present invention reduces the actual charging current of the capacitor C0 by adding a current mirror module, thereby increasing the delay Tdelay, and makes the chip area of ​​the circuit much smaller than the chip area of ​​the traditional circuit.

Description

Technical Field

[0001] The invention belongs to the technical field of circuit design and relates to a delay circuit. Background Art

[0002] The delay circuit is a circuit that can output the enable function after a period of time after the input enable signal. Normally, when you press the switch, the motor starts or shuts down immediately, but with the delay circuit, you can wait for a period of time (the time can be adjusted) before starting or shutting down. For example, the voice-activated LED light will not turn off until a period of time after the voice-activated light is turned on, which is to provide convenience for passers-by to walk later.

[0003] In integrated circuit design, in order to design a larger delay Tdelay and ensure accuracy, the same current source is used. Currently, most current sources are used to charge the capacitor C0 to a certain threshold to make a signal delay circuit. Figure 1 , Figure 1 FIG. 1 is a functional block diagram of a delay circuit in the prior art. Figure 1 As shown, the delay circuit includes a current source, an input module, a capacitor C0 and a comparator. The capacitor C0 and the input module are connected in parallel between the positive input terminal Vc and the voltage terminal Vss of the comparator, the negative input terminal of the comparator is connected to the reference voltage Vref, and the current source is connected between the voltage terminal Vcc and the voltage terminal Vc. Once the input module inputs the control signal IN for opening and closing, the voltage difference on the capacitor C0 changes from 0V in the initial state to Vref, and the change value is Vref. At this time, the comparator outputs the control signal for opening and closing, that is, the control signal is delayed by the time Tdelay.

[0004] See also Figure 2 , Figure 2 Shown Figure 1 Schematic diagram of waveforms of each node in the delay circuit. Figure 2 As shown, when the input voltage IN is at a high level, the voltage terminal Vc starts to increase from 0. When its voltage value increases to the reference voltage Vref, the comparator outputs a high level after a delay time Tdelay.

[0005] Assuming the current source is I0, and usually the reference voltage Vref is fixed in the circuit, then:

[0006] I0*Tdelay=C0*Vref

[0007] However, many application circuits require a relatively large delay time Tdelay. After selecting a suitable current source I0, based on the above formula, to obtain a more ideal state, a large capacitor C0 is required. However, increasing the volume of capacitor C0 in integrated circuit design requires a larger layout area, which means more cost. Summary of the invention

[0008] In order to solve the above technical problems, the present invention proposes a delay circuit, and its technical solution is as follows:

[0009] A delay circuit comprises a current source, an input and initialization module, a capacitor C0, a current mirror module and a judgment output module; the capacitor C0 is connected between the positive input terminal of the judgment output module and one input terminal of the current mirror module, the positive input terminal of the judgment output module is connected to a voltage terminal Vcp, and the other input terminal of the current mirror module is connected to a voltage terminal Vcn; the negative input terminal of the judgment output module is connected to a reference voltage Vref; the current source is connected between the voltage terminal Vcc and the voltage terminal Vcp; one terminal of the input and initialization module is connected to the voltage terminal Vss, the input terminal of the input and initialization module is connected to IN, the first output terminal of the input and initialization module is connected to the voltage terminal Vcp, and the negative input terminal of the input and initialization module is connected to a reference voltage Vref; the current source is connected between the voltage terminal Vcc and the voltage terminal Vcp; one terminal of the input and initialization module is connected to the voltage terminal Vss, the input terminal of the input and initialization module is connected to IN, the first output terminal of the input and initialization module is connected to the voltage terminal Vcp, and the negative input terminal of the input and initialization module is connected to the reference voltage Vref. The second output terminal is connected to the voltage terminal Vcn, the first current loop of the current mirror module is from the voltage terminal Vcp to the voltage terminal Vss, and the second current loop of the current mirror module is from the voltage terminal Vcn to the voltage terminal Vss; when the input voltage IN of the input and initialization module is the first control level, the ratio of the current I2 of the first current loop to the current I4 of the second current loop is m:1; once the voltage of the voltage terminal Vcp is greater than the reference voltage Vref, the judgment output module outputs the second control level, and when the second control level reaches the same as the first control level, the delay time Tdelay is the time difference between the starting point of the first control level and the starting point of the second control level.

[0010] Furthermore, the current mirror module includes a first N-type transistor NFET1 and a second N-type transistor NFET2; the ratio of the channel width to length ratio of the first N-type transistor NFET1 and the channel width to length ratio of the second N-type transistor NFET2 is 1:m; the gates of the first N-type transistor NFET1 and the second N-type transistor NFET2 are connected to the voltage terminal Vcn; the sources of the first N-type transistor NFET1 and the second N-type transistor NFET2 are connected to the voltage terminal Vss; the drain of the first N-type transistor NFET1 is connected to the voltage terminal Vcn, and the drain of the second N-type transistor NFET2 is connected to the voltage terminal Vcp.

[0011] Furthermore, the delay time is: Tdelay=(m+1)C0*(Vref-Vth) / I1, wherein Vth is the turn-on threshold of NFET1, that is, the final voltage of the voltage terminal Vcn.

[0012] Furthermore, the current source includes a current mirror and a bias current module, the current mirror includes a first P-type transistor PFET1 and a second P-type transistor PFET2, the first P-type transistor PFET1, the second P-type transistor PFET2 and the bias current module are used to form a current constant current source to charge the voltage terminal Vcp connected to the capacitor C0.

[0013] Furthermore, the input and initialization module includes an inverter INV, a third N-type transistor NFET3 and a fourth N-type transistor NFET4; the inverter INV is connected between the input terminal IN and the gates of the third N-type transistor NFET3 and the fourth N-type transistor NFET4, the drain of the third N-type transistor NFET3 is connected to the voltage terminal Vcn, the drain of the fourth N-type transistor NFET4 is connected to the voltage terminal Vcp, and the source of the third N-type transistor NFET3 and the fourth N-type transistor NFET4 is connected to the voltage terminal Vss.

[0014] Furthermore, the judgment output module is a comparison module.

[0015] It can be concluded from the above technical solution that in the embodiment of the delay circuit of the present invention, when designing a larger delay time Tdelay requirement, the purpose of reducing the capacitance value of capacitor C0 can be achieved under the same current source condition. If, Vcc = 5V, Vss = 0V, reference voltage Vref = 2.5V, Vth = 0.7V, m = 8, the capacitance value in the circuit of the present invention only needs about 15.4% of the capacitance value of the traditional circuit. That is to say, when the circuit is laid out, capacitor C0 usually occupies the main area. Therefore, the chip area of ​​the circuit formed by the present invention is much smaller than the chip area of ​​the traditional circuit, so that its production cost is also much smaller than that of the traditional circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The figure shows a functional block diagram of a delay circuit in the prior art.

[0017] Figure 2 Shown Figure 1 Waveform diagram of each node in the medium delay circuit

[0018] Figure 3 The figure shows a functional block diagram of a delay circuit in an embodiment of the present invention.

[0019] Figure 4 FIG. 1 is a schematic diagram of a preferred embodiment of a delay circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The following is combined with Figure 3-4 , the specific implementation modes of the present invention are further described in detail.

[0021] Please see attached Figure 3 , Figure 3 FIG. 2 is a functional block diagram of a delay circuit in an embodiment of the present invention. Figure 3 As shown, the delay circuit includes a current source, an input and initialization module, a capacitor C0, a current mirror module and a judgment output module.

[0022] Among them, the capacitor C0 is connected between the positive input terminal of the judgment output module and one input terminal of the current mirror module, the positive input terminal of the judgment output module is connected to the voltage terminal Vcp, and the other input terminal of the current mirror module is connected to the voltage terminal Vcn and the connection point of the positive input terminal of the judgment output module; the negative input terminal of the judgment output module is connected to the reference voltage Vref; the current source is connected between the voltage terminal Vcc and the voltage terminal Vcp; one terminal of the input and initialization module is connected to the voltage terminal Vss, the input terminal of the input and initialization module is connected to IN, the first output terminal of the input and initialization module is connected to the voltage terminal Vcp, the second output terminal of the input and initialization module is connected to the voltage terminal Vcn, the first current loop of the current mirror module is from the voltage terminal Vcp to the voltage terminal Vss, and the second current loop of the current mirror module is from the voltage terminal Vcn to the voltage terminal Vss; when the input voltage IN of the input and initialization module is the first control level, the ratio of the current I2 of the first current loop to the current I4 of the second current loop is m:1.

[0023] Once the voltage at the voltage terminal Vcp is greater than the reference voltage Vref, the judgment output module outputs a second control level. When the second control level reaches the same as the first control level, the delay time Tdelay is the time difference between the starting point of the first control level and the starting point of the second control level.

[0024] That is to say, the actual charging current is reduced and the delay time Tdelay is increased through the current mirror module. Therefore, the delay circuit of the present invention can increase the delay time Tdelay without increasing the capacitance of the capacitor C0 and maintaining the current constant current source.

[0025] See also Figure 4 , Figure 4 FIG. 1 is a schematic diagram of a preferred embodiment of a delay circuit in an embodiment of the present invention. In an embodiment of the present invention, the judgment output module is a comparison module which can be a comparator. The supply voltage Vcc of the current source and the comparator can be 5 volts, for example.

[0026] Specifically, capacitor C0 is connected between the positive input terminal of the judgment output module and one input terminal of the current mirror module. As can be seen from the circuit diagram, the positive input terminal of the judgment output module is connected to the voltage terminal Vcp, and the other input terminal of the current mirror module is connected to the voltage terminal Vcn; the negative input terminal of the judgment output module is connected to the reference voltage Vref.

[0027] The current source is connected between the voltage terminal Vcc and the voltage terminal Vcp; the first initialization loop of the input and initialization module is from the voltage terminal Vcp to the voltage terminal Vss.

[0028] The first current loop of the current mirror module is from the voltage terminal Vcp to the voltage terminal Vss, the input terminal of the input and initialization module is connected to IN, the second initialization loop of the input and initialization module is from the voltage terminal Vcn to the voltage terminal Vss, and the second current loop of the current mirror module is from the voltage terminal Vcn to the voltage terminal Vss.

[0029] In an embodiment of the present invention, the current mirror module may include a first N-type transistor NFET1 and a second N-type transistor NFET2; the ratio of the channel width to length ratio of the first N-type transistor NFET1 and the channel width to length ratio of the second N-type transistor NFET2 is 1:m; the gates of the first N-type transistor NFET1 and the second N-type transistor NFET2 are connected to a voltage terminal Vcn; the sources of the first N-type transistor NFET1 and the second N-type transistor NFET2 are connected to a voltage terminal Vss; the drain of the first N-type transistor NFET1 is connected to the voltage terminal Vcn, and the drain of the second N-type transistor NFET2 is connected to the voltage terminal Vcp.

[0030] When the input voltage IN of the input and initialization module is at the first control level, the ratio of the current I2 of the first current loop to the current I4 of the second current loop is m: 1. Once the voltage of the voltage terminal Vcp is greater than the reference voltage Vref, the judgment output module outputs the second control level, and when the second control level reaches the same as the first control level, the delay time Tdelay is the time difference between the start point of the first control level and the start point of the second control level.

[0031] Usually, the delay time is: Tdelay = (m+1)C0*(Vref-Vth) / I1

[0032] Wherein, Vth is the turn-on threshold of the first N-type transistor NFET1, that is, the final voltage of the voltage terminal Vcn. In other words, the delay time Tdelay is determined by m, the capacitance of the capacitor C0, Vth and the reference voltage. If the capacitance of the capacitor C0, Vth and the reference voltage remain unchanged, the larger the m, the longer the delay time Tdelay.

[0033] The current source may include a current mirror and a bias current module. The current mirror includes a first P-type transistor PFET1 and a second P-type transistor PFET2. The first P-type transistor PFET1, the second P-type transistor PFET2 and the bias current module are used to form a current constant current source to charge the Vcp end of the capacitor C0.

[0034] The input and initialization module includes an inverter INV, a third N-type transistor NFET3 and a fourth N-type transistor NFET4; the inverter INV is connected between the input terminal IN and the gates of the third N-type transistor NFET3 and the fourth N-type transistor NFET4, the drain of the third N-type transistor NFET3 is connected to the voltage terminal Vcn, the drain of the fourth N-type transistor NFET4 is connected to the voltage terminal Vcp, and the source of the third N-type transistor NFET3 and the fourth N-type transistor NFET4 is connected to the voltage terminal Vss.

[0035] In the embodiment of the present invention, for the convenience of description, it can be assumed that VSS=0V, and the above parameters can be set to reference voltage Vref=2.5V, Vth=0.7V, m=8, etc.

[0036] When the delay circuit is in the working initialization state, the input voltage IN of the input and initialization module is 0V, the inverter INV outputs a high level, the third N-type transistor NFET3 and the fourth N-type transistor NFET4 are turned on, Vcn is Vcp is 0V, and the comparator U1 outputs OUT is 0V; at this time, the delay circuit is in the initial state and is in standby state.

[0037] When the delay circuit starts to work, the input voltage IN of the input and initialization module becomes high to Vcc, the inverter INV outputs a low level, and the third N-type transistor NFET3 and the fourth N-type transistor NFET4 are turned off; at this time, the first P-type transistor PFET1, the second P-type transistor PFET2 and the bias current module form a current constant current source to charge the voltage end Vcp of the capacitor C0; at this time, the first N-type transistor NFET1 and the second N-type transistor NFET2 form a current mirror pair, and NFET2 discharges I2 to the Vcp end, and at this time:

[0038] I1-I2=I3, I2=m*I4, I3=I4, so I3=I4=I1 / (m+1)

[0039] Since Tdelay=CV / I, Tdelay=(m+1)C0*(Vref-Vth) / I1

[0040] Among them, Vref-Vth is the voltage drop change on capacitor C0, and Vth is the turn-on threshold of NFET1, that is, the final Vcn voltage.

[0041] When Vcp>Vref, the output of the comparator module U1 is high, that is, the output OUT = VCC. In other words, the delay time Tdelay is the time from the rising edge of the input voltage IN to the rising edge of the output OUT. When the input voltage IN becomes low, the entire circuit re-enters the initial state.

[0042] In summary, the present invention reduces the actual charging current of the capacitor C0 by adding a current mirror module, thereby increasing the delay Tdelay, that is, the purpose of reducing the capacitance value of the capacitor C0 can be achieved with the same current source, and the chip area of ​​the circuit formed is much smaller than that of the traditional circuit chip area, thereby achieving its production cost is also much lower than that of the traditional circuit.

[0043] The above-described embodiments are only preferred embodiments of the present invention, and the embodiments are not intended to limit the patent protection scope of the present invention. Therefore, any equivalent structural changes made using the description and drawings of the present invention should also be included in the protection scope of the present invention.

Claims

1. A delay circuit, characterized in that: It includes a current source, an input and initialization module, a capacitor C0, a current mirror module and a judgment output module; the capacitor C0 is connected between the positive input terminal of the judgment output module and one input terminal of the current mirror module, the positive input terminal of the judgment output module is connected to the voltage terminal Vcp, and the other input terminal of the current mirror module is connected to the voltage terminal Vcn; the negative input terminal of the judgment output module is connected to the reference voltage Vref; the current source is connected between the voltage terminal Vcc and the voltage terminal Vcp; one terminal of the input and initialization module is connected to the voltage terminal Vss, the input terminal of the input and initialization module is connected to IN, the first output terminal of the input and initialization module is connected to the voltage terminal Vcp, the second output terminal of the input and initialization module is connected to the voltage terminal Vcn, the first current loop of the current mirror module is from the voltage terminal Vcp to the voltage terminal Vss, and the second current loop of the current mirror module is from the voltage terminal Vcn to the voltage terminal Vss; when the input voltage IN of the input and initialization module is a first control level, the ratio of the current I2 of the first current loop to the current I4 of the second current loop is m:1; Once the voltage of the voltage terminal Vcp is greater than the reference voltage Vref, the judgment output module outputs a second control level. When the second control level reaches the same level as the first control level, the delay time Tdelay is the time difference between the start point of the first control level and the start point of the second control level. The current mirror module includes a first N-type transistor NFET1 and a second N-type transistor NFET2; the ratio of the channel width-to-length ratio of the first N-type transistor NFET1 and the channel width-to-length ratio of the second N-type transistor NFET2 is 1:m; the gates of the first N-type transistor NFET1 and the second N-type transistor NFET2 are connected to the voltage terminal Vcn; the sources of the first N-type transistor NFET1 and the second N-type transistor NFET2 are connected to the voltage terminal Vss; the drain of the first N-type transistor NFET1 is connected to the voltage terminal Vcn, and the drain of the second N-type transistor NFET2 is connected to the voltage terminal Vcp; The judgment output module is a comparison module.

2. The delay circuit according to claim 1, characterized in that: The delay time is: Tdelay=(m+1)C0*(Vref-Vth) / I1 Wherein, Vth is the turn-on threshold of NFET1, that is, the final voltage of the voltage terminal Vcn.

3. The delay circuit according to claim 1, characterized in that: The current source includes a current mirror and a bias current module. The current mirror includes a first P-type transistor PFET1 and a second P-type transistor PFET2. The first P-type transistor PFET1, the second P-type transistor PFET2 and the bias current module are used to form a current constant current source to charge the voltage terminal Vcp connected to the capacitor C0.

4. The delay circuit according to claim 1, characterized in that: The input and initialization module includes an inverter INV, a third N-type transistor NFET3 and a fourth N-type transistor NFET4; the inverter INV is connected between the input terminal IN and the gates of the third N-type transistor NFET3 and the fourth N-type transistor NFET4, the drain of the third N-type transistor NFET3 is connected to the voltage terminal Vcn, the drain of the fourth N-type transistor NFET4 is connected to the voltage terminal Vcp, and the source of the third N-type transistor NFET3 and the fourth N-type transistor NFET4 is connected to the voltage terminal Vss.

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