Device and method for increasing transmission power

Abstract

The present invention discloses an apparatus and method for reducing unwanted CIM3 emissions in a wireless communication device, so that the transmit (TX) power level applied in the RU can be increased without exceeding regulatory emission requirements. In some aspects, unwanted emissions can be reduced by offsetting or changing the local oscillator (LO) frequency during TX operation. Some embodiments relate to a fast locking PLL with adjustable bandwidth, which can be controlled to increase the PLL bandwidth during RX to TX conversion to provide fast locking to the new LO frequency. Some aspects relate to configuring LO frequency offsets for different RUs when multiple RUs are allocated within a frequency band.

Description

Technical Field

[0001] The present application relates generally to methods and apparatus for wireless communications and, more particularly, to wireless transmissions utilizing Wi-Fi networks. Background Art

[0002] Wireless networks use radio frequency (RF) waves to allow communication between wireless communication devices over long distances without the limitations of wire-based communication systems. In a typical wireless communication device, a transmitter obtains an RF input signal containing information such as voice or data and formats the RF input signal into an appropriate radio frequency (RF) radio signal in a predetermined frequency band for transmission through one or more RF antennas. In the transmitter, the RF input signal may be a radio frequency (RF) having a frequency F. IF The intermediate frequency (IF) signal is mixed with the intermediate frequency (IF) signal in the mixer. LO The local oscillator (LO) signal is mixed to generate a carrier frequency F RF The RF radio signal is transmitted by the RF input signal. A wireless communication device may have a receiver, and typically has a transceiver, which includes both a transmitter and a receiver in one package. In the receiver, the received and amplified RF radio signal is mixed with the LO signal in a mixer to extract the RF input signal (sometimes also called a baseband signal), which can be further demodulated to reproduce the above-mentioned information conveyed therein.

[0003] In a Wi-Fi network, wireless communication devices communicate data wirelessly via, for example, a wireless access point (AP) or in an ad-hoc fashion within the range of the Wi-Fi network. Wireless communication devices can be portable and can draw power from a mobile power source such as a rechargeable or replaceable battery, without being tethered to a power network for power or data communications.

[0004] Wi-Fi signals in a Wi-Fi network communicate based on the 802.11 protocol. In some Wi-Fi networks, Wi-Fi signals are transmitted based on orthogonal frequency-division multiple access (OFDMA) transmission technology, in which subsets of subcarrier frequency bands are allocated to different users.

[0005] In OFDMA transmissions such as those specified in 802.11ax, subsets of time-frequency resources are allocated to allow simultaneous data transmission from multiple users. For example, the wide channels specified in 802.11ac (20MHz, 40MHz, 80MHz, 80+80MHz, and 160MHz) can be subdivided into a set of subcarriers ("tones") using OFDMA. Adjacent frequency bands are combined into resource units (RUs), and the transmitter can select the best RU for each specific receiver to reduce interference and improve the signal to noise ratio (SNR). A RU can include 26, 52, 106, 242, 484, 996, or 2×996 frequency bands. Each wide RU can be divided into two RUs that are approximately twice as narrow. 20MHz bandwidth, 40MHz bandwidth, 80MHz bandwidth and 80+80(160)MHz bandwidth correspond to 242-tone RU, 484-tone RU, 996-tone RU and two 996-tone RU respectively. For example, for 20MHz bandwidth, nine 26-tone RUs can be used, and at the same time, four 52-tone RUs can be used alternately. Summary of the invention

[0006] The following summary is illustrative only and is not intended to be limiting in any way. That is, the following overview is provided to introduce the concepts, highlights, benefits, and advantages of the novel and non-obvious technologies described herein. Selected embodiments are further described in the detailed description below. Therefore, the following summary is neither intended to identify the essential features of the claimed subject matter nor to be used to determine the scope of the claimed subject matter.

[0007] The present invention discloses an apparatus and method for reducing unwanted CIM3 emission in a wireless communication device, so that the transmission (TX) power level applied in the RU can be increased without exceeding the regulatory emission requirements. In some aspects, the unwanted emission can be reduced by shifting or changing the local oscillator (LO) frequency during TX operation. Some embodiments relate to a fast locking PLL with adjustable bandwidth, which can be controlled to increase the PLL bandwidth during the RX to TX conversion to provide a fast lock to the new local oscillator (LO) frequency. Some aspects relate to configuring LO frequency offsets for different RUs when multiple RUs are allocated within a frequency band.

[0008] According to some embodiments, the present invention discloses a method for operating a device for wireless communication in a plurality of allocated resource units (RUs) within a frequency band. The method includes, for one or more RUs among the plurality of RUs: receiving a receive (RX) signal in the RU and demodulating the RX signal using a local oscillator (LO) signal; changing the frequency of the LO signal; and, after changing the frequency of the LO signal, modulating a transmit (TX) data packet for transmission using the LO signal.

[0009] In some embodiments, the method further comprises: providing the LO signal using a phase locked loop (PLL); wherein changing the frequency of the LO signal comprises: locking the PLL from a first LO frequency to a second LO frequency.

[0010] In some embodiments, locking from the first LO frequency to the second LO frequency is accomplished in a duration of no more than 5 μs.

[0011] In some embodiments, the PLL includes: a phase frequency detector PFD, a voltage controlled oscillator VCO, and at least one charge pump coupled between the PFD and the VCO, wherein changing the frequency of the LO signal includes: increasing the bandwidth of the PLL before changing the frequency of the LO signal.

[0012] In some embodiments, the input terminal of the VCO is coupled to a reference voltage node via a resistor, wherein changing the frequency of the LO signal further comprises: adjusting a value of the resistor to maintain a damping ratio of the PLL unchanged.

[0013] In some embodiments, increasing the bandwidth of the PLL includes increasing the magnitude of a charge pump current in the at least one charge pump.

[0014] In some embodiments, the input terminal of the VCO is coupled to a reference voltage node via a capacitor, wherein increasing the bandwidth of the PLL includes: adjusting the amplitude of the capacitor.

[0015] In some embodiments, the PLL further includes a frequency divider coupled to the PFD, wherein increasing the bandwidth of the PLL includes adjusting a division factor of the frequency divider.

[0016] In some embodiments, the PLL is configured to provide one or more reference pulses to the PFD, wherein increasing the bandwidth of the PLL comprises increasing a rate of pulses in the one or more reference pulses.

[0017] In some embodiments, the method further comprises: for each of the one or more RUs, determining a LO frequency offset based on the RU and the frequency band, wherein changing the frequency of the LO signal comprises: changing the frequency of the LO signal by the LO frequency offset.

[0018] In some embodiments, the one or more RUs include a first RU and a second RU, the first RU being closer to an edge of the frequency band than the second RU, and a first LO frequency offset determined for the first RU is higher in magnitude than a second LO frequency offset determined for the second RU.

[0019] According to some embodiments, the present invention discloses an apparatus for wirelessly transmitting a transmit (TX) signal during a TX period and wirelessly receiving a receive (RX) signal during an RX period. The apparatus includes a phase-locked loop (PLL) and a controller, the PLL being configured to generate an oscillator (LO) signal, the controller being coupled to the PLL and being configured to change the frequency of the LO signal during a transition between an RX period and a TX period. The RX signal is demodulated using the LO signal, and the TX signal is modulated using the LO signal.

[0020] In some embodiments, the PLL includes: a phase frequency detector (PFD); a voltage controlled oscillator (VCO); and at least one charge pump coupled between the PFD and the VCO, wherein the controller is further configured to: increase the bandwidth of the PLL before changing the frequency of the LO signal.

[0021] In some embodiments, the input terminal of the VCO is coupled to a reference voltage node via a programmable resistor, and the controller is configured to adjust a value of the programmable resistor to maintain a damping ratio of the PLL unchanged.

[0022] In some embodiments, the programmable resistor includes a resistor and a switch coupled to the resistor.

[0023] In some embodiments, the controller is further configured to increase the magnitude of a charge pump current in the at least one charge pump.

[0024] In some embodiments, the input of the VCO is coupled to a reference voltage node via a programmable capacitor, and the controller is further configured to increase the bandwidth of the PLL by adjusting the amplitude of the programmable capacitor.

[0025] In some embodiments, the programmable capacitance includes a capacitor and a switch coupled to the capacitor.

[0026] In some embodiments, the PLL further includes a frequency divider coupled to the PFD, and the controller is further configured to increase the bandwidth of the PLL by adjusting a frequency division factor of the frequency divider.

[0027] In some embodiments, the PLL further includes: a reference unit coupled to the PFD, the reference unit configured to receive one or more reference pulses and generate one or more modified pulses based on the one or more reference pulses for the PFD, wherein the modified pulses have a higher pulse rate than the one or more reference pulses received by the reference unit.

[0028] In some embodiments, the reference unit includes a plurality of delay lines configured to receive a reference pulse of the one or more reference pulses and generate a plurality of delayed reference pulses for each reference pulse.

[0029] In some embodiments, the reference unit further includes a multiplexer coupled between the plurality of delay lines and the PFD, the multiplexer configured to combine the plurality of delayed reference pulses to generate the modified pulse.

[0030] In some embodiments, the PLL is configured to change the frequency of the LO signal within a duration not exceeding 5 μs.

[0031] Those skilled in the art will no doubt understand these and other objects of the present invention after reading the following detailed description of the preferred embodiments shown in the accompanying drawings. The detailed description will be given in the following embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings are included to provide a further understanding of the embodiments of the present invention, and the accompanying drawings are incorporated into and constitute a part of the embodiments of the present invention. The accompanying drawings illustrate implementations of the embodiments of the present invention and, together with the description, are used to explain the principles of the embodiments of the present invention. It is understood that the drawings are not necessarily drawn to scale, as some components may be shown not to scale with the actual implementation size to clearly illustrate the concepts of the embodiments of the present invention.

[0033] Figure 1A is a schematic frequency domain diagram illustrating undesired emissions due to nonlinear intermodulation products.

[0034] Figure 1B is a schematic frequency domain diagram illustrating shifting a local oscillator (LO) frequency during TX operation according to some embodiments.

[0035] Figure 2 is a timing diagram illustrating local oscillator (LO) frequency during transitions between RX and TX operations in a wireless communication device according to some embodiments.

[0036] Figure 3 is a schematic diagram of components in a wireless communication device 300 having a fast locking PLL according to some embodiments.

[0037] Figure 4 According to some embodiments, Figure 3 A series of timing diagrams illustrating an exemplary process of shifting the local oscillator (LO) frequency in a fast lock PLL are shown.

[0038] Figure 5 is a schematic diagram of an exemplary fast locking PLL 500 according to some embodiments.

[0039] Figure 6 According to some embodiments, Figure 5 A schematic flow chart of a process 600 for controlling an offset local oscillator (LO) frequency in a fast lock PLL is shown.

[0040] 7A to 7D are schematic diagrams each showing an embodiment of a PLL with an adjustable bandwidth.

[0041] Fig. 7E According to some embodiments Fig.7D Schematic timing diagram of the modified reference clock (clock) generated in the PLL.

[0042] Fig. 8A is a schematic diagram illustrating a first embodiment of LO frequency offset configuration for different RU locations.

[0043] Figure 8B is a schematic diagram illustrating a second embodiment of LO frequency offset configuration for different RU locations.

[0044] Fig. 9 is a schematic diagram illustrating RU allocation in a 40 MHz HE PPDU.

[0045] Fig.10 is a schematic diagram illustrating channel allocation for wide 80 MHz and 160 MHz bandwidths.

[0046] In the following detailed description, for the purpose of illustration, many specific details are set forth so that those skilled in the art can more thoroughly understand the embodiments of the present invention. However, it is apparent that one or more embodiments may be implemented without these specific details, and different embodiments may be combined as needed, and should not be limited to the embodiments listed in the accompanying drawings. DETAILED DESCRIPTION

[0047] The following description is a preferred embodiment of the present invention, which is only used to illustrate the technical features of the present invention, and is not used to limit the scope of the present invention. Certain words are used throughout the specification and claims to refer to specific components. It should be understood by those skilled in the art that manufacturers may use different names to refer to the same components. Therefore, the present specification and claims do not use the difference in name as a way to distinguish components, but use the difference in function of the components as a basis for distinction. The terms "component", "system" and "device" used in the present invention can be entities related to computers, wherein the computer can be hardware, software, or a combination of hardware and software. The terms "including" and "comprising" mentioned in the following description and claims are open-ended terms, so they should be interpreted as "including, but not limited to...". In addition, the term "coupled" means an indirect or direct electrical connection. Therefore, if a device is described as coupled to another device, it means that the device can be directly electrically connected to the other device, or indirectly electrically connected to the other device through other devices or connection means.

[0048] Corresponding numbers and symbols in the various figures of the drawings generally refer to corresponding parts unless otherwise indicated. The drawings are drawn to clearly illustrate the relevant parts of the embodiments and are not necessarily drawn to scale.

[0049] The term "substantially" or "approximately" as used herein means that within an acceptable range, a person skilled in the art can solve the technical problem to be solved and basically achieve the technical effect to be achieved. For example, "approximately equal to" means that a certain error from "completely equal to" is acceptable to a person skilled in the art without affecting the correctness of the result.

[0050] The wireless signal has undesired emissions on one or more frequencies outside the necessary bandwidth allocated for wireless signal transmission. The power level of the undesired emission is subject to regulatory emission requirements such as the Federal Communications Commission (FCC). According to protocols such as Wi-Fi 802.11ax, users are assigned RUs with dedicated narrow bandwidths for signal transmission. Transmit power is aggregated within the allocated bandwidth using linear transmitters and harmonic rejection mixers. Despite this, there may still be undesired emissions whose power levels violate FCC emission specifications. For example, although OFDMA allows different transmit (TX) powers to be applied to different RUs, increasing the TX power for the RU will result in an increase in undesired emissions, such as third-order counter-intermodulation products (3rd-order counter-intermodulation product, CIM3) caused by third-order nonlinearities in the transmitter. Therefore, the TX power for the RU is limited to avoid exceeding the emission requirements.

[0051] The present invention discloses a device and method for reducing CIM3 transmission in a wireless communication device, so that the TX power level applied in the RU can be increased without exceeding the transmission requirements. Therefore, as a result of increasing the Tx power level, the wireless communication device can achieve higher transmission efficiency, accuracy and range.

[0052] In some aspects of the present application, undesired emissions can be reduced by shifting or changing the local oscillator (LO) frequency between transmit (TX) operation and receive (RX) operation, so that different local oscillator (LO) frequencies are used to modulate / demodulate the RX signal and the TX signal. For example, the LO frequency used to demodulate the RX signal is F LO , and the LO frequency used to modulate the TX signal is F LO +δf or F LO -δf. In an embodiment of the present invention, by changing the local oscillator (LO) frequency between TX packets and RX packets, unwanted CIM3 transmission can be reduced. For example, if the LO frequency is offset to align with the data unit (RU) frequency, CIM3 transmission is reduced.

[0053] During high data rate wireless communication, it is desirable to complete the change of the local oscillator (LO) frequency in a short time to avoid interruption of continuous RX and TX operations. Some aspects of the present application relate to a fast locking phase locked loop (PLL) in a wireless communication device, which can be controlled to quickly change the local oscillator (LO) frequency during the transition / transition between the RX window and the TX window. In some embodiments, the fast locking PLL has an adjustable bandwidth and is controlled to first increase the bandwidth of the PLL before changing the local oscillator (LO) frequency to achieve faster locking during the transition to the new local oscillator (LO) frequency. After locking, the bandwidth of the PLL is reduced to a normal level to maintain the accuracy of the PLL. In some embodiments, the change of the local oscillator (LO) frequency is achieved in a short time (e.g., within 5 microseconds (μs) or within 2 microseconds).

[0054] A PLL with an adjustable bandwidth for changing the frequency of a local oscillator (LO) can be implemented in a variety of ways, as described in detail below. In an embodiment of the present invention, the bandwidth of a fast locking PLL is adjustable. In short, in some embodiments, the charge pump current in the PLL can be changed to adjust the bandwidth. In some embodiments, the resistance and / or capacitance RC values ​​(impedance and / or capacitance RC values) between the reference voltage node and the voltage-controlled oscillator (VCO) can be adjusted to select the bandwidth. In some embodiments, the bandwidth can be adjusted by changing the frequency division factor / ratio N (N-ratio) of the divider (divider, also referred to as a divider) in the PLL. In yet other embodiments, the reference pulse provided to the PLL can be modified to have a higher pulse rate.

[0055] Still other aspects relate to methods for configuring LO frequency shift amounts for different RUs when multiple RUs are allocated within a frequency band. In an embodiment of the present invention, for multiple RUs, it is not necessary for each RU to have the same LO frequency offset during the transition from RX to TX. For some RUs, it is necessary to have a higher LO frequency offset or no LO frequency offset at all to reduce transmission. In some embodiments, the LO frequency offsets for different channels are different. For example, RUs closer to the edge of the frequency band can have a higher magnitude LO frequency offset to improve transmission performance.

[0056] Figure 1A FIG1A is a schematic frequency domain diagram illustrating undesired emissions due to nonlinear intermodulation products. FIG1A illustrates frequency bands 20 and 22, and an RU 10 for RX or TX in band 20. Undesired emissions 12 occur below the local oscillator (LO) frequency F due to third order harmonics in the transceiver circuit. LO Specifically, for CIM3, the undesired emission 12 is at F LO -3×ΔF is the center, where ΔF is located at F LO and the center RF frequency of the RU 10. As the TX power level in the band 20 increases, the power level of the unwanted CIM3 emissions 12 also increases and there is a risk of exceeding the emission requirements 14 (e.g., -48 dBm / MHz required by the FFC specification) at the nearby band 22. As a result, the TX power level cannot be increased beyond the maximum level due to the limitations of the emission requirements. One object of the present application is to reduce the impact of CIM3 emissions to allow the TX power level to be further increased beyond Figure 1A The maximum level allowed for the scene.

[0057] Figure 1B is a schematic frequency domain diagram of shifting the local oscillator (LO) frequency during TX operation according to some embodiments. Figure 1B In the case of LO ', to get closer to the center frequency of RU 10. At the same time, IF is correspondingly reduced to ΔF' so that the RF frequency of RU is maintained. LO '-3×ΔF' is centered, which is far from band 22, and, in the case Figure 1AThe emission at band 22 is shown to be eliminated. Thus, shifting the LO frequency during TX helps to relax the TX CIM3 requirement and allows an increase in TX power levels.

[0058] It should be understood that although Figure 1B In the example, F LO offset by a positive amount, but this is not required, and, in some embodiments, TX F LO The offset can be negative. For example, when F LO is located to the right of the center frequency of RU. Correspondingly, F LO When the offset of TX is negative, the offset of IF is positive to keep the RF frequency constant. It should also be understood that while CIM3 transmission is shown as an example, other undesired transmissions from nonlinear mixing or other mechanisms may also exist and may also benefit from the disclosed aspects of shifting the TX local oscillator (LO) frequency.

[0059] Figure 2 is a timing diagram illustrating a local oscillator (LO) frequency during a transition between RX and TX operations in a wireless communication device / apparatus according to some embodiments. Figure 2 As shown, during the first transition 221, the local oscillator (LO) frequency increases from F at TX cycle 202 to F at TX cycle 203. LO_TX Offset to different value F at RX cycle 212 LO_RX , and shifts to F during the second transition 222 from the RX cycle 212 to the TX cycle 204 LO_TX During an RX period, the device receives an RX signal in one of the one or more RUs and based on the F LO_RX The device demodulates the RX signal based on the LO signal, for example, mixing the received RX signal with the LO signal. LO_TX (It is from F LO_RX The LO signal obtained by the offset (i.e., the LO signal obtained by the offset) modulates the TX data packet, for example, the data packet is mixed with the LO signal before transmission. Since the offset LO signal is used during the TX period, undesired emissions (e.g., CIM3 emissions) are reduced and the maximum TX power level can be increased without violating the CIM3 emission requirements.

[0060] In the embodiment of the present invention, in order to prevent data transmission interruption during wireless communication, as Figure 2 As shown in F LO_RX and F LO_TXThe time spent in transitioning between needs to be minimized. According to one aspect, a fast locking PLL is provided, which has a means for completing the shift of the local oscillator (LO) frequency and locking to the new local oscillator (LO) frequency in a short time (e.g., no more than 5μs, no more than 2μs, no more than 1μs, or within a duration between 1μs and 10μs). In some embodiments, the PLL is controlled to perform a "gear shift" to a higher bandwidth during the local oscillator (LO) frequency transition to achieve fast locking, and then shift back to a lower normal bandwidth after locking to the new local oscillator (LO) frequency to make the integrated phase noise lower.

[0061] Figure 3 FIG. 1 is a schematic diagram of components in a wireless communication device 300 having a fast locking PLL according to some embodiments. In the device 300, the PLL 320 generates a local oscillator (LO) with a frequency F LO The LO signal 303 is mixed with the received RF signal 305 (which has an RF frequency F at the mixer 304). RF ) is mixed to generate an intermediate frequency F IF signal. Figure 3 In the illustrated embodiment, PLL 320 generates a local oscillator (LO) frequency F having an offset LO The mixer 308 combines the LO signal 307 with the IF signal (which has a frequency F IF -δf) to generate an RF signal 309 for transmission (having an RF frequency F RF In another embodiment, the PLL 320 can adjust the frequency F of the LO signal to LO The offset is “-δf”, so that the frequency F of the intermediate signal IF is shifted accordingly by “+δf” to maintain the frequency of the RF signal 309 unchanged.

[0062] Table 1

[0063] RX Mode TX Mode LO frequency <![CDATA[F LO ]]> <![CDATA[F LO +δf]]> IF frequency <![CDATA[F IF ]]> <![CDATA[F IF -δf]]> RF frequency <![CDATA[F RF ]]> <![CDATA[F RF ]]>

[0064] exist Figure 3In the embodiment, the PLL 320 is controlled by the controller 302 (for example, the controller can be a digital signal processor (DSP)) to change the local oscillator (LO) frequency between the RX mode and the TX mode according to Table 1. Table 1 summarizes the LO frequency, IF frequency and RF frequency during the operation of the device 300 according to some embodiments. During the transition from the RX mode to the TX mode, the PLL 320 is controlled by the controller 302 to change the F LO The amount of "δf" is changed to reduce unwanted emissions as described elsewhere in this disclosure. Accordingly, the device 300 will change the IF frequency by an amount of "-δf" using suitable techniques known to those of ordinary skill in the art so that the combined RF frequency for TX remains at the same F RF It should be understood that δf can be any reasonable value and can be positive (to increase F LO ) or negative (to reduce F LO ), which is not limited in this embodiment of the present invention.

[0065] Figure 3 Controller 302 is shown coupled to PLL 320 via control data path 322 ( Figure 3 In some embodiments, in response to a control signal sent from the controller 302 in the control data path 322, the PLL 320 is controlled to change the local oscillator (LO) frequency. Figure 3 An example of using the control signal "LO_index" to specify the LO frequency offset δf for a given channel or RU is shown. The control signal "Fast_Locking_EN" is used to trigger the PLL to switch to a fast locking mode to lock to a new LO frequency more quickly. In some embodiments, the PLL increases its bandwidth in the fast locking mode and restores the PLL bandwidth to a normal lower level after locking is completed. Although not shown, it should be understood that additional or different control signals and / or parameter data can be transmitted in the control data path 322 to control the operation of the PLL 320.

[0066] Controller 302 may include any suitable logic, processor and / or memory elements, and may include any suitable processing device, such as, but not limited to, a central processing unit (CPU), a digital signal processor (DSP), an addressable controller, a general or special purpose microprocessor, a microcontroller, an addressable microprocessor, a programmable processor, a programmable controller, a special purpose processor, a special purpose controller, or any other suitable processing device. Some or all components within controller 302 may be packaged as a system-on-a-chip (SOC), which in some embodiments may include PLL 320 and other components, such as Figure 3 In addition, it should be understood that Figure 3 is a simplified representation of controller 302. An actual implementation of controller 302 may include separate circuits for processing RX and TX data and sending and receiving data and control signals to components such as PLL 320.

[0067] The controller 302 may include a non-transitory computer-readable storage medium, which may include, for example, volatile and / or non-volatile memory. The non-transitory computer-readable storage medium may store one or more instructions, such as, but not limited to, firmware, to program one or more processors to perform any method or process described herein. In some examples, the components disclosed herein may read parameters that affect the functions performed by the components. These parameters may be physically stored in any form of suitable memory, including volatile memory (e.g., RAM) or non-volatile memory (e.g., but not limited to flash memory, EPROM, or EEPROM). In addition, the parameters may be logically stored in a proprietary data structure (e.g., a database or file defined by a user space application process) or a public shared data structure (e.g., an application registry defined by an operating system). In addition, some examples provide systems and user interfaces that allow external entities to modify parameters to configure the behavior of the components. As described above, the terms "code," "program," or "software" are used in a general sense herein to refer to any type of computer code or computer executable instruction set that can be used to program a computer or other processor to implement various aspects of the present invention. In addition, it should be understood that, according to an aspect of this embodiment, when executing the method of the present invention, one or more computer programs do not need to reside on a single computer or processor, but can be distributed on a plurality of different computers or processors in a modular manner to realize various aspects of the present invention. The computer executable instruction can be in various forms, such as program modules, performed by one or more computers or other devices. Usually, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or realize specific abstract data types. Usually, the functions of program modules can be combined or distributed in various embodiments as needed. Instructions can be stored durably as coded signals, and the instructions can make the processor perform any function described herein.

[0068] According to some embodiments, Figure 4 It is explained in Figure 3 A series of timing diagrams illustrating an exemplary process of shifting the local oscillator (LO) frequency in a fast lock PLL are shown. Figure 4A default local oscillator (LO) frequency indicated by LO_index of 4'b0000 is shown for RX cycle 402. After transitioning to TX cycle 404, a shifted local oscillator (LO) frequency having an LO frequency offset δf is indicated by LO_index of 4'bxxxx, which is restored to the default local oscillator (LO) frequency after transitioning from TX cycle 404 to RX cycle 406, e.g., after the end of TX cycle 404, LO_index becomes 4'b0000. Cycle 408 is a TX cycle indicated as having an unchanged default local oscillator (LO) frequency. It should be appreciated that any suitable encoding scheme may be used to program LO_index to indicate the amount of LO frequency. The bit length in LO_index and the type of information conveyed therein are as follows: Figure 4 As shown, Figure 4 This is merely an example and aspects of the present invention are not limited thereto.

[0069] Still refer to Figure 4 , Figure 4 It is shown that Fast_locking_EN is used to trigger a change in PLL bandwidth during the transition between RX / TX cycles to allow fast locking to a new LO frequency value. In particular, at the end of the RX cycle 402, Fast_locking_EN changes from low to high and remains high during the transition period 412 from the RX cycle to the TX cycle to indicate switching to a higher PLL bandwidth. Similarly, at the beginning of the TX cycle 404, Fast_locking_EN changes from high to low and remains low during the TX cycle 404 to indicate switching back to a lower PLL bandwidth; at the end of the TX cycle 404, Fast_locking_EN changes from low to high and remains high during the transition period 414 from the TX cycle to the RX cycle to indicate switching to a higher PLL bandwidth. It should be understood that the low-to-high transition shown for Fast_locking_EN in the periods 412 and 414 is only an example, and in other embodiments of the present invention, opposite polarity or any other suitable encoding method may also be used.

[0070] Figure 5 is a schematic diagram of an exemplary fast locking PLL 500 according to some embodiments. The PLL 500 includes a phase-frequency detector (PFD), a voltage controlled oscillator (VCO), at least one charge pump (CP) coupled between the PFD and the VCO, and a resistor (impedance) R coupled between ground and an input terminal of the VCO. Pand capacitance C P , and a divider with a division factor N, such as a multi-modulus divider (MMD).

[0071] Figure 6 According to some embodiments, Figure 5 Schematic flow chart of process 600 for controlling local oscillator (LO) frequency offset in a fast lock PLL shown. At block 602 of process 600, the value of LO_index is read to determine whether a switch of local oscillator (LO) frequency should be performed. If the value of LO_index is zero, process 600 ends. As a variation of process 600, if it is not necessary to read the index to determine whether a change in local oscillator (LO) frequency is required, block 602 can be omitted for the process starting from block 604.

[0072] If the value of LO_index requires a change in LO frequency, Fast_Locking_EN is set to 1 at block 6604 to enable a wide PLL bandwidth. At block 606, PLL parameters are changed, such as, but not limited to, the frequency division factor of the frequency divider in the PLL and the control code (Process Code) Pcode that controls the VCO to adjust the frequency, to switch the local oscillator (LO) frequency. In an embodiment of the present invention, the frequency can be adjusted by using the control code Pcode. For example, for ease of understanding, an example is given for example, if Pcode=1, frequency=9GHz, Pcode=2, frequency=9.1GHz, Pcode=3, frequency=9.2GHz, then when the current frequency=9GHz is expected to be adjusted to 9.2GHz, the control code Pcode can be changed from 1 to 3. Block 608 provides an appropriate waiting time for the new local oscillator (LO) frequency to be locked. At block 610, Fast_Locking_EN is set to 0 to disable the wide PLL bandwidth and restore the PLL bandwidth to a normal value from the wide PLL bandwidth.

[0073] It should be understood that although Figure 4 and Figure 6 Blocks 604, 610 of FIG. 5 show an example of switching between wide and normal PLL bandwidth levels during a local oscillator (LO) frequency switching operation, but aspects of the present application are not limited to having two bandwidth levels. For example, the PLL may have one or more intermediate bandwidth levels and may be controlled to switch to the highest bandwidth, then one or more intermediate bandwidths, and then return to the normal bandwidth level to quickly lock to the new LO frequency.

[0074] 7A to 7D Several exemplary implementations of a PLL with a means for adjusting the PLL bandwidth to provide fast lock are shown.

[0075] Fig. 7A is a schematic diagram illustrating a first embodiment of a PLL 700A with adjustable bandwidth. Fig. 7A As shown, the PLL 700A includes one or more programmable current sources 702, which are controlled by the controller to increase or decrease the charge pump current I CP The magnitude of Therefore, I CP Increase α 2 The bandwidth will be increased by α times, where Kvco represents the slope of the control voltage of the VCO and the output frequency. The programmable current source 702 can be implemented by any suitable circuit known in the art.

[0076] At the same time, the damping coefficient with I CP is proportional to the square root of CP Growth α 2 times, the damping factor will increase by α times (α>1). In order to stabilize δ before and after bandwidth adjustment, Figure 5 The resistor R shown P The value of I CP The change is adjusted to R P / α to maintain δ at a constant level. In FIG7A , the resistor R P It is a programmable resistor, that is, its value can be adjusted. P are implemented as having values ​​R P / α and (1-1 / α)R P The switch 704 is provided when I CP Increased α 2 When the PLL bandwidth is increased by a factor of 2, the switch can be controlled to make (1-1 / α)R P The resistor is short-circuited, so R P The effective resistance from R P The value becomes R P / α to maintain the damping coefficient. It should be understood that the programmable resistor R P It can be implemented in any suitable manner known in the art and should not be limited to Fig. 7A The example shown in .

[0077] Figure 7B FIG. 1 is a schematic diagram illustrating a second embodiment of a PLL 700B with adjustable bandwidth. In the PLL 700B, the capacitor C Pand resistor R P The values ​​of are adjusted simultaneously to change the PLL bandwidth ω n and at the same time stabilize the damping factor δ. In particular, when C P Change to C P / α 2 And R P becomes α·R P When the bandwidth ω n will become α·ω n , while the damping factor δ remains constant.

[0078] exist Figure 7B In the circuit, the capacitor C P is programmable capacitance, resistance R P is the programmable resistor. The programmable capacitor is composed of C P / α 2 The first capacitance is (1-1 / α 2 )·C P The programmable resistor is (α-1)·R P The first resistor and the second resistor R P The first switch 706 is coupled in parallel with the first resistor, and the second switch 708 is coupled in series between the top terminals of the first capacitor and the second capacitor. The switches 706 and 708 are closed during normal mode operation to generate a voltage between the input terminal 710 of the VCO and ground. P The effective resistance R in series P , so that the PLL has a first bandwidth ω n When switches 706 and 708 are open, the capacitance changes from C P Reduced to C P / α 2 , the bandwidth of the PLL becomes α·ω n It should be understood that the programmable capacitor C P and resistor R P It can be implemented in any suitable manner known in the art and should not be limited to Figure 7B The example shown in .

[0079] Figure 7C FIG. 1 is a schematic diagram illustrating a third embodiment of a PLL 700C having an adjustable bandwidth. In the PLL 700C, the frequency divider (e.g., Figure 7C The bandwidth is increased by a division factor or ratio N of the MMD in the feedback path. Figure 7C In the case of MMD, when the division factor changes from N to N / α 2 When the bandwidth ω n becomes α·ωn To stabilize the damping factor δ, the impedance Rp can be adjusted to R P / α, which can be obtained by Fig. 7A In addition, in the process of adjusting the bandwidth, Figure 7C The coupling CK REF The divider factor of the MMD is also changed to allow the PLL to lock to the new LO frequency, for example, the divider factor of the MMD is changed from N to N / α 2 When, accordingly, the coupling CK REF The frequency division factor of the divider is changed from α 2 becomes 1.

[0080] Fig.7D is a schematic diagram illustrating a fourth embodiment of a PLL 700D having an adjustable bandwidth. Fig. 7A Instead of increasing the charge pump current, the PLL 700D provides a reference unit 712 which converts the reference pulse CK REF and CK MMD As input and generates CK REF and CK MMD Modified versions of the DAC with higher pulse rates are provided to the PFD to increase bandwidth and provide faster locking.

[0081] Fig. 7E According to some embodiments Fig.7D A schematic timing diagram of the modified reference clock (clock) generated in the PLL. Fig. 7E It is shown that for each pulse in the normal bandwidth mode 720, an additional three pulses are generated in the wide bandwidth mode 718. It can be appreciated that Fig. 7E In the example, CK REF and CK MMD The pulse rate of the modified version is increased by 3 times, that is, its frequency is the original reference pulse CK REF and CK MMD It should be understood that each reference clock CK REF and CK MMD More or fewer times the additional pulses may be used.

[0082] Return to reference Fig.7D ,exist Fig.7D In FIG. 1 , the reference unit 712 includes a plurality of delay lines 714 that can generate a plurality of delayed copies of a single pulse in the input clock signal (eg, Fig. 7E3 delayed copies are shown). The delay line 714 is coupled to a multiplexer (MUX) 716 which multiplexes the output of the delay line into modified pulses REFi and MMDi for provision to the PFD.

[0083] Still reference Fig.7D , in order to stabilize the damping factor δ, the impedance R p Adjusted to R P / α, which can be obtained by Fig. 7A The switch 704 described above is implemented.

[0084] Some aspects relate to configuring LO frequency offsets for different RUs when multiple RUs are allocated within a frequency band.

[0085] Fig. 8A FIG. 1 is a schematic diagram illustrating a first embodiment of LO frequency offset configuration for different RU allocations. Fig. 8A The RU position in a 40MHz high efficiency (HE) PHY Protocol Data Unit (PPDU) is shown. Fig. 8A In the embodiment, the channels in the edge RUs located in regions 802 (Edge-L) and 804 (Edge-R) can be configured to have a shifted local oscillator (LO) frequency during TX operation to reduce unwanted emissions. The amplitude (or absolute value) of the LO frequency offset δf can have half the data bandwidth (DBW), and its positive or negative polarity depends on the relative position of the local oscillator (LO) frequency and the channel frequency. For example, the polarity of the frequency offset corresponding to the RU in region 804 is positive, and the polarity of the frequency offset corresponding to the RU in region 802 is negative. In one embodiment, the amplitude or absolute value does not exceed half of the bandwidth (i.e., the frequency band, 40 MHz as described above). In an embodiment of the present invention, there are multiple data units (RUs) allocated in the frequency band, and for one or more of the multiple RUs, the one or more RUs include a first RU and a second RU, and the first RU (such as Fig. 8A RUs in regions 802 and 804) are larger than the second RU (e.g. Fig. 8A The middle region of the LO frequency offset (excluding regions 802 and 804) is closer to the edge of the frequency band, and the first LO frequency offset determined for the first RU is higher in magnitude than the second LO frequency offset determined for the second RU. Fig. 8AIn one example, the magnitude of the frequency offset determined for the first RU in regions 802, 804 may be 20 MHz, the polarity of the former being negative and the polarity of the latter being positive, and the frequency offset determined for the second RU in the middle region being 0.

[0086] Figure 8B FIG8B is a schematic diagram illustrating a second embodiment of the LO frequency offset configuration for different RU locations. Fig. 8A 806 (Edge-LL), 808 (Edge-L), 810 (Edge-RR), and 812 (Edge-R). The LO frequency offset δf for each RU group can be plus or minus one-half of DBW.

[0087] Fig. 9 is a schematic diagram illustrating RU allocation in a 40 MHz HE PPDU. Fig. 9 The reference number of each RU is annotated with numbers 0-64. According to some embodiments, Table 2 is Fig. 9 Table 3 lists the grouping of RUs into groups Edge_LL[0], Edge_LL[1], Edge_L[0], Edge_L[1], Edge_R[0], Edge_R[1], Edge_RR[0], and Edge_RR[1], where each group can be assigned a different LO frequency offset, according to some embodiments.

[0088] Table 2

[0089]

[0090]

[0091] Table 3

[0092]

[0093] Table 4

[0094]

[0095] Fig.10 is a schematic diagram illustrating channel allocation for wide 80 MHz and 160 MHz bandwidths. Table 4 is a list of TX LO frequency changes or offsets that may be required for Fig.10 The channel configuration shown has a 160Hz bandwidth allocation.

[0096] Although the present invention has been described by way of example and in terms of preferred embodiments, it should be understood that the present invention is not limited to the disclosed embodiments. Instead, it is intended to cover various modifications and similar structures (as will be apparent to those skilled in the art), for example, combinations or replacements of different features in different embodiments. Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar structures.

Claims

1. A method for increasing transmission power, characterized in that: The method operates a device to perform wireless communication in a plurality of resource units RU allocated in a frequency band, and the method comprises: receiving a received RX signal of at least one RU of the plurality of RUs and demodulating the RX signal using a local oscillator LO signal; When transitioning from receive operation to transmit operation, changing the frequency of the LO signal by an LO frequency offset; and, After changing the frequency of the LO signal, modulating a transmit TX data packet for transmission using the changed LO signal; The plurality of RUs include a first RU and a second RU, the first RU is closer to an edge of the frequency band than the second RU, and a first LO frequency offset determined for the first RU is higher in magnitude than a second LO frequency offset determined for the second RU.

2. The method according to claim 1, characterized in that The method further includes: The LO signal is provided by a phase-locked loop (PLL); wherein changing the frequency of the LO signal includes: locking the PLL from a first LO frequency to a second LO frequency.

3. The method according to claim 2, characterized in that Locking from the first LO frequency to the second LO frequency is accomplished in a duration of no more than 5 μs.

4. The method according to claim 2, characterized in that The PLL includes: a phase frequency detector PFD, a voltage controlled oscillator VCO, and at least one charge pump coupled between the PFD and the VCO, wherein changing the frequency of the LO signal includes: The bandwidth of the PLL is increased before changing the frequency of the LO signal.

5. The method according to claim 4, characterized in that The input terminal of the VCO is coupled to a reference voltage node via a resistor, wherein changing the frequency of the LO signal further comprises: The value of the resistor is adjusted to maintain the damping ratio of the PLL constant.

6. The method according to claim 4, characterized in that Increasing the bandwidth of the PLL includes increasing the magnitude of a charge pump current in the at least one charge pump.

7. The method according to claim 4, characterized in that The input terminal of the VCO is coupled to a reference voltage node via a capacitor, wherein increasing the bandwidth of the PLL includes: adjusting the amplitude of the capacitor.

8. The method according to claim 4, characterized in that The PLL also includes a frequency divider coupled to the PFD, wherein increasing the bandwidth of the PLL includes adjusting a division factor of the frequency divider.

9. The method according to claim 4, characterized in that The PLL is configured to provide one or more reference pulses to the PFD, wherein increasing the bandwidth of the PLL includes increasing a rate of pulses in the one or more reference pulses.

10. The method according to claim 1, characterized in that The method further includes: For each of the plurality of RUs, the LO frequency offset is determined based on the RU and the frequency band.

11. A wireless communication device for wirelessly transmitting a TX signal during a transmission TX period and wirelessly receiving an RX signal during a reception RX period through a plurality of RUs allocated within a frequency band, wherein: The device includes: a phase-locked loop (PLL) configured to generate a local oscillator (LO) signal; and a controller coupled to the PLL and configured to change the frequency of the LO signal by an LO frequency offset during a transition between the RX cycle and the TX cycle to generate a changed LO signal; wherein, The RX signal is demodulated using the LO signal, and the TX signal is modulated using the changed LO signal; The plurality of RUs include a first RU and a second RU, the first RU is closer to an edge of the frequency band than the second RU, and a first LO frequency offset determined for the first RU is higher in magnitude than a second LO frequency offset determined for the second RU.

12. The device according to claim 11, characterized in that The PLL includes: Phase frequency detector PFD; A voltage controlled oscillator VCO; and at least one charge pump coupled between the PFD and the VCO; The controller is further configured to: increase the bandwidth of the PLL before changing the frequency of the LO signal.

13. The device according to claim 12, characterized in that The input terminal of the VCO is coupled to a reference voltage node via a programmable resistor, and the controller is configured to adjust the value of the programmable resistor to maintain a damping ratio of the PLL unchanged.

14. The device according to claim 13, characterized in that The programmable resistor includes a resistor and a switch coupled to the resistor.

15. The device according to claim 12, characterized in that The controller is also configured to increase the magnitude of a charge pump current in the at least one charge pump.

16. The device according to claim 12, characterized in that An input terminal of the VCO is coupled to a reference voltage node via a programmable capacitor, and the controller is further configured to increase a bandwidth of the PLL by adjusting a magnitude of the programmable capacitor.

17. The device according to claim 16, characterized in that The programmable capacitor includes a capacitor and a switch coupled to the capacitor.

18. The device according to claim 12, characterized in that The PLL further includes a frequency divider coupled to the PFD, and the controller is further configured to increase a bandwidth of the PLL by adjusting a frequency division factor of the frequency divider.

19. The device according to claim 12, characterized in that The PLL further includes: a reference unit coupled to the PFD, the reference unit configured to receive one or more reference pulses and generate one or more modified pulses based on the one or more reference pulses for the PFD, wherein the modified pulses have a higher pulse rate than the one or more reference pulses received by the reference unit.

20. The device according to claim 19, characterized in that The reference unit includes a plurality of delay lines configured to receive reference pulses of the one or more reference pulses and generate a plurality of delayed reference pulses for each reference pulse.

21. The device according to claim 20, characterized in that The reference unit also includes a multiplexer coupled between the plurality of delay lines and the PFD, the multiplexer configured to combine the plurality of delayed reference pulses to generate the modified pulse.

22. The device according to claim 11, characterized in that The PLL is configured to change the frequency of the LO signal within a duration not exceeding 5 μs.

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