Virtual ports for connecting core-independent peripherals

Abstract

The microcontroller (102) has a central processing unit (120) and a plurality of peripheral devices (130) and a plurality of port bit circuits (106) provided through at least one input / output port (108). At least one port bit circuit (106) of the plurality of port bit circuits is not connected to an external pin (112, 114), and the at least one port bit circuit is configurable to route (119) a signal received at the port bit circuit to a selected peripheral device (130) of the microcontroller.

Description

[0001] Related patent applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 857,036, filed on June 4, 2019, the contents of which are hereby incorporated by reference in their entirety. Technical Field

[0003] The present disclosure relates to microcontrollers including I / O ports and core independent peripherals (CIPs), and more particularly to their interconnection. Background Art

[0004] A microcontroller typically includes a central processing unit (CPU), program and data storage memory, input-output (I / O) ports, and multiple peripherals manufactured on an integrated circuit (IC) die ("chip"). Some of these peripherals may be core independent peripherals (CIPs), which are defined as peripherals that can be operated without CPU input. The IC die may be encapsulated (packaged) in an IC package having wiring terminals ("pins"), through which external circuits may be connected to the IC die. The electrical connection points on the IC die may be "pads" and may be connected to the IC package pins with bonding wires. Most external wiring pins are associated with the I / O ports of the microcontroller, wherein each I / O port pin is fixedly associated with one bit of the I / O port. Corresponding IC die pads are used for these I / O ports and are wire-bonded to corresponding external pins. Other external pins provide the IC die DC power supply and grounding. The I / O port pins are typically so-called multi-function pins and may be shared with peripherals under program control. To this end, there may be certain predefined associations for each pin, or a so-called peripheral port select (PPS) logic may allow selection of a variety of assignable peripheral functions.

[0005] Core independent peripherals (CIPs) are designed to handle their tasks without code execution or supervision by the central processing unit (CPU) to maintain their operation. Therefore, they simplify the implementation of complex control systems and provide designers with flexibility for innovation. CIPs are internally integrated and receive inputs from internal and external sources, and can provide outputs to internal and external targets (such as other integrated peripherals or external components). However, not all input and / or output connections of all core independent peripherals (CIPs) are available to all other CIPs, but they may have one or more connections that are only available to the corresponding external pins. To connect between different CIPs that are not within the normal internal selection options, external port pins must be used to make the connection. On low pin count devices, this can be problematic because it can result in a lock / reduction in available port pins. Therefore, larger devices must be used and equipped with a corresponding number of additional port pins. The main disadvantage is the cost and size of larger devices. Another option is to significantly increase the connection selection registers and associated multiplexer circuits for all CIPs to allow selection of any other CIP connected to it, which is not a feasible option in most cases.

[0006] As mentioned above, I / O ports are used for external digital I / O of microcontrollers. They are fixedly assigned to external pins. Depending on the number of available external pins, a corresponding number of I / O ports can be implemented. These I / O ports are usually not considered peripherals, but provide external digital interfaces directly controlled by the CPU. This specification distinguishes the term "I / O port" as not equivalent to any peripheral or module in the microcontroller. Their main port I / O function can be overwritten during the configuration process so that the associated external pins are then controlled by the selected peripheral. Peripheral devices can be, for example, but not limited to PWM modules, timers, digital-to-analog converters (DACs) or analog-to-digital converters (ADCs), rather than I / O ports. For example, once reallocated, pins can now be used as analog input pins of ADCs or output pins of serial interfaces. Ports are usually 8-pin or 16-pin ports, referred to as port A, port B, port C, etc., however, especially on low-pin devices, each port or only a single port may have fewer independent bits, while on other devices, more independent bits may also be available. For example, a 6-pin microcontroller may have only a single port with 4 bits (e.g., PORTA0, PORTA1, PORTA2, and PORTA3), and a 14-pin microcontroller may have only two ports, such as Port A and Port C with single bits PORTA0-PORTA5 and PORTC0-PORTC5. Other configurations are possible. Summary of the invention

[0007] Therefore, what is needed, especially for microcontrollers with a small number of external pins, is the possibility to route signals internally without significantly increasing the number of multiplexer circuits.

[0008] According to one embodiment, a microcontroller includes a central processing unit and a plurality of peripheral device units and a plurality of port bit circuits provided through at least one input / output port, wherein at least one port bit circuit of the plurality of port bit circuits is not connected to an external pin, and wherein at least one port bit circuit is capable of being configured to route a signal received at the port bit circuit to a selected peripheral device of the microcontroller.

[0009] According to another embodiment, any port bit that is not connected to an external pin may be initially disabled and may be re-enabled by configuration. According to another embodiment, the microcontroller may include a configurable fuse for re-enabling the port bit. According to another embodiment, at least one port bit may be connected to a die pad. According to another embodiment, an input signal may be provided by a bit of a bit register latch. According to another embodiment, at least one port bit circuit may include a first multiplexer configured to select a signal. According to another embodiment, the microcontroller may also include a selection circuit including a multiplexer controlled by a first register and configured to select a signal. According to another embodiment, at least one port bit circuit may include a second multiplexer configured to select a destination for the signal. According to another embodiment, the second multiplexer may be controlled by a second register and may be configured to assign at least one port bit circuit to a selected peripheral device of the microcontroller. According to another embodiment, the microcontroller may also include at least one additional I / O port circuit having a plurality of bits, wherein at least some of the plurality of bits are assigned to external pins of the microcontroller.

[0010] According to another embodiment, a method for operating a microcontroller is provided, the microcontroller including a central processing unit and a plurality of peripheral device units and a plurality of port bit circuits provided through at least one input / output port, wherein at least one port bit circuit of the plurality of port bit circuits is not connected to an external pin, the method may include: selecting a signal source for at least one port bit circuit; selecting a destination for at least one port bit circuit, whereby the at least one port bit circuit routes a signal from the selected signal source received at the at least one port bit circuit to a selected peripheral device of the microcontroller.

[0011] According to another embodiment of the above method, any port bit that is not connected to an external pin may be initially disabled, the method further comprising: configuring the microcontroller to enable at least one input / output port via at least one configuration register. According to another embodiment of the above method, the selected input signal source may be a port latch of at least one port bit circuit, the method further comprising: writing a value into the port latch by a central processing unit to provide an input signal for the selected output source. According to another embodiment of the above method, selecting an input source and / or selecting a destination may be performed by programming a register, wherein the register controls a first multiplexer for selecting a signal source and a second multiplexer for selecting a destination. According to another embodiment of the above method, the microcontroller may include a programming / debugging interface coupled to at least one port bit circuit, the method further comprising: coupling an in-circuit emulator / debugger device to the programming / debugging interface of the microcontroller; detecting a logic state of a signal within at least one port bit circuit; and forwarding the logic state to the in-circuit emulator / debugger device.

[0012] According to yet another embodiment, a microcontroller may include a central processing unit, a plurality of peripheral devices, and a plurality of input / output ports, wherein at least one of the input / output ports includes a plurality of bits connected to external pins of the microcontroller, and wherein at least one port bit circuit of the plurality of input / output ports is not connected to the external pins, and wherein at least one port bit circuit is capable of being configured to route a signal received at the port bit circuit to a selected peripheral device of the microcontroller, wherein any port bit not connected to the external pin is initially disabled and can be re-enabled by configuration, wherein at least one port bit circuit includes a first multiplexer configured to select a signal, and wherein the first multiplexer is coupled to bits of a port latch register and to outputs of the plurality of peripheral devices of the microcontroller.

[0013] According to another embodiment, the microcontroller may include a configurable fuse for re-enabling the port bit. According to another embodiment, at least one port bit may be connected to a die pad. According to another embodiment, the first multiplexer may be controlled by a configuration register and configured to provide an input signal. According to another embodiment, at least one port bit circuit may include a second multiplexer configured to select a destination for the input signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] A more complete understanding of the present disclosure may be obtained by referring to the following description taken in conjunction with the accompanying drawings, in which:

[0015] Figure 1 shows a schematic plan view of an integrated circuit die in an integrated circuit package according to the teachings of the present disclosure;

[0016] Figure 1a The logic circuitry for enabling / disabling unused I / O ports is shown in more detail.

[0017] Figure 2 A schematic block diagram of a CIP port coupled to hardware input-output pads is shown.

[0018] Figure 3 A schematic block diagram of a virtual CIP port according to certain exemplary embodiments of the present disclosure is shown.

[0019] Figure 4 A circuit is shown including a conventional low pin microcontroller.

[0020] Figure 5 Shown in a similar Figure 4 The circuit shown uses a first embodiment of a microcontroller.

[0021] Figure 6 Shown in a similar Figure 4 A second embodiment of a microcontroller used in the circuit shown;

[0022] Figure 7 An embodiment of a microcontroller according to the present specification is shown, the microcontroller being coupled to an in-circuit emulator and a host computer; and

[0023] Figure 8 A flow chart for powering up a microcontroller according to various embodiments is shown. DETAILED DESCRIPTION

[0024] Small pin count microcontrollers or low pin count microcontrollers (e.g., 6-pin microcontrollers or 8-pin microcontrollers) are typically built using the same IC die as used in higher pin count devices (e.g., 14-pin), which means that there is unused port logic, but it is initially disabled. Disabling such unused ports can be achieved by internal wire bonding or by fuses or any other suitable means. According to various embodiments, such disabling may be covered during manufacturing or may not be established so that these ports are still valid when not connected to the outside. Other embodiments of the present disclosure allow active coverage of disabling, thereby enabling these unused ports to provide internal interconnection between internal peripheral devices, which would otherwise be impossible. The enabling of such unused ports ("virtual ports") can be achieved using fuse bits in configuration registers, which will cover typical wire bonding disabling mechanisms such as in the die, and allow virtual connection ports to be created within the device for establishing internal connections and virtual test points. The term "virtual port" as used herein for the present disclosure is defined as a port that is inaccessible outside the IC package. A "virtual port" may typically include 8 port bits and may implement corresponding input / output circuitry, as will be described in more detail below. However, a "virtual port" may be designed to have only a single port bit or more than 8 bits. In the following, a port bit circuit is a single bit of an I / O port or a "virtual port" that specifies an input / output circuit.

[0025] Embodiments of the present disclosure may include a set of, for example, but not limited to, 8-24 connection points (port bits) that may be used to connect peripheral devices or CIPs, particularly in low pin count devices. In addition, these ports may be accessed by a circuit emulator or in-circuit debugger (ICD), which would allow debugging in, for example, a device manufactured by the assignee of the present application. The data is displayed in the logic analyzer functionality built into the X Integrated Development Environment (IDE). This also allows the creation of overlays and driving inputs for peripheral / CIP configurations under software control.

[0026] Advantages of using "virtual ports" can be reducing the size of data used to be transmitted through conventional input selection multiplexers, increasing the number of possible peripheral or CIP interconnections, being able to allow software input of signals to peripherals or CIPs where a logic analyzer can be used to display those signals, and the die size can remain essentially the same.

[0027] At present, as mentioned above, when the tube core is installed in the integrated circuit package, the unused ports are disabled using, for example, bonding options, as will be described in more detail below. According to the specific exemplary embodiments of the present disclosure, one or more fuses in the configuration word can be used to override the disablement, re-enable all available ports or re-enable each disabled port bit circuit. During the programming of the device, these fuses can be reset and programmed using, for example, configuration registers. In these embodiments, since the hardware is present on the tube core, little or no additional cost is required. It can use additional configuration bits and associated logic to re-enable the required port pins. It can also use modifications to the assembler and compiler tools to re-enable ports, pins and register alias tables.

[0028] As used herein, a port bit may be connected to an internal connection pad on an integrated circuit die that includes a plurality of peripheral devices or CIPs and a CPU. A port bit may be connected to an external integrated circuit pin for further connection to a circuit external to the integrated circuit package. According to this specification, a port or port bit is also considered a "virtual port" or "virtual port bit" if it is not connected to an external pin.

[0029] Referring now to the drawings, the details of the exemplary embodiments are schematically shown. Like elements in the drawings will be represented by like numerals, and similar elements will be represented by like numerals with different lower case letter suffixes.

[0030] See also Figure 1 , shows a schematic plan view of an integrated circuit die in an integrated circuit package according to the teachings of the present disclosure. An integrated circuit (IC) die 104 includes a central processing unit (CPU) 120 and a plurality of peripheral devices 130 as well as a memory 125 and a plurality of I / O ports forming a microcontroller. The IC die 104 has a plurality of connection pads 106, 112, 114 thereon, which can be configured as ports, dedicated functions or power supplies. These ports can be programmed to be coupled to selected IC die circuits, such as peripheral devices 130, which can be CIPs. Some of the pads 106 are used to connect to the power supply (VDD) and ground (VSS) required for the IC die circuits. Some of the pads 106 can be connected to external pins 108 on the IC package 102 using bonding wires 110. Typically, there are more pads 106 than external pins 108 in a low-pin microcontroller. However, some embodiments may have the same number of pads as external pins. In such devices, a "virtual port" may be implemented but without an associated pad on the IC die, as will be explained in more detail below.

[0031] Figure 1A plurality of pads 106 are shown that are not connected to external pins. These pads 106 that are not connected to the outside can be internally coupled to corresponding I / O ports for use in a higher pin housing, as described above. In an embodiment where a wire bonding method is used to disable unused ports, Figure 1 Additional first pads 112 and second pads 114 are shown. The die 104 may include stored data defining which pads are not used in various housing options. The first pad 112 may be connected to the decoding logic 118 using a pull-up resistor, and the second pad 114 may be connected to ground. The wire bond 116 connects the first pad 112 and the second pad 114 so that the first pad 112 can be pulled to ground and the decoding logic 118 will responsively disable those I / O ports associated with the unconnected pads 106 according to the stored data. There may be multiple pads 112 and associated disable data defining the I / O ports to be disabled to allow various predefined ports to be disabled according to different variants of the corresponding microcontroller. By Figure 1 The wire bond disabling shown is only one approach, and other disabling means may be used, such as fuse 119 indicated by a dashed line. For example, a fuse may be coupled between pads 112 and 114 to play the same role as wire 116. Fuse 119 may be set or reset according to predefined limits. Alternatively, decoding logic 118 may be implemented for each pad 106 that may not be connected associated with an I / O port, such as Figure 1 106 and logic 118 in the unused pads 106 and logic 118. However, such a solution would require the application of a bonding wire between each unused pad and the ground pad. Alternatively, each pad that may be unused may have an associated fuse for disabling the associated I / O port, as shown by the dotted line between the unused pads 106 and the fuse 119. One or more fuses 119 may be resettable and are typically set during the configuration of the device. According to various embodiments, the only requirement for disabling a port is that such disabling can be overwritten and is therefore not permanent.

[0032] Figure 1aA more detailed block diagram of the enabling circuit is shown. Only three pads 106 that are not connected to the outside are shown. Each pad 106 is coupled to an associated I / O port circuit 160, as will be described in more detail below. The logic circuit 150 is configured to enable or disable each I / O port circuit 160 according to the logic signal received from the decoding logic 118. Disabling can be achieved by simply not powering the corresponding I / O port circuit. However, a variety of disabling forms can be provided, such as blocking any control and data signals. However, turning off the power supply of the circuit 160 avoids unnecessary power consumption. The logic circuit 150 may include a configuration register to allow the disabled I / O port 160 to be re-enabled. For example, according to one embodiment, the logic circuit 150 may include a special function register 155, which stores which I / O port circuits in the I / O port circuit are initially disabled. The CPU 120 may be programmed to cover this initial setting stored in the register 155. Alternatively, a dedicated instruction may be used to re-enable a previously disabled I / O port circuit 160.

[0033] See also Figure 2 , depicts a schematic block diagram of an I / O port coupled to hardware input-output pads 106 and external pins 108. I / O pads 106 can be configured as digital input or output, analog input or output, and can be tri-state, open collector, or analog driver. The output section is shown in Figure 2 The lower part is shown in the figure, while the input part of the port bit circuit is shown in the upper part. Figure 2Only one bit is shown in the , however, as previously described, a port may include more than one bit, and typically has 8 or 16 bits, and may have any number of bits in low pin devices. Therefore, since a port may be designed to have only a single bit, the terms "port" and "port bit" are used interchangeably in this specification. The configuration of the basic digital I / O functions of the I / O pads 106 and pins 108 may be selected by signals from the configuration register 260. The configuration register 260 may include separate or combined registers for controlling tri-states (indicated as registers TRIS in the register set 260), pull-up and / or pull-down functions, analog input selection, output and input values ​​(indicated as registers LAT and registers PORT in the register set 260, respectively), and other configuration parameters. The tri-state signal control signal TRISx may be generated by the associated bits of the register TRIS and fed to the logic circuit 224, which includes a driver for the output stage 240 and generates control signals for transistors 232 and transistors 234. Logic circuit 224 may include controllable drivers for transistor 232 and transistor 234, and signal TRIS may be used to disable these drivers, thereby controlling the tri-state function of driver stage 240. If programmed as an output port, bit register latch 208 provides the basic digital output function of the CPU for the bit presented to the D input of bit register latch 208 on the data bus. Multiplexer 210 is then set to input 0 by signal Sel. Multiplexer 210 typically includes only a few (e.g., Figure 2 The three shown in Figure 1 allow pin 108 to be operated as a predefined input of a multi-function pin. For example, pin 108 can be operated as a digital I / O pin, a serial data output pin of a first peripheral device PerA, a timer output pin of a second peripheral device PerB, or an analog input pin that is usually set by default. There may be more or fewer combinations, but conventional designs are usually limited in the number of possible predefined selections. Each multi-function pin 108 usually has a different predefined selection set. This selection is usually automatically performed when the corresponding peripheral device is configured by software. For example, if a serial port peripheral device is enabled, the I / O port circuit of the corresponding associated multi-function pin 108 will be controlled by a signal Sel to select the corresponding input associated with the corresponding peripheral device.

[0034] According to some embodiments, a first peripheral pin select unit (PPS) 212 extends the functionality of such a conventional multiplexer and allows, for example, the assignment of various other outputs of various peripheral devices used with the pin 108 via the n input lines 211. However, the configuration of the PPS is not performed automatically, but rather the first PPS 212 includes programmable registers (as will be described in Figure 3), which allows a predefined number of output signals to be selected from various peripherals to be routed to pin 108. A more complete description of PPS is found in Section 10.4 of the "dsPIC33E / PIC24E Family Ref. Manual, Sect. 10 / I / O Ports", 2009-2013, available from Microchip Technology Inc., the entire contents of which are incorporated herein by reference.

[0035] As described above, the first PPS 212 provides more output selections from a variety of peripheral devices via line 211 than conventional multiplexers, which are typically limited to only a few selections. The peripheral pin selection unit may also provide additional input selections, as will be described in more detail below with respect to the multiplexer 202 that forms the second PPS. A PPS such as the first PPS 212 may be simply explained as an extended multiplexer controlled by a configuration register (not shown). Its primary purpose is the same as that of the multiplexer 210, i.e., routing various internal output signals to the driver stage 240. Figure 2 Only one embodiment of an I / O port circuit is shown. Other more or less complex I / O port circuits may be used to control the I / O functions of external pins 108.

[0036] According to one embodiment, multiplexer 210 routes the output signal of bit register latch 208 via logic 224 to an output driver stage 240, which may include a pair of driver MOSFETs 232 and MOSFET 234 arranged to drive pad 106 and external pin 108 to a logic high or logic low. Logic 224 may be included in the driver stage, or may optionally be implemented to further enable, for example, open drain functionality and / or provide weak or strong pull-up and / or pull-down resistors for that port corresponding to settings in configuration register 260 via control signal 238. Output driver stage 240 may optionally provide one or more analog pass gates 236 to provide additional analog output functionality for pad 106 / pin 108. As shown in FIG. Figure 2As shown, according to one embodiment, the multiplexer 210 may have two additional inputs coupled to the peripheral device PerA and the peripheral device PerB, respectively, thereby allowing a basic multi-function pin. According to the control signal SEL provided by the peripheral device, the multiplexer 210 selects one of the bit register latch 208 or other inputs to allow output control of the peripheral device. The first PPS 212 may optionally be implemented, which allows various peripheral output functions to be further selected by multiplexing the output of the multiplexer 210 with the additional signal 211. The first PPS 212 is controlled by the signal 228, which is controlled by the associated configuration register ( Figure 2 The logic (not shown) for decoding the settings in (not shown) is generated.

[0037] The input functions / portions are controlled by drivers 204, 216, 218 and multiplexer 202 and / or multiplexer 270 and multiplexer 214. Signal ANSELx disables driver 216 and driver 218 to operate pad 106 / pin 108 as an analog input port. Multiplexer 214 selects between Schmitt trigger driver 216 and TTL driver 218 in response to control signal INLVLx, which can provide TTL or Schmitt trigger input in response to the selected one of driver 216, driver 218. According to various embodiments, only one of these drivers is implemented. Multiplexer 202 forms part of the second PPS and responds to the input assignment registers ( Figure 2106 / pin 108 is provided as an input pin for a wider selection of specific peripheral devices similar to the first PPS. Multiplexer 202 provides inputs for multiple other pads and associated IO / port circuits, and provides a single output signal for one peripheral device PerE. Depending on the number of peripheral devices that may require input signals, multiple such multiplexers 202 may be implemented in the second PPS. Alternatively or in addition, as shown by the dotted line, a conventional multiplexer 270 may be implemented that allows input signals to be routed from pad 106 / pin 108 to a selected peripheral device similar to multiplexer 210. A more complex description of the input PPS is provided in the file "dsPIC33E / PIC24E Family Reference Manual, Chapter 10 / I / O Ports". The multiplexer 270 can be controlled by a signal 275 to select one of its multiple outputs to couple to its input, which is connected to the output of the multiplexer 214 or directly to the pad 106 / pin 108. Similar to the multiplexer 210, when configuring the selected peripheral device PerC or peripheral device PerD assigned to the multi-function pin 108, the multiplexer 260 is controlled by the signal 275 provided by the peripheral device PerC and the peripheral device PerD.

[0038] The basic digital input function of the CPU is provided by driver 204, which drives its output onto the data bus in response to the received read PORTx control signal. In addition, the user can also read the output of the bit register latch 208 through driver 206, which is similarly arranged to drive its output onto the data bus in response to the received read LATx control signal. Figure 2 Various port functions and configurations are shown. Although the bit register latch 208 and driver 204 and the basic driver stage 240 provide basic digital I / O functions, other functions can be added or omitted individually depending on the implementation and desired multi-functions of the corresponding port. The output stage 240 can also provide ESD protection, such as Figure 2 The port can also optionally provide an interrupt function through a detection circuit 250, which can generate an interrupt INT to the CPU.

[0039] See also Figure 3 , depicts a schematic block diagram of a "virtual port" circuit for a single bit according to a specific exemplary embodiment of the present disclosure, such as Figure 1a However, except that there are no external pins connected via pads 106, the general port design can also be used as shown in FIG. Figure 2 The port designs shown are identical. Figure 3Certain portions of the port bit circuitry that may be used when the port is enabled as a "virtual port" are shown. In some embodiments, as shown by the dashed lines, no pads 106 may be physically connected to output / input lines 318 (shown as 318a and 318b). Figure 3 The "virtual port" circuit shown may therefore not be physically coupled to the I / O pad 106, but still have the functionality of connecting to the "virtual port". The "virtual port" circuit, although not connected to external pins, is used as a routing device to switch internal signals to peripheral devices that would otherwise be unavailable internally. Therefore, in the "virtual port circuit", output signals can now be considered input signals, and input signals can be considered output signals. According to some embodiments, the signal conditioning logic 314 controlled by signal 316 can also be omitted. If present, the signal conditioning logic 314 can be permanently configured to provide standard output functions, such as ramp control, pull-up, pull-down, and open-drain functions. However, according to a method similar to Figure 2 In some embodiments of the logic circuit 224 in FIG. 1 , the configuration of the signal conditioning logic 314 for providing pull-up, pull-down, and open-drain functions may be used for a "virtual port". In other embodiments, the analog signals, tri-state, and pull-up control provided by the signal conditioning logic 314 may not be required, nor may the analog signals, tri-state, and pull-up control provided by the signal conditioning logic 314 be required. Figure 2 The port drivers and TTL / Schmitt triggers used in the microcontroller are shown in FIG. 1 . If they are present, their functionality may be disabled accordingly, or the most appropriate one may be selected. If the microcontroller design is dedicated to a specific number of external pins, there may be no unused ports, and a minimal configuration of a "virtual port" may be implemented with or without pads 106, thereby omitting those circuits that are only needed when connecting actual external pins to the ports.

[0040] According to one embodiment, multiplexers 310, 330 may be used to connect various peripheral devices together. The first multiplexer 330 corresponds to Figure 2 270 in the first embodiment, and the second multiplexer 310 corresponds to the multiplexer 210. Also, as explained above, when the corresponding peripheral device is configured, these multiplexers 330, 310 are automatically controlled by the logic circuit 311 to select the input or output signal. Figure 3 Logic circuitry 311 is shown receiving configuration control data from the corresponding peripheral device assigned to a particular "virtual port" circuit.

[0041] Alternatively or additionally, such as Figure 2The PPS shown in the first PPS 212 and the second PPS 202 in FIG. 1 can provide an expanded selection of peripheral devices that provide signals and peripheral devices that receive selected signals. Specifically, the PPS may be a preferred method for internally routing signals between different peripheral devices through "virtual ports" because its configuration is controlled by registers rather than automatically controlled by the configuration of the peripheral devices.

[0042] to this end, Figure 3 A first PPS 302 is shown that includes a plurality of multiplexers 302a...302n, each multiplexer including an output coupled to a different peripheral device. The multiplexers 302a...302n are controlled by a logic circuit 303 that is configured to decode the settings of an output allocation register 360. Each multiplexer 302a...302n may be associated with one output allocation register 360, or the output allocation register 360 may be configured to provide setting information for a plurality of multiplexers 302a...302n. Thus, the signals received on the lines 318a, 318b will be routed to the inputs of the selected peripheral devices through the multiplexers 302a...302n.

[0043] If desired, a bit register latch 308 and drivers 304, 306 for software input of control signals to selected peripheral devices may be implemented. According to some embodiments, bit register latch 308 and drivers 304, 306 may not be implemented. In addition, according to the teachings of the present disclosure, the port interrupt provided by circuit 320 may be a desired feature. According to various embodiments, any desired functionality may be implemented. Therefore, if a port is already available and would be disabled in a conventional device, the re-enabling of such a port may use any functionality it supports to route signals to the peripheral device.

[0044] Figure 3 A power supply circuit 301 is shown that provides power to the various components of the "virtual port" circuit. This allows each bit of the "virtual port" to be individually disabled by controlling the corresponding power supply. The power supply circuit 301 is connected from the logic circuit 150 (in Figure 1a 150) receives one or more signals. Disabling and re-enabling various "virtual port" circuits is optional. According to one embodiment, all I / O port circuits that are not connected to external pins are initially disabled (e.g., by not supplying them with power) and can be re-enabled by logic circuit 150, as described above. According to some embodiments, all I / O ports are initially enabled and can be disabled by software, for example, if not required in a particular application. According to other embodiments, all I / O port circuits are always enabled.

[0045] At a minimum, the "virtual port" circuit will use a multiplexer 330 or PPS 302 to select the "virtual port" signal provided on lines 318a, 318b. In order to select the "virtual port" signal, a bit register latch 308 and / or another multiplexer circuit is provided at a minimum. The multiplexer circuit includes a multiplexer 310 and / or a PPS 312. Similarly, the multiplexer 311 is controlled by control logic 311 that receives configuration data from the assigned peripheral device to automatically select the corresponding peripheral device when it has been configured. PPS 312 includes a multiplexer controlled by a logic circuit 313, which decodes the corresponding output allocation register 370. The output allocation register 370 is associated with a specific "virtual port circuit" and its stored information defines which output signal of which peripheral device will be selected by the multiplexer of PPS 312. Drivers 304 and / or 306 may be used for debugging, specifically for providing logic analyzer functionality via an integrated programming / debugging interface. For example, driver 304 allows reading the logic state of lines 318a, 318b, and driver 306 allows reading the current output logic state of latch 308.

[0046] Figure 3 Also shown are some other exemplary control registers 380 and 390 for directly controlling "virtual ports" via the CPU. Each bit of the logic control register 380 and the latch register 390 can control different bits of the "virtual port". For example, a single bit in the latch register 390 corresponds to a bit register latch 308. In the embodiment where the logic circuit 316 is used and, for example, controls the pull-up function, a single bit of the register 380 directly controls the function through the line 316. The corresponding other bits in the registers 380 and 390 control the corresponding other port circuits. As explained above, the output allocation register 360 and the input allocation register 370 are not bit-organized registers like the registers 380 and 390. They are usually registers in a plurality of configuration registers of the peripheral pin selection circuits 302 and 312, and are therefore organized in different ways. As described above, the input allocation register 370 can be configured to define the selected input signal source by writing the corresponding code word into the register 370. For example, if 4 bits are used, one of 16 different input signal sources can be defined that are routed to the multiplexer of the PPS 312. Therefore, these four bits are routed to the corresponding logic 313 that controls the PPS 312. An 8-bit register can assign one of 256 different input sources to the corresponding port bit. Therefore, the input assignment register 370 can be designed according to the number of available input signals.

[0047] Output allocation registers 360 may be designed to be associated with a single peripheral input, so that the value stored in such registers may define the corresponding port bit circuit. Figure 3 As shown, 16 multiplexers 302a...302n may be present in the input PPS 302, each multiplexer having an output for a different peripheral device. Therefore, the register 360 is controlled by, for example, a four-bit logic 303 that controls a corresponding one of the multiplexers 302a...302n to select the signal provided on the lines 318a, 318b as the input signal for the corresponding peripheral device. The multiplexers 302a...302n may have one of their multiple inputs unconnected to allow a default setting in which no signal is routed to the corresponding peripheral device through the multiplexers 302a...302n. Likewise, the number of bits used to encode such an assignment may vary depending on the number of available peripheral inputs.

[0048] Depending on the functionality implemented, such as, for example, signal conditioning logic 314 and / or interrupt circuitry 320, more or fewer additional control registers for the “virtual port” circuitry may be provided.

[0049] Figure 4 As shown previously Figure 1 The conventional microcontroller 410 shown with 8 external power pins 420, 430 and multi-function pins 440a...440f provides a certain output signal only through external pin 440b. Another peripheral device may need this signal at one of its inputs, which can also be configured to be connected through external pin 440d. Therefore, the external circuit must provide a signal connection 450 to connect pins 440b and 440d. The user now loses 2 external pins that can be used for other functions. In the case where another 2 external pins are required for other purposes, the user must use a different microcontroller with more external pins to design its circuit.

[0050] Figure 5 A first embodiment of a microcontroller 500 according to the present specification is shown. The microcontroller includes a plurality of port bits that are routed to die pads 510 that are not connected to external pins. These pads 510 are typically disabled, for example, by not providing power to the output portion 520 and input portion 540 of the corresponding I / O port circuit. During configuration of the device, the associated port bits of the pads 510 are re-enabled by powering these portions 520, 540, and now operate as a "virtual port" circuit. The output portion 520 and input portion 540 of the port bits are therefore coupled to the pads 510 and can now be used as a switch board for providing internal connections. Figure 5Also shown are exemplary multiplexers or PPS circuits 530 and 550 for selecting input signals provided by peripheral device 560 and routing the input signals to corresponding selected peripheral devices 570 as indicated by the inner dashed connecting lines.

[0051] Figure 6 Another example according to various embodiments is shown, in which a dedicated design of a microcontroller 600 with a small number of external pins is enhanced using a "virtual port". The design includes only the necessary number of pads, in other words, there are exactly the same number of pads and external pins. However, for other reasons, some designs may include more pads. However, the design of the die of the microcontroller 600 only has the number of ports corresponding to the number of available external pins, in this example, with 6 port bits and associated I / O port circuits (not shown). According to one embodiment, the design is enhanced by providing at least one additional port bit circuit that is not connected to the die pads and external pins. The port bit circuit includes an input portion 640 and an output portion 620 and associated multiplexers 630 and 650 of the corresponding virtual port. Multiplexers 630 and 650 are also preferably part of the corresponding PPS.

[0052] Figure 5 and Figure 6 Both embodiments can be described above with respect to Figure 2 and Figure 3 As described, in particular, regarding Figure 6 Both implementations can now be internally routed in Figure 4 The signals routed externally in the circuit shown, thus freeing up two additional external pins while only requiring one additional port bit circuit. According to various embodiments, a predefined number of these additional port bits can be implemented that can form a "virtual port". Although particularly advantageous for low pin count microcontrollers, the various embodiments disclosed herein can also be implemented in high pin count devices that do not provide internal routing of all input and / or output signals for various peripherals (particularly core independent peripherals). Thus, the "virtual port" operates as an internal switch plane for the internal signals of the microcontroller. The use of a "virtual port" can also allow for the reduction of conventional internal input selection multiplexers (e.g. Figure 2 The size of the multiplexers 210 and 270 shown in the figure) that would otherwise need to be as described in the background section. Because the "virtual ports" provide additional connection possibilities, these conventional input multiplexers may not need to be designed to allow every possible connection and therefore have a reduced size.

[0053] Figure 7Another embodiment of a microcontroller 700 used in conjunction with an in-circuit emulator or programmer / debugger is shown. The microcontroller may be any microcontroller according to the present specification. Here, a 12-pin device with an exemplary "virtual port" 710 and an integrated programmer / debugger circuit 720 is shown. The programmer / debugger circuit 720 provides debugging capabilities of the chip as known in the art, for example, by using a dedicated interface 770 of multi-function pins 780 and 790. The debugger circuit 720 has access to the "virtual port" circuit 710 and can transmit the real-time logic states of the input / output signals routed through the "virtual port" 710 to the in-circuit emulator / debugger 760. Therefore, the in-circuit emulator / debugger device 760 can receive these logic states and forward them to an integrated development environment (IDE), such as MPLAB X manufactured by the assignee of the present application. The IDE runs on a host 750 and can now provide, for example, a logic analyzer function of signals routed through various "virtual port" circuits.

[0054] Figure 8 FIG. 8 is a flow chart showing a microcontroller power-up process according to various embodiments. In step 810, the microcontroller receives supply voltages Vdd, Vss through external pins. During step 810, the microcontroller may power up various circuits according to its design. The microcontroller may be, for example, Figure 1 The microcontroller 102 shown has a plurality of pads 106 that are not connected to the outside. Figure 1a As shown, the pad is coupled to the corresponding I / O port circuit 160 and the bonding wire 116 between the pads 112 and 114. In step 820, the decoding logic circuit 118 is powered on and decodes the logic state of the pad 112 when pulled to ground, and thus sends a signal to the logic circuit 150, which disables the corresponding I / O circuit 160 coupled to the pad 106 that has no external connection. Disabling the unconnected I / O port is preferably performed by not providing a supply voltage to the I / O port circuit 160.

[0055] Other configurations of the microcontroller 102 may be performed before or after step 820. If the user does not need an unused I / O port for routing internal signals as described above, power-on may be terminated and firmware as programmed in the microcontroller may be executed. However, if the user wants to use a certain I / O port circuit 160 to route internal signals, the firmware may first execute step 830. This step includes instructions for re-enabling a predefined set of disabled I / O ports. To this end, the logic circuit 150 may include a set register 155, which may be programmed by the CPU to re-enable previously disabled I / O ports. Alternatively, a dedicated instruction may be executed, which defines which I / O ports of the disabled I / O ports are re-enabled. Firmware 840 may then also include instructions for configuring the virtual port to route signals internally as needed.

Claims

1. A microcontroller comprising a central processing unit and a plurality of peripheral device units and a plurality of port bit circuits provided through at least one input / output port, each port bit circuit comprising a latch for providing an output to the input / output port, wherein at least one port bit circuit of the plurality of port bit circuits is not connected to an external pin, and wherein the at least one port bit circuit is configurable to route a signal received at the port bit circuit to a selected peripheral device of the microcontroller.

2. A microcontroller comprising a central processing unit, a plurality of peripheral devices and a plurality of input / output ports, wherein at least one of the input / output ports comprises a plurality of bits connected to external pins of the microcontroller, and wherein at least one of the plurality of input / output ports has a port bit circuit that is not connected to the external pin, and wherein the at least one port bit circuit is configurable to route a signal received at the port bit circuit to a selected peripheral device of the microcontroller, wherein any port bit not connected to the external pin is initially disabled and can be re-enabled by configuration, wherein the at least one port bit circuit comprises a first multiplexer configured to select the signal, and wherein the first multiplexer is coupled to bits of a port latch register and to outputs of the plurality of peripheral devices of the microcontroller.

3. A microcontroller according to claim 1, wherein any port bit not connected to an external pin is initially disabled and can be re-enabled by configuration.

4. A microcontroller according to any one of claims 1 to 3, comprising configurable fuses for re-enabling port bits.

5. The microcontroller according to any one of claims 1 to 3, wherein the at least one port bit is connected to a die pad.

6. A microcontroller according to any one of claims 1 to 3, wherein the input signal is provided by a bit of a bit register latch.

7. The microcontroller of claim 6, wherein the at least one port bit circuit comprises a first multiplexer configured to select the signal. 8 . The microcontroller according to claim 1 , further comprising a selection circuit, the selection circuit comprising a multiplexer controlled by the first register and configured to select the signal.

9. The microcontroller according to any one of claims 1 to 3, wherein the at least one port bit circuit comprises a second multiplexer configured to select a destination for the signal.

10. The microcontroller of claim 9, wherein the second multiplexer is controlled by a second register and is configurable to assign the at least one port bit circuit to a selected peripheral device of the microcontroller.

11. The microcontroller according to any one of claims 1 to 3, further comprising at least one further I / O port circuit having a plurality of bits, wherein at least some of the plurality of bits are allocated to external pins of the microcontroller.

12. The microcontroller of claim 7, wherein the first multiplexer is controlled by a configuration register and is configured to provide the input signal.

13. A method for operating a microcontroller, the microcontroller comprising a central processing unit and a plurality of peripheral device units and a plurality of port bit circuits provided through at least one input / output port, each port bit circuit comprising a port latch for providing an output to the input / output port, wherein at least one port bit circuit of the plurality of port bit circuits is not connected to an external pin, the method comprising: selecting a signal source for the at least one port bit circuit; A destination is selected for the at least one port bit circuit, whereby the at least one port bit circuit routes a signal received at the at least one port bit circuit from a selected signal source to a selected peripheral device of the microcontroller.

14. The method of claim 13, wherein any port bits not connected to external pins are initially disabled, the method further comprising: The microcontroller is configured via at least one configuration register to enable the at least one input / output port.

15. The method according to any one of claims 13 to 14, wherein the selected signal source is a port latch of the at least one port bit circuit, the method further comprising: A value is written into the port latch by the central processing unit to provide an input signal for the selected signal source.

16. The method according to any one of claims 13 to 14, wherein selecting the signal source and / or selecting the destination is performed by programming a register, wherein the register controls a first multiplexer that selects the signal source and a second multiplexer that selects the destination.

17. The method according to any one of claims 13 to 14, wherein the microcontroller comprises a programming / debugging interface coupled to the at least one port bit circuit, the method further comprising: coupling an in-circuit emulator / debugger device to the programming / debugging interface of the microcontroller; detecting a logic state of a signal within the at least one port bit circuit; as well as The logic state is forwarded to the in-circuit emulator / debugger device.

Images