Smart Charge Pump Architecture for Flash Memory Arrays

Abstract

The present disclosure relates to a non-volatile memory device and a method for generating an overvoltage value in the memory device, the memory device being composed of a plurality of sub-arrays and comprising: at least one decoding and sensing circuit system associated with each sub-array; a charge pump architecture for each sub-array, comprising a pump stage for increasing an input voltage value and obtaining an overvoltage output value; a control and JTAG interface in the memory device; and at least one register set coupled to the charge pump architecture and driven by a logic circuit portion to receive at least one activation signal, the activation signal selecting a particular charge pump architecture associated with a memory sub-array among the plurality of sub-arrays.

Description

Technical Field

[0001] The present invention relates to semiconductor non-volatile memory devices, and more particularly to a new flash memory array assembly including an intelligent charge pump architecture for a flash memory portion associated with a system-on-chip (SoC) device. Background Art

[0002] Flash memory is a type of non-volatile memory that can retain stored data without requiring electricity to be periodically refreshed. An important feature of flash memory is that it can be erased in blocks, rather than one byte at a time. Each erasable memory block contains a number of non-volatile memory cells arranged in a matrix of rows and columns. Each cell is coupled to a word line, a bit line, and a source line. The cells are programmed and erased by manipulating the voltages on the word lines, bit lines, and source lines.

[0003] Flash memory devices are typically powered by a low voltage power supply, such as 1.8 V and / or 3.3 V. However, such low voltages are not sufficient to perform all operations in the array.

[0004] Flash memories are often equipped with a charge pump that boosts the voltage levels provided by the reference voltage generator; these boosted voltage levels are applied to the memory cells during write and erase operations.

[0005] A charge pump is an externally controlled device where the output is compared to some reference value, except that the ratio of the comparison value is allowed to match, such as the known Dickson charge pump with a diode and MOSFET for driving a capacitor. Figure 1A shows a schematic diagram of a Dickson positive charge pump, Figure 1B A schematic diagram of a Dickson negative charge pump is shown.

[0006] The operating mechanism is established using a non-overlapping two-phase clock. The purpose is to store charge in one capacitor using one phase and transfer that charge to another capacitor using the other phase. Proper modulation of the phases allows the charge pump to store charge in a capacitor and transfer it to another capacitor, thereby increasing an equivalent value relative to a reference.

[0007] In the first stage, a capacitor is connected across the power supply, charging it to the same voltage. In the second stage, the circuit is reconfigured so that the capacitor is in series with the power supply and the load. This doubles the voltage across the load to the sum of the original power supply voltage and the capacitor voltage. The pulsed nature of the higher voltage switching output is often smoothed using an output capacitor. The number of stages affects the final output voltage of the circuit.

[0008] The architecture of the charge pump is even more important in all memory sections embedded or associated in a system-on-chip, where the reliability of the architecture and the possibility to use the charge pump to obtain various internal voltage values ​​are crucial. Summary of the invention

[0009] On the one hand, the present application relates to a charge pump architecture for a memory device composed of multiple sub-arrays, the architecture comprising: a pump stage chain for increasing an input voltage value and obtaining an overvoltage output value; and at least one register group coupled to the pump stage chain and driven by a logic circuit portion to receive at least one activation signal, the activation signal selecting a specific charge pump architecture associated with a memory sub-array among the multiple sub-arrays.

[0010] Another aspect of the present application relates to a non-volatile memory device, which is composed of multiple sub-arrays, including: at least one decoding and sensing circuit system, associated with each sub-array; a charge pump architecture, for each sub-array, including a pump stage for increasing input voltage values ​​and obtaining overvoltage output values; a control and JTAG interface, in the memory device; and at least one register group, coupled to the charge pump architecture and driven by a logic circuit portion to receive at least one activation signal, which selects a specific charge pump architecture associated with a memory sub-array among the multiple sub-arrays.

[0011] Another aspect of the present application relates to a method for generating an overvoltage value in a memory device, the memory device being composed of multiple sub-arrays and including at least one micro-sequencer and a charge pump architecture, the method comprising: assigning a programmable address to each charge pump architecture associated with each different sub-array; providing a logic circuit portion that receives at least one activation signal, the activation signal selecting a specific charge pump architecture associated with a memory sub-array among the multiple sub-arrays; selecting a charge pump architecture for a read, erase or write operation to be performed on the memory sub-array; and the activation signal selecting a specific charge pump architecture integrated in a JTAG protocol. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1A A schematic diagram showing a positive charge pump having a known structure used in a semiconductor memory device;

[0013] Figure 1B A schematic diagram showing a negative charge pump having a known structure used in a semiconductor memory device;

[0014] Figure 2 A schematic diagram showing a host device (e.g., a system on chip) coupled to a non-volatile memory component according to an embodiment of the present disclosure;

[0015] Figure 3 is a schematic diagram of a memory component of the present disclosure associated with a host device or SoC structure, the memory component including at least one microsequencer and dedicated circuits for programming, reading and erasing phases involving a charge pump;

[0016] Figure 4 According to one embodiment of the present disclosure Figure 3 A schematic diagram of the internal arrangement of a portion of a memory component;

[0017] Figure 5 is a schematic diagram of a Joint Test Action Group (JTAG) logic structure incorporated into a memory component of the present disclosure;

[0018] Figure 6 is a schematic diagram of a smart charge pump architecture of a memory component of the present disclosure;

[0019] Fig. 7A yes Figure 6 A more detailed schematic diagram of a portion of the charge pump architecture shown;

[0020] Figure 7B is a more detailed schematic block diagram of components of the charge pump architecture of the present disclosure; and

[0021] Figure 8 Shown is a diagram of a finite state machine that evolves through multiple states according to the JTAG standard protocol. DETAILED DESCRIPTION

[0022] Non-volatile Flash memory is one of the fundamental building blocks of today’s modern electronic systems, especially Real-Time Operating Systems (RTOS). The operation of non-volatile Flash memory is managed by a controller that includes embedded firmware, which performs the required write / read / erase operations.

[0023] Non-volatile memory can provide persistent data by saving stored data when power is not supplied, and can include NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistance variable memory such as phase change random access memory (PCRAM), self-selected chalcogenide memory, resistive random access memory (RRAM), 3D XPoint memory (3DXP), and magnetoresistive random access memory (MRAM).

[0024] More specifically, flash memory is a non-volatile memory that holds stored data and is characterized by very fast access times. In addition, it can be erased in blocks, rather than one byte at a time. Each erasable memory block contains a plurality of non-volatile memory cells arranged in a matrix of rows and columns. Each cell is coupled to an access line and / or a data line.

[0025] The cells are programmed and erased by manipulating the voltages on the access and data lines; to do this, the memory component requires a voltage value that is elevated compared to the supply voltage, so the memory structure includes one or more positive charge pumps for the read and programming phases of the memory cells, and a negative charge pump for the erase phase of the memory cells.

[0026] With reference to the accompanying drawings, in particular Figure 2 By way of example, devices and methods relating to a non-volatile memory device 1 or component and a host device 10 for such a memory device will be disclosed herein.

[0027] The host device 10 may be a system on a chip having an embedded memory component 1 or a more complex electronic device including a system coupled to a memory device, which will be described in other embodiments of the present disclosure with reference to other drawings.

[0028] Currently, complex semiconductor structure technology known as system on chip (SoC) proposes the integration of at least one embedded non-volatile memory. However, when the lithography node is lower than 28 nanometers, especially when the size is increased to higher than 128 megabits, such embedded memories are becoming large macros in SoC and are becoming increasingly difficult to manage.

[0029] The present disclosure proposes to increase the memory size by providing a structurally independent memory component 1 coupled to a host device 10 or a system on a chip. The memory component 1 is constructed as an independent device implemented in a single die by manufacturing technology dedicated to flash memory devices. The size of this memory portion is expanded to more than 256 Mbits or even 512 Mbits.

[0030] This non-volatile memory component 1 includes a flash memory cell array 90 and circuitry located around the memory array and closer to a plurality of peripheral pads, as will be disclosed below. This memory component 1 has a variable size depending on the size of its memory array, which can range in value from 128 Mbits to 512 Mbits or more, as manufactured by the user.

[0031] More specifically, the flash memory assembly 1 includes an I / O circuit 5 , a microsequencer 3 , and a sense amplifier 9 .

[0032] The flash memory assembly 1 also includes a command user interface (CUI) 4, a voltage and current reference generator 7, a charge pump architecture 2 and a decoding circuit system 8 located at the periphery of the array.

[0033] For reading the memory cells of the array 90, a dedicated circuit section is provided which includes an optimized read finite state machine for ensuring high read performance, such as branch prediction, fetch / prefetch, interrupt management, error correction, etc.

[0034] To write and erase the memory cells of array 90, a dedicated logic circuit section is provided which includes a simplified reduced instruction set computer (RISC) controller or a modified finite state machine, or the dedicated logic circuit section is a logic circuit for processing programming and erasing algorithms.

[0035] The memory component 1 is associated and linked to the host device 10, or is associated and linked to and partially overlaps with a SoC structure, and a corresponding semiconductor area of ​​the SoC structure is used for other logic circuits and provides support for the overlapped structurally independent memory portion 1.

[0036] The coupling between the SoC structure and the memory component 1 is achieved by interconnecting a plurality of corresponding pads or pin terminals facing each other in a circuit arrangement that maintains the alignment of the pads even if the size of the memory component 1 should be modified.

[0037] For completeness, it should be noted that the memory component 1 can be coupled to the SoC structure or host device 10 by flip chip technology or other coupling technology. Flip chip technology is also known by its abbreviation C4 (controlled collapse chip connection), which is a method of interconnecting a semiconductor device, such as an IC chip and / or a microelectromechanical system (MEMS), with an external circuit system, wherein the external circuit system has solder bumps deposited on the chip pads. In the final wafer processing step, the solder bumps are deposited on the chip pads on the top side of the wafer. In order to mount the chip to the external circuit system (e.g., a circuit board or another chip or wafer), the chip is flipped so that its top surface is facing down, and the pads are aligned one by one so that the pads are aligned with the matching pads on the external circuit. The solder is then reflowed to complete the interconnection.

[0038] In one embodiment of the present disclosure, the pad arrangement of the memory component 1 is implemented on the surface of the memory component 1. More specifically, the pads are implemented on an array so that when the memory component 1 is turned over, its pads face the corresponding pads of the SoC structure. Even a larger size memory component can be supported and interconnected with the pads of the SoC structure as long as the position and misalignment of its interconnection pads are maintained.

[0039] In one embodiment of the present disclosure, the charge pump architecture 2 is specifically used for a memory component 1 that is strictly associated with a host device 10 or a SoC structure and includes a JTAG logic structure.

[0040] This flash memory module 1 uses interconnection pads of the array and logic circuit portions to achieve interconnection with the host device 10 or SoC structure.

[0041] For example, the final configuration may be a face-to-face interconnected SoC / Flash Memory array with sense amplifiers connected to the SoC in a direct memory access type of memory configuration, along with JTAG logic structures and control pins for testing and other purposes.

[0042] Figure 3 A more detailed schematic diagram of a flash memory assembly 1 of the present disclosure is shown, comprising: a memory array 90, a microsequencer 3, a control and JTAG logic structure 500, and circuit portions 20, 25 and 30 for managing the charge pump during the programming, reading and erasing phases, respectively.

[0043] In an embodiment of the present disclosure, the memory array is constructed as a collection of sub-arrays 400, such as Figure 4 In this way, the sectors are smaller, the access time is significantly reduced and the overall throughput of the memory component is increased compared to known solutions.

[0044] The scan chains of each sub-array 400 are connected together to form a specific shift register 450 to properly test the above interconnections.

[0045] The advantage of this architecture is that it is very scalable and the density of the final device can be expanded and / or reduced simply by mirroring sub-arrays and generating connections.

[0046] Direct memory access can reduce the resulting delay that the SoC may incur when reading data.

[0047] In the following of this disclosure, it will be apparent that the output of the sense amplifier SA associated with each sub-array 400 is latched by an internal circuit to enable the sense amplifier to perform a further internal read operation to prepare a second nibble or group of at least 128 bits. This second nibble is transferred to the output of the flash array, using a clock signal or an additional enable signal to transfer the content read at the sense amplifier level to a channel of a host device or SoC.

[0048] Each sense amplifier SA is directly connected to the modified JTAG cell 420 so that these modified Jtag cells and sense amplifiers are integrated in a single output circuit section. This minimizes the delay in propagating the output of the memory array to the SoC.

[0049] Figure 4 A schematic diagram of a JTAG logic structure 500 incorporated into the memory component 1 of the present disclosure is shown, the JTAG logic structure using a boundary scan cell configured according to IEEE Standard 1149.1.

[0050] The JTAG logic structure is a special interface added to the chip. Depending on the version of JTAG, two, four, or five pins are added.

[0051] The connector pins are: TDI (test data input), TDO (test data output), TCK (test clock), TMS (test mode select), and optional TRST (test reset).

[0052] The TRST pin is an optional active-low reset for the test logic, usually asynchronous, but sometimes synchronous, depending on the chip. If the pin is not available, the test logic can be reset by using TCK and TMS to switch synchronously to a reset state. It is important to note that resetting the test logic does not necessarily mean resetting anything else. There are usually some processor-specific JTAG operations that can reset all or part of the chip being debugged.

[0053] Since only one data line is available, the protocol is serial. The clock input is at the TCK pin. One bit of data is passed in at TDI and out to TDO on each rising edge of the TCK clock. Different instructions can be loaded. Instructions for a typical IC might read the chip ID, sample an input pin, drive (or float) an output pin, manipulate chip functionality, or bypass (transmit from TDI to TDO to logically shorten a chain of multiple chips).

[0054] As with any clock signal, data supplied to TDI must be valid for a chip-specific setup time before the associated (here, rising) clock edge and a hold time after it. TDO data is valid some chip-specific time after the falling edge of TCK.

[0055] Figure 4 and 5 The example shows four dedicated test pins, namely test data input (TDI), test mode select (TMS), test clock (TCK), and test data output (TDO), and one optional test pin, namely test reset (TRST).

[0056] These pins are collectively referred to as the Test Access Port (TAP). However, the JTAG logic structure 500 includes a finite state machine, called a TAP controller 570, which receives three signals as inputs: TCK, TMS, and TRST. The TAP controller 570 is a 16-state final state machine FSM that controls every step of the operation of the JTAG logic structure 500. Each instruction to be executed is stored in an instruction register 520.

[0057] Figure 5 The composition of registers incorporated into the JTAG logic structure 500 of the present disclosure is shown. A boundary scan shift register 550 is coupled to the TDI pin in serial mode and provides an output through a multiplexer 560 to the TDO output pin.

[0058] The test clock TCK is fed in through another dedicated device input pin and the operation mode is controlled by a dedicated “test mode select” (TMS) serial control signal, both of which are applied to the TAP controller 570 .

[0059] Then, various control signals related to the instruction are provided by decoder 590.

[0060] The instruction register (IR) 520 includes n bits (n ≥ 2) and is implemented to store each current instruction. The architecture includes a 1-bit bypass register ( Figure 4 not shown) and identification register 530.

[0061] Additional register 580 is used as a shift data register for interacting with the core of the host device during the write and / or read phases of the memory component.

[0062] Now, the command user interface represented by TAP controller 570 is based on IEEE1149 and IEEE1532 standards, both of which implement low signal count interfaces, namely, TMS, TCK, TDI, TDO and TRST (optional), which have the ability to modify the internal contents of each associated memory sub-array 400.

[0063] In one embodiment of the present disclosure, Figure 6 As shown, the charge pump architecture 2 has at least one register group 640 and a simple charge pump logic circuit 660 to be associated with the flash memory array 90 , thereby obtaining a smart charge pump architecture 2 .

[0064] This intelligent charge pump architecture 2 is associated with each sub-array 400 of the flash memory array 90 .

[0065] This smart charge pump architecture2 can yield huge benefits during the Flash array test phase. It provides all the required voltages without any external support (i.e. test machine, external generator).

[0066] However, the charge pump of the present disclosure may also be used for other different purposes, and it may also be shared between sub-arrays 400 of the memory array 90 .

[0067] In order to fully understand the difference between the present invention and known solutions, it must be noted that in a standalone Flash memory, when a single operation is performed at a time, a resident micro-sequencer drives the output voltage of the charge pump to drive the correct operation inside the array.

[0068] On the contrary, according to the embodiments of the present disclosure, for example Figure 3As shown, the structure of the memory component 1 including the flash array 90 is associated with a microsequencer 3 which exchanges signals with circuit portions 20, 25 and 30 dedicated to the programming, reading and erasing phases of the charge pump architecture 2 of the present disclosure.

[0069] A multi-operation flash array 90, such as the one incorporated into the memory assembly 1, would require multiple independent charge pumps 2 to ensure different executions (operations) in different blocks. In contrast, the solution disclosed herein provides a pump architecture 2 that enables it to provide the required voltages for different phases of operation on the memory array.

[0070] The need for parallel operation also causes a change in the operation method of the charge pump architecture 2, that is, it requires an independent charge pump logic 660 to operate so that a specific micro-sequencer 3 drives high-performance operations in different sub-arrays of the memory array 90.

[0071] The pump 2 associated with each sub-array 400 may be configured using the microsequencer 3 as described below.

[0072] Figure 7B A more detailed view of the registers of block 780 is shown in , where registers 710 for setting a specific pump for a specific memory sub-array, or a target step to reach a target output voltage, are also reported.

[0073] The non-volatile pump address register 720 is used to assign an addressing method, i.e., a code for addressing, to each pump in each subarray. The pump address register 720 is a volatile copy of the pump address for independence of pump operation. An external FSM and / or RISC can provide input and start signals to this logic and then wait for the result.

[0074] exist Figure 6 and 7A In the embodiment, the general block is indicated by numeral 650, and the general block includes a positive or negative pump chain, such as Figure 1A This is because the memory array requires positive and negative pumps in performing various operations of the memory cell, and it may happen that the positive and negative pumps must be activated at the same time.

[0075] Once configured, once the trigger (start or run signal) is valid, pump 2 (positive or negative) can be used simultaneously. This is because some operations (such as erase) require both positive (flash cell source / body terminal) and negative (flash cell gate terminal) voltages at the same time.

[0076] There is also a signal (pump_halt) which allows to pause the voltage evolution when the signal is active and restart when the signal is inactive (allowing to support certain functionalities such as erase suspend).

[0077] In order to better understand all the features of the charge pump architecture 2, it is necessary to explain how the logic circuit portion 660 is fed and how the register set 640 is considered to be a JTAG pump register set.

[0078] As is well known in the art, the Joint Test Action Group (JTAG) standard protocol provides a method for testing interconnects on a printed circuit board that is implemented at the IC level using serial shift registers located around the device boundary.

[0079] IEEE Standard 1149.1, commonly referred to as digital boundary scan, provides a method for testing interconnections between integrated circuits on a board without the use of physical test probes, which introduces the addition of boundary scan cells consisting of multiplexers and latches to each pin on the device. In addition, another standard adopted in system programming, IEEE1532, allows the internal configuration of components to be changed in a programmable and non-programmable manner using the JTAG infrastructure.

[0080] Figure 8 The state diagram of a finite state machine FSM operating according to standard IEEE1149.1 is shown. This FSM includes sixteen states, two of which, the shift instruction register (ShiftIR) and the shift data register (ShiftDR), allow interaction with the memory array during the write and / or read phases. There are six "stable states" in which keeping TMS stable prevents the state from changing. In all other states, TCK always changes state.

[0081] Figure 8 A test access port TAP 800 is schematically shown as a finite state machine that handles all operations related to testing of an integrated circuit, such as a memory device.

[0082] A sequence of logic "0" and "1" signals applied to the TMS pin controls the operation of the chip architecture through the boundary scan structure.

[0083] The first thing to consider is starting from the test logic reset state when the circuit is powered on, indicated by numeral 810. In this particular state, all boundary scan cells are in the so-called transparent state, and the parallel input PINs are internally connected to the parallel outputs POUT, and all input pins are connected to the core of the integrated circuit.

[0084] By driving an appropriate sequence of logic values ​​"1" and "0" as the TMS signal, the output multiplexer can be set to shift the TDI input to the first instruction to obtain the output TDO. Signal TMS drives the TAPFSM in ShiftDr or ShiftIR to connect TDI and TDO to the register.

[0085] To transfer the instruction, we need to enter the state ShiftIR numbered 830, and to reach this state, we need to apply the following sequence: set 0 to TMS and drive one clock pulse to TCK, then, reach the Run / Idle state 820.

[0086] Now a "1" is selected from state 820, which is passed to the selection of data register scan 840 and instruction register scan 845. Further, by a "0" on TMS, the capture stage of the instruction register 850 can be reached.

[0087] The capture phase allows capturing Fig. 7A The last two bits of the instruction register 520 in the READ mode are captured. Capturing means using parallel inputs to capture the value in each cell of the selected register.

[0088] Further, a "0" is driven to the Shift IR, which allows the input value TDI to be passed to the output TDO. After a number of clocks equal to the size of the register, the value at the input TDI appears at the output TDO.

[0089] Keeping TMS at "0", the ShiftIR state 830 can be maintained to shift the bits received on the TDI pin to the output TDO.

[0090] This state 830 may be maintained for all clock cycles required to shift all input bits.

[0091] The ShiftIR state 830 is maintained for a number of clock cycles corresponding to the number of bits in the IR 720 minus one. At the end of the sequence, the Exit-1 IR state 855 is reached.

[0092] From this breakout state 855, it moves to the update state 860 which drives a "1" TMS, which is when the new instruction takes effect. The boundary scan cell reverts to test mode, where the input pins are isolated from the core circuitry.

[0093] The test vectors may now be sent to the core circuitry by reaching Shift DR state 870 .

[0094] The state of the data register is similar to the state of the instruction register.

[0095] Thus, by the sequence 1-0-0, the ShiftDR state 870 can be reached.

[0096] Via Capture DR 875, the first multiplexer MO1 of the boundary scan cell is connected to the parallel input PINs and all input pins of the boundary scan registers capture their input values.

[0097] Now turning to Shift DR 870, the multiplexer changes its state, allowing the serial input SIN to be captured, and the scan path moves from the TDI input to the output pin TDO via the boundary scan register.

[0098] The circuit remains in this state for a number of clock cycles corresponding to the number of boundary scan cells minus 1. However, the boundary scan is one of the possible data registers, selected by the appropriate instruction in the IR register.

[0099] When passing the Exit-1 DR 880 state and reaching the Update DR state 885, the new test vector is output to the output pin.

[0100] The sequence is repeated from update to capture to allow new test vectors to be introduced into the circuit system.

[0101] exist Figure 8 An example of a process for addressing a specific charge pump architecture 2 is schematically shown in FIG. 1 , which is an example of a FSM evolving in different states, as follows:

[0102] ShiftIR:Pump_Address_Instruction

[0103] ShiftDR:Pump_address_shift_in to select the desired pump

[0104] ShiftIR:Vo_Target_Instruction

[0105] This last command is loaded only into the selected pump.

[0106] An alternative example of an instruction flow to address a specific charge pump architecture 1 is as follows:

[0107] ShiftDR:Vo_target_value shifts in

[0108] ShiftIR:Vo_Target_Step_Instruction

[0109] This last command is loaded only into the selected pump.

[0110] A further example of an instruction flow addressing a particular charge pump architecture 2 is as follows:

[0111] ShiftDR:Vo_Target_Step_value shifts in

[0112] ShiftIR:Vo_Target_Size_Instruction

[0113] This last command is loaded only into the selected pump.

[0114] A further example of an instruction flow addressing a particular charge pump architecture 1 is as follows:

[0115] ShiftDR:Vo_Target_Size_value shifted in

[0116] ShiftIR:Pump_Service_Instruction

[0117] This last command is loaded only into the selected pump.

[0118] Another example of an instruction flow addressing a specific charge pump architecture 2 is as follows:

[0119] ShiftDR:Vo_Service_value shifted in

[0120] This command can provide additional information to the charge pump, i.e., standby information, test mode input, etc.

[0121] Yet another example of an instruction flow addressing a particular charge pump architecture 1 is as follows:

[0122] Run / Test_Idle

[0123] The instruction starts executing the pump and / or forces the setting of a service register bit for the selected pump, which determines whether the pump must be run when the run / test_idle bit is set.

[0124] As we can see, TAP includes test data input and test data output as well as clock signals. More specifically, the shift data register ShiftDR reports the state of the TDI connection to the register. In this state, the register contents are passed into and / or out of the device.

[0125] Similarly, the shift instruction register ShiftIR also reports the state of the TDI connection to the register in which the instruction is loaded.

[0126] More specifically, the shift data register ShiftDR reports the state of the signal TDI connected to the register in which the register contents are transferred into and / or out of the device.

[0127] Similarly, the shift instruction register ShiftIR also reports the state of the TDI connection to the register in which the instruction is loaded.

[0128] Since multiple cores are required inside the host device 10 or SoC, the internal registers 580 of the JTAG interface must be able to support address and data registers. In particular, four address registers (from each sub-array 400) are generated to fill the different addresses of each sub-array 400, and for each sub-array portion, four different data outputs are triggered for the read register [0:3]. Communication with the SoC is performed by connecting the selected read register (i.e., the output named POU [127:0]) directly to the input of the channel of the host device 10 or SoC structure.

[0129] This mechanism allows preloading the controller with data to reduce latency values ​​to very low values.

[0130] For completeness, it is important to note that the JTAG state machine can be reset, access the instruction register, or access data selected by the instruction register.

[0131] To use JTAG, the host device connects to the target's JTAG signals (TMS, TCK, TDI, TDO, etc.) through some kind of JTAG adapter, which may need to deal with issues such as level translation and galvanic isolation. The adapter connects to the host using some kind of interface (such as USB, PCI, Ethernet, etc.).

[0132] The host device 10 communicates with the TAP block 570 by manipulating TMS and TDI in conjunction with TCK, and reading the result through TDO (the only standard host-side input). The TMS / TDI / TCK output conversion creates the basic JTAG communication primitive, on which the higher-level protocol is built:

[0133] State switching: In which all TAP signals are in the same state and that state changes on TCK transitions.

[0134] So, at a basic level, using JTAG involves reading and writing instruction and its associated data registers, and sometimes involves running multiple test cycles. Behind these registers is hardware that is not specified by JTAG and has its own state that is affected by JTAG activity.

[0135] Each primary input signal and primary output signal is supplemented with a multi-purpose memory element called a boundary scan cell, which is essentially a shift register 550.

[0136] A parallel load operation, referred to as a "capture" operation, causes the value of a signal on a device input pin to be loaded into an input cell, and causes the value of a signal passed from the core logic to a device output pin to be loaded into an output cell.

[0137] The parallel unloading operation, called the "update" operation, causes the signal value already present in the output scan unit to be transferred out through the device output pin. Depending on the nature of the input scan unit, the signal value already present in the input scan unit will be transferred to the core logic. The update operation also allows the value in the register to be confirmed (i.e. the shifting introduces a bit that can be paused). When the update state is reached in the IEEE 1149.1 FSM, the register value is fixed, i.e. it is a latched signal that updates the target register value.

[0138] Data may also be shifted around the shift register in a serial mode, starting at a dedicated device input pin called "Test Data In" (TDI) and terminating at a dedicated device output pin called "Test Data Out" (TDO).

[0139] Thus, the edge connector input, called TDI, is connected to the TDI of the first device. TDO from the first device is connected to the TDI of the second device, and so on, creating a global scan path that terminates at the edge connector output, called TDO.

[0140] The test clock TCK is fed in via another dedicated device input pin, and the operating mode is controlled by a dedicated "Test Mode Select" (TMS) serial control signal.

[0141] In one embodiment of the present disclosure, the TDI and TDO signals are used to drive the Figure 6 The register set 640 of the charge pump architecture 2 is shown.

[0142] Compared to the configuration of the charge pump of a standalone flash memory device, the present disclosure provides several hardware modifications, in particular:

[0143] Converting the charge pump into an intelligent subsystem by providing a register set 640 and a logic circuit section 660;

[0144] Producing an appropriate output voltage with an appropriate shape (i.e., step amplitude and size of the Vo output value of the pump chain section 650) and with appropriate delays in the generation steps;

[0145] Integration with JTAG protocol;

[0146] Assigning programmable addresses to the charge pump architecture 2 to allow identification of a different pump for each different sub-array 400 of the flash array 90;

[0147] Provide at least one pair of registers interconnected using TDI / TDO logic in register group 640:

[0148] - an address register to drive a specific pump for a specific sub-array; and

[0149] - The amplitude of the step register, which is used to define the step size of the Vo value.

[0150] One embodiment of the present disclosure relates to a charge pump architecture for a memory device composed of a plurality of sub-arrays, the architecture comprising:

[0151] - stage chain, used to increase the input voltage value and obtain the overvoltage output value;

[0152] - at least one register set 640, coupled to said stage chain 650 and driven by a logic circuit portion 660, to receive at least one activation signal, said activation signal selecting a particular charge pump architecture associated with a memory sub-array.

[0153] Register set 640 includes at least one pair of registers: one for activating a particular charge pump architecture 2 associated with memory sub-array 400, and another for defining the value of the pump output voltage.

[0154] In addition, register set 640 includes a JTAG finite state machine, such as Fig. 7A Shown, No. 750.

[0155] The logic circuit portion 660 selects and activates the corresponding pump chain 650 of each sub-array 400 of the memory array 90 via the register set 640, thereby selecting not only the pump but also its activity. Thus, if the pump architecture is required to provide an appropriate overvoltage value for the read phase, the logic circuit portion 660 will select the pump of the sub-array involved in the read phase.

[0156] Similarly, if the pump architecture is required to provide an appropriate overvoltage value for a write phase, the logic circuit portion 660 will select the overvoltage value and the number and location of the pumps of the sub-array 400 involved in the write phase.

[0157] Furthermore, if the pump architecture 2 is required to provide an appropriate overvoltage value for the erase phase, the logic circuit portion 660 will select the overvoltage value and the number and location of the pumps of the sub-array involved in the erase phase.

[0158] Alternatively, the address register described above is a lock table for recording the quality and location of the pumps required to handle specific operating activities on the flash memory array 90. Therefore, there are pumps for the read or erase phase and pumps for the write phase, and the logic circuit portion 660 selects and activates the corresponding pumps simply by selecting a logic value.

[0159] It should also be considered that the read phase is not performed during the erase phase, so no specific pump architecture is required for simultaneous reading and erasing, but the multi-purpose structure of the charge pump architecture 1 is used for both the read and erase phases, which is obviously driven in an appropriate manner to obtain the overvoltage value required for the specific operation of the corresponding memory sub-array.

[0160] More specifically, the erase operation is done in 3 macro steps:

[0161] 1) Pre-programming stage: Program all cells of the selected block;

[0162] 2) Erase pulse;

[0163] 3) Verification, using edge reference voltage read operations to ensure reliability;

[0164] Repeat loops (2) and (3) until the block is erased or a predefined timeout is reached. If the timeout is reached, the erase result is a failure.

[0165] The pump architecture 1 is activated while the controller of the memory array processes other activities, such as preparing the circuit parts dedicated to the read and / or write phases. Therefore, the pump architecture 1 will reach the required overvoltage value within the time frame in which the controller processes other activities.

[0166] In the following, reference is made to Fig. 7A Further features of the circuit structure related to the charge pump of the present disclosure are disclosed, wherein Fig. 7A The basic internal structure of register group 580 is schematically shown.

[0167] The finite state machine 750 is bidirectionally connected to the pump chain 650 to apply the appropriate input reference voltage value Vin and phase modulation, and regulate the appropriate value Vout of the output.

[0168] Even this state machine 750 can be considered as a JTAG state machine. Although, the pump FSM 750 interfaces with the previously disclosed JTAG FSM, it works differently as a step-by-step logic to perform adjustments and maintenance through comparisons.

[0169] Finite state machine 750 is also bidirectionally connected to a set of registers of block 780, each of which contains a target value that the charge pump architecture 2 should achieve, such as a target output voltage, a target time for the output voltage to reach its value, and the state of some other registers.

[0170] refer to Figure 7B A more detailed view of the registers of block 780 is shown. As already noted, register 710 is used to set a specific pump for a specific memory sub-array, or to set the register for a target step to reach a target output voltage. The non-volatile pump address register 720 is used to assign an addressing method to each pump in each sub-array, i.e., a code for addressing. The pump address register 720 is a volatile copy of the pump address for independence of pump operation. An external FSM and / or RISC provides input and start signals to this logic and then waits for the result.

[0171] In any case, all registers of block 780 can be selected according to the value of the TDI input signal. More specifically, the content is loaded by the TDI signal, and the register is addressed to drive the TMS signal to move in the JTAG finite state machine.

[0172] The logic circuit portion 660 is responsible for running the correct phase sequence to match the required settings in the JTAG pump register 640 and reporting the status. The logic circuit portion 660 is linked to the run / test_idle state of the JTAG state machine.

[0173] The logic circuit part 660 is also responsible for updating the state of the register group of block 780 and, if necessary, the direct signal of the microsequencer 3.

[0174] More specifically, the logic circuit portion 660 of the charge pump should allow the following settings:

[0175] The duration step size, which defines how long a voltage must be maintained;

[0176] Target final voltage: the value of Vo target voltage;

[0177] Dedicated hardware, in terms of the definition of the hardware part involved in the charge pump architecture:

[0178] -Start operation, when run / test_idle is reached;

[0179] - Provide feedback to the microsequencer;

[0180] - Disable the pump when not in use to minimize power consumption.

[0181] The charge pump architecture 2 of the present disclosure is driven by an internal microsequencer 3 (i.e., a flash memory controller). The microsequencer 3 properly configures the pump blocks, and then, once the pumps are triggered by a start (run) signal, they implement the requested Vout voltage shape by comparing with an inherent reference and wait states to reach the final voltage, because the pumps have one or more voltage regulators inside that require a reference voltage value, such as Fig. 7A As shown, the pump may include a regulator implementing a D / A converter involving high voltage values ​​(positive or negative).

[0182] The logic circuit portion 660 is further responsible for running the correct phase sequence to match the required settings in the JTAG pump registers and report the status.

[0183] The charge pump logic is linked to the run / test_idle state of the JTAG state machine.

[0184] The charge pump logic is also responsible for updating the status in the registers and, if necessary, the direct signals to the microsequencer.

[0185] The charge pump architecture proposed in the present disclosure allows multiple operations in addressing different sub-arrays of the flash memory array 90 .

[0186] In addition, the new pump architecture allows the charge pump to be driven using the JTAG protocol in different situations, such as:

[0187] - for execution;

[0188] - For testing;

[0189] -For on-site fault analysis.

[0190] An advantage of the disclosed charge pump architecture is that it provides a unique charge pump design and reduces verification time and design time.

[0191] Also, it is a reusable block thanks to the smarts and registers.

[0192] A further advantage is provided by the full reusability of the charge pump architecture, which can be used for different purposes and shared between sub-arrays of memory devices.

Claims

1. A charge pump architecture (2) for a memory device composed of a plurality of sub-arrays (400), the architecture comprising: A pump stage chain for increasing the input voltage value and obtaining an overvoltage output value; and at least one register set coupled to the pump stage chain and driven by a logic circuit portion (660) to receive at least one activation signal, the activation signal selecting a charge pump architecture (2) associated with a memory subarray (90) of the plurality of subarrays (400), and The register group includes a non-volatile pump address register for allocating a code to each pump in each sub-array for addressing.

2. The charge pump architecture of claim 1 , wherein: The register set includes at least one first register for activating the charge pump architecture associated with the memory sub-array; and a second register that defines the value of the pump output voltage.

3. The charge pump architecture of claim 1 , wherein: The at least one register set includes a Joint Test Action Group (JTAG) finite state machine (750).

4. The charge pump architecture of claim 3, wherein: The finite state machine is bidirectionally connected to the chain of pump stages to apply a suitable value of the input reference voltage Vin and regulate a suitable value at the output Vout.

5. The charge pump architecture of claim 3, wherein: The logic circuit portion is linked to the run / test_idle state of the JTAG finite state machine.

6. The charge pump architecture of claim 5, wherein: The registers of the register group can be selected according to the value of the test data input TDI signal of the JTAG protocol, the content is loaded by the TDI signal, and the registers are addressed to drive the test mode selection TMS signal to move in the JTAG finite state machine.

7. The charge pump architecture of claim 5, wherein: The register is used to associate a pump architecture with the memory sub-array for providing overvoltage values ​​for at least read and write phases.

8. The charge pump architecture according to any one of claims 1 to 5, wherein: The contents of all registers of the register bank are programmable.

9. A non-volatile memory device, comprising a plurality of sub-arrays, comprising: at least one decoding (8) and sensing circuitry coupled to each sub-array (400); a charge pump architecture (2), for each sub-array, comprising a pump stage for increasing an input voltage value and obtaining an excess voltage output value; control and JTAG interface in said non-volatile memory device; as well as at least one register set coupled to the charge pump architecture (2) and driven by a logic circuit portion (660) to receive at least one activation signal, the activation signal selecting a charge pump architecture associated with a memory subarray (90) of the plurality of subarrays (400), and The register group includes a non-volatile pump address register for allocating a code to each pump in each sub-array for addressing.

10. The nonvolatile memory device according to claim 9, wherein: The register set (640) includes at least one first register for activating the charge pump architecture associated with the memory sub-array; and a second register that defines the value of the pump output voltage.

11. The nonvolatile memory device according to claim 9, wherein: The register set (640) includes a JTAG finite state machine (750).

12. The nonvolatile memory device according to claim 11, wherein: The finite state machine is bidirectionally connected to the chain of pump stages of the charge pump architecture (2) to apply a suitable value of the input reference voltage Vin and regulate a suitable value at the output Vout.

13. The nonvolatile memory device according to claim 11, wherein: The logic circuit portion (660) is linked to the run / test_idle state of the JTAG finite state machine.

14. The nonvolatile memory device according to claim 11, wherein: The registers of the register group can be selected according to the value of the test data input TDI signal of the JTAG protocol, the content is loaded by the TDI signal, and the registers are addressed to drive the test mode selection TMS signal to move in the JTAG finite state machine.

15. The nonvolatile memory device according to claim 11, wherein: The finite state machine is also bidirectionally connected to a set of registers, and each register includes a target value for the charge pump architecture.

16. The nonvolatile memory device according to claim 15, wherein: The target value is included in the group including at least one target output voltage and at least one target time to reach the output voltage.

17. The non-volatile memory device according to any one of claims 9 to 15, wherein: The contents of the registers of the register bank are programmable.

18. A method for generating an overvoltage value in a memory device, the memory device being composed of a plurality of sub-arrays and comprising at least one micro-sequencer and a charge pump architecture (2), the at least one micro-sequencer being configured to correctly configure the charge pump architecture (2), the method comprising: assigning a programmable address to each charge pump architecture associated with each different sub-array; providing a logic circuit portion (660) receiving at least one activation signal, the activation signal selecting a charge pump architecture associated with a memory subarray of the plurality of subarrays (400); selecting a charge pump architecture for a read, erase, or write operation to be performed on the memory subarray (90); as well as The activation signal selects a charge pump architecture associated with the memory sub-array integrated in the JTAG protocol, and The charge pump architecture (2) includes a non-volatile pump address register for assigning a code to each pump in each sub-array for addressing.

19. The method according to claim 18, wherein: JTAG registers are provided to assign programmable addresses to each charge pump architecture associated with each different sub-array.

20. The method according to claim 18, wherein: The logic circuit portion also defines the value of the pump output voltage.

21. The method according to claim 19, wherein: The JTAG registers include a JTAG finite state machine (750).

22. The method according to any one of claims 18 to 21, wherein: The JTAG finite state machine (750) is bidirectionally connected to the pump stage chain of the charge pump architecture to apply an appropriate value of the input reference voltage Vin and regulate an appropriate value at the output Vout.

23. The method according to any one of claims 18 to 21, wherein: The logic circuit portion is linked to the run / test_idle state of the JTAG finite state machine (750).

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