Tunable drive

Abstract

An embodiment provides a tunable drive circuit (180) that operates by: monitoring (160) the frequency of a ring oscillator (140) of an electrical integrated circuit (110) connected to an optical modulator (121) to determine an operating characteristic of the electrical integrated circuit (110); and setting drive voltages of a plurality of tunable inverters (FIG. 1: 182, FIG. 7: 730, 760) and a plurality of fixed gain inverters (FIG. 1: 182, FIG. 7: 740, 750) based on the operating characteristic. The tuning inverter and the plurality of fixed gain inverters control an optical modulator (121), wherein each of the plurality of tunable inverters (FIG. 7: 730, 760) is connected in parallel with a corresponding fixed gain inverter (FIG. 7: 740, 750) of the plurality of fixed gain inverters on a first arm (FIG. 7: 610A) and a second arm (FIG. 7: 610B) connected to the optical modulator (121); and the amplification strength of the plurality of tunable inverters is set based on operating characteristics.

Description

Technical Field

[0001] Embodiments presented herein generally relate to drivers for use with Mach-Zehnder interferometers (MZIs) and other optical modulators. More specifically, the embodiments disclosed herein provide more consistent operation in process corners, thereby improving power consumption, bandwidth availability, and process yield. Background Art

[0002] The power consumption of an optical modulator driver is determined by the capacitive load being driven, the frequency of operation, the voltage supply, the choice of CMOS (complementary metal oxide semiconductor) technology, and the architecture of the modulator. However, when a batch of modulator drivers is manufactured, small changes in the design can result in a variety of modulator drivers that meet the production specification but have significantly different power consumption requirements. Consistent modulator drivers at either end of the production specification for a given configuration are referred to herein as process corners. In an MZI or other modulator with two arms, the modulator driver process corners can include modulator drivers with drivers at one end of the specification (e.g., a "fast" driver) or with drivers at the other end of the specification (e.g., a "slow" driver). Each of the process corners for a given configuration can exhibit different power consumption requirements, and a driver can be selected for the modulator of that configuration based on the highest required power consumption of one of the process corners. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] In order that the features of the present disclosure set forth above may be understood in detail, a more particular description of the disclosure, briefly summarized above, may be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate typical embodiments and are therefore not to be considered limiting; other equally effective embodiments are contemplated.

[0004] Figure 1 is a block diagram of a photonic platform according to an embodiment of the present disclosure.

[0005] Figure 2A A multi-segment electro-optical modulation device according to embodiments described herein is shown, such as may be used as a modulator.

[0006] Figure 2B is a schematic diagram of a modulator segment coupled to an output segment of an exemplary modulator driver according to embodiments described herein.

[0007] Figure 3A and Figure 3B is a block diagram of a driver according to embodiments described herein.

[0008] Figure 4is a block diagram of an exemplary conversion stage of a modulator driver according to embodiments described herein.

[0009] Figure 5A and Figure 5B A schematic diagram of an input stage of a driver according to an embodiment of the present disclosure is provided.

[0010] Figure 6 A schematic diagram of a buildup stage according to an embodiment of the present disclosure is shown, the buildup stage comprising a buffer chain arranged in series on a first arm and a second arm.

[0011] Figure 7 Schematic diagrams of individual buffers according to embodiments of the present disclosure are shown.

[0012] Figure 8 is a flow chart of a method for tuning a driver of a modulator according to an embodiment of the present disclosure.

[0013] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation. DETAILED DESCRIPTION

[0014] Overview

[0015] One embodiment presented in the present disclosure provides a tunable driver circuit, comprising: a plurality of buffers arranged in series, wherein a given buffer of the plurality of buffers is configured to receive a first input and a second input and generate a first output and a second output, and wherein each buffer of the plurality of buffers comprises: a first tunable inverter electrically connected to a first input node configured to receive the first input and a first output node configured to carry the first output; a first fixed inverter electrically connected in parallel with the first tunable inverter to the first input node and the first output node; and a second tunable a first cross-coupled inverter having an input connected to the first input node and an output connected to the second input node; and a second cross-coupled inverter connected in parallel with the first cross-coupled inverter and having an output connected to the first input node and an input connected to the second input node.

[0016] One embodiment presented in the present disclosure provides a method for tuning a tunable drive circuit, the method comprising: monitoring the frequency of a ring oscillator of an electrical integrated circuit connected to an optical modulator to determine an operating characteristic of the electrical integrated circuit; setting drive voltages for a plurality of tunable inverters and a plurality of fixed-gain inverters based on the operating characteristics, the plurality of tunable inverters and the plurality of fixed-gain inverters controlling the optical modulator, wherein each of the plurality of tunable inverters is connected in parallel with a corresponding fixed-gain inverter of the plurality of fixed-gain inverters on a first arm and a second arm connected to the optical modulator; and setting amplification strengths of the plurality of tunable inverters based on the operating characteristics.

[0017] One embodiment presented in the present disclosure provides an electrical integrated circuit, comprising: a frequency comparator connected to a ring oscillator and an external reference clock signal, the frequency comparator being configured to determine an operating characteristic of an electrical circuit connected to an optical modulator based on a frequency difference between the ring oscillator and the external reference clock signal; an electrical driver connected to the optical modulator and configured to drive a phase shift of a first optical signal carried on a first arm of the optical modulator relative to a second optical signal carried on a second arm of the optical modulator, the electrical driver comprising: a first signal path connected to the first arm of the optical modulator, wherein the first signal path comprises: a first inductor electrically connected to a first node on the first signal path and a second node on the first signal path; a first tunable gain inverter electrically connected to a second node on the first signal path and a third node on the first signal path; and a first fixed gain inverter electrically connected to the second node and the third node.

[0018] Exemplary embodiments

[0019] The present disclosure provides systems and methods for tuning the electrical driver of an optical modulator based on the operational switching characteristics of individual modulator drivers connected to and driven by a given electrical driver. Rather than setting the drive voltage and amplification characteristics of the electrical driver based on the modulator's most power-intensive operating characteristics (e.g., the modulator's worst-case power consumption characteristics that still meet design parameters / specifications for the type / class / number of parts of the modulator) regardless of the actual operating characteristics of the individual modulator, the driver circuits described herein allow the drive voltage and amplification characteristics to be matched to the operating mode of the individual modulator. By individualizing the drive voltage and amplification characteristics of the electrical driver, manufacturers of photonic platforms (or devices used therein) can thereby improve power consumption at less power-intensive process corners (e.g., avoiding supplying excessive voltage to individual components), increase signaling bandwidth availability, and improve process yield by expanding the operational characteristics of the process corners that define the design parameters / specifications for a class of modulators.

[0020] Figure 1 FIG1 is a block diagram of a photonics platform 100 including an electrical integrated circuit (EIC) 110 and an optical integrated circuit (OIC) 120. The EIC 110 and the OIC 120 include different components that are manufactured using different processes and are bonded together to provide electrical control and monitoring of optical signals and monitoring of process corner performance of the EIC 110.

[0021] EIC 110 includes a frequency comparator 130, a ring oscillator 140, and an electrical driver 180 (generally driver 180) connected to OIC 120. In some embodiments, EIC 110 includes a reference clock 150, a processor 160, and a programmable voltage regulator 170. In some embodiments, one or more of reference clock 150, processor 160, and regulator 170 may be provided external to EIC 110, such as through a temporary connection to test equipment or a connection to a second electrical circuit.

[0022] The OIC 120 includes an optical modulator 121, such as a Mach-Zehnder interferometer (MZI). The OIC 120 may include one or more optical modulators 121, each associated with a connection to the driver 180, and other optical elements (and associated electrical interconnects) such as, but not limited to, waveguides, optical interfaces (e.g., optically connecting the OIC 120 to a second optical circuit or optical cable), photodetectors, light generators, lenses, reflectors, and the like.

[0023] During self-test or external calibration, EIC 110 interfaces with OIC 120, and frequency comparator 130 compares the frequency of ring oscillator 140 with the clock signal from reference clock 150 to determine the operating characteristics of driver 180. Depending on how driver 180 is manufactured, individual arms of driver 180 can exhibit different operating characteristics, typically categorized as Fast (denoted by F), Slow (denoted by S), or Typical (denoted by T), which indicates the duty cycle of the N or P channel of modulator 121. The Fast corner exhibits higher carrier mobility than the Typical and Slow corners, and the Slow corner exhibits lower carrier mobility than the Typical and Fast corners, which affects the speed at which a given transistor in driver 180 can switch and the amount of power required to effect transistor switching.

[0024] Frequency comparator 130 provides a process / voltage / temperature (PVT) reading to processor 160, which can be burned into EIC 110 as a chip fuse value. Processor 160 interprets the frequency of ring oscillator 140 to determine which process corner (e.g., FF, FS, TT, SF, or SS) driver 180 belongs to and how to set / tune driver 180 for that process corner. Processor 160 sets the gain of one or more tunable inverters in the accumulation stage 182 of driver 180 to account for the identified process corner of driver 180 and sets the supply voltage of regulator 170 accordingly. Setting the programmable drive of each tunable inverter in the accumulation stage 182 controls excess peaking in driver 180 within process variations, which protects transistors from damage (e.g., due to overvoltage) and reduces optical eyeclosure in the optical signal modulated by modulator 121.

[0025] Regulator 170 provides a supply voltage (denoted herein as V DD ) serves as a drive voltage and / or reference voltage for various components in the driver 180 (including the input stage 181 and the accumulation stage 182), which controls the strength and power consumption of the driver 180. By matching the power supplied to the process corner exhibited by the individual drivers 180, the regulator 170 can apply a more consistent amount of power to different process corners and use less power in fast and typical process corners compared to a regulator 170 configured to supply power levels based on performance characteristics of slow process corners.

[0026] As shown, the driver 180 includes an input stage 181 and an accumulation stage 182, although several input stages 181 and accumulation stages 182 may be included to control several modulators 121 or components thereof. The input stage 181 may include various through-terminals and differential amplifier circuitry, such as those described with respect to FIG. Figure 5A and Figure 5B The example is illustrated and discussed in more detail. The accumulation stage 182 amplifies and adjusts the strength of the differential signal generated in the input stage 181 and supplies the amplified signal 190 1-n to the modulator 121. The number n of amplified signals 190 is based on the number of modulators 121 and their individual stages on the OIC 120. Figure 6 and Figure 7 Exemplary circuitry for accumulation stage 182 is discussed in greater detail.

[0027] Figure 2A 1 shows a multi-segment electro-optical modulation device according to embodiments described herein, such as may be used as modulator 121. Specifically, Figure 2A An MZI type modulation device 200 is shown that includes an input 205 that receives an optical signal (eg, a continuous wave signal) and an output 245 that transmits a signal based on a wavelength for driving an optical modulator segment 220. 1-n , 225 1-n The input end 205 includes a beam splitter 210 (eg, a y-beam splitter) that divides the incident continuous wave into each of the branches 2151 and 2152. The divided optical signals each pass through each modulation segment 220. 1-n , 225 1-n , as described above. The modulation segments 220, 225 of each branch 215 can be grouped into pairs 230, such that pair 2301 corresponds to modulation segments 2201 and 2251, pair 2302 corresponds to modulation segments 2202 and 2252, and so on. In one embodiment, at least one of the pairs 230 is used for thermal biasing of the modulation device 200. For example, the modulation device 200 can DC bias at a quadrature point by providing appropriate signals to the thermal bias pair(s) to heat a portion of the modulation device 200 (referred to as a DC bias portion (not shown)). Although n segments are shown for each branch 2151, 2152, it is also possible to have a different number of modulation segments per branch. The modulated optical signals from each of the branches 215 are then recombined using a combiner 240 (e.g., a y-combiner) to form a modulated output optical signal at an output terminal 245. Furthermore, the structure shown in the modulation device 200 can be used with any of the modulators and features disclosed herein.

[0028] Figure 2Bis a schematic diagram of a pair of modulator segments 230 coupled to the output of the modulator driver 180 according to embodiments described herein. Specifically, the diagram represents an electrical equivalent model of the pair 230 of modulator segments 220, 225 of the modulator 121 of a SISCAP (Silicon-Insulator-Silicon Capacitor) device.

[0029] Each modulator segment 220, 225 includes a resistor R representing the resistance of the P-type region of the SISCAP device. P (shown as resistors 270, 275, respectively), and a resistor R representing the resistance of the N-type region N (Shown as resistors 250, 255 respectively). The resistance R of each modulator segment 220, 225 P 、R N The two devices are coupled via capacitance C (shown as capacitors 260 and 265, respectively), which typically represents the capacitance across the gate oxide, or gate dielectric (also referred to as a capacitive junction) of a SISCAP device. In a SISCAP device, typically one of the N and P plates of capacitors 260 and 265 is driven by driver 180 at a different voltage based on the corresponding data signal 201A, 201B (generally, data signal 201), and the other plate is maintained at a constant DC voltage V poly (Indicated by connection 280). Although Figure 2B shows that the P-type region remains at V poly , and the N-type region is driven with a variable voltage of the data signal 201, but in other embodiments, the N-type region can be kept at V poly , and the P-type region is driven according to the data signal 201 .

[0030] As shown, the electrical contacts of the N-type region are coupled at input terminals 202A, 202B (generally input terminals 202) to a first arm 290A (generally amplifier arm 290) and a second arm 290B of the amplifier chain of the driver 180, which provide the data signal 201A and the complement data signal 201B, respectively. Each amplifier arm 290 is powered by a shared voltage V DD drive, and includes various inverters, inductors, and electrostatic discharge (ESD) protection devices (also known as ESD protectors), which will be Figure 6 and Figure 7201 and 202B. The amplifier arms 290 are discussed in more detail. Each amplifier arm 290 receives a corresponding data signal 201 and outputs an amplified data signal 203A, 203B (collectively, amplified data signal 203) to a corresponding input terminal 202A, 202B of pair 230. Thus, the amplified data signal 203 generally represents a fully rail-to-rail data signal 201, albeit at different voltages matching the capabilities of the SISCAP device. In an embodiment using an even number of inverters, if data signal 201A corresponds to data (DATA) and data signal 201B corresponds to the logical complement of data ( In an embodiment using an odd number of inverters, if data signal 201A corresponds to data (DATA) and data signal 201B corresponds to the logical complement of data ( Instead of (DATA), DATA*, ​​etc.), then the amplified data signal 203A corresponds to the complement, and the amplified data signal 203B corresponds to the data.

[0031] Figure 3A and Figure 3B is a block diagram of a driver 180 according to embodiments described herein. Generally, driver arrangement 300 illustrates an example of high-level functionality of driver 180, and driver arrangement 350 illustrates an exemplary implementation of driver arrangement 300. Although the functionality of driver arrangement 300 is illustrated as a series of multiple functional stages, alternative embodiments may provide a different order or different functional stages. For example, the functional stages (or portions of stages) may be performed in a different order, additional stages may be included or some stages may be omitted, or some functional stages may be performed simultaneously. Additionally, the various functional stages may be provided as separate integrated circuits, or some or all of the functional stages may be included within a shared integrated circuit.

[0032] As shown, the driver arrangement 300 receives a differential input signal 302. Generally, differential signaling is a method of electrically transmitting information using two complementary signals (called a differential pair) sent on two paired wires or traces. Because external signal interference such as noise tends to affect both wires in the same way, and because the transmitted information is contained in the difference between the complementary signals, differential signaling generally provides improved resilience to electromagnetic noise compared to single-ended signaling. Typically, single-ended signaling uses one signal relative to an unpaired reference voltage (e.g., ground) to transmit information. The noise immunity of differential signaling may be advantageous when used with low-voltage, high-speed electronic systems, such as modern communication systems. The differential input signal 302 can be an analog signal or a digital signal.

[0033] In many cases, modulator 121 may require specific signal characteristics at its input that do not match the data characteristics included in differential input signal 302 (e.g., they may be specific to a communication standard). In some embodiments, the modulation efficiency of modulator 121 depends on the voltage output range provided by the circuitry of driver 180 and where the operating characteristics of modulator 121 fall within the production boundaries of that type of modulator 121. For example, a first compliant modulator 121 in a first process corner may require X mW (milliwatts) of power, while a second compliant modulator in a second process corner may require Y mW of power. By adjusting the supply voltage and inverter gain for a specific process corner, rather than setting driver 180 based on the requirements of a specific process corner, manufacturers can reduce power consumption differences between relative process corners due to process variations in manufacturing driver 180 (e.g., reduce Δ(X,Y)).

[0034] In conversion stage 304, the differential input signal 302 is converted by driver circuitry to generate a complementary CMOS signal. Among other functions, the conversion may include various amplification stages of the differential input signal. In one embodiment, conversion stage 304 provides a rail-to-rail complementary CMOS output signal. The information included in the complementary CMOS signal may be further processed in processing stage 306, and the resulting signal may be amplified in amplification stage 308 to produce a complementary CMOS output signal 310 suitable for driving the modulator. Amplification stage 308 may include multiple stages of amplifier circuitry that collectively boost the output signal to a desired voltage range for operating modulator 121.

[0035] Driver arrangement 350 provides an example of driver arrangement 300. A current mode logic (CML) input signal 352 is received at a CML to CMOS conversion stage 354 of driver arrangement 350. CML is a type of differential digital logic family that is typically configured to transmit data at rates up to 40 gigabits per second (Gb / s) and higher using printed circuit boards. Due to its relatively small output voltage swing and relatively fast current switching, CML is often used in the design of high-speed electronic systems. Compared to other logic families, CML may specify additional requirements, such as termination circuitry (discussed further below). In one embodiment, CML to CMOS conversion stage 354 includes a differential amplifier whose output is coupled to at least one transimpedance amplifier (TIA). In one embodiment, CML to CMOS conversion stage 354 includes one or more amplification stages after the TIA to boost the signal to a rail-to-rail complementary CMOS output signal suitable for driving a CMOS-based modulator.

[0036] The output signal from the CML-to-CMOS conversion stage can undergo additional processing before being amplified to the desired output level of modulator 121. As shown, data multiplexing stage 356 allows the output signal data to be changed during operation. For example, data multiplexing stage 356 can allow a test signal or other desired signal to be selected for output to modulator 121. Following data multiplexing stage 356, the signal is amplified in output amplifier stage 358 to an output range suitable for driving an output signal 360 of a CMOS-based modulator.

[0037] Figure 4 is a block diagram of an exemplary conversion stage of the modulator driver 180 according to embodiments described herein. The conversion stage 400 generally corresponds to Figure 3B 354 of the CML to CMOS conversion stage.

[0038] The CML input signal 352 is received at the differential input terminals 402A, 402B. Differential signals 405, 405N corresponding to the CML input signal 352 are passed through the termination circuit system 410 before being received at the differential amplifier stage 415. For example, according to CML requirements, the termination circuit system 410 may include a 50 Ohm (Ω) resistor for each differential input terminal 402 and a reference voltage (e.g., V DD ) pull-up resistor. Figure 5A An example of terminal circuitry 410 is provided in .

[0039] Differential signals 405N and 405P are received and amplified at differential amplifier stage 415. Output signals 420N and 420P from differential amplifier stage 415 are provided to first inverter amplifier stage 425. In one embodiment, inverter amplifier stage 425 includes one or more TIAs. In one embodiment, inverter amplifier stage 425 includes one TIA applied to each output signal 420N and 420P. The outputs of first inverter amplifier stage 425 are signals 430N and 430P. Each of signals 430N and 430P is provided to a common-mode feedback stage 435 and a linked and cross-coupled inverter amplifier stage 445. Based on signals 430N and 430P, common-mode feedback stage 435 outputs a control signal 440 to differential amplifier stage 415. Control signal 440 is used to control the bias of inverter amplifier stage 425 by modifying the properties of output signals 420N and 420P.

[0040] The linked and cross-coupled inverter amplifier stage 445 includes one or more stages of coupled inverters, including cross-coupled inverters. Output signals 450N, 450P from the linked and cross-coupled inverter amplifier stage 445 are provided to output terminals 452P, 452N and are collectively referred to as output signal 450. In one embodiment, the output signal 450 from the conversion stage 400 is a rail-to-rail complementary CMOS signal with an output range suitable for driving the CMOS-based modulator 121.

[0041] Figure 5A and Figure 5B A schematic diagram of an input stage 181 of a driver 180 is provided in accordance with an embodiment of the present disclosure. Figure 5A A first portion of the input stage 181 is shown, corresponding generally to the through-termination circuitry 410 . Figure 5B Generally corresponds to the differential amplifier stage 415 , the inverter amplifier stage 425 , and the common mode feedback stage 435 provided to the first inverter amplifier stage 425 .

[0042] Figure 5A An embodiment of a through-terminal circuitry is shown as it may be used in the terminal circuitry 410. The through-terminal circuitry of the terminal circuitry 410 receives the differential signals 405P, 405N and carries the differential output signals 405P, 405N on two arms to terminals A and B and then to the circuitry of the differential amplifier stage 415 (an example of which is shown in FIG. Figure 5B shown in ).

[0043] The through-termination circuitry 410 includes three sets of electrostatic discharge (ESD) protectors 540A-F (generally, ESD protectors 540) on each arm, the ESD protectors 540 including a first diode 541 connected from ground to the arm and a second diode 542 connected from the arm to a reference voltage (e.g., V DD )'s second diode 542.

[0044] Each arm includes an inductive through-voltage divider (e.g., a T-coil structure) comprising a first inductor 550A, 550B connected in series / coupled with a second inductor 555A, 555B, and a through-bridge capacitor 560A, 560B connected in parallel to the inductor. The first inductor 550A, 550B is connected to a first node 501A, 501B and a second node 502A, 502B, respectively, and the second inductor 555A, 555B is connected to a second node 502A, 502B and a third node 503A, 503B, respectively. The through-bridge capacitor 560A, 560B is connected at the first node 501A, 501B and the third node 503A, 503B, respectively.

[0045] Each arm runs from a second node 502A, 502B to a first node 501A, 501B. A resistive voltage divider comprising a first voltage dividing resistor 565A and a second voltage dividing resistor 565B links the first arm with the second arm between third nodes 503A, 503B. In various embodiments, the first voltage dividing resistor 565A and the second voltage dividing resistor 565B have the same resistance, but different resistances may be used in other embodiments to define different ratios between the two arms, and one or more terminating resistors (not shown) may be added to each arm to reduce return reflections of the signals carried thereon.

[0046] The capacitance and inductance between the second ESD protector 504B and the third ESD protector 504C are Figure 5A 570A and inductor 575A. Similarly, the capacitance and inductance between the fifth ESD protector 504E and the sixth ESD protector 504F are shown in FIG. Figure 5A denoted as capacitor 570B and inductor 575B.

[0047] A resistive voltage divider including a first voltage divider resistor 580A and a second voltage divider resistor 580B links terminals A and B together after the third ESD protector 504C and the sixth ESD protector 504F. In various embodiments, the first voltage divider resistor 580A and the second voltage divider resistor 580B have the same resistance to define a reference voltage V midway between terminals A and B. CM In various embodiments, the common mode voltage V is generated by an independent generator (not shown). CM The resistors create a high impedance connection to nodes A and B to set the nodes to the generated V CM .

[0048] Now turn Figure 5BAt the circuitry providing differential amplifier stage 415, differential signals 405 and 405N from the circuitry of terminal circuitry 410 are received at terminals A and B, respectively. Differential amplifier stage 415 includes a differential amplifier comprising a first pair of MOS devices (i.e., transistors 510A and 510B; generally, first pair of MOS devices 510) having a first conductivity type (e.g., n-channel), wherein each of the first pair of MOS devices 510 is configured to receive one differential signal 405P or 405N with reference to a source 520. First pair of MOS devices 510 may also be generally referred to as a differential pair. Differential pairs generally provide some noise immunity and common-mode rejection, which results in increased input sensitivity suitable for low-voltage input signals. The differential amplifier also includes a second pair of MOS devices (i.e., transistors 515A and 515B; generally, second pair of MOS devices 515) having a different conductivity type (e.g., p-channel). Each of the second pair of MOS devices generally operates as a current source load for the corresponding MOS device in the first pair. For example, transistor 515A is coupled to transistor 510A, and transistor 515B is coupled to transistor 510B. Differential amplifier output signals 420P, 420N represent the common-mode output of the differential pair, which is provided at the respective drains of transistors 510A, 510B.

[0049] Output signals 420P and 420N are received at a first inverter amplifier stage 425. As shown, the first inverter amplifier stage 425 includes a first TIA coupled to one output of the differential amplifier and a second TIA coupled to the other output of the differential amplifier. Each TIA includes a corresponding inverter 530A, 530B and feedback resistors 531A, 531B. The first inverter amplifier stage 425 is generally configured to generate a second amplified signal (i.e., signals 430P, 430N) based on the first amplified signal (i.e., signals 420N, 420P). Because the input and output of each TIA are coupled via a corresponding feedback resistor 531, the input and common-mode output of the TIA can be controlled to have voltage values ​​close to the trip point of the corresponding inverter 530. In addition, the circuitry of the first inverter amplifier stage 425 may include a second inverter 532A, 532B in each signal path. Embodiments using an odd number of stages in the chained and cross-coupled inverter amplifier stage 445 (with respect to Figure 6 and Figure 7 As discussed in more detail), the second inverters 532A, 532B may be omitted.

[0050] although Figure 5B Not shown, each of the inverters 530, 532, 536 can use a shared drive voltage V DD To supply electricity.

[0051] In some embodiments, any voltage offset in the differential output signals 420N, 420P is mitigated by measuring the common-mode output at the output of the TIA and comparing the common-mode output to the trip point of the inverter amplifier. Feedback or control signal 440 based on the difference value can be provided to the current source load of the differential amplifier (i.e., transistors 515A, 515B) to adjust the common-mode output of the differential pair. The adjustment of the common-mode output of the differential pair by control signal 440 is propagated to the input of the TIA, which in turn adjusts the bias voltage of the TIA to follow the trip point of inverter 536. In some embodiments, the common-mode output of the TIA is selected to have a voltage value close to the trip point of the continuous inverter sequence (e.g., inverters 532A, 532B), which results in a large gain available at the continuous inverter, almost reaching the full rail-to-rail CMOS output level generated by the continuous inverter.

[0052] As shown, the common-mode feedback stage 435 includes resistors 535A, 535B, each coupled to the output of a corresponding TIA and to the input of an inverter 536. The trace carrying the control signal 440 may include one or more components for filtering or conditioning the control signal 440. For example, the output of the inverter 536 may have a phase difference with the voltage source V DD 536. In one embodiment, the (conditioned) control signal 440 is coupled to the gates of the p-channel transistors 515A, 515B. In one embodiment, the characteristics of the resistors 535A, 535B and / or the inverter 536 are selected to provide the desired control signal 440.

[0053] Depend on Figure 5B The signals 430N, 430P output by the arrangement shown in may be provided to the accumulation stage 182, for example, Figure 6 The accumulation level shown in . Figure 6 A schematic diagram of an accumulation stage 182 is shown, which includes a buffer 630 arranged in series on a first arm 610A and a second arm 610B. 1-n Chain. Figure 7 An exemplary schematic diagram of an individual buffer 630 is provided in .

[0054] exist Figure 6 In the embodiment, the first arm 610A receives the signal 430P, which is provided to the buffer 630. 1-n 's corresponding first arm stage, which outputs signal 450P to modulator 121. Figure 6 The second arm 610B receives the signal 430N, which is provided to the buffer 630 1-n The corresponding second arm stage outputs signal 450N to the modulator 121.

[0055] In various embodiments, the first arm 610A and the second arm 610B include respective ESD protectors 640A, 640B between the last buffer 630n and the modulator 121. Each of the ESD protectors 640A, 640B includes a first diode 641A, 641B connected from ground to the respective arm, and a first diode 641A, 641B connected from the respective arm to a reference voltage V DD The second diodes 642A, 642B.

[0056] Figure 7 A schematic diagram of individual buffers 630 is shown, where the first arm 610A travels through the first node 715, the second node 725, and the third node 735, and the second arm 610B travels through the fourth node 745, the fifth node 755, and the sixth node 765. Consecutive buffers 630 are connected such that the previous buffer 630 x The third node 735 is connected to the next buffer 630 x+1 The first node 715 and the previous buffer 630 x The sixth node is connected to the next buffer 630 x+1 Thus, any number of buffers 610 may be arranged in series in the arrangement 1-n .

[0057] The first inductor 710 is disposed between the first node 715 and the second node 725 , and the second inductor 720 is disposed between the fourth node 745 and the fifth node 755 , which increases the available bandwidth of the signal carried on the buffer 630 without consuming additional power.

[0058] A cross-coupled pair of inverters 770 and 780 is disposed between the second node 725 and the fifth node 755 to provide DC offset correction.The first cross-coupled inverter 770 and the second cross-coupled inverter 780 are oriented in opposite orientations to each other.

[0059] The first adjustable gain inverter 730 and the first fixed gain inverter 740 are arranged in parallel with each other between the second node 725 and the third node 735. Similarly, the second fixed gain inverter 750 and the second adjustable gain inverter 760 are arranged in parallel with each other between the fifth node 755 and the sixth node 765. In some embodiments, the rear buffer 630 in the accumulation stage 182 x+1 The gain of the adjustable gain inverter 730, 760 is higher than that of the first buffer 630. x The gains of the gain inverters 730 and 760 can be adjusted so that the strength of the signal gradually becomes stronger in the accumulation stage 182.

[0060] Each of the inverters 730, 740, 750, 760, 770, 780 has the same driving voltage V applied by the programmable regulator 170. DD . Driving voltage V DD The value of V and the gain programmed for the adjustable gain inverters 730, 760 are based on the operating characteristics of the modulator 121 being driven by the accumulation stage 182. DD , manufacturers can mitigate excessive peaking within specific process corners that can cause output optical blinding and damage transistors in modulator 121. Thus, the presently described driver 180 can drive signals for a wide range of modulators 121 at lower power consumption than comparable designs because the driver 180 is optimized for the individual drive strength of a specific modulator 121, rather than the slow-slow process corners across all driver / modulator pairs, as other drivers 180 are optimized for. This provides more consistent power consumption across all process corners, and does not consume additional power in typical or fast process corners.

[0061] Figure 8 8 is a flow chart of a method 800 for tuning the driver 180 of the modulator 121. The method 800 begins at block 810, where the processor 160 monitors the frequency of the ring oscillator 140 connected to the driver 180 to determine operating characteristics of the driver 180. In various embodiments, the operating characteristics include identifying the process corner (e.g., fast-fast, slow-slow, typical-typical) to which the driver 180 belongs.

[0062] At block 820, processor 160 configures voltage regulator 170 to provide reference voltage VDD at an appropriate voltage level to driver 180 based on the determined operating characteristics of driver 180. In various embodiments, voltage VDD serves as a driving voltage or reference voltage for various components in driver 180, including ESD protectors, inverters (amplification and cross-coupling), and transistors.

[0063] At block 830, the processor 160 sets the amplification strength of a plurality of tunable (i.e., adjustable gain) inverters included in the accumulation stage 182 of the driver 180. In various embodiments, each of the differential signals is carried on a separate arm of the driver, and the tunable inverters on each arm are individually tuned based on the operating characteristics of the driver 180 to which the given arm of the driver 180 is connected. The tunable inverters are arranged in parallel with pairs of non-tunable (i.e., fixed gain) inverters, and several pairs of inverters are arranged in series (with increasing strength) within the accumulation stage 182.

[0064] Method 800 may then end.

[0065] In the present disclosure, reference is made to various embodiments. However, the scope of the present disclosure is not limited to the specific embodiments described. On the contrary, any combination of the features and elements described, whether or not related to different embodiments, is contemplated to implement and practice the contemplated embodiments. In addition, when the elements of an embodiment are described in the form of "at least one of A and B", it should be understood that embodiments comprising only element A, only element B, and both elements A and B are contemplated. In addition, although some embodiments disclosed herein may achieve advantages over other possible solutions or over the prior art, whether a given embodiment achieves a particular advantage does not limit the scope of the present disclosure. Therefore, the various aspects, features, embodiments, and advantages are merely illustrative and are not considered elements or limitations of the appended claims, except as expressly set forth in the claim(s). Similarly, reference to the "present invention" should not be interpreted as a generalization of any inventive subject matter disclosed herein and should not be considered elements or limitations of the appended claims, except as expressly set forth in the claim(s).

[0066] The flowchart illustrations and block diagrams in the accompanying drawings illustrate the architecture, functionality and operation of possible implementations of the systems, methods and computer program products according to various embodiments. In this regard, each box in the flowchart illustration or block diagram can represent a module, segment, or code portion comprising one or more executable instructions for implementing a specified (one or more) logical function. It should also be noted that in some alternative embodiments, the functions mentioned in the box can appear in an order other than the order mentioned in the figure. For example, two boxes shown in succession can actually be executed roughly at the same time, or the boxes can sometimes be executed in the opposite order, depending on the functionality involved. It should also be noted that each box shown in the block diagram and / or flowchart and the combination of boxes in the block diagram and / or flowchart illustration can be implemented by a system based on special-purpose hardware that performs a specified function or action, or a combination of special-purpose hardware and computer instructions.

[0067] In view of the foregoing, the scope of the present disclosure is determined by the following claims.

Claims

1. A driver circuit comprising: A plurality of buffers arranged in series, wherein each of the plurality of buffers is configured to receive an input and produce an output, and wherein each of the plurality of buffers comprises: a first tunable inverter electrically connected to a first input node configured to receive a first input and a first output node configured to carry a first output; a first fixed inverter electrically connected in parallel to the first input node and the first output node together with the first tunable inverter; a second tunable inverter electrically connected to a second input node and a second output node, the second input node being configured to receive a second input and the second output node being configured to carry a second output; a second fixed inverter connected in parallel to the second input node and the second output node together with the second tunable inverter; a first cross-coupled inverter having an input connected to the first input node and an output connected to the second input node; and a second cross-coupled inverter connected in parallel with the first cross-coupled inverter and having an output connected to the first input node and an input connected to the second input node, The first tunable inverter of a subsequent buffer among the multiple buffers and the second tunable inverter of the subsequent buffer among the multiple buffers are tuned to have a greater gain than the first tunable inverter of a previous buffer among the multiple buffers and the second tunable inverter of the previous buffer among the multiple buffers.

2. The driver circuit according to claim 1, wherein The plurality of buffers are arranged such that a first output node of a preceding buffer among the plurality of buffers is electrically connected to a first input node of a succeeding buffer among the plurality of buffers via a first inductor, and such that a second output node of the preceding buffer among the plurality of buffers is electrically connected to a second input node of the succeeding buffer among the plurality of buffers via a second inductor.

3. The driver circuit according to claim 1 or 2, wherein: A last buffer of the plurality of buffers is connected to the optical modulator via the first arm and the second arm; wherein the first arm comprises a first electrostatic discharge protector; and Wherein, the second arm includes a second electrostatic discharge protector.

4. The driver circuit according to claim 1 or 2, further comprising an input stage configured to differentiate a differential input signal into a first data signal and a second data signal, the second data signal being a logical complement of the first data signal.

5. The driver circuit according to claim 1 or 2, wherein: The first tunable inverter and the second tunable inverter are tuned for the identified process corner of the driver circuit.

6. A method for tuning a modulator driver, comprising: monitoring a frequency of a ring oscillator of an electrical integrated circuit coupled to the optical modulator to determine an operational characteristic of the electrical integrated circuit; as well as setting amplification strengths of the plurality of tunable inverters based on the operating characteristics, Wherein, when the plurality of tunable inverters are arranged in a chain, the amplification strength of the plurality of tunable inverters is set to apply stronger amplification to a subsequent tunable inverter among the plurality of tunable inverters relative to a previous tunable inverter among the plurality of tunable inverters.

7. The method according to claim 6, further comprising: setting drive voltages for a plurality of tunable inverters and a plurality of fixed-gain inverters based on the operating characteristics, the plurality of tunable inverters and the plurality of fixed-gain inverters controlling the optical modulator, wherein each of the plurality of tunable inverters is connected in parallel with a corresponding one of the plurality of fixed-gain inverters on first and second arms connected to the optical modulator; and The driving voltage is set for a plurality of cross-coupled inverters, wherein each pair of cross-coupled inverters is connected in parallel to the first arm and the second arm.

8. The method according to claim 6 or 7, wherein: The operating characteristics indicate a process corner of an electrical driver to which the plurality of tunable inverters and the plurality of fixed-gain inverters belong.

9. An electrical integrated circuit comprising: a frequency comparator connected to the ring oscillator and an external reference clock signal, the frequency comparator configured to determine an operational characteristic of an electrical circuit connected to the optical modulator based on a frequency difference between the ring oscillator and the external reference clock signal; an electrical driver connected to the optical modulator and configured to drive a phase shift of a first optical signal carried on a first arm of the optical modulator relative to a second optical signal carried on a second arm of the optical modulator, the electrical driver comprising: a first signal path connected to the first arm of the optical modulator, wherein the first signal path comprises: a first inductor electrically connected to a first node on the first signal path and a second node on the first signal path; a first tunable gain inverter electrically connected to the second node on the first signal path and a third node on the first signal path; and a first fixed gain inverter electrically connected to the second node and the third node, Wherein, the first signal path further includes: a third inductor electrically connected to a seventh node on the first signal path and an eighth node on the first signal path; a third tunable gain inverter electrically connected to the eighth and ninth nodes on the first signal path; and a third fixed-gain inverter electrically connected to the seventh node and the eighth node; and The first gain of the first tunable gain inverter and the third gain of the third tunable gain inverter are set based on the operating characteristics, and the third gain is greater than the first gain.

10. The electrical integrated circuit of claim 9, further comprising: a second signal path connected to a second node of the second arm of the optical modulator, wherein the second signal path comprises: a second inductor electrically connected to a fourth node and a fifth node on the second signal path; a second tunable gain inverter electrically connected to the fifth node on the second signal path and a sixth node on the second signal path; and A second fixed-gain inverter is electrically connected to the fifth node and the sixth node.

11. The electrical integrated circuit according to claim 10, wherein: A first gain of the first tunable gain inverter and a second gain of the second tunable gain inverter are set based on the operating characteristic.

12. An electrical integrated circuit according to claim 10 or 11, wherein: The first signal path carries a first signal to the first arm of the optical modulator, and the second signal path carries a logic complement of the first signal to the second arm of the optical modulator.

13. The electrical integrated circuit of claim 12, wherein: The first signal is applied to a first capacitive connection of the first arm of the optical modulator, and the logic complement is applied to a first capacitive connection of the second arm of the optical modulator, wherein a second capacitive connection of the first arm and a second capacitive connection of the second arm are maintained at a constant voltage.

14. The electrical integrated circuit according to claim 10 or 11, further comprising: A cross-coupling element, the cross-coupling element comprising: a first coupled inverter having a first input electrically connected to the second node and a first output electrically connected to the fifth node; and A second coupled inverter has a second output terminal electrically connected to the second node and a second input terminal electrically connected to the fifth node.

15. The electrical integrated circuit of claim 14, further comprising: a voltage regulator configured to generate a driving voltage, the driving voltage being set based on the operating characteristic and configured to apply the driving voltage to the first tunable gain inverter, the second tunable gain inverter, the first fixed gain inverter, the second fixed gain inverter, the first coupled inverter, and the second coupled inverter.

16. An electrical integrated circuit according to any one of claims 9 to 11, wherein The first signal path further comprises: An electrostatic discharge protector is attached between the third node and the optical modulator.

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