Memory wear management

Abstract

The present application relates to memory wear management. A device may include an interface controller and a non-volatile memory. The interface controller may manage a wear leveling procedure for a memory bank in the non-volatile memory. For example, the interface controller may select a row in a memory bank for the wear leveling procedure. The interface controller may store data from the row in a buffer in the interface controller. The interface controller may then pass the data to the non-volatile memory so that the non-volatile memory may write the data to a second row of the memory bank.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 050,283, entitled “MEMORY WEAR MANAGEMENT,” filed by Malik et al. on July 10, 2020, which is assigned to the assignee of this application and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to memory wear management. Background Art

[0004] The following relates generally to one or more memory systems and, more particularly, to memory wear management in the system.

[0005] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, usually represented by a logical 1 or a logical 0. In some instances, a single memory cell can support more than two states, any of which can be stored. In order to access the stored information, a component can read or read out at least one storage state in the memory device. In order to store information, a component can write or program a state in the memory device.

[0006] There are various types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selected memory, chalcogenide memory technology, etc. Memory cells can be volatile or non-volatile. Non-volatile memory such as FeRAM can maintain its stored logic state for an extended period of time even in the absence of external power. Volatile memory devices such as DRAM may lose their stored state when disconnected from the external power supply. Summary of the invention

[0007] An apparatus is described. The apparatus may include: a nonvolatile memory, the nonvolatile memory including a memory bank; and an interface controller coupled to the nonvolatile memory. The interface controller may be operable to cause the apparatus to: select a physical row address in the memory bank for a procedure to move data from a first row of the memory bank to a second row of the memory bank; determine to initiate the procedure for the first row of the memory bank based at least in part on the physical row address, wherein the physical row address is associated with the first row; and as part of the procedure, issue a read command to the nonvolatile memory for the physical row address associated with the first row.

[0008] An apparatus is described. The apparatus may include: a non-volatile memory, the non-volatile memory including a plurality of memory banks; and an interface controller coupled to the non-volatile memory. The interface controller may include: a first logic component configured to manage a program that moves data between rows of memory banks in the non-volatile memory; a register coupled to the first logic component and configured to store one or more pointers associated with the rows of the memory banks; and a second logic component coupled to the register and configured to determine a physical row address based at least in part on the one or more pointers stored in the register.

[0009] An apparatus is described. The apparatus may include: a nonvolatile memory including a memory bank; and an interface controller coupled to the nonvolatile memory. The interface controller may be operable to cause the apparatus to: determine a first physical row address of a first row of the memory bank storing data to be transferred to a second row of the memory bank; transfer a read command for the first physical row address to the nonvolatile memory; transfer the data to a register in the interface controller based at least in part on transmitting the read command; and transfer the data from the register to the nonvolatile memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 An example of a system supporting memory wear management according to examples as disclosed herein is presented.

[0011] Figure 2 An example of a memory subsystem supporting memory wear management according to examples as disclosed herein is presented.

[0012] Figure 3 An example of a device supporting memory wear management according to examples as disclosed herein is presented.

[0013] Figure 4 An example of a process flow supporting memory wear management according to examples as disclosed herein is presented.

[0014] Figure 5 An example of a timing diagram supporting memory wear management according to examples as disclosed herein is shown.

[0015] Figure 6 A block diagram of a device supporting memory wear management according to aspects of the present disclosure is shown.

[0016] Figure 7 and 8 A flow chart illustrating one or more methods of supporting memory wear management according to examples as disclosed herein is shown. DETAILED DESCRIPTION

[0017] Devices such as electronic devices may include a main memory (e.g., a main memory used to store information during other operations) and an auxiliary memory that may operate as a cache. Such a configuration may allow the device to benefit from the advantages of non-volatile memory (e.g., non-volatility, high storage capacity, low power consumption) while maintaining compatibility with a host device. However, repeated access to memory cells in a non-volatile memory may wear out the non-volatile memory cells and reduce the durability of the non-volatile memory cells (e.g., by modifying various characteristics of the memory cells in a manner that impairs functionality). In order to maintain the durability of the non-volatile memory, the device may perform a wear leveling procedure that moves data between various locations in the non-volatile memory, such as rows of a library, which may prevent memory cells at a given address from being over-accessed. However, during the wear leveling procedure for a row, other rows in the library may not be accessible, which may delay satisfying a host device's request for data from the library.

[0018] According to the techniques described herein, a device can continue to service data requests for a library during a wear leveling procedure by managing the wear leveling procedure at an interface controller, which can allow the device to access rows in the library other than the rows undergoing the wear leveling procedure. For example, the interface controller can implement the wear leveling procedure in two phases: a read phase and a write phase. During the read phase, data in the first row of the library can be read and temporarily stored in a buffer of the interface controller; and during the write phase, data can be transferred from the buffer to a non-volatile memory and stored in the second row of the library. Because the read phase and the write phase can be separable (e.g., can be performed discontinuously), the rows involved in the wear leveling procedure can be closed between the read phase and the write phase, so that one or more other rows in the library can be accessed. This means that the device can service data requests for the library during the wear leveling procedure, which can improve system performance in addition to other benefits.

[0019] Originally in reference Figure 1 and 2 Features of the present disclosure are described in the context of the memory systems and subsystems described. Figure 3 The device described, as referenced Figure 4 The process flow described and as referenced Figure 5 The features of the present disclosure are described in the context of the timing diagrams described. These and other features of the present disclosure are described in conjunction with reference to Figure 6-8 The described memory wear management related apparatus diagrams and flow charts are further illustrated and described with reference thereto.

[0020] Figure 1 An example of a memory system 100 supporting cache management in a memory subsystem according to examples as disclosed herein is shown. The memory system 100 may be included in an electronic device such as a computer or a phone. The memory system 100 may include a host device 105 and a memory subsystem 110. The host device 105 may be a processor or a system on a chip (SoC) that interfaces with an interface controller 115 and other components of the electronic device including the memory system 100. The memory subsystem 110 may store electronic information (e.g., digital information, data) for the host device 105 and provide access to the electronic information. The memory subsystem 110 may include an interface controller 115, a volatile memory 120, and a non-volatile memory 125. In some examples, the interface controller 115, the volatile memory 120, and the non-volatile memory 125 may be included in the same physical package such as package 130. However, the interface controller 115, the volatile memory 120, and the non-volatile memory 125 may be disposed on different respective dies (e.g., silicon dies).

[0021] The devices in the memory system 100 may be coupled via various conductive lines (e.g., traces, printed circuit board (PCB) wiring, redistribution layer (RDL) wiring) that may enable information (e.g., commands, addresses, data) to be transferred between the devices. The conductive lines may constitute a channel, a data bus, a command bus, an address bus, etc.

[0022] The memory subsystem 110 may be configured to provide the benefits of the non-volatile memory 125 while maintaining compatibility with the host device 105, which supports protocols for different types of memory, such as the volatile memory 120, as well as other examples. For example, the non-volatile memory 125 may provide benefits such as non-volatility, higher capacity, or lower power consumption (e.g., relative to the volatile memory 120). However, the host device 105 may be incompatible with or inefficiently configured for various aspects of the non-volatile memory 125. For example, the host device 105 may support voltages, access latencies, protocols, page sizes, etc. that are incompatible with the non-volatile memory 125. To compensate for the incompatibility between the host device 105 and the non-volatile memory 125, the memory subsystem 110 may be configured with a volatile memory 120 that may be compatible with the host device 105 and used as a cache for the non-volatile memory 125. Thus, the host device 105 may use a protocol supported by the volatile memory 120 while benefiting from the advantages of the non-volatile memory 125 .

[0023] In some instances, the memory system 100 may be included in or coupled to a computing device, an electronic device, a mobile computing device, or a wireless device. The device may be a portable electronic device. For example, the device may be a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet connection device, etc. In some instances, the device may be configured to perform two-way wireless communication through a base station or an access point. In some instances, the device associated with the memory system 100 may be capable of machine type communication (MTC), machine to machine communication (M2M), or device to device (D2D) communication. In some instances, the device associated with the memory system 100 may be referred to as a user equipment (UE), a station (STA), a mobile terminal, etc.

[0024] The host device 105 may be configured to interface with the memory subsystem 110 using a first protocol (e.g., low power double data rate (LPDDR)) supported by the interface controller 115. Thus, in some instances, the host device 105 may interface directly with the interface controller 115 and indirectly with the non-volatile memory 125 and the volatile memory 120. In alternative instances, the host device 105 may interface directly with the non-volatile memory 125 and the volatile memory 120. The host device 105 may also interface with other components of the electronic device comprising the memory system 100. The host device 105 may be or include a SoC, a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or the host device may be a combination of these types of components. In some instances, the host device 105 may be referred to as a host.

[0025] The interface controller 115 may be configured to interface with the volatile memory 120 and the non-volatile memory 125 on behalf of the host device 105 (e.g., based on one or more commands or requests issued by the host device 105). For example, the interface controller 115 may facilitate the retrieval and storage of data in the volatile memory 120 and the non-volatile memory 125 on behalf of the host device 105. Thus, the interface controller 115 may facilitate the transfer of data between various subcomponents, such as between at least some of the host device 105, the volatile memory 120, or the non-volatile memory 125. The interface controller 115 may interface with the host device 105 and the volatile memory 120 using a first protocol and may interface with the non-volatile memory 125 using a second protocol supported by the non-volatile memory 125.

[0026] The non-volatile memory 125 may be configured to store digital information (e.g., data) for an electronic device including the memory system 100. Thus, the non-volatile memory 125 may include one or more memory cell arrays and a local memory controller configured to operate the one or more memory cell arrays. In some instances, the memory cells may be or include FeRAM cells (e.g., the non-volatile memory 125 may be FeRAM). The non-volatile memory 125 may be configured to interface with the interface controller 115 using a second protocol different from the first protocol used between the interface controller 115 and the host device 105. In some instances, the latency of the non-volatile memory 125 for access operations may be longer than that of the volatile memory 120. For example, retrieving data from the non-volatile memory 125 may take longer than retrieving data from the volatile memory 120. Similarly, writing data to the non-volatile memory 125 may take longer than writing data to the volatile memory 120. In some examples, the page size of non-volatile memory 125 may be smaller than that of volatile memory 120 , as described herein.

[0027] The volatile memory 120 may be configured to operate as a cache for one or more components such as the non-volatile memory 125. For example, the volatile memory 120 may store information (e.g., data) for an electronic device that includes the memory system 100. Thus, the volatile memory 120 may include one or more memory cell arrays and a local memory controller configured to operate the one or more memory cell arrays. In some examples, the memory cells may be or include DRAM cells (e.g., the volatile memory may be DRAM). The non-volatile memory 125 may be configured to interface with the interface controller 115 using a first protocol used between the interface controller 115 and the host device 105.

[0028] In some examples, the latency of volatile memory 120 for access operations may be shorter than that of nonvolatile memory 125. For example, retrieving data from volatile memory 120 may take less time than retrieving data from nonvolatile memory 125. Similarly, writing data to volatile memory 120 may take less time than writing data to nonvolatile memory 125. In some examples, the page size of volatile memory 120 may be larger than that of nonvolatile memory 125. For example, the page size of volatile memory 120 may be 2 kilobytes (2kB), and the page size of nonvolatile memory 125 may be 64 bytes (64B) or 128 bytes (128B).

[0029] Although the non-volatile memory 125 may be a higher density memory than the volatile memory 120, accessing the non-volatile memory 125 may take longer than accessing the volatile memory 120 (e.g., due to different architectures and protocols, among other reasons). Therefore, operating the volatile memory 120 as a cache may reduce latency in the memory system 100. As an example, a host device 105 access request for data may be satisfied relatively quickly by retrieving the data from the volatile memory 120 rather than from the non-volatile memory 125. To facilitate the operation of the volatile memory 120 as a cache, the interface controller 115 may include a plurality of buffers 135. The buffers 135 may be disposed on the same die as the interface controller 115 and may be configured to temporarily store data for transfer between the volatile memory 120, the non-volatile memory 125, or the host device 105 (or any combination thereof) during one or more access operations (e.g., storage operations and retrieval operations).

[0030] An access operation may also be referred to as an access process or an access procedure and may involve one or more sub-operations performed by one or more of the components of the memory subsystem 110. Examples of access operations may include storage operations in which data provided by the host device 105 is stored in (e.g., written to) the volatile memory 120 or the non-volatile memory 125 (or both), and retrieval operations in which data requested by the host device 105 is obtained (e.g., read) from the volatile memory 120 or the non-volatile memory 125 and returned to the host device 105.

[0031] To store data in the memory subsystem 110, the host device 105 may initiate a storage operation (or "storage process") by transmitting a storage command (also referred to as a storage request, a write command, or a write request) to the interface controller 115. The storage command may target a set of nonvolatile memory cells in the nonvolatile memory 125. In some instances, the set of memory cells may also be referred to as a portion of a memory. The host device 105 may also provide data to be written to the set of nonvolatile memory cells to the interface controller 115. The interface controller 115 may temporarily store the data in a buffer 135-a. After storing the data in the buffer 135-a, the interface controller 115 may transfer the data from the buffer 135-a to the volatile memory 120 or the nonvolatile memory 125, or both. In a write-through mode, the interface controller 115 may transfer the data to both the volatile memory 120 and the nonvolatile memory 125. In a write-back mode, the interface controller 115 may transfer the data only to the volatile memory 120.

[0032] In either mode, the interface controller 115 may identify an appropriate set of one or more volatile memory cells in the volatile memory 120 for storing data associated with the storage command. To this end, the interface controller 115 may implement a set-associative mapping, in which each set (e.g., a block) of one or more nonvolatile memory cells in the nonvolatile memory 125 may be mapped to multiple sets of volatile memory cells in the volatile memory 120. For example, the interface controller 115 may implement an n-way associative mapping that allows data from a set of nonvolatile memory cells to be stored in one of n sets of volatile memory cells in the volatile memory 120. Thus, the interface controller 115 may manage the volatile memory 120 as a cache of the nonvolatile memory 125 by referencing the n sets of volatile memory cells associated with the target set of nonvolatile memory cells. As used herein, unless otherwise described or indicated, an object "set" may refer to one or more of the objects. Although described with reference to set associative mapping, interface controller 115 may manage volatile memory 120 as a cache by implementing one or more other types of mapping, such as direct mapping or associative mapping, among other examples.

[0033] After determining which set of n volatile memory cells are associated with the target set of non-volatile memory cells, the interface controller 115 may store the data in one or more volatile memory cells in the set of n volatile memory cells. In this way, subsequent retrieval commands of the host device 105 for data may be efficiently satisfied by retrieving the data from the lower latency volatile memory 120 rather than retrieving the data from the higher latency non-volatile memory 125. The interface controller 115 may determine which set of n volatile memory 120 to store the data based on one or more parameters associated with the data stored in the set of n volatile memory 120, such as the validity, age, or modification status of the data. Thus, a storage command of the host device 105 may be satisfied in whole (e.g., in write-back mode) or in part (e.g., in write-through mode) by storing the data in the volatile memory 120. To track data stored in volatile memory 120, interface controller 115 may store, for one or more sets of volatile memory cells (eg, for each set of volatile memory cells), tag addresses indicating nonvolatile memory cells having data stored in a given set of volatile memory cells.

[0034] To retrieve data from the memory subsystem 110, the host device 105 may initiate a retrieval operation (also referred to as a retrieval process) by transmitting a retrieval command (also referred to as a retrieval request, a read command, or a read request) to the interface controller 115. The retrieval command may target a set of one or more non-volatile memory cells in the non-volatile memory 125. Upon receiving the retrieval command, the interface controller 115 may check the volatile memory 120 for the requested data. For example, the interface controller 115 may check the requested data in n sets of volatile memory cells associated with the target set of non-volatile memory cells. If one of the n sets of volatile memory cells stores the requested data (e.g., stores data for the target set of non-volatile memory cells), the interface controller 115 may transfer the data from the volatile memory 120 to the buffer 135-a (e.g., in response to determining that one of the n sets of volatile memory cells stores the requested data) so that the data can be transmitted to the host device 105. The term "hit" may be used to refer to a scenario in which the volatile memory 120 stores the data requested by the host device 105. If the n sets of one or more volatile memory cells do not store the requested data (e.g., the n sets of volatile memory cells store data for a set of non-volatile memory cells but not a target set of non-volatile memory cells), the interface controller 115 may pass the requested data from the volatile memory 125 to the buffer 135-a (e.g., in response to determining that the n sets of volatile memory cells do not store the requested data) so that the data can be transmitted to the host device 105. The term "miss" may be used to refer to a scenario in which the volatile memory 120 does not store the data requested by the host device 105.

[0035] In a miss scenario, after passing the requested data to the buffer 135-a, the interface controller 115 may pass the requested data from the buffer 135-a to the volatile memory 120 so that a subsequent read request for the data may be satisfied by the volatile memory 120 instead of the non-volatile memory 125. For example, the interface controller 115 may store the data in one of the n volatile memory cell sets associated with the non-volatile memory cell target set. However, the n volatile memory cell sets may already be storing data for other non-volatile memory cell sets. Therefore, in order to save this other data, the interface controller 115 may pass the other data to the buffer 135-b so that the data may be passed to the non-volatile memory 125 for storage. Such a process may be referred to as "eviction", and the data passed from the volatile memory 120 to the buffer 135-b may be referred to as "victim" data. In some cases, the interface controller 115 may pass a subset of the victim data from the buffer 135-b to the non-volatile memory 125. For example, the interface controller 115 may communicate one or more subsets of the victim data that have changed since the data was initially stored in the non-volatile memory 125. In some cases, data that is inconsistent between the volatile memory 120 and the non-volatile memory 125 (e.g., due to updates in one memory but not the other) may be referred to as “modified” or “dirty” data. In some instances (e.g., when the interface controller is operating in a mode such as a write-back mode), dirty data may be data that is present in the volatile memory 120 but not in the non-volatile memory 125.

[0036] In some examples, the memory subsystem 110 may perform a wear leveling procedure on the nonvolatile memory 125 to maintain the endurance of the nonvolatile memory 125, among other benefits. The wear leveling procedure may shift data along the rows of the nonvolatile memory so that repeated requests for data (e.g., row hammer (RH) attacks) do not result in repeated accesses to the same memory cells, which may wear out the nonvolatile memory cells and reduce their reliability. In some examples, the memory interface controller 115 may initiate the wear leveling procedure by sending a memory management (MM) command to the nonvolatile memory 125. The memory management command may cause the nonvolatile memory 125 to move data from a first row of a memory bank in the nonvolatile memory 125 to a second row of a memory bank. However, during this time, other rows of the memory bank may not be accessible, which means that function commands for the data (e.g., those originating at the host device 105) cannot be serviced until the wear leveling procedure is completed. As a result, the latency of the system 100 may increase, which may negatively impact the performance of the system 100.

[0037] According to the techniques described herein, the interface controller 115 can manage a wear leveling procedure for a memory bank so that functional commands for data in the memory bank can be serviced during the wear leveling procedure. The interface controller 115 can implement a wear leveling procedure for the memory bank by executing the wear leveling procedure in multiple stages, which can allow the non-volatile memory 125 to service functional commands for the data between stages. For example, the interface controller 115 can complete a read phase of the wear leveling procedure, service a certain number of one or more functional commands for the data, and then complete a write phase of the wear leveling procedure. Therefore, the latency of the system 100 can be reduced by servicing data requests during the wear leveling procedure, which can improve the performance of the system 100.

[0038] Figure 2 An example of a memory system 200 supporting cache management in a memory subsystem according to an example as disclosed herein is shown. The memory subsystem 200 may be a reference Figure 1 Thus, the memory subsystem 200 may be configured as described with reference to Figure 1 The memory subsystem 200 may include an interface controller 202, a volatile memory 204, and a non-volatile memory 206. The interface controller, the volatile memory, and the non-volatile memory may be respectively as described in reference Figure 1 The examples of the interface controller 115, the volatile memory 120 and the non-volatile memory 125 described above are shown in FIG. 1 . Thus, the interface controller 202 may be as described with reference to FIG. Figure 1 The depicted representative host device interfaces with the volatile memory 204 and the non-volatile memory 206. For example, the interface controller 202 can operate the volatile memory 204 as a cache for the non-volatile memory 206. Operating the volatile memory 204 as a cache can allow the subsystem to provide the benefits of the non-volatile memory 206 (e.g., non-volatility, high density storage) while maintaining compatibility with host devices that support a different protocol than the non-volatile memory 206.

[0039] exist Figure 2 In the figure, the dashed lines between components represent data flow or data communication paths, and the solid lines between components represent command flow or command communication paths. In some cases, memory subsystem 200 is one of multiple similar or identical subsystems that can be included in an electronic device. In some instances, each subsystem can be referred to as a slice and can be associated with a corresponding channel of a host device.

[0040] The non-volatile memory 206 may be configured to operate as a main memory (e.g., a memory for long-term data storage) of a host device. In some cases, the non-volatile memory 206 may include one or more FeRAM cell arrays. Each FeRAM cell may include a selection component and a ferroelectric capacitor and may be accessed by applying an appropriate voltage to one or more access lines such as a word line, a plate line, and a digit line. In some instances, a subset of FeRAM cells coupled to an activated word line may be read out, for example, in parallel or simultaneously, without having to read out all FeRAM cells coupled to the activated word line. Therefore, the page size of the FeRAM array may be different from (e.g., smaller than) the DRAM page size. In the context of a memory device, a page may refer to a memory cell in a row (e.g., a group of memory cells having a common row address), and a page size may refer to the number of memory cells or column addresses in a row or the number of column addresses accessed during an access operation. Alternatively, a page size may refer to the size of data processed by various interfaces. In some cases, different memory device types may have different page sizes. For example, a DRAM page size (eg, 2 kB) may be a superset of a non-volatile memory (eg, FeRAM) page size (eg, 64B).

[0041] A smaller page size of a FeRAM array can provide various efficiency benefits because an individual FeRAM cell may require more power to read or write than an individual DRAM cell. For example, a smaller page size of a FeRAM array can promote efficient energy usage because a smaller number of FeRAM cells can be activated when the associated information changes less. In some examples, the page size of the FeRAM cell array can be changed, for example, dynamically (e.g., during operation of the FeRAM cell array) depending on the nature of the data and commands operated with the FeRAM.

[0042] Although an individual FeRAM cell may require more power to read or write than an individual DRAM cell, a FeRAM cell can maintain its stored logic state for an extended period of time in the absence of an external power source because the ferroelectric material in the FeRAM cell can maintain a non-zero electric polarization in the absence of an electric field. Therefore, including a FeRAM array in non-volatile memory 206 can provide efficiency benefits relative to volatile memory cells (e.g., DRAM cells in volatile memory 204) because it can reduce or eliminate the requirement to perform refresh operations.

[0043] The volatile memory 204 may be configured to operate as a cache for the non-volatile memory 206. In some cases, the volatile memory 204 may include one or more DRAM cell arrays. Each DRAM cell may include a capacitor including a dielectric material for storing a charge representing a programmable state. The memory cells of the volatile memory 204 may be logically grouped or arranged into one or more memory banks (referred to herein as "banks"). For example, the volatile memory 204 may include sixteen banks. The memory cells in the bank may be arranged in a grid or an array of crossed columns and rows, and each memory cell may be accessed or refreshed by applying appropriate voltages to the digit lines (e.g., column lines) and word lines (e.g., row lines) for the memory cells. The rows of the bank may be referred to as pages, and the page size may refer to the number of columns or memory cells in the row. As noted, the page size of the volatile memory 204 may be different from (e.g., greater than) the page size of the non-volatile memory 206.

[0044] The interface controller 202 may include various circuits for interfacing (e.g., communicating) with other devices such as a host device, a volatile memory 204, and a non-volatile memory 206. For example, the interface controller 202 may include a data (DA) bus interface 208, a command and address (C / A) bus interface 210, a data bus interface 212, a C / A bus interface 214, a data bus interface 216, and a C / A bus interface 264. The data bus interfaces may support information transfer using one or more communication protocols. For example, the data bus interface 208, the C / A bus interface 210, the data bus interface 216, and the C / A bus interface 264 may support information transferred using a first protocol (e.g., LPDDR signaling), while the data bus interface 212 and the C / A bus interface 214 may support information transferred using a second protocol. Therefore, the various bus interfaces coupled to the interface controller 202 may support different amounts of data or data rates.

[0045] The data bus interface 208 may be coupled to the data bus 260, the transaction bus 222, and the buffer circuit system 224. The data bus interface 208 may be configured to transmit and receive data through the data bus 260 and to transmit and receive control information (e.g., confirmation / negative confirmation) or metadata through the transaction bus 222. The data bus interface 208 may also be configured to transfer data between the data bus 260 and the buffer circuit system 224. The data bus 260 and the transaction bus 222 may be coupled to the interface controller 202 and the host device so that a conductive path is established between the interface controller 202 and the host device. In some instances, the pins of the transaction bus 222 may be referred to as data mask inversion (DMI) pins. Although one data bus 260 and one transaction bus 222 are shown, any number of data buses 260 and any number of transaction buses 222 coupled to one or more data bus interfaces 208 may exist.

[0046] The C / A bus interface 210 may be coupled to the C / A bus 226 and the decoder 228. The C / A bus interface 210 may be configured to transmit and receive commands and addresses via the C / A bus 226. The commands and addresses received via the C / A bus 226 may be associated with data received or transmitted via the data bus 260. The C / A bus interface 210 may also be configured to transmit the commands and addresses to the decoder 228 so that the decoder 228 may decode the commands and relay the decoded commands and associated addresses to the command circuitry 230.

[0047] The data bus interface 212 may be coupled to the data bus 232 and the memory interface circuitry 234. The data bus interface 212 may be configured to transmit and receive data over the data bus 232, which may be coupled to the non-volatile memory 206. The data bus interface 212 may also be configured to pass data between the data bus 232 and the memory interface circuitry 234. The C / A bus interface 214 may be coupled to the C / A bus 236 and the memory interface circuitry 234. The C / A bus interface 214 may be configured to receive commands and addresses from the memory interface circuitry 234 and relay the commands and addresses to the non-volatile memory 206 (e.g., to a local controller of the non-volatile memory 206) over the C / A bus 236. The commands and addresses transmitted over the C / A bus 236 may be associated with the data received or transmitted over the data bus 232. The data bus 232 and the C / A bus 236 may be coupled to the interface controller 202 and the nonvolatile memory 206 such that a conductive path is established between the interface controller 202 and the nonvolatile memory 206 .

[0048] The data bus interface 216 may be coupled to the data bus 238 and the memory interface circuitry 240. The data bus interface 216 may be configured to transmit and receive data over the data bus 238, which may be coupled to the volatile memory 204. The data bus interface 216 may also be configured to pass data between the data bus 238 and the memory interface circuitry 240. The C / A bus interface 264 may be coupled to the C / A bus 242 and the memory interface circuitry 240. The C / A bus interface 264 may be configured to receive commands and addresses from the memory interface circuitry 240 and relay the commands and addresses to the volatile memory 204 (e.g., to a local controller of the volatile memory 204) over the C / A bus 242. The commands and addresses transmitted over the C / A bus 242 may be associated with the data received or transmitted over the data bus 238. The data bus 238 and the C / A bus 242 may be coupled to the interface controller 202 and the volatile memory 204 such that a conductive path is established between the interface controller 202 and the volatile memory 204 .

[0049] In addition to the bus and bus interface for communicating with the coupled devices, the interface controller 202 may also include circuitry for operating the non-volatile memory 206 as a main memory and the volatile memory 204 as a cache. For example, the interface controller 202 may include command circuitry 230, buffer circuitry 224, cache management circuitry 244, one or more engines 246, and one or more schedulers 248.

[0050] Command circuitry 230 may be coupled to buffer circuitry 224, decoder 228, cache management circuitry 244, and scheduler 248, among other components. Command circuitry 230 may be configured to receive command and address information from decoder 228 and store the command and address information in queue 250. Command circuitry 230 may include logic 262 that processes command information (e.g., from a host device) and stored information from other components (e.g., cache management circuitry 244, buffer circuitry 224) and uses the information to generate one or more commands for scheduler 248. Command circuitry 230 may also be configured to pass address information (e.g., address bits) to cache management circuitry 244. In some examples, logic 262 may be a circuit configured to operate as a finite state machine (FSM).

[0051] Buffer circuit system 224 can be coupled to data bus interface 208, command circuit system 230, memory interface circuit system 234, and memory interface circuit system 240. Buffer circuit system 224 can include a set of one or more buffer circuits for at least some of the banks (if not every bank) of volatile memory 204. Buffer circuit system 224 can also include components (e.g., a memory controller) for accessing the buffer circuits. In one example, volatile memory 204 can include sixteen banks, and buffer circuit system 224 can include sixteen sets of buffer circuits. Each set of buffer circuits can be configured to store data from or for (or both) a corresponding bank of volatile memory 204. As an example, the set of buffer circuits for bank 0 (BK0) can be configured to store data from or for (or both) the first bank of volatile memory 204, and the buffer circuits for bank 15 (BK15) can be configured to store data from or for (or both) the sixteenth bank of volatile memory 204.

[0052] Each buffer circuit set in the buffer circuit system 224 may include a pair of buffers. The pair of buffers may include one buffer (e.g., an open page data (OPD) buffer) configured to store data targeted by an access command (e.g., a store command or a retrieve command) from a host device and another buffer (e.g., a victim page data (VPD) buffer) configured to store data for an eviction process generated by an access command. For example, the buffer circuit set of BK0 may include buffer 218 and buffer 220, which may be instances of buffers 135-a and 135-b, respectively. Buffer 218 may be configured to store BK0 data targeted by an access command from a host device. And buffer 220 may be configured to store data passed from BK0 as part of an eviction process triggered by an access command. Each buffer in the buffer circuit set may be configured with a size (e.g., storage capacity) corresponding to the page size of the volatile memory 204. For example, if the page size of the volatile memory 204 is 2kB, the size of each buffer may be 2kB. Thus, in some instances, the size of the buffer may be equal to the page size of volatile memory 204 .

[0053] Cache management circuit system 244 can be coupled to command circuit system 230, engine 246 and scheduler 248 and other components. Cache management circuit system 244 can include a cache management circuit set of one or more banks (e.g., each bank) of volatile memory. As an example, cache management circuit system 244 can include sixteen cache management circuit sets of BK0 to BK15. Each cache management circuit set can include two memory arrays that can be configured to store storage information of volatile memory 204. As an example, the cache management circuit set of BK0 can include a memory array 252 (e.g., a CDRAM tag array (CDT-TA)) and a memory array 254 (e.g., a CDRAM valid (CDT-V) array) that can be configured to store storage information of BK0. In some examples, the memory array can also be referred to as an array or a buffer. In some cases, the memory array can be or include a volatile memory cell, such as an SRAM cell.

[0054] The storage information may include content information, validity information, or dirty information (or any combination thereof) associated with the volatile memory 204. The content information (which may also be referred to as tag information or address information) may indicate which data is stored in the set of volatile memory cells. For example, the content information (e.g., tag address) of the set of one or more volatile memory cells may indicate which set of one or more non-volatile memory cells currently has the data stored in the set of one or more volatile memory cells. The validity information may indicate whether the data stored in the set of volatile memory cells is actual data (e.g., data with an expected order or form) or placeholder data (e.g., random or virtual data with no expected or significant order). And the dirty information may indicate whether the data stored in the set of one or more volatile memory cells of the volatile memory 204 is different from the corresponding data stored in the set of one or more non-volatile memory cells of the non-volatile memory 206. For example, the dirty information may indicate whether the data stored in the set of volatile memory cells has been updated relative to the data stored in the non-volatile memory 206.

[0055] The memory array 252 may include memory cells that store storage information (e.g., content and validity information) of an associated bank (e.g., BKO) of the volatile memory 204. The storage information may be stored on a per-page basis (e.g., for each page of an associated non-volatile memory bank, there may be corresponding storage information). The interface controller 202 may check the requested data in the volatile memory 204 by referencing the storage information in the memory array 252. For example, the interface controller 202 may receive a retrieval command for data in a set of non-volatile memory cells in the non-volatile memory 206 from a host device. The interface controller 202 may reference the storage information in the memory array 252 using a set of one or more address bits (e.g., a set of row address bits) to which the access request is directed. For example, using a set associative mapping, the interface controller 202 may reference the content information in the memory array 252 to determine which set of volatile memory cells, if any, stores the requested data.

[0056] In addition to storing content information of volatile memory cells, the memory array 252 may also store validity information indicating whether the data in the set of volatile memory cells is actual data (also referred to as valid data) or random data (also referred to as invalid data). For example, the volatile memory cells in the volatile memory 204 may initially store random data and continue to do so until the volatile memory cells are written with data from the host device or the non-volatile memory 206. In order to keep track of which data is valid, the memory array 252 may be configured to set a bit for each set of volatile memory cells when actual data is stored in the set of volatile memory cells. This bit may be referred to as a validity bit or a validity flag. As with the content information, the validity information stored in the memory array 252 may be stored on a per-page basis. Therefore, in some instances, each validity bit may indicate the validity of the data stored in the associated page.

[0057] The memory array 254 may be similar to the memory array 252 and may also include memory cells that store validity information for a bank (e.g., BK0) of the volatile memory 204 associated with the memory array 252. However, the validity information stored in the memory array 254 may be stored on a sub-block basis, as opposed to the memory array 252 being stored on a per-page basis. For example, the validity information stored in the memory cells of the memory array 254 may indicate the validity of data of a subset of volatile memory cells in a set (e.g., a page) of volatile memory cells. As an example, the validity information in the memory array 254 may indicate the validity of each subset of data (e.g., 64B) in a page of data stored in BK0 of the volatile memory 204. Storing the content information and the validity information in the memory array 252 on a per-page basis may allow the interface controller 202 to quickly and efficiently determine whether the data in the volatile memory 204 is a hit or a miss. Storing the validity information on a sub-block basis may allow the interface controller 202 to determine which subsets of data to save in the non-volatile memory 206 during the eviction process.

[0058] Each cache management circuit set may also include corresponding register pairs coupled to the command circuit system 230, the engine 246, the memory interface circuit system 234, the memory interface circuit system 240, and the memory array and other components for the cache management circuit set. For example, the cache management circuit set may include a first register (e.g., register 256, which may be an open page tag (OPT) register) configured to receive storage information (e.g., one or more bits of tag information, validity information, or dirty information) from the memory array 252 or the scheduler 248-b or both. The cache management circuit system set may also include a second register (e.g., register 258, which may be a victim page tag (VPT) register) configured to receive storage information from the memory array 254 and the scheduler 248-a or both. The information in registers 256 and 258 may be passed to the command circuit system 230 and the engine 246 to enable decisions to be made by these components. For example, command circuitry 230 may issue a command to read non-volatile memory 206 or volatile memory 204 based on content information from register 256 .

[0059] The engine 246-a may be coupled to the registers 256, the registers 258, and the scheduler 248. The engine 246-a may be configured to receive storage information from the various components and issue commands to the scheduler 248 based on the storage information. For example, when the interface controller 202 is in a first mode such as a write-through mode, the engine 246-a may issue commands to the scheduler 248-b and in response, the scheduler 248-b may initiate or facilitate the transfer of data from the buffer 218 to both the volatile memory 204 and the non-volatile memory 206. Alternatively, when the interface controller 202 is in a second mode such as a write-back mode, the engine 246-a may issue commands to the scheduler 248-b and in response, the scheduler 248-b may initiate or facilitate the transfer of data from the buffer 218 to the volatile memory 204. In the case of a write-back operation, the data stored in the volatile memory 204 may be ultimately transferred to the non-volatile memory 206 during a subsequent eviction process.

[0060] The engine 246-b may be coupled to the register 258 and the scheduler 248-a. The engine 246-b may be configured to receive storage information from the register 258 and issue commands to the scheduler 248-a based on the storage information. For example, the engine 246-b may issue a command to the scheduler 248-a to initiate or facilitate the transfer of dirty data from the buffer 220 to the non-volatile memory 206 (e.g., as part of an eviction process). If the buffer 220 contains a data set (e.g., victim data) transferred from the volatile memory 204, the engine 246-b may indicate which one or more subsets (e.g., which 64B) of the data set in the buffer 220 should be transferred to the non-volatile memory 206.

[0061] The scheduler 248-a may be coupled to various components of the interface controller 202 and may facilitate access to the non-volatile memory 206 by issuing commands to the memory interface circuitry 234. The commands issued by the scheduler 248-a may be based on commands from the command circuitry 230, the engine 246-a, the engine 246-b, or a combination of these components. Similarly, the scheduler 248-b may be coupled to various components of the interface controller 202 and may facilitate access to the volatile memory 204 by issuing commands to the memory interface circuitry 240. The commands issued by the scheduler 248-b may be based on commands from the command circuitry 230 or the engine 246-a, or both.

[0062] The memory interface circuitry 234 may communicate with the nonvolatile memory 206 through one or more of the data bus interface 212 and the C / A bus interface 214. For example, the memory interface circuitry 234 may prompt the C / A bus interface 214 to relay commands issued by the memory interface circuitry 234 to a local controller in the nonvolatile memory 206 through the C / A bus 236. And the memory interface circuitry 234 may transmit data to or receive data from the nonvolatile memory 206 through the data bus 232. In some examples, the commands issued by the memory interface circuitry 234 may be supported by the nonvolatile memory 206 instead of the volatile memory 204 (e.g., the commands issued by the memory interface circuitry 234 may be different from the commands issued by the memory interface circuitry 240).

[0063] The memory interface circuitry 240 may communicate with the volatile memory 204 through one or more of the data bus interface 216 and the C / A bus interface 264. For example, the memory interface circuitry 240 may prompt the C / A bus interface 264 to relay commands issued by the memory interface circuitry 240 to a local controller of the volatile memory 204 through the C / A bus 242. And the memory interface circuitry 240 may transmit data to or receive data from the volatile memory 204 through the one or more data buses 238. In some examples, the commands issued by the memory interface circuitry 240 may be supported by the volatile memory 204 instead of the non-volatile memory 206 (e.g., the commands issued by the memory interface circuitry 240 may be different from the commands issued by the memory interface circuitry 234).

[0064] Together, the components of interface controller 202 may operate non-volatile memory 206 as main memory and volatile memory 204 as cache. Such operations may be prompted by one or more access commands (e.g., read / retrieve commands / requests and write / store commands / requests) received from a host device.

[0065] In some examples, the interface controller 202 may receive a storage command from a host device. The storage command may be received via the C / A bus 226 and passed to the command circuit system 230 via one or more of the C / A bus interface 210 and the decoder 228. The storage command may include or be accompanied by an address bit that targets a memory address of the non-volatile memory 206. The data to be stored may be received via the data bus 260 and passed to the buffer 218 via the data bus interface 208. In write-through mode, the interface controller 202 may pass data to both the non-volatile memory 206 and the volatile memory 204. In write-back mode, the interface controller 202 may pass data to only the volatile memory 204. In either mode, the interface controller 202 may first check to see if the volatile memory 204 has a memory cell available to store the data. To this end, command circuitry 230 may reference memory array 252 (e.g., using a set of memory address bits) to determine whether one or more of the n sets of volatile memory cells (e.g., pages) associated with the memory address are empty (e.g., storing random or invalid data). In some cases, a set of volatile memory cells in volatile memory 204 may be referred to as a line or cache line.

[0066] If one of the n volatile memory cell association sets is available for storing information, the interface controller 202 may transfer the data from the buffer 218 to the volatile memory 204 for storage in the volatile memory cell set. However, if none of the volatile memory cell association sets is empty, the interface controller 202 may initiate an eviction process to make room for the data in the volatile memory 204. The eviction process may involve transferring old data (e.g., existing data) in one of the n volatile memory cell association sets to the buffer 220. Dirty information of the old data may also be transferred to the memory array 254 or register 258 for identifying a dirty subset of the old data. After the old data is stored in the buffer 220, the new data may be transferred from the buffer 218 to the volatile memory 204, and the old data may be transferred from the buffer 220 to the non-volatile memory 206. In some cases, the dirty subset of the old data is transferred to the non-volatile memory 206, and the clean subset (e.g., the unmodified subset) is discarded. The dirty subset may be identified by the engine 246 - b based on dirty information passed to the memory array 254 or registers 258 during the eviction process (eg, from the volatile memory 204 ).

[0067] In another example, the interface controller 202 may receive a retrieval command from the host device. The retrieval command may be received via the C / A bus 226 and passed to the command circuit system 230 via one or more of the C / A bus interface 210 and the decoder 228. The retrieval command may include address bits that target the memory address of the non-volatile memory 206. Before attempting to access the target memory address of the non-volatile memory 206, the interface controller 202 may check to see if the volatile memory 204 stores data. To this end, the command circuit system 230 may refer to the memory array 252 (e.g., using a memory address bit set) to determine whether one or more of the n volatile memory unit sets associated with the memory address store the requested data. If the requested data is stored in the volatile memory 204, the interface controller 202 may pass the requested data to the buffer 218 for transmission to the host device via the data bus 260.

[0068] If the requested data is not stored in the volatile memory 204, the interface controller 202 may retrieve the data from the non-volatile memory 206 and pass the data to the buffer 218 for transmission to the host device via the data bus 260. In addition, the interface controller 202 may pass the requested data from the buffer 218 to the volatile memory 204 so that the data can be accessed with lower latency during a subsequent retrieval operation. However, before passing the requested data, the interface controller 202 may first determine whether one or more of the n volatile memory unit association sets are available to store the requested data. The interface controller 202 may determine the availability of the n volatile memory unit association sets by communicating with a set of related cache management circuits. If the volatile memory unit association sets are available, the interface controller 202 may pass the data in the buffer 218 to the volatile memory 204 without performing an eviction process. Otherwise, the interface controller 202 may pass the data from the buffer 218 to the volatile memory 204 after performing an eviction process.

[0069] The memory subsystem 200 may be implemented in one or more configurations including a single-chip version and a multi-chip version. The multi-chip version may include one or more components of the memory subsystem 200, including the interface controller 202, the volatile memory 204, and the non-volatile memory 206 (as well as other components or combinations of components), on a chip separate from the chip that includes one or more other components of the memory subsystem 200. For example, in a multi-chip version, a corresponding separate chip may include each of the interface controller 202, the volatile memory 204, and the non-volatile memory 206. In contrast, the single-chip version may include the interface controller 202, the volatile memory 204, and the non-volatile memory 206 on a single chip.

[0070] In some examples, the memory subsystem 200 can implement a wear leveling program to mitigate the deleterious effects of repeated accesses to non-volatile memory cells in the non-volatile memory 206. The wear leveling program can move data between rows of a memory bank so that repeated requests for data do not result in repeated accesses to the same row. For example, the wear leveling program can move data from one row in a memory bank to another row in a memory bank. By continuing to perform the wear leveling program over time, the data in the memory bank can be constantly shuffled between rows, which can reduce the likelihood that a row will be over-accessed.

[0071] To implement a wear leveling procedure for a bank in the non-volatile memory 206, the interface controller 202 may issue a memory management command to the non-volatile memory 206. The non-volatile memory 206 may respond to the memory management command by performing a read operation on a first row of the bank and a write operation on a second row of the bank. The read operation and the write operation may be performed in succession (e.g., consecutively, without being interrupted by other access operations for the bank) to reduce the complexity of managing the wear leveling procedure at the non-volatile memory 206. However, performing the read operation and the write operation in succession may mean that the memory bank is not actually accessible for the duration of the wear leveling procedure (e.g., approximately 400 nanoseconds). This is because only one row in a bank can be activated at a time, and the successive read operations and write operations do not leave time to activate rows that are not involved in the wear leveling procedure. Therefore, using these other techniques, any commands for data in the bank that arrive during the procedure cannot be serviced until the wear leveling procedure ends.

[0072] According to the techniques described herein, a wear leveling procedure can be managed by the interface controller 202, as opposed to other components of the memory subsystem, such as the non-volatile memory 206. For example, the interface controller 202 can control when the non-volatile memory 206 performs read operations and write operations of the wear leveling procedure for the memory bank. By separating these operations in time, the interface controller 202 can reduce the amount of continuous time that the memory bank is inaccessible (e.g., from about 400 nanoseconds to about 160 nanoseconds) and provide a window during which function commands for the memory bank can be serviced. Therefore, the wait time to satisfy the function command can be reduced, which can improve the performance of the memory subsystem 200.

[0073] As described herein, satisfying a command may refer to completing a request associated with the command (e.g., storing provided data, returning requested data), while servicing a command may refer to performing one or more operations to satisfy the command. The distinction between servicing a command and satisfying a command may be with respect to the origin and termination of the command.

[0074] Figure 3 An example of a device 300 supporting memory wear management according to an example disclosed herein is shown. The device 300 may include a memory device 300 as described in reference Figure 1 The memory subsystem 110 described or as referenced Figure 2 Aspects of the memory subsystem 200 described herein. The device 300 may include an interface controller 305 and a non-volatile memory 310, which may be coupled to each other via one or more buses 315 (e.g., a data bus, a C / A bus, a transaction bus). Although not shown, the device 300 may include a volatile memory that operates as a cache. As described herein, the interface controller 305 may manage a wear leveling procedure of the non-volatile memory 310 so that during the wear leveling procedure, the memory bank undergoing the procedure may still be accessed to service functional data requests.

[0075] The non-volatile memory 310 may include a plurality of memory banks, each of which may include a plurality of memory rows (e.g., memory row 330). For example, the non-volatile memory 310 may include thirty-two memory banks, represented as B0 to B32, each of which may include memory rows 1 to N. Memory rows within a memory bank may be distinguished by a physical row address, which may identify a memory cell of a corresponding word line. The memory banks may be logically or physically grouped into memory management groups. For example, the memory banks may be divided into eight memory management groups, represented as MM Group 0 to MM Group 7. As described in more detail herein, a wear leveling procedure may be implemented on a per-bank basis (e.g., one bank at a time) or on a per-memory management group basis (e.g., in parallel for multiple banks). The non-volatile memory 310 may include one or more local controllers for processing and executing commands and additional circuitry for accessing memory cells and moving data.

[0076] A memory wear leveling procedure may involve moving data from a first row of a memory bank to a second row of a memory bank. To achieve this without overwriting stored data, at any given time, each memory bank may have one or more rows that are empty (e.g., storing random or redundant data). When it is time for a wear leveling procedure, a first memory row (e.g., row N-1) may be selected for the wear leveling procedure. The first memory row ("source memory row") may be selected based on a source pointer, which may be a set of bits indicating which memory row in the memory bank is to undergo the wear leveling procedure next. Additionally, a second memory row (e.g., an empty row, such as row N) in the memory bank may be selected for storing data from the first memory row. A second memory row ("target memory row") may be selected based on a target pointer, which may be a set of bits indicating which memory row in the memory bank is to store data from the source row. In some instances, the source pointer indicates a physical row address associated with the source row, and the target pointer indicates a physical row address associated with the target row.

[0077] After the wear leveling procedure is completed, the source pointer can be modified (e.g., decremented) to point to the next source memory row (e.g., row 6), and the target pointer can be modified (e.g., decremented) to point to the next target memory row (e.g., row N-1) (unless either pointer indicates the last row (e.g., row 0), in which case the pointers can wrap around to row N). Thus, the target pointers and source pointers can be used to manage the wear leveling procedure.

[0078] In addition to the target pointer and source pointer that implement the wear leveling procedure, the interface controller 305 can also use an offset pointer that implements address translation (e.g., converting a logical row address into a physical row address). The logical row address can be a virtual address generated by the host device and used to reference the row where the data is expected to be stored, while the physical row address can be an actual address of the physical row where the identification data is actually stored. The logical address can be used by the host device so that, among other reasons, the impact of the wear leveling procedure is effectively hidden from the host device. However, because the non-volatile memory 310 operates on physical addresses, the logical address can be mapped to the physical address to facilitate communication between the host device and the non-volatile memory 310. For example, the logical address can be mapped to the physical address based on the offset pointer, which can be a set of bits indicating the offset (e.g., difference) between the logical row address and the physical row address. Such mappings may be referred to as translation or conversion in this article.

[0079] like Figure 3 As shown in the example in , the offset pointer may initially be zero (0) because the logical address of data A is the same as the physical address of data A (and so on for the other data). However, after the data in rows 0 to N have been uniformly shifted up by one row (e.g., after eight wear leveling (WL) procedures), the offset pointer may be updated to one (1) to indicate that the offset between the logical address and the physical address is one. Similarly, the source pointer may be updated to indicate row N, and the target pointer may be updated to indicate row 0.

[0080] To manage and facilitate the wear leveling procedures as described herein, interface controller 305 may include logic components, registers, buffers, queues, and other circuitry.

[0081] For example, the interface controller 305 may include a wear leveling manager 320, which may be a logic component responsible for managing a wear leveling procedure for the non-volatile memory 310. The wear leveling manager 320 may manage pointers for wear leveling stored in registers 325 and determine when to initiate a wear leveling procedure for a memory bank (or memory management group). The wear leveling manager 320 may also issue wear leveling commands (WL commands) that initiate different phases of the wear leveling procedure. For example, the wear leveling manager 320 may issue a WL read command that initiates a read phase of the wear leveling procedure and may issue a WL write command that initiates a write phase of the wear leveling procedure. The wear leveling command may be a command used to facilitate a wear leveling procedure and may therefore be distinguished from a functional command used to facilitate a non-wear leveling procedure (e.g., data storage of a host device, data retrieval of a host device).

[0082] The interface controller 305 may also include registers 325, which may be coupled to the wear leveling manager 320 and the address translator 335, as well as other components. The registers 325 may include one or more registers that store pointers for the wear leveling routine and the address translation routine. For example, the registers 325 may store one or more source pointers and / or one or more target pointers that facilitate the wear leveling routine and one or more offset pointers that facilitate the address translation routine. The pointers may be stored in corresponding registers or in the same register. The pointers and information related to the pointers may be exchanged between the registers 325, the wear leveling manager 320, and the address translator 335.

[0083] In some instances, register 325 can store pointers on the basis of each library, which can achieve wear leveling of each library. For example, each memory library can have a corresponding target pointer, source pointer and offset pointer stored in a register corresponding to the memory library. Therefore, different pointers can be applicable to different memory libraries. In another instance, register 325 can store pointers on the basis of each MM group, which can achieve wear leveling of each MM group. For example, each MM group can have a corresponding target pointer, source pointer and offset pointer stored in a register corresponding to the MM group. Therefore, different pointers can be applicable to different MM groups. In other instances, register 325 can store a single target pointer, source pointer and offset pointer that can be applicable to all memory libraries in non-volatile memory.

[0084] The interface controller 305 may also include an address translator 335, which may be a logical component coupled to the host device, the register 325, and the scheduler 340, as well as other components. The address translator 335 may translate a logical address (LA) into a physical address (PA). For example, the address translator 335 may translate a logical address received from the host device into a physical address based on an offset pointer from the register 325. Logical addresses, physical addresses, pointers, and other information associated with address translation may be exchanged between the address translator 335 and other components of the interface controller 305.

[0085] The interface controller 305 may also include a scheduler 340, which may be a logical component coupled to the address translator 335, the wear leveling manager 320, the buffer 345, and the memory interface 350, among other components. The scheduler 340 may receive function commands (having logical addresses translated into physical addresses by the address translator 335) from the host device and wear leveling commands (having physical addresses) from the wear leveling manager 320. The scheduler 340 may sort, queue, and schedule the function commands and the wear leveling commands and convert the function commands and the wear leveling commands into commands understood (e.g., supported) by the memory interface 350. The scheduler 340 may also detect when the function command is associated with data involved in a wear leveling procedure. In such cases, the scheduler 340 may use the buffer 345 to enable the interface controller 305 to satisfy the function command, as opposed to using the non-volatile memory 310. In some instances, the scheduler 340 is as described in reference to Figure 2 An instance of a scheduler 248-a is described.

[0086] The interface controller 305 may also include a memory interface 350, which may be a logical component coupled to the scheduler 340, the buffer 345, and the non-volatile memory 310, as well as other components. The memory interface 350 may receive commands (e.g., function commands, wear leveling commands) from the scheduler 340 and process the commands for transmission to the non-volatile memory 310 via the bus 315. The memory interface 350 may also receive data (e.g., data to be stored in the non-volatile memory 310) from the scheduler 340 or a buffer (e.g., buffer 218) and relay the data to the non-volatile memory 310. Similarly, the memory interface 350 may receive data (e.g., requested data) from the non-volatile memory 310 and relay the data to the scheduler 340, a buffer (e.g., buffer 218), or a buffer 345. In some instances, the memory interface 350 is a memory interface as described in reference to FIG. Figure 2 An example of memory interface circuitry 234 is depicted.

[0087] The interface controller 305 may also include a buffer 345, which may be a buffer, array, or register coupled to the scheduler 340 and the memory interface 350, as well as other components. The buffer 345 may store data involved in the wear leveling procedure ("wear leveling data"). In some instances, the buffer 345 may include a buffer for each memory bank in the non-volatile memory 310, and each buffer may store wear leveling data for the memory bank corresponding thereto. For example, buffer 0 may store data from a source memory row of bank 0 until the data is ready to be stored in a target row of bank 0. Thus, the buffer 345 may receive wear leveling data from the memory interface 350 (e.g., as part of a read phase of a wear leveling procedure) and transmit wear leveling data to the memory interface 350 (e.g., as part of a write phase of a wear leveling procedure). In some instances (e.g., when a function command is associated with wear leveling data, a source memory row, or a target memory row), the buffer 345 may also exchange data with the scheduler 340.

[0088] The interface controller 305 may also include registers 355, which may be coupled to the wear leveling manager 320 and the host device and other components. The registers 355 may include one register for each memory bank in the non-volatile memory 310, and each register may store activity information for the memory bank corresponding thereto. For example, register 0 may store activity information for memory bank 0, register 1 may store activity information for memory bank 1, and so on. The activity information may refer to information indicating an activity level of a memory bank, which may include the number of times a memory bank has been activated. For example, register 0 may maintain a counter that is incremented each time an activate command is received for memory bank 0.

[0089] Activity information may be passed from registers 355 to wear leveling manager 320 so that wear leveling manager 320 may determine when to initiate a wear leveling procedure. For example, wear leveling manager 320 may initiate a wear leveling procedure for a memory bank when the number of activation commands for the memory bank exceeds a threshold number.

[0090] In some examples, the wear leveling manager 320 can additionally or alternatively be coupled to a timer so that the elapsed time can be used as a basis for initiating a wear leveling procedure (e.g., so that the wear leveling procedure can be performed periodically). For example, the wear leveling manager 320 can initiate a wear leveling procedure for a memory bank when the amount of time since the most recent wear leveling procedure for the memory bank exceeds a threshold amount of time.

[0091] Thus, the interface controller 305 may be configured to manage a wear leveling procedure for the non-volatile memory 310. Various aspects of the wear leveling procedure managed by the interface controller 305 are described in greater detail herein and with reference to Figure 4 describe.

[0092] Figure 4 An example of a process flow 400 for supporting memory wear management according to an example disclosed herein is shown. The process flow 400 may be performed by a processor as described in reference to Figure 1 The memory subsystem 110 described in reference Figure 2 The memory subsystem 200 described or referenced Figure 3 300 is an example of a process flow implemented by a device such as the described device. Thus, the device may include an interface controller and a non-volatile memory. Process flow 400 may illustrate the operation of the interface controller and the non-volatile memory when the interface controller manages a wear leveling procedure for the non-volatile memory. Operations performed by the interface controller may be represented by white boxes, and operations performed by the non-volatile memory may be represented by shaded boxes.

[0093] In some examples, aspects of the process flow 400 may be implemented by a controller and other components. Additionally or alternatively, aspects of the process flow 400 may be implemented as instructions stored in a memory (e.g., firmware stored in the volatile memory 120 and / or the non-volatile memory 125). For example, the instructions, when executed by a controller, may cause the controller to perform the operations of the process flow 400.

[0094] As described herein, the interface controller can separate the wear leveling procedure for the memory bank into a read phase 420 and a write phase 440, which can allow the interface controller to service function commands for the memory bank during the wear leveling procedure (e.g., after the wear leveling procedure begins but before the wear leveling procedure completes). Although described with reference to a single memory bank, the operations of the process flow 400 can be implemented in parallel on multiple memory banks (e.g., on a management group basis or on an all memory bank basis in a non-volatile memory).

[0095] Alternative examples of process flow 400 may be implemented in which some operations are performed in a different order than described or not performed at all. In some examples, process flow 400 may include operations not mentioned below (e.g., additional operations may be added). In addition, some operations may be performed in parallel (e.g., simultaneously or during overlapping times).

[0096] At 402, the device may determine to initiate a wear leveling procedure for a memory bank. For example, the wear leveling manager 320 may determine to initiate a wear leveling procedure for memory bank 0. The wear leveling manager 320 may determine to initiate a wear leveling procedure based on activity information of memory bank 0 or based on a timer of memory bank 0. For example, the wear leveling manager 320 may determine to initiate a wear leveling procedure for memory bank 0 based on a number of activation commands for memory bank 0 exceeding a threshold number. Or the wear leveling manager 320 may determine to initiate a wear leveling procedure for memory bank 0 based on an amount of time since a last wear leveling procedure for memory bank 0 exceeding a threshold amount of time. For example, the wear leveling manager 320 may determine to initiate a wear leveling procedure for memory bank 0 periodically.

[0097] At 404, the device may select a memory row for a wear leveling procedure. For example, the wear leveling manager 320 may select a source row and a target row. The row may be selected based on pointer information received from the register 325. For example, the source row may be selected based on a source pointer for memory bank 0, and the target row may be selected based on a target pointer for memory bank 0. By managing the wear leveling procedure at the interface controller 305, the device 300 may avoid address translations that may otherwise occur, thereby saving time and / or processing resources. For example, instead of issuing a wear leveling command with a logical row address to the non-volatile memory 310 - and thus requiring the non-volatile memory 310 to perform an address translation to determine the associated physical row address - the interface controller 305 may issue a wear leveling command with a physical address, thereby avoiding the need for address translation at the non-volatile memory 310. Further, the interface controller 305 may avoid address translation for the wear leveling routine entirely by 1) receiving the source and destination pointers from the registers 325 (because the source and destination pointers directly indicate physical addresses and therefore do not require translation) and 2) passing the physical address (as opposed to the logical address) along with the wear leveling command to the scheduler 340. Thus, the configuration of the device 300 may allow the device 300 to avoid address translation for the wear leveling routine.

[0098] At 406, the device may issue a wear leveling read command to the non-volatile memory. For example, the interface controller 305 may issue a wear leveling read command to the non-volatile memory 310. The read command may include or be accompanied by an indication of a source row (e.g., a physical address of the source row). The read command may be preceded by an activation command for the source row or a memory bank associated with the source row. In some examples, issuing the wear leveling read command may include: at 408, the wear leveling manager 320 issuing the wear leveling command to the scheduler 340; and at 410, the scheduler 340 relaying the wear leveling read command to the memory interface 350 for transmission to the non-volatile memory 310 via the bus 315.

[0099] Wear leveling commands communicated between components of the interface controller 305 may be formatted differently depending on the components involved in the communication. Although described with reference to a wear leveling read command, similar operations may be performed for other commands associated with wear leveling (e.g., an activate command, a wear leveling write command, a precharge command, etc.).

[0100] At 412, the nonvolatile memory may activate source rows in the memory bank selected for the wear leveling procedure. For example, the nonvolatile memory 310 may activate source rows in memory bank 0. Activating a row may also be referred to as opening a row and may involve applying an activation voltage to a word line associated with the row (e.g., so that data in the row can be read during a read operation). The nonvolatile memory may also read data from the source row. At 414, the nonvolatile memory closes the source row and passes the wear leveling data to the device. For example, the nonvolatile memory 310 may close the source row in memory bank 0 and pass the wear leveling data to the interface controller 305 via the bus 315 and the memory interface 350. Closing a row may also be referred to as deactivating or precharging a row and may involve removing the activation voltage from the word line associated with the row and / or latching the data read from the row. Closing the row in memory bank 0 after reading the wear leveling data may allow other rows in memory bank 0 to be opened and accessed during the wear leveling procedure.

[0101] At 416, the device may receive wear leveling data from the nonvolatile memory. For example, the interface controller 305 may receive the wear leveling data from the nonvolatile memory 310. At 418, the device may store the wear leveling data in a buffer associated with the memory bank selected for the wear leveling procedure. For example, the memory interface 350 may store the wear leveling data for the memory bank 0 in buffer 0 in buffer 345. The operations between 406 and 418 may be part of a read phase 420 of the wear leveling procedure. Because the source rows are closed at the end of the read phase 420, the device is able to access other rows of the memory bank 0 to service the function command while the wear leveling procedure is in progress, which may reduce latency.

[0102] In some examples, at 422, the device may receive a function command associated with a memory bank undergoing a wear leveling procedure. For example, the interface controller 305 may receive a read command or a write command for memory bank 0 from a host device coupled to the interface controller 305. The read command may request data from a logical address of the non-volatile memory, while the write command may request that the provided data be stored at a logical address of the non-volatile memory array. The function command may be relayed to the scheduler 340 along with a translation of the logical address (e.g., a physical address associated with the logical address). The physical address may be determined by the address translator 335 based on an offset pointer stored in the register 325 and other pointers.

[0103] In some examples, at 424, the device can determine whether the data associated with the function command is also associated with a wear leveling procedure. For example, if the function command is a read command, the scheduler 340 can determine whether the data requested by the read command is data that is subject to a current wear leveling procedure (e.g., an ongoing wear leveling procedure). The scheduler 340 can make this determination by comparing the physical address of the read command with the physical address of the wear leveling procedure. If the physical addresses do not match, then at 426, the device can retrieve the data from the non-volatile memory and return it to the host device (e.g., by referring to Figure 2 If the physical addresses match, then at 428, the scheduler 340 may respond by reading the requested data from the buffer 345 (e.g., buffer 0) and returning the requested data to the host device (e.g., ... as described in reference to FIG. Figure 2 The buffer 218 described above is used to satisfy the read command.

[0104] If the function command received at 422 is a write command, the scheduler 340 can determine whether the physical address associated with the write command is data that is subject to the current wear leveling procedure. The scheduler 340 can make this determination by comparing the physical address of the wear leveling procedure with the physical address associated with the write command. If the physical addresses do not match, at 426, the device 300 can satisfy the write command by storing the provided data in the non-volatile memory 310. If the physical addresses match, at 428, the scheduler 340 can satisfy the write command by writing the provided data to the buffer 345 (e.g., buffer 0). Thus, the device can service and satisfy the function command during the wear leveling procedure.

[0105] At 430, the device may pass a wear leveling write command and wear leveling data to the non-volatile memory as part of a write phase 440 of the wear leveling procedure. For example, the interface controller 305 may pass the wear leveling data and the wear leveling write command to the non-volatile memory 310. The write command may include or be accompanied by an indication of a target row (e.g., a physical address of the target row). The write command may be preceded by an activation command for the target row or a memory bank associated with the target row. In some examples, issuing the wear leveling write command may include: at 432, the wear leveling manager 320 issuing the wear leveling write command to the scheduler 340; at 434, the scheduler 340 relaying the wear leveling write command to the memory interface 350; and at 436, the memory interface 350 retrieving the wear leveling data from the buffer 345 (e.g., buffer 0). Thus, the memory interface 350 may transmit the wear leveling data and the wear leveling write command to the non-volatile memory 310 via the bus 315.

[0106] At 438, the device may activate the target row of the memory bank selected for the wear leveling procedure, write the wear leveling data to the target row, and close the target row. For example, the non-volatile memory 310 may activate the target row in the memory bank 0, write the wear leveling data to the target row, and close the target row. Thus, the write phase 440 of the wear leveling procedure as well as the wear leveling procedure itself may be completed.

[0107] In some examples, the device may update the pointers in register 325 after completing the wear leveling procedure for memory bank 0. For example, wear leveling manager 320 may update the source pointer, the destination pointer, and / or the offset pointer to indicate the new physical address of non-volatile memory 310. In this way, subsequent wear leveling procedures may involve the new row of memory bank 0, which may increase the efficacy of the wear leveling techniques described herein.

[0108] Although described with reference to a single memory bank, the operations of process flow 400 may be implemented in parallel or in series on multiple memory banks. In some instances, the wear leveling procedures performed on other memory banks may involve the same physical row addresses of the source and target rows. In other instances, the wear leveling procedures performed on other memory banks may involve different physical row addresses of the source and target rows.

[0109] Figure 5 An example of a timing diagram 500 supporting memory wear management according to an example as disclosed herein is shown. The timing diagram 500 can show signals exchanged between an interface controller and a non-volatile memory, as described herein. The signals can include command signals 505 and address signals 510, which can be transmitted between the interface controller and the non-volatile memory via one or more C / A buses. The signals illustrate how functional commands can be serviced during a wear leveling procedure managed by the interface controller as described herein. In the timing diagram 500, wear leveling commands and data can be represented by shaded shapes, and functional commands can be represented by white shapes. A clock signal 540 can be used to synchronize operations at the interface controller and the non-volatile memory.

[0110] At time t1, the interface controller may transmit a precharge command (PRE) for memory bank 0 (B0) to the nonvolatile memory. In some instances, the precharge command may be a precharge command (PREpb) for each bank. The precharge command may indicate to the nonvolatile memory that the data is to be saved in memory bank 0 and any open rows are to be closed. Thus, memory bank 0 may be prepared for a wear leveling procedure. At time t2, the interface controller may transmit an activation command (ACT) for a source row in memory bank 0 to the nonvolatile memory. The activation command may indicate to the nonvolatile memory that the source row is to be activated for the wear leveling procedure. Thus, the nonvolatile memory may activate the source row. At time t3, the interface controller may transmit a read command for memory bank 1 to the nonvolatile memory. The nonvolatile memory may service a read command for memory bank 1 (not shown).

[0111] At time t4, the interface controller may transmit a wear leveling read command for a source row in memory bank 0 to the nonvolatile memory. The wear leveling read command may instruct the nonvolatile memory to read data from the source row and return the data to the interface controller (e.g., for storage in a buffer, as described in reference to FIG. 1 ). Figure 3Buffer 0 in buffer 345 is depicted. The amount of time that wear leveling data 515 is stored in the buffer may be represented by cycle 520. After reading the data from the source row, the nonvolatile memory may close the source row (e.g., automatically or in response to a precharge command from the interface controller) so that other rows in memory bank 0 may be accessed for the function command. Thus, read phase 525 may include transmitting an activate command at time t2, transmitting a wear leveling read command at time t4, storing the wear leveling data in the buffer, and closing the source row in memory bank 0. The duration of the read phase may be shorter or longer than shown, but may end before the function activate command for memory bank 0 is transmitted at time t7.

[0112] After storing the wear leveling data in the buffer, but before storing the wear leveling data in the target row, the interface controller may issue functional commands to memory bank 0 and other memory banks. For example, the interface controller may transmit a functional read command for the row in memory bank 2 to the nonvolatile memory at time t5 and transmit a functional read command for the row in memory bank 3 to the nonvolatile memory at time t6. The nonvolatile memory may serve and satisfy these functional read commands as described herein. The interface controller may also transmit a functional activation command for the row in memory bank 0 to the nonvolatile memory at time t7 and transmit a functional read command for the row in memory bank 0 to the nonvolatile memory at time t8. The row may be any row in memory bank 0 that is not involved in the ongoing wear leveling procedure. Therefore, the nonvolatile memory may activate the row in memory bank 0 and read data from the row. Such behavior is possible because the source row in memory bank 0 is closed at the end of the read phase 525. After reading data from the row, the nonvolatile memory may close the row so that other rows in memory bank 0 may be accessed for function commands or wear leveling commands.

[0113] At time t9, the interface controller may transmit a wear leveling activation command for a target row in memory bank 0 to the nonvolatile memory. In response to the activation command, the nonvolatile memory may activate the target row in memory bank 0. At time t10, the interface controller may transmit a wear leveling write command for a target row in memory bank 0 to the nonvolatile memory. In response to the wear leveling write command, the nonvolatile memory may write wear leveling data to the target row, thereby completing the write phase 535 of the wear leveling procedure, which ends the wear leveling procedure. After writing the wear leveling data to the target row, the nonvolatile memory may close the target row (e.g., automatically or in response to a precharge command from the interface controller) so that other rows in memory bank 0 may be accessed for subsequent commands.

[0114] Thus, the memory interface may issue an interleave function command 545 for the memory banks undergoing the wear leveling procedure by separating the read phase 525 and the write phase 535 of the wear leveling procedure.

[0115] Figure 6 A block diagram 600 of a device 605 supporting memory wear management according to an example disclosed herein is shown. The device 605 may be as described in reference to Figure 1 , 2 3 and 4. Thus, the device may include a non-volatile memory including one or more memory banks and an interface controller coupled to the non-volatile memory. The device 605 may include an address manager 610, a wear leveling (WL) command manager 615, a register manager 620, a memory interface manager 625, a non-volatile memory manager 630, and a function command manager 635. Each of these modules may include circuitry configured to perform the functions described herein. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses or other conductive connections).

[0116] In a first example, the address manager 610 may select a physical row address in a memory bank for a procedure to move data from a first row of the memory bank to a second row of the memory bank. The procedure may be a wear leveling procedure as described herein. The WL command manager 615 may determine to initiate a procedure for a first row of the memory bank based at least in part on the physical row address, wherein the physical row address is associated with the first row. As part of the procedure, the WL command manager 615 may also issue a read command to the non-volatile memory for the physical row address associated with the first row.

[0117] In some instances, register manager 620 may transfer data to a register in an interface controller based at least in part on issuing a read command. In some instances, memory interface manager 625 may transfer data from the register to a non-volatile memory. In some instances, non-volatile memory manager 630 may store data in a second row of a memory bank. In some instances, memory interface manager 625 may transfer second data to or from a memory bank between transferring the data to the register and transferring the data to the non-volatile memory.

[0118] In some instances, the function command manager 635 can receive a read command for a logical row address from the host device. In some instances, the function command manager 635 can determine that the logical row address is associated with the first row based at least in part on a pointer stored in a second register of the interface controller. In some instances, the register manager 620 can return data from the register to the host device based at least in part on the logical row address being associated with the first row.

[0119] In some instances, the function command manager 635 may receive a write command for a logical row address from the host device, the write command being associated with the second data. In some instances, the function command manager 635 may determine that the logical row address is associated with the first row based at least in part on a pointer stored in a second register of the interface controller. In some instances, the register manager 620 may replace the data in the register with the second data based at least in part on receiving the write command for the logical row address.

[0120] In some examples, the WL command manager 615 may issue a write command for a second physical row address associated with a second row of the memory bank to the nonvolatile memory based at least in part on issuing the read command. In some examples, the function command manager 635 may issue an access command associated with the memory bank to the nonvolatile memory between issuing the read command and the write command. In some examples, the function command manager 635 may issue an access command associated with the memory bank to the nonvolatile memory between issuing the read command and the write command.

[0121] In some instances, the physical row address is selected based at least in part on a pointer stored in a register of the interface controller.In some instances, register manager 620 may select a second physical row address associated with a second row based at least in part on a second pointer stored in a register.

[0122] In some examples, nonvolatile memory manager 630 may store data in a second row of the memory bank after issuing the read command.In some examples, register manager 620 may update one or more pointers in a register of the interface controller based at least in part on storing data in the second row of the memory bank.

[0123] In some examples, the nonvolatile memory includes a second memory bank. In some examples, the address manager 610 can select a second physical row address in the second memory bank for a second procedure to move second data between rows of the second memory bank, wherein the procedure and the second procedure at least partially overlap in time.

[0124] In some examples, the address manager 610 may determine a first physical row address of a first row of the memory bank storing data to be transferred to a second row of the memory bank. The WL command manager 615 may transfer a read command for the first physical row address to the non-volatile memory. The register manager 620 may transfer the data to a register in the interface controller based at least in part on the transfer read command. And the memory interface manager 625 may transfer the data from the register to the non-volatile memory.

[0125] In some examples, the WL command manager 615 may communicate a write command to the non-volatile memory, wherein the data is stored in the second row of the memory bank based at least in part on the write command.

[0126] In some examples, the memory interface manager 625 may transfer the second data to or from the memory bank after transferring the data to the register and before transferring the data to the non-volatile memory.

[0127] In some instances, the WL command manager 615 may initiate a wear leveling procedure for the memory bank, wherein the wear leveling procedure includes moving data from a first row to a second row of the memory bank. In some instances, the WL command manager 615 may determine that a threshold duration has expired since a previous wear leveling procedure was completed, wherein the wear leveling procedure is initiated based at least in part on the determination that the threshold duration has expired. In some instances, the WL command manager 615 may determine that a threshold number of activation commands have been directed to the memory bank since a previous wear leveling procedure was completed, wherein the wear leveling procedure is initiated based at least in part on the determination that a threshold number of activation commands have been directed to the memory bank.

[0128] Figure 7 A flowchart illustrating one or more methods 700 for supporting memory wear management according to aspects of the present disclosure is shown. The operations of the method 700 may be implemented by a memory subsystem or components thereof as described herein. For example, the operations of the method 700 may be implemented by a memory subsystem or components thereof as described in reference to Figures 1 to 6 The memory subsystem described herein performs. In some examples, the memory subsystem may execute a set of instructions to control functional elements of the memory subsystem to perform the described functions. Additionally or alternatively, the memory subsystem may use dedicated hardware to perform various aspects of the described functions.

[0129] In some examples, the operations of method 700 may be performed by an apparatus including a non-volatile memory and an interface controller. The non-volatile memory may include one or more memory banks and may be coupled to the interface controller.

[0130] At 705, the method may include selecting a physical row address in a memory bank for moving data from a first row of the memory bank to a second row of the memory bank. The operations of 705 may be performed according to the methods described herein. In some examples, aspects of the operations of 705 may be performed as described in reference to Figure 6 The described address manager is implemented.

[0131] At 710, the method may include determining a first row start procedure for a memory bank based at least in part on a physical row address, wherein the physical row address is associated with the first row. The operations of 710 may be performed according to the methods described herein. In some examples, aspects of the operations of 710 may be performed as described in reference to Figure 6 The described address manager is implemented.

[0132] At 715, the method may include issuing a read command for a physical row address associated with the first row to the non-volatile memory as part of the program. The operations of 715 may be performed according to the methods described herein. In some examples, aspects of the operations of 715 may be described by reference to Figure 6 The WL command manager described here executes.

[0133] In some examples, an apparatus as described herein may perform one or more methods, such as method 700. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: a program to select a logical row address in a memory bank for moving data from a first row of the memory bank to a second row of the memory bank; determine a physical row address associated with the first row of the memory bank based at least in part on the logical row address and one or more pointers stored in a register of an interface controller; and as part of the program, issue a read command for the physical row address to a non-volatile memory.

[0134] Some examples of the method 700 and apparatus described herein may further include operations, features, components, or instructions for transferring data to a register in an interface controller based at least in part on issuing a read command. Some examples of the method 700 and apparatus described herein may further include operations, features, components, or instructions for: transferring data from the register to a non-volatile memory; and storing the data in a second row of the memory bank. Some examples of the method 700 and apparatus described herein may further include operations, features, components, or instructions for transferring a second data to or from the memory bank between transferring the data to the register and transferring the data to the non-volatile memory.

[0135] Some examples of the method 700 and apparatus described herein may further include operations, features, components, or instructions for transferring data to a register in the interface controller based at least in part on issuing a read command. Some examples of the method 700 and apparatus described herein may further include operations, features, components, or instructions for: receiving a read command for a logical row address from a host device; determining that the logical row address is associated with the first row based at least in part on a pointer stored in a second register of the interface controller; and returning data from the register to the host device based at least in part on the logical row address being associated with the first row.

[0136] Some examples of the method 700 and the apparatus described herein may further include operations, features, components, or instructions for transferring data to a register in an interface controller based at least in part on issuing a read command. Some examples of the method 700 and the apparatus described herein may further include operations, features, components, or instructions for receiving a write command for a logical row address from a host device, the write command being associated with the second data. Some examples of the method 700 and the apparatus described herein may further include operations, features, components, or instructions for determining that the logical row address is associated with the first row based at least in part on a pointer stored in a second register of the interface controller. Some examples of the method 700 and the apparatus described herein may further include operations, features, components, or instructions for replacing the data in the register with the second data based at least in part on receiving a write command for the logical row address.

[0137] Some examples of the method 700 and apparatus described herein may further include operations, features, components, or instructions for issuing a write command for a second physical row address associated with a second row of the memory bank to the nonvolatile memory based at least in part on issuing the read command. Some examples of the method 700 and apparatus described herein may further include operations, features, components, or instructions for issuing an access command associated with the memory bank to the nonvolatile memory between issuing the read command and the write command.

[0138] In some examples, the physical row address is selected based at least in part on a pointer stored in a register of the interface controller. Some examples of method 700 and apparatus described herein may further include operations, features, components, or instructions for selecting a second physical row address associated with a second row based at least in part on a second pointer stored in a register.

[0139] Some examples of the method 700 and apparatus described herein may further include operations, features, components, or instructions for storing data in a second row of the memory bank after issuing the read command. Some examples of the method 700 and apparatus described herein may further include operations, features, components, or instructions for updating one or more pointers in a register of the interface controller based at least in part on storing the data in the second row of the memory bank.

[0140] Some examples of method 700 and the apparatus described herein may further include operations, features, components, or instructions for a second program for selecting a second physical row address in a second memory bank (of a non-volatile memory) for moving second data between rows of the second memory bank, wherein the program and the second program overlap at least partially in time.

[0141] Figure 8 800 for supporting memory wear management according to aspects of the present disclosure. The operations of the method 800 may be implemented by a memory subsystem or components thereof as described herein. For example, the operations of the method 800 may be implemented by a memory subsystem or components thereof as described herein. Figures 1 to 6 The memory subsystem described herein performs. In some examples, the memory subsystem may execute a set of instructions to control functional elements of the memory subsystem to perform the described functions. Additionally or alternatively, the memory subsystem may use dedicated hardware to perform various aspects of the described functions.

[0142] In some examples, the operations of method 800 may be performed by an apparatus including a non-volatile memory and an interface controller. The non-volatile memory may include one or more memory banks and may be coupled to the interface controller.

[0143] At 805, the method may include determining a first physical row address of a first row of a memory bank storing data to be transferred to a second row of the memory bank. The operations of 805 may be performed according to the methods described herein. In some examples, aspects of the operations of 805 may be performed as described in reference to Figure 6 The described address manager is implemented.

[0144] At 810, the method may include transmitting a read command for a first physical row address to a non-volatile memory. The operations of 810 may be performed according to the methods described herein. In some examples, aspects of the operations of 810 may be performed as described in reference to Figure 6 The WL command manager described here executes.

[0145] At 815, the method may include transferring data to a register in the interface controller based at least in part on the transfer read command. The operations of 815 may be performed according to the methods described herein. In some examples, aspects of the operations of 815 may be described by reference to Figure 6 The register manager described here performs the following operations.

[0146] At 820, the method may include transferring data from the register to the non-volatile memory. The operations of 820 may be performed according to the methods described herein. In some examples, aspects of the operations of 820 may be described in detail with reference to Figure 6 The described memory interface manager performs

[0147] In some examples, an apparatus as described herein may perform one or more methods, such as method 800. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: determining a first physical row address of a first row of a memory bank storing data to be transferred to a second row of the memory bank; transferring a read command for the first physical row address to a non-volatile memory; transferring the data to a register in an interface controller based at least in part on the transfer read command; and transferring the data from the register to the non-volatile memory.

[0148] In some examples of method 800 and apparatus described herein, determining storage information may include operations, features, means, or instructions for communicating a write command to the nonvolatile memory, wherein data is stored in a second row of the memory bank based at least in part on the write command.

[0149] In some examples of method 800 and apparatus described herein, determining storage information may include operations, features, means, or instructions for transferring second data to or from a memory bank after transferring the data to a register and before transferring the data to a non-volatile memory.

[0150] In some instances of method 800 and apparatus described herein, determining storage information may include an operation, feature, component, or instruction for initiating a wear leveling procedure for a memory bank, wherein the wear leveling procedure includes moving data from a first row to a second row of the memory bank. In some instances of method 800 and apparatus described herein, determining storage information may include an operation, feature, component, or instruction for determining that a threshold duration has expired since a previous wear leveling procedure was completed, wherein the wear leveling procedure is initiated based at least in part on determining that the threshold duration has expired. In some instances of method 800 and apparatus described herein, determining storage information may include an operation, feature, component, or instruction for determining that a threshold number of activation commands have been directed to a memory bank since a previous wear leveling procedure was completed, wherein the wear leveling procedure is initiated based at least in part on determining that a threshold number of activation commands have been directed to a memory bank.

[0151] In some examples, an apparatus as described herein may perform aspects of methods 700 and 800. The apparatus may include a nonvolatile memory including a plurality of memory banks and an interface controller coupled to the nonvolatile memory. The interface controller may include: a first logic component (e.g., a wear leveling manager 320) configured to manage a program that moves data between rows of memory banks in the nonvolatile memory; a register (e.g., one of the registers 325) coupled to the first logic component and configured to store one or more pointers associated with the rows of the memory banks; and a second logic component (e.g., an address translator 335) coupled to the register and configured to determine a physical row address based at least in part on the one or more pointers stored in the register. The one or more pointers may be associated with a single memory bank of the plurality of memory banks. Or the one or more pointers may be associated with a subset of the plurality of memory banks.

[0152] In some examples, the interface controller includes a buffer (eg, one of buffers 345) configured to store data from one row of the memory bank and intended for another row of the memory bank indicated by the one or more pointers.

[0153] In some instances, the interface controller includes a second register (e.g., one of the registers 355) coupled to the first logic component and operable to maintain a counter for a memory bank in the plurality of memory banks, wherein the counter for the memory bank indicates a number of activation commands received for the memory bank.

[0154] In some examples, the interface controller includes a third logic component (e.g., memory interface 350) coupled to the second logic component and configured to transmit access commands for the physical rows indicated by the one or more pointers to the non-volatile memory. In some examples, the interface controller includes a fourth logic component (e.g., scheduler 340) coupled to the third logic component and configured to schedule access commands transmitted by the third logic component.

[0155] It should be noted that the methods described above describe possible embodiments, and that operations and steps may be rearranged or otherwise modified, and other embodiments are possible. In addition, parts from two or more methods may be combined in a method.

[0156] The information and signals described herein may be represented using any of a variety of different processes and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some figures may show multiple signals as a single signal; however, one of ordinary skill in the art will appreciate that a signal may represent a signal bus, where the bus may have various bit widths.

[0157] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports a flow of signals between the components. Components are considered to be in electronic communication with each other (or in conductive contact, connected, or coupled to each other) if there is any conductive path between the components that can support a flow of signals between the components at any time. At any given time, the conductive paths between components that are in electronic communication with each other (or in conductive contact or connected or coupled to each other) may be open circuits or closed circuits based on the operation of the device containing the connected components. The conductive paths between the connected components may be direct conductive paths between the components, or the conductive paths between the connected components may be indirect conductive paths that may include intermediate components such as switches, transistors, or other components. In some instances, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0158] The term "coupling" refers to a condition of moving from an open circuit relationship between components where signals cannot currently be transmitted between components via a conductive path to a closed circuit relationship between components where signals can be transmitted between components via a conductive path. When a component such as a controller couples other components together, the component causes a change that allows signals to flow between the other components via a conductive path that previously did not allow signals to flow.

[0159] The term "isolation" refers to a relationship between components in which a signal is not currently able to flow between the components. Components are isolated from one another if an open circuit exists between the components. For example, components separated by a switch positioned between two components are isolated from one another when the switch is open. When a controller isolates two components, the controller effects a change that prevents a signal from flowing between the components using a conductive path that previously allowed the signal to flow.

[0160] The devices including memory arrays discussed herein may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate may be a silicon-on-insulator (SOI) substrate such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP) or an epitaxial layer of a semiconductor material on another substrate. The conductivity of a substrate or a sub-region of a substrate may be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate or by any other doping means.

[0161] The switching components or transistors discussed herein may represent field effect transistors (FETs) and include three-terminal devices including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials such as metals. The source and drain may be conductive and may include heavily doped, for example, degenerate semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., most carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may make the channel conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0162] The description set forth herein describes example configurations in conjunction with the accompanying drawings and does not represent all examples that can be implemented within the scope of the claims or are within the scope of the claims. The term "exemplary" as used herein means "serving as an example (example, instance) or illustration", rather than "preferred" or "better than other examples." The detailed description contains specific details for providing an understanding of the described technology. However, these technologies can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid blurring the concepts of the described examples.

[0163] In the accompanying drawings, similar components or features may have the same reference number. Further, components of the same type may be distinguished by following the reference number with a dash and a second reference that distinguishes between the similar components. If only the first reference number is used in the specification, the description applies to any of the similar components having the same first reference number without regard to the second reference number.

[0164] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0165] A protocol may define one or more communication procedures and one or more communication parameters that are supported for use by a device or component. For example, a protocol may define various operations, the timing and frequency of these operations, the meaning of various commands or signals or both, one or more addressing schemes for one or more memories, the type of communication for reserved pins, the size of data processed at various components such as interfaces, the data rate supported by various components such as interfaces, or the bandwidth supported by various components such as interfaces, and other parameters and metrics or any combination thereof. The use of shared protocols can enable interaction between devices because each device can operate in a manner that is expected, recognized, and understood by the other device. For example, two devices supporting the same protocol can interact according to the policies, procedures, and parameters defined by the protocol, while two devices supporting different protocols may be incompatible.

[0166] To illustrate, two devices supporting different protocols may not be compatible because the protocols define different addressing schemes (e.g., different numbers of address bits). As another illustration, two devices supporting different protocols may not be compatible because the protocols define different delivery procedures for responding to a single command (e.g., the burst length or number of bytes allowed in response to a command may be different). Merely translating commands into actions should not be construed as using two different protocols. Conversely, protocols may be considered different if the corresponding procedures or parameters defined by the two protocols are different. For example, a device may be said to support two different protocols if it supports different addressing schemes or different delivery procedures for responding to commands.

[0167] The various illustrative blocks and modules described in conjunction with the disclosure herein may be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0168] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the function can be stored on a computer-readable medium as one or more instructions or codes or transmitted by a computer-readable medium. Other examples and embodiments are within the scope of the present disclosure and the appended claims. For example, due to the nature of the software, the above functions can be implemented using software executed by a processor, hardware, firmware, hard wiring, or any combination thereof. The features of the implementation functions can also be physically located at various locations, including being distributed so that the various parts of the functions are implemented at different physical locations. Also, as used herein (included in the claims), as used in a list of items (e.g., a list of items ending with phrases such as "at least one of ... or "one or more of ..."), "or" indicates an inclusive list, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" should not be interpreted as a reference to a conditional closed set. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0169] Computer-readable media includes non-transitory computer storage media and communication media including any media that promotes computer programs to be transferred from one place to another.Non-transitory storage media can be any available media that can be accessed by a general or special computer.By way of example and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage devices, disk storage devices or other magnetic storage devices or can be used for carrying or storing expected program code means in the form of instructions or data structures and any other non-transitory media that can be accessed by a general or special computer or a general or special processor.And, any connection is appropriately referred to as computer-readable media.For example, if coaxial cable, optical fiber cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwave are used to transmit software from a website, server or other remote source, the coaxial cable, optical fiber cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwave are included in the definition of media. Disk or disc, as used herein, includes CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0170] The description herein is provided to enable those skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is intended to conform to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus for memory operation, comprising: a non-volatile memory, the non-volatile memory comprising a memory bank; as well as an interface controller coupled to the non-volatile memory and operable to cause the apparatus to: selecting a physical row address in the memory bank for use in a procedure for moving data from a first row of the memory bank to a second row of the memory bank, wherein the physical row address selected for the procedure is based at least in part on a pointer associated with an address translation; determining to initiate the program for the first row of the memory bank based at least in part on the physical row address, wherein the physical row address is associated with the first row; issuing, as part of the procedure, a read command to the nonvolatile memory for the physical row address associated with the first row; as part of the procedure, storing the data in the second row of the memory bank based at least in part on issuing the read command; and Based at least in part on storing the data in the second row of the memory bank, updating one or more pointers in registers of the interface controller, wherein the one or more pointers include the pointer associated with an address translation.

2. The apparatus of claim 1, wherein the program comprises a wear leveling program.

3. The apparatus of claim 1 , wherein the interface controller is operable to cause the apparatus to: The data is transferred to the register of the interface controller based at least in part on issuing the read command.

4. The apparatus of claim 3, wherein the interface controller is operable to cause the apparatus to: transferring the data from the register to the non-volatile memory; and The data is stored in the second row of the memory bank.

5. The apparatus of claim 4, wherein the interface controller is operable to cause the apparatus to: Between transferring the data to the register and transferring the data to the non-volatile memory, second data is transferred to or from the memory bank.

6. The apparatus of claim 1, wherein the interface controller is operable to cause the apparatus to: A write command is issued to the nonvolatile memory for a second physical row address associated with the second row of the memory bank based at least in part on issuing the read command.

7. The apparatus of claim 1 , wherein the physical row address is selected based at least in part on a pointer stored in the register of the interface controller, and wherein the interface controller is operable to cause the apparatus to: A second physical row address associated with the second row is selected based at least in part on a second pointer stored in the register.

8. The apparatus of claim 1 , wherein the non-volatile memory comprises a second memory bank, and wherein the interface controller is operable to cause the apparatus to: A second physical row address in the second memory bank is selected for use in a second procedure of moving second data between rows of the second memory bank, wherein the procedure and the second procedure at least partially overlap in time.

9. An apparatus for memory operation, comprising: a non-volatile memory, the non-volatile memory comprising a memory bank; as well as an interface controller coupled to the non-volatile memory and operable to cause the apparatus to: a procedure for selecting a physical row address in the memory bank for moving data from a first row of the memory bank to a second row of the memory bank; determining to initiate the program for the first row of the memory bank based at least in part on the physical row address, wherein the physical row address is associated with the first row; issuing, as part of the procedure, a read command to the nonvolatile memory for the physical row address associated with the first row; transferring the data to a register in the interface controller based at least in part on issuing the read command; receiving a second read command for the logical row address from the host device; determining that the logical row address is associated with the first row based at least in part on a pointer stored in a second register of the interface controller; and The data is returned from the register to the host device based at least in part on the logical row address being associated with the first row.

10. An apparatus for memory operation, comprising: a non-volatile memory, the non-volatile memory comprising a memory bank; as well as an interface controller coupled to the non-volatile memory and operable to cause the apparatus to: a procedure for selecting a physical row address in the memory bank for moving data from a first row of the memory bank to a second row of the memory bank; determining to initiate the program for the first row of the memory bank based at least in part on the physical row address, wherein the physical row address is associated with the first row; issuing, as part of the procedure, a read command to the nonvolatile memory for the physical row address associated with the first row; transferring the data to a register in the interface controller based at least in part on issuing the read command; receiving a write command for a logical row address from a host device, the write command being associated with second data; determining that the logical row address is associated with the first row based at least in part on a pointer stored in a second register of the interface controller; and The data in the register is replaced with the second data based at least in part on receiving the write command for the logical row address.

11. An apparatus for memory operation, comprising: a non-volatile memory, the non-volatile memory comprising a memory bank; and an interface controller coupled to the non-volatile memory and operable to cause the apparatus to: a procedure for selecting a physical row address in the memory bank for moving data from a first row of the memory bank to a second row of the memory bank; determining to initiate the program for the first row of the memory bank based at least in part on the physical row address, wherein the physical row address is associated with the first row; issuing, as part of the procedure, a read command to the nonvolatile memory for the physical row address associated with the first row; issuing a write command to the nonvolatile memory and based at least in part on issuing the read command for a second physical row address associated with the second row of the memory bank; and An access command associated with the memory bank is issued to the nonvolatile memory between issuing the read command and the write command.

12. An apparatus for memory operation, comprising: a non-volatile memory comprising a plurality of memory banks; and An interface controller, the interface controller is coupled to the non-volatile memory, the interface controller comprising: a first logic component configured to manage a process of moving data between rows of memory banks in the non-volatile memory; a register coupled to the first logic component and configured to store one or more pointers associated with the row of the memory bank; and a second logic component coupled to the register and configured to convert a logical address received from a host system into a physical row address based at least in part on the one or more pointers stored in the register, and configured to communicate the physical row address to a third logic component that schedules an access command for issuance to the non-volatile memory.

13. The apparatus of claim 12, wherein the interface controller further comprises: A buffer is configured to store data from one row of the memory bank and intended for another row of the memory bank indicated by the one or more pointers.

14. The apparatus of claim 12, wherein the interface controller further comprises: A second register is coupled to the first logic component and is operable to maintain a counter for the memory bank of the plurality of memory banks, wherein the counter for the memory bank indicates a number of activate commands received for the memory bank.

15. The device of claim 12, wherein the one or more pointers are associated with a single memory bank of the plurality of memory banks.

16. The device of claim 12, wherein the one or more pointers are associated with a subset of the plurality of memory banks.

17. The apparatus of claim 13, wherein the interface controller further comprises: A fourth logic component is coupled to the third logic component and is configured to send the access command scheduled by the third logic component to a non-volatile memory.

18. An apparatus for memory operation, comprising: a non-volatile memory, the non-volatile memory comprising a memory bank; and an interface controller coupled to the non-volatile memory and operable to cause the apparatus to: determining a first physical row address of a first row of the memory bank storing data to be transferred to a second row of the memory bank, wherein determining the first physical row address storing the data to be transferred is based at least in part on a pointer associated with an address translation; transmitting a read command for the first physical row address to the nonvolatile memory; transferring the data to a register in the interface controller based at least in part on transmitting the read command; transferring the data from the register to the non-volatile memory; storing the data in the second row of the memory bank based at least in part on transferring the data to the non-volatile memory; and Based at least in part on storing the data in the second row of the memory bank, updating one or more pointers in a second register of the interface controller, wherein the one or more pointers include the pointer associated with an address translation.

19. The apparatus of claim 18, wherein the interface controller is operable to cause the apparatus to: A write command is communicated to the non-volatile memory, wherein the data is stored in the second row of the memory bank based at least in part on the write command.

20. The apparatus of claim 18, wherein the interface controller is operable to cause the apparatus to: Second data is transferred to or from the memory bank after transferring the data to the register and before transferring the data to the non-volatile memory.

21. The apparatus of claim 18, wherein the interface controller is operable to cause the apparatus to: A wear leveling procedure is initiated for the memory bank, wherein the wear leveling procedure includes moving the data from the first row to the second row of the memory bank.

22. The apparatus of claim 21, wherein the interface controller is operable to cause the apparatus to: A determination is made that a threshold duration has expired since a previous wear leveling procedure was completed, wherein the wear leveling procedure is initiated based at least in part on the determination that the threshold duration has expired.

23. The apparatus of claim 21, wherein the interface controller is operable to cause the apparatus to: A determination is made that a threshold number of activation commands have been directed to the memory bank since a previous wear leveling procedure was completed, wherein the wear leveling procedure is initiated based at least in part on determining that the threshold number of activation commands have been directed to the memory bank.

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