A method, apparatus, device, and storage medium for compiling simulation files.

Abstract

This application provides a method, apparatus, device, and storage medium for compiling simulation files, relating to the front-end development field of integrated circuit chips. The method includes: upon receiving a compilation instruction, determining multiple blocks to be compiled and merging information corresponding to the simulation file set according to a first segmentation strategy, wherein each block to be compiled is independent; performing parallel compilation operations based on the multiple blocks to be compiled to obtain multiple compilation results; and performing a linking operation based on the merging information and the multiple compilation results to obtain an executable file. This method enables the compilation time to be controlled within a specified time range as the chip integration scale increases, thus breaking the positive correlation between compilation time and chip integration scale.

Description

Technical Field

[0001] This application relates to the front-end development field of integrated circuit chips. Specifically, this application relates to a method, apparatus, device, and storage medium for compiling simulation files. Background Technology

[0002] In the early stages of integrated circuit chip development, design and verification are inextricably linked. Electronic design automation (EDA) vendors' chip verification technicians send specific stimuli to the chip and detect the response signals to determine if the design's logic and specifications are correct. To meet the demands of large-scale testing, chip verification technicians typically use simulation software to verify the design's correctness. This process generates a large number of simulation files. A crucial task in developing test programs is compiling these simulation files into testable models. As chip integration increases, the number of simulation files also grows (reaching hundreds or even thousands), requiring more hardware resources and increasing compilation time.

[0003] Therefore, the compilation time increases with the integration scale of the chip, exhibiting a positive correlation. How to overcome this positive correlation is an urgent problem to be solved. Summary of the Invention

[0004] The purpose of this application is to address the technical drawback that the compilation time increases as the chip integration scale increases.

[0005] According to one aspect of the embodiments of this application, a method for compiling a simulation file is provided, the method comprising:

[0006] When a compilation instruction is received, the simulation file set is determined according to the first segmentation strategy, including multiple blocks to be compiled and merging information, where each block to be compiled is independent of the others.

[0007] Perform parallel compilation operations on multiple blocks to be compiled to obtain multiple compilation results;

[0008] Based on the merge information and multiple compilation results, a linking operation is performed to obtain the executable file.

[0009] According to another aspect of the embodiments of this application, an apparatus for compiling simulation files is provided, the apparatus comprising:

[0010] The first segmentation module is used to determine multiple blocks to be compiled and merging information corresponding to the simulation file set according to the first segmentation strategy, wherein each block to be compiled is independent of each other.

[0011] The parallel compilation module is used to perform parallel compilation operations on multiple blocks to be compiled, resulting in multiple compilation results.

[0012] The linker module is used to perform linking operations based on merge information and multiple compilation results to obtain an executable file.

[0013] According to another aspect of the present application, an electronic device is provided, the electronic device including a memory, a processor and a computer program stored in the memory, the processor executing the computer program to implement the steps of the method shown in one aspect of the present application.

[0014] According to another aspect of the embodiments of this application, a computer-readable storage medium is provided, on which a computer program is stored, characterized in that, when the computer program is executed by a processor, it implements the steps of the method shown in one aspect of the embodiments of this application above.

[0015] The beneficial effects of the technical solutions provided in this application are:

[0016] This application provides a method for compiling a simulation file. The method mainly involves a series of compilation operations performed after receiving compilation instructions. Specifically, the simulation file is divided according to a first segmentation strategy to obtain multiple blocks to be compiled, along with merging information describing the logical relationships between these blocks. Since the block division is automatic according to the first segmentation strategy, the tediousness of manual block division and the problem of incomplete block division are avoided. Based on the summarized compilation results and merging information, a linking operation is performed to obtain an executable file. Because each block to be compiled is independent, the compilation operations for each block can be performed in parallel. Furthermore, the advantage of the first segmentation strategy is that it controls the estimated compilation time of each block within a specified time range. Therefore, the time required for multiple parallel compilation processes is roughly the same, resulting in the overall compilation time being controlled within the specified time range. Moreover, this method is more effective as the chip integration scale increases. Therefore, as the chip scale increases, the compilation time can be controlled within a specified time range, breaking the positive correlation between compilation time and chip integration scale. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments of this application will be briefly introduced below.

[0018] Figure 1 A flowchart illustrating a method for compiling a simulation file, provided as an embodiment of this application;

[0019] Figure 2aA schematic diagram of the overall compilation process in an application scenario provided by an embodiment of this application;

[0020] Figure 2b A schematic diagram illustrating the compilation process of a single block, provided for an embodiment of this application;

[0021] Figure 2c A schematic diagram of a parallel compilation process provided for an embodiment of this application;

[0022] Figure 3 This is a schematic diagram of a device for compiling simulation files, provided in an embodiment of this application. Detailed Implementation

[0023] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0025] IC: Integrated Circuit. An integrated circuit is a miniature electronic device or component. Using specific processes, transistors, resistors, capacitors, inductors, and other components required for a circuit, along with interconnected wiring, are fabricated on one or several small pieces of semiconductor wafers or dielectric substrates. These are then packaged in a casing to form a miniature structure with the required circuit function, where all components are structurally integrated into a single unit.

[0026] HDL: Hardware Description Language, specifically refers to a new type of language used to describe the behavior, register transfer, or structure of hardware circuits. Currently, the most widely used hardware description languages ​​include ABEL, AHDL, Verilog, and VHDL. Among them, Verilog and VHDL are the two most popular. Since Verilog and VHDL are existing technologies, their descriptions can be found in existing technologies; for simplicity, they will not be elaborated upon here.

[0027] In the embodiments of this application, the language used for the design of integrated circuits can be any of the hardware description languages ​​listed in the prior art.

[0028] Currently, to address the problems mentioned in the background section, EDA vendors commonly use a solution of compiling the chip as a whole, employing incremental compilation to improve efficiency. However, for a complex design, chip design progresses towards functionalization from beginning to end. Therefore, when the chip design reaches maturity, a significant portion of the circuit logic remains identical between two compiled versions, meaning it hasn't been modified. This is especially true in later compilations, where the results of unchanged parts from the previous compilation can be reused. Existing technology considers reusing the results of unchanged parts from the previous compilation in later compilations as incremental compilation. Thus, incremental compilation can significantly improve compilation efficiency. Furthermore, EDA vendors also offer block-based compilation techniques based on functional design principles to further enhance compilation efficiency.

[0029] Because this incremental compilation method relies on the timestamps of some simulation files, it cannot accurately determine whether the content of other simulation files has changed. Furthermore, due to the coupling relationships between modules, incremental compilation may not be the right choice. In addition, block compilation technology often requires manual planning of module boundaries, which increases the complexity of the compilation process and significantly raises the probability of problems.

[0030] Therefore, the compilation time increases with the size of the chip integration, exhibiting a positive correlation. How to overcome this positive correlation is an urgent problem to be solved.

[0031] To address the aforementioned technical problems, embodiments of this application provide a method, apparatus, device, and storage medium for compiling simulation files. The method can be implemented by a terminal device / system. The device / system involved in this application embodiment is capable of running applications that can compile simulation files. This terminal device / system connects to a server or contains a server itself, and the server is used to compile simulation files.

[0032] The technical solutions of this application and their effects are described below through several exemplary embodiments. It should be noted that the following embodiments can be referenced, borrowed from, or combined with each other. Identical terms, similar features, and similar implementation steps in different embodiments will not be repeated.

[0033] Figure 1 A flowchart illustrating a method for compiling simulation files provided in this application embodiment is shown below. Figure 1 As shown, the method includes the following steps:

[0034] S110, when a compilation instruction is received, the multiple blocks to be compiled and the merging information corresponding to the simulation file set are determined according to the first segmentation strategy, wherein each block to be compiled is independent of the others.

[0035] Upon receiving the compilation instruction, the terminal device / system reads the identifier of the project to be compiled carried in the compilation instruction. This project includes multiple simulation files, which together form a simulation file set. Specifically, this project is a design project for an integrated circuit. The project records the storage path and filename of each simulation file, the reference relationships between each file, and the reference or link relationships between interfaces or modules within each file.

[0036] For example, the simulation file set may include files with the following suffixes: .v (programs written in Verilog, used to describe the components, connections, and logic of hardware circuits), .c (C language, used for hardware circuit modeling), .vhdl (programs written in VHDL, used to describe the components, connections, and logic of hardware circuits), .sv (Verilog language, used to describe the components, connections, and logic of hardware circuits, as well as chip verification environments), .h (header files corresponding to C language files, which may include various macro definitions and referenced library files; this type of file generally participates in pre-compilation), .vh or .svh (header files corresponding to Verilog language; this type of file participates in compilation along with files with the .sv suffix), etc. It should be noted that files with the .c suffix represent files written in C language, files with the .vhdl suffix represent simulation files written in VHDL language, and .v files represent simulation files written in Verilog language; other file types follow the same logic.

[0037] S120 performs parallel compilation operations based on multiple blocks to be compiled, resulting in multiple compilation results.

[0038] The multiple compilation results can consist of the compilation results of each block to be compiled, or they can consist of the compilation results of some blocks to be compiled, as well as the compilation results of the sub-blocks to be compiled corresponding to some blocks to be compiled.

[0039] S130 performs a linking operation based on the merge information and multiple compilation results to obtain an executable file.

[0040] This application provides a method for compiling a simulation file. The method mainly involves a series of compilation operations performed after receiving compilation instructions. Specifically, the simulation file is divided according to a first segmentation strategy to obtain multiple blocks to be compiled, along with merging information describing the logical relationships between these blocks. Since the segmentation is automatic according to the first segmentation strategy, the tediousness of manual segmentation and the problem of incomplete segmentation are avoided. Based on the summarized compilation results and merging information, a linking operation is performed to obtain an executable file. Because each block to be compiled is independent, the compilation operations for each block can be performed in parallel. Furthermore, the advantage of the first segmentation strategy is that it controls the estimated compilation time of each block within a specified time range. Therefore, the time required for multiple parallel compilation processes is roughly the same, resulting in the overall compilation time being controlled within the specified time range. Moreover, this method is more effective as the chip integration scale increases. Therefore, as the chip integration scale increases, the compilation time can be controlled within a specified time range, thus breaking the positive correlation between compilation time and chip integration scale.

[0041] This application provides a possible implementation method. Before compilation, the simulation file set needs to be segmented. The first segmentation strategy provided in this application specifically includes two segmentation approaches: initial segmentation based on existing segmentation information corresponding to the simulation file set, or initial segmentation according to a preset strategy. Therefore, this application specifically includes S111 and S112 (not shown in the figure), specifically:

[0042] S111, when historical segmentation information corresponding to the simulation file set exists, or when manual segmentation information corresponding to the simulation file set exists, the simulation file set is segmented according to the historical segmentation information or the manual segmentation information to obtain multiple blocks to be compiled, and segmentation information corresponding to each block to be compiled in the multiple blocks to be compiled.

[0043] or,

[0044] S112, when the historical segmentation information and manual segmentation information corresponding to the simulation file set do not exist, the simulation file set is segmented according to the allocated server resources, the type of each simulation file and the estimated compilation time to obtain multiple blocks to be compiled, as well as the segmentation information corresponding to each block to be compiled.

[0045] Historical segmentation information or manual segmentation information is based on the experience summarized from previous compilation processes or the experience of designers. It is difficult to use during the first compilation or in the early stages of integrated circuit design. However, this segmentation strategy is frequently used in the mature stage of integrated circuit design to save compilation time.

[0046] On the one hand, since the design of large-scale integrated circuits is generally geared towards functionalization, the resulting simulation file set can be divided into multiple modules. On the other hand, the general hardware circuit design process follows a top-down design principle. Therefore, after dividing the simulation file set into hierarchical levels according to the top-down principle, the functions represented by the top-level or first few layers of files are divided into several blocks. There are also some common files in this simulation file set, which can also be considered as a block.

[0047] Specifically, the server is the primary hardware resource for compiling simulation files. Since multiple compilation blocks need to be compiled in parallel (each CPU on the server handles the compilation of one block during actual compilation), the number of blocks should be determined based on the number of servers provided and their hardware configuration (e.g., the number of CPUs per server). Because the server compiles each simulation file serially when compiling the blocks, the actual compilation time for each block is the sum of the actual compilation times of each simulation file within that block. Since the compilation time varies for each type of simulation file—files with the .vhdl extension take significantly longer to compile, while files with .h or .c extensions take relatively shorter—it is also necessary to consider the type of simulation file to estimate the compilation time for each file.

[0048] In addition, since the top-down principle is also taken into account when dividing the blocks, each block to be compiled can remain independent of the others.

[0049] Specifically, the segmentation information corresponding to the block to be compiled may include the name of the block to be compiled (generally the filename of the top-level file, and the name of the first function executed in the top-level file). The block to be compiled includes the name and storage path of each simulation file, and the connection relationship with other blocks, etc.

[0050] In one possible implementation, determining the merging information includes: determining the merging information based on the segmentation information corresponding to each block to be compiled.

[0051] Specifically, the split set of files to be compiled becomes multiple independent modules. In the later linking operation, it is necessary to link multiple compilation results. Therefore, it is also necessary to create the connection relationship between each block to be compiled, that is, to determine the merging information based on the splitting information corresponding to each block to be compiled.

[0052] The first segmentation strategy in the method for compiling simulation files provided in this application includes two segmentation approaches. In the first approach, the historical segmentation information and manual segmentation information fully leverage the advantages of accumulated experience and technical personnel skills from previous compilation processes. Segmentation based on this experience ensures that the estimated compilation time of each segmented block is controlled within a specified timeframe. Conversely, if no prior experience is available, reasonable segmentation is performed based on the type of each simulation file, its estimated compilation time, and the allocated server resources. This also allows the estimated compilation time of each segmented block to be compiled to be controlled within a specified range, thus providing a solid foundation for subsequent parallel compilation. After obtaining the segmentation information for each block, merging information can be determined based on this information to facilitate linking the compilation results during the linking operation, thereby obtaining an executable file.

[0053] Because the simulation files involved in this application involve complex algorithms and a large amount of computation, the hardware of ordinary computer devices is generally insufficient to support the calculations required during the compilation process. Therefore, such simulation files are typically sent to a server for compilation.

[0054] This application embodiment also provides a possible implementation method, which performs parallel compilation operations on multiple blocks to be compiled to obtain multiple compilation results, including S121 and S122 (not shown in the figure):

[0055] S121, assign a server to each of the multiple blocks to be compiled;

[0056] S122, in parallel, perform the following operations for each of the multiple blocks to be compiled: when the block to be compiled meets the preset conditions, send the block to be compiled to the corresponding server for compilation; obtain the actual compilation time corresponding to the compilation operation; and determine whether to determine the compilation result corresponding to the compilation operation as one of the multiple compilation results based on the relationship between the actual compilation time and the preset time threshold.

[0057] In one possible implementation, obtaining the actual compilation time corresponding to the compilation operation specifically includes: obtaining the actual compilation time corresponding to the compilation operation through the monitor of the terminal device / system.

[0058] In addition, if the block to be compiled is not the block obtained from the initial segmentation, the corresponding segmentation information also needs to be obtained.

[0059] The preset condition is whether the chunk to be compiled does not conform to the incremental compilation standard. If it does not conform to the incremental compilation standard, it needs to be sent to the server for compilation.

[0060] In one possible implementation, when the block to be compiled meets the incremental compilation conditions, the method further includes: performing an incremental compilation operation and determining the compilation result of the incremental compilation operation as one of multiple compilation results.

[0061] The criterion for determining whether to perform incremental compilation on a simulation file is based on the timestamp of the simulation file, which is the timestamp of the last modification to the simulation file. The criterion for determining whether to perform incremental compilation on a block to be compiled is based on the timestamps of all simulation files in the block to be compiled.

[0062] Specifically, the most recent compilation result of the block to be compiled is obtained, along with the compilation time of the compilation operation. If the timestamp of any file in the block to be compiled corresponds to a time point before the compilation time point, it is determined that the incremental compilation standard is met. If the timestamp of any file in the block to be compiled corresponds to a time point after the compilation time point, it indicates that some files in the block to be compiled have been modified, and the modification operation occurred after the compilation time point. Therefore, it is determined that the incremental compilation standard is not met, and the block to be compiled needs to be recompiled.

[0063] In the design process of large-scale integrated circuits, there may be thousands or even tens of thousands of files. When determining whether to incrementally compile a simulation file, it is necessary to check not only the timestamp of the simulation file but also the timestamps of other files associated with it. This undoubtedly increases the compilation time. Among these other files are header files. However, since header files (e.g., header files with the .h extension) are already compiled during the pre-compilation stage, if a header file is modified, its timestamp cannot be obtained during the formal compilation stage. Therefore, if no other files besides the header file have been modified, the result of incremental compilation will be that incremental compilation is possible, leading to incorrect compilation results. In the incremental compilation judgment conditions provided in this application, since each block to be compiled is an independent entity, and each block to be compiled contains only a few or dozens of files, the scope of judging whether incremental compilation conditions are met can be expanded to every simulation file in the block to be compiled (including the aforementioned header files with the .h extension). By checking the timestamps of all simulation files in the block to be compiled, it is determined whether incremental compilation is required. If incremental compilation is not required, compilation is performed via the server. Compared to existing technologies, the incremental compilation determination method provided in this application improves the accuracy of compilation operations. It should be noted that the timestamp of a file involved in this application embodiment is specifically used to identify the time when the file was last modified.

[0064] For example, the modification includes adding new code content, which may specifically include adding new components, new circuit logic, etc.

[0065] The method for compiling simulation files provided in this application embodiment can also perform incremental compilation operations on blocks that meet the incremental compilation conditions during the compilation operation on the server, that is, use historical compilation results. This method has the technical effect of significantly shortening the compilation time of the blocks to be compiled.

[0066] While the multiple compilation blocks obtained according to the first segmentation strategy have some merit, if the designer makes too many changes to some of these blocks, segmenting them based on experience or pre-set strategies can still lead to actual compilation times far exceeding the estimated times. Therefore, the first segmentation strategy has shortcomings in certain situations.

[0067] This application embodiment also provides a possible implementation method, which uses the compilation time obtained by the monitor during the compilation process to determine whether it is necessary to further divide the block to be compiled according to the second segmentation strategy. Specifically: when the actual compilation time is less than or equal to a first time threshold and greater than a preset second time threshold, the compilation result corresponding to the compilation operation is determined as one of multiple compilation results, wherein the first time threshold is greater than the second time threshold. Alternatively, when the actual compilation time is greater than the preset first time threshold, the block to be compiled is divided according to the second segmentation strategy to obtain multiple sub-blocks to be compiled, and the segmentation information of each sub-block to be compiled; based on the relationship between the actual compilation time of each sub-block to be compiled and the preset time threshold, it is determined whether to divide the corresponding sub-block to be compiled according to the second segmentation strategy; when the corresponding sub-block to be compiled does not need to be divided, the segmentation information of the corresponding sub-block to be compiled is updated to the merging information, and the compilation result corresponding to the corresponding sub-block to be compiled is determined as one of multiple compilation results.

[0068] Specifically, after obtaining multiple sub-blocks to be compiled, a server is allocated to each sub-block, and then each sub-block is compiled in parallel. During the compilation process, a monitor tracks the compilation process of each sub-block, obtaining the compilation result and corresponding segmentation information for each sub-block.

[0069] Specifically, when a sub-block to be compiled no longer needs to be split, its splitting information can be updated in the merge information. In the subsequent linking operation, the connection relationships between each compilation result can be determined based on the connection relationships between the sub-blocks and other blocks or between sub-blocks recorded in the merge information, and then the linking operation can be performed.

[0070] In one possible implementation, when the corresponding sub-block to be compiled does not need to be split, the method further includes: storing the compilation result of the sub-block to be compiled or the compilation result of the sub-block to be compiled, and sharing it to the public area of ​​the terminal device / system line, so that other chip designers can refer to the compilation result when they need to perform compilation operations on the simulation file set.

[0071] In addition, the segmentation information corresponding to the block to be compiled, or the segmentation information corresponding to the sub-block to be compiled, is stored to form historical segmentation information.

[0072] In one possible implementation, after obtaining the actual compilation time of each sub-block to be compiled, the method further includes: determining whether the actual compilation time is within a first time threshold and a second time threshold.

[0073] When the actual compilation time is greater than the second time threshold but less than or equal to the first time threshold, it is determined that the sub-block to be compiled does not need to be segmented; when the actual compilation time is greater than the first time threshold, the sub-block to be compiled needs to be segmented again according to the second segmentation strategy. It should be noted that the process of segmentation and verification of whether the segmentation is successful can refer to other implementation methods provided in the embodiments of this application, and will not be elaborated here for the sake of simplicity.

[0074] In addition, in the embodiments of this application, the division of blocks to be compiled or sub-blocks to be compiled is required until the actual compilation time of the sub-blocks is not greater than a first time threshold.

[0075] When the actual compilation time is less than the second time threshold, the sub-block to be compiled is merged into other sub-blocks with the shortest actual compilation time.

[0076] In one possible implementation, the blocks to be compiled are divided according to the second segmentation strategy to obtain multiple sub-blocks to be compiled, as well as the segmentation information corresponding to each sub-block to be compiled.

[0077] Specifically, all simulation files in the block to be compiled are determined, as well as the estimated compilation time of each simulation file; all simulation files are sequentially combined or split to obtain multiple sub-blocks to be compiled, wherein the estimated compilation time of the sub-block to be compiled is greater than the second time threshold and less than or equal to the first time threshold, and each sub-block to be compiled is independent of each other.

[0078] For example, the first time threshold is 2 hours, and the second time threshold is 20 minutes. This is because the compilation time needs to be controlled to prevent it from being too long or too short, as excessively short compilation times waste compilation resources (e.g., server resources). The block to be compiled contains 100 files, of which 95 files have a compilation time of 1 minute each, and the other 5 files have compilation times of 1 hour, 30 minutes, 27 minutes, 50 minutes, and 48 minutes respectively. First, following a top-down approach, the structure of the block to be compiled is shown. From the top-level files, several files are selected as the basis for sub-blocks. Then, based on these files, other related files are added to the sub-blocks. Finally, the estimated compilation time for each sub-block is determined. Sub-blocks with estimated compilation times between 20 minutes and 2 hours are selected as the sub-blocks to be compiled. Other sub-blocks with estimated compilation times outside this range are further split until the estimated compilation time of the split sub-blocks falls within the 20 minutes to 2 hours range.

[0079] In addition, by dividing the blocks to be compiled according to the top-down principle, each sub-block to be compiled can remain independent of each other.

[0080] The method for compiling simulation files provided in this application can check whether the blocks to be compiled according to the first segmentation strategy are reasonable during the compilation process. If they are not reasonable, improvements are made. Since the first segmentation strategy calculates the estimated compilation time, and the content of some simulation files in the current simulation file set is updated, the actual compilation time may exceed the ideal compilation time. Therefore, further segmentation is required. If blocks with unsatisfactory actual compilation times still appear after segmentation, further segmentation is required until the actual compilation time of all blocks is within the ideal compilation time range. After the segmentation is completed, the segmentation information needs to be updated to the merging information, and the compilation results of the segmented blocks will also be used as the final compilation results.

[0081] To more clearly describe the embodiments of this application, the embodiments of this application also provide Figure 2a , Figure 2b and Figure 2c Let's explain further. Among them, Figure 2a The parallel compilation process, indicated by the dashed box, specifically refers to... Figure 2b and Figure 2c The process shown; Figure 2c The middle part refers to the compilation indicated by the dashed line, which is the allocation server. Figure 2b The process shown; Figure 2c Specifically, execution begins from block 1 to block N.

[0082] See Figure 2aThis application embodiment also provides a method for compiling simulation files provided in the above embodiments, and a specific application example to provide a process for overall compilation in an application scenario.

[0083] In this diagram, the first step is to determine if there is any segmentation information. Specifically, it checks for historical or manually generated segmentation information. If so, the simulation file is segmented based on the existing segmentation information, resulting in blocks 1 through N (corresponding to multiple blocks to be compiled in the above embodiment), and a merge information file is generated accordingly. If not, the file is segmented according to server resources, the file type of each simulation file in the simulation file set, and the estimated compilation time, following a top-down approach, and a merge information file is generated. In the parallel compilation process, blocks 1 through N are compiled in parallel. After compilation, the compilation result for each block is obtained. According to the connection logic between each block recorded in the merge information file, a linking operation is performed on the compilation results of each block, ultimately obtaining the completed compilation result, which is then an executable file.

[0084] After identifying multiple compilation blocks, a server is assigned to each block before the parallel compilation process begins. The following section uses the compilation process of block 1 as an example to illustrate the block compilation process.

[0085] See Figure 2b This application also provides a process for compiling a single block.

[0086] Determine if block 1 meets the conditions for incremental compilation. If it does, perform incremental compilation, thus ending the compilation process for block 1. The result of the most recent compilation operation for block 1 is used as the result of the current compilation process.

[0087] If it does not meet the requirements, block 1 will be sent to the server for compilation.

[0088] See Figure 2c This application also provides a parallel compilation process in its embodiments.

[0089] If block 1 does not meet the conditions for incremental compilation, it needs to be sent to the server for compilation. During the compilation process of block 1 on the server, the compilation process is monitored by the terminal device / system monitor, and after compilation is completed, the actual compilation time and corresponding segmentation information of block 1 are obtained. It is determined whether the actual compilation time is within the expected time (e.g., between 20 minutes and 2 hours). If it is, the segmentation is reasonable. If the actual compilation time is not within the expected time and is large, it needs to be segmented again. That is, block 1 is divided into sub-blocks 11 to 1N, where the estimated compilation time of each sub-block is within the expected time and they are independent of each other. Then, each sub-block is sent to the server again for compilation in parallel, and the actual compilation time of each sub-block is obtained again. Similarly, it is determined whether the actual compilation time of the sub-block meets the expected time. If it does, the segmentation information corresponding to the sub-block is fed back and the merged file is updated. If it does not meet the conditions, the sub-blocks that do not meet the conditions need to be segmented, compiled, and judged again until the actual compilation time of each sub-block is within the expected time.

[0090] See Figure 3 This application provides an apparatus 300 for compiling simulation files, which may include:

[0091] The first segmentation module 310 is used to determine multiple blocks to be compiled and merging information corresponding to the simulation file set according to the first segmentation strategy, wherein each block to be compiled is independent of each other; the parallel compilation module 320 is used to perform parallel compilation operations based on the multiple blocks to be compiled to obtain multiple compilation results; the linking module 330 is used to perform linking operations based on the merging information and multiple compilation results to obtain an executable file.

[0092] This application embodiment also provides a possible implementation, wherein the simulation file set includes multiple simulation files, and the first segmentation module 310, in determining the multiple blocks to be compiled corresponding to the simulation file set according to the first segmentation strategy, is specifically used for:

[0093] When historical segmentation information corresponding to the simulation file set exists, or when manual segmentation information corresponding to the simulation file set exists, the simulation file set is segmented according to the historical segmentation information or the manual segmentation information to obtain multiple blocks to be compiled, and segmentation information corresponding to each block to be compiled in the multiple blocks to be compiled.

[0094] or,

[0095] When the historical segmentation information and manual segmentation information corresponding to the simulation file set are not available, the simulation file set is segmented according to the allocated server resources, the type of each simulation file and the estimated compilation time, to obtain multiple blocks to be compiled, as well as the segmentation information corresponding to each block to be compiled.

[0096] In one possible implementation, the first segmentation module 310, in determining the merging information, is specifically used to: determine the merging information based on the segmentation information corresponding to each block to be compiled.

[0097] This application embodiment also provides a possible implementation method in which the parallel compilation module 320, in performing parallel compilation operations on multiple compilation blocks to obtain multiple compilation results, specifically performs the following: allocating a server for each of the multiple compilation blocks; and performing the following operations in parallel for each of the multiple compilation blocks to be compiled: when the compilation block meets a preset condition, sending the compilation block to the corresponding server for compilation operation; obtaining the actual compilation time corresponding to the compilation operation; and determining whether to determine the compilation result corresponding to the compilation operation as one of the multiple compilation results based on the relationship between the actual compilation time and a preset time threshold.

[0098] In one possible implementation, the parallel compilation module 320 determines whether to select the compilation result corresponding to the compilation operation as one of multiple compilation results based on the relationship between the compilation time and a preset time threshold. Specifically, when the actual compilation time is less than or equal to a first time threshold and greater than a preset second time threshold, the compilation result corresponding to the compilation operation is selected as one of multiple compilation results, wherein the first time threshold is greater than the second time threshold.

[0099] In one possible implementation, the device includes a second segmentation module 340, which is specifically used to: when the actual compilation time is greater than a preset first time threshold, segment the block to be compiled according to a second segmentation strategy to obtain multiple sub-blocks to be compiled, and segmentation information of each sub-block to be compiled in the multiple sub-blocks to be compiled.

[0100] The second segmentation module 340 is specifically used to determine all simulation files in the block to be compiled, as well as the estimated compilation time of each simulation file; and to perform combination or segmentation operations on all simulation files in sequence to obtain multiple sub-blocks to be compiled. The estimated compilation time of the sub-block to be compiled is greater than the second time threshold and less than or equal to the first time threshold. The multiple sub-blocks to be compiled are independent of each other.

[0101] The parallel compilation module 320 is also used to determine whether to divide the corresponding sub-blocks to be compiled according to the second segmentation strategy based on the relationship between the actual compilation time of each sub-block to be compiled and the preset time threshold. When the corresponding sub-block to be compiled does not need to be divided, the segmentation information of the corresponding sub-block to be compiled is updated to the merging information, and the compilation result corresponding to the corresponding sub-block to be compiled is determined to be one of multiple compilation results.

[0102] In one possible implementation, the preset condition is whether the block to be compiled does not meet the incremental compilation standard. The parallel compilation module 320 is also used to: when the block to be compiled meets the incremental compilation condition, perform incremental compilation operation, and determine the compilation result of the incremental compilation operation as one of multiple compilation results.

[0103] This application provides an electronic device, including a memory, a processor, and a computer program stored in the memory. The processor executes the computer program to implement the steps of a method for compiling a simulation file as shown in this application. Compared with the prior art, this method can achieve the following: as the integration scale of the chip increases, the compilation time can be controlled within a specified time range, thus breaking the positive correlation between compilation time and chip integration scale.

[0104] This application provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it can implement the steps and corresponding content of the aforementioned method embodiments.

[0105] Those skilled in the art should understand that, unless otherwise stated, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the terms “comprising” and “including” as used in embodiments of this application mean that the corresponding feature can be implemented as the presented feature, information, data, step, operation, element, and / or component, but do not exclude implementation as other features, information, data, step, operation, element, component, and / or combinations thereof supported by the art. It should be understood that when we say that an element is “connected” or “coupled” to another element, the one element can be directly connected or coupled to the other element, or it can mean that the one element and the other element establish a connection relationship through an intermediate element. Furthermore, “connected” or “coupled” as used herein can include wireless connection or wireless coupling. The term “and / or” as used herein indicates at least one of the items defined by the term; for example, “A and / or B” indicates implementation as “A,” or implementation as “A,” or implementation as “A and B.”

[0106] It should be understood that although arrows indicate various operation steps in the flowcharts of this application's embodiments, the order in which these steps are implemented is not limited to the order indicated by the arrows. Unless explicitly stated herein, in some implementation scenarios of this application's embodiments, the implementation steps in each flowchart can be executed in other orders as required. Furthermore, some or all steps in each flowchart, based on the actual implementation scenario, may include multiple sub-steps or multiple stages. Some or all of these sub-steps or stages can be executed at the same time, and each sub-step or stage can also be executed at different times. In scenarios where execution times differ, the execution order of these sub-steps or stages can be flexibly configured according to requirements, and this application's embodiments do not limit this.

[0107] The above description is only an optional implementation method for some implementation scenarios of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application without departing from the technical concept of this application also fall within the protection scope of the embodiments of this application.

Claims

1. A method for compiling simulation files, characterized in that, include: When a compilation instruction is received, the simulation file set is determined according to the first segmentation strategy, including multiple blocks to be compiled and merging information, where each block to be compiled is independent of the others. Perform parallel compilation operations on the multiple blocks to be compiled to obtain multiple compilation results; Based on the merged information and the multiple compilation results, a linking operation is performed to obtain an executable file; The parallel compilation operation based on the multiple blocks to be compiled, resulting in multiple compilation results, includes: Assign a server to each of the plurality of blocks to be compiled; In parallel, perform the following operations for each of the plurality of blocks to be compiled: When the block to be compiled meets the preset conditions, the block to be compiled is sent to the corresponding server for compilation. Obtain the actual compilation time corresponding to the compilation operation; Based on the relationship between the actual compilation time and the preset time threshold, determine whether to determine the compilation result corresponding to the compilation operation as one of the multiple compilation results; The step of determining whether to identify the compilation result corresponding to the compilation operation as one of the plurality of compilation results based on the relationship between the actual compilation time and the preset time threshold includes: When the actual compilation time is greater than the preset first time threshold, the block to be compiled is divided according to the second segmentation strategy to obtain multiple sub-blocks to be compiled, and the segmentation information of each sub-block to be compiled in the multiple sub-blocks to be compiled; Based on the relationship between the actual compilation time of each sub-block to be compiled and the preset time threshold, determine whether to divide the corresponding sub-block to be compiled according to the second segmentation strategy; When the corresponding sub-block to be compiled does not need to be split, the splitting information of the corresponding sub-block to be compiled is updated to the merging information, and the compilation result corresponding to the corresponding sub-block to be compiled is determined to be one of the multiple compilation results; The step of segmenting the block to be compiled according to the second segmentation strategy to obtain multiple sub-blocks to be compiled, and the segmentation information of each sub-block to be compiled, includes: Determine all simulation files in the block to be compiled, and the estimated compilation time for each simulation file; All the simulation files are sequentially combined or split to obtain multiple sub-blocks to be compiled. The estimated compilation time of each sub-block to be compiled is greater than a preset second time threshold and less than or equal to the first time threshold. The multiple sub-blocks to be compiled are independent of each other.

2. The method according to claim 1, characterized in that, The simulation file set includes multiple simulation files, and the step of determining multiple blocks to be compiled corresponding to the simulation file set according to the first segmentation strategy includes: When the historical segmentation information corresponding to the simulation file set exists, or when the manual segmentation information corresponding to the simulation file set exists, the simulation file set is segmented according to the historical segmentation information or the manual segmentation information to obtain the plurality of blocks to be compiled, and the segmentation information corresponding to each block to be compiled in the plurality of blocks to be compiled; or, When the historical segmentation information and the manual segmentation information corresponding to the simulation file set are not available, the simulation file set is segmented according to the allocated server resources, the type of each simulation file and the estimated compilation time to obtain the multiple blocks to be compiled, and the segmentation information corresponding to each block to be compiled.

3. The method according to claim 2, characterized in that, Determining the merged information includes: The merging information is determined based on the segmentation information corresponding to each block to be compiled.

4. The method according to claim 1, characterized in that, The step of determining whether to identify the compilation result corresponding to the compilation operation as one of the plurality of compilation results based on the relationship between the actual compilation time and the preset time threshold further includes: When the actual compilation time is less than or equal to the first time threshold and greater than the second time threshold, the compilation result corresponding to the compilation operation is determined as one of the plurality of compilation results, wherein the first time threshold is greater than the second time threshold.

5. The method according to claim 1, characterized in that, The preset condition is whether the block to be compiled does not conform to the incremental compilation standard, and the method further includes: When the block to be compiled meets the incremental compilation conditions, an incremental compilation operation is performed, and the compilation result of the incremental compilation operation is determined as one of the multiple compilation results.

6. An apparatus for compiling simulation files, characterized in that, The device includes: The first segmentation module is used to determine multiple blocks to be compiled and merging information corresponding to the simulation file set according to the first segmentation strategy, wherein each block to be compiled is independent of each other. The parallel compilation module is used to perform parallel compilation operations based on the multiple blocks to be compiled, and obtain multiple compilation results; The linking module is used to perform a linking operation based on the merged information and the multiple compilation results to obtain an executable file; Specifically, the parallel compilation module is used for: Assign a server to each of the plurality of blocks to be compiled; In parallel, perform the following operations for each of the plurality of blocks to be compiled: When the block to be compiled meets the preset conditions, the block to be compiled is sent to the corresponding server for compilation. Obtain the actual compilation time corresponding to the compilation operation; Based on the relationship between the actual compilation time and the preset time threshold, determine whether to determine the compilation result corresponding to the compilation operation as one of the multiple compilation results; Specifically, when the parallel compilation module performs the operation of determining whether to assign the compilation result corresponding to the compilation operation to one of the multiple compilation results based on the relationship between the actual compilation time and the preset time threshold, it is used for: When the actual compilation time is greater than the preset first time threshold, the block to be compiled is divided according to the second segmentation strategy to obtain multiple sub-blocks to be compiled, and the segmentation information of each sub-block to be compiled in the multiple sub-blocks to be compiled; Based on the relationship between the actual compilation time of each sub-block to be compiled and the preset time threshold, determine whether to divide the corresponding sub-block to be compiled according to the second segmentation strategy; When the corresponding sub-block to be compiled does not need to be split, the splitting information of the corresponding sub-block to be compiled is updated to the merging information, and the compilation result corresponding to the corresponding sub-block to be compiled is determined to be one of the multiple compilation results; Specifically, when the parallel compilation module performs the operation of dividing the block to be compiled according to the second segmentation strategy to obtain multiple sub-blocks to be compiled, and the segmentation information of each sub-block to be compiled, the operation is used to: Determine all simulation files in the block to be compiled, and the estimated compilation time for each simulation file; All the simulation files are sequentially combined or split to obtain multiple sub-blocks to be compiled. The estimated compilation time of each sub-block to be compiled is greater than a preset second time threshold and less than or equal to the first time threshold. The multiple sub-blocks to be compiled are independent of each other.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the steps of the method according to any one of claims 1-5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-5.

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