FPGA routing method that uses idle logic resources to improve routing efficiency

Abstract

The present application discloses an FPGA wiring method for improving wiring efficiency by utilizing vacant logic resources, and relates to the field of FPGA. The method adds an intervention step in the conventional wiring iteration process. For a pending area that is determined to be difficult to resolve resource conflicts, a new signal path is formed by the vacant logic resources in the area and added to the wiring diagram, that is, the vacant logic resources whose input and output ends are originally not connected on the wiring diagram are converted into wiring resources with connected paths. In this way, it is unrealistic to continue iterating, and the wire network in the candidate area can have more optional paths, making resource conflicts easier to resolve, improving wiring efficiency, and speeding up wiring completion.

Description

Technical Field

[0001] The present invention relates to the field of FPGA, and in particular to an FPGA wiring method for improving wiring efficiency by utilizing idle logic resources. Background Art

[0002] FPGA routing is the process of connecting the occupied logic units using the device's programmable interconnection resources after the chip is laid out. When routing the FPGA, it is generally necessary to abstract the programmable logic resources on the FPGA, including the interconnection resources, into a wiring diagram. The wiring diagram has representations of all underlying modules, architectures, and interconnection resources. Then, a signal to be processed is selected in a predetermined order, and the source and destination module locations related to the signal are found according to the chip layout results. The wiring diagram is searched using a wiring algorithm such as a congestion negotiation algorithm to find unoccupied resources to obtain a routing path from the source to the destination. If no path with completely unoccupied resources is found, the routing path of this signal can be obtained by forcibly using resources that have been occupied by other signals. At this time, the resource is repeatedly occupied by multiple signals to form a conflict, and the conflict needs to be resolved later. The routing path used by this signal is recorded on the wiring diagram, and the corresponding resource is marked as occupied. The above process is repeated until all signals have a routing path, and then the signals with duplication or conflict are rerouted to resolve the conflict until there is no conflict in which the routing resources are reused by multiple signals to obtain the routing result.

[0003] The commonly used FPGA routing algorithm is the congestion negotiation algorithm, which is as follows. Please combine Figure 1 The process shown:

[0004] (1) Create a wiring diagram and read in the user's design netlist and constraints.

[0005] (2) Select the network in the user design netlist that does not have a connection tree or the node in the existing connection tree that involves resource sharing conflicts. If the line network If the tree is not connected yet, proceed directly to step (3). If there is already a connection tree containing nodes involved in resource sharing conflicts, the line network All existing connection trees are removed and cleared for rewiring, and then step (3) is executed.

[0006] (3) Line mesh The source Put into connection tree Middle pair connection tree initialization.

[0007] (4) Initialize the priority queue PQ (PrioritQueue) to a connection tree , set the routing cost of all nodes in the priority queue PQ to 0. In the first loop, the connection tree Only the source point , so there are only source points in the priority queue PQ .

[0008] (5) Remove the node m with the lowest wiring cost from the priority queue PQ and check whether the node m is a wire mesh. destination point.

[0009] (6) If node m is not a wire network Destination , traverse all fan-out nodes n of node m and add them to PQ, and determine the routing cost of each fan-out node n as cost=cn+Pim, where cn is the node cost of the fan-out node n and Pim is the source node The total cost to node m is expressed as the historical cost of the fan-out node n. Re-execute step (4).

[0010] (7) If node m is a wire network Destination , then by the destination point (Point m) trace back to the source point , update the node cost cn of all nodes on the path, and add all nodes on the path to the network Connection tree Update the connection tree , execute steps (3) to (4) again until the wire network is found When updating the node cost cn, it is generally updated based on the number of shared conflicts, the length of the routing resources, the timing redundancy, etc. of the node.

[0011] In the above method, the node cost cn of the node with resource sharing conflict increases cumulatively, so it is less likely to be selected as a path when searching for a new routing path, which can reduce the probability of resource sharing conflict. Repeat the above (2) to (7) to traverse each wire net in the user design netlist that has not been routed or has routing path conflicts, and iterate until the conflict is eliminated, all wire nets in the user design netlist are routed, and there is no resource sharing conflict between all connection trees. When the congestion is too high and the number of resource sharing conflicts is large, the wire nets involved in the resource sharing conflict may not be able to find unoccupied resources and are difficult to separate, and the conflict cannot be eliminated; or the congestion negotiation progresses slowly, causing the operation to time out or the number of iterations to reach the set threshold, which will lead to routing failure. Routing takes up a lot of running time in the FPGA application development process. The quality and efficiency of routing directly affect the application development efficiency and user experience. Summary of the invention

[0012] In view of the above problems and technical requirements, the inventors have proposed an FPGA wiring method that utilizes idle logic resources to improve wiring efficiency. The technical solution of the present invention is as follows:

[0013] An FPGA wiring method for improving wiring efficiency by utilizing idle logic resources, the method comprising:

[0014] In the process of implementing routing for each net in the user input netlist based on the routing diagram using a preset routing algorithm, when the routing iteration process for the user input netlist reaches a predetermined condition, the number of resource conflicts for each region in the FPGA is determined based on the current connection tree of each net, each region includes a number of routing resource nodes, and the number of resource conflicts for the region reflects the situation in which each routing resource node in the current region is shared by multiple nets and thus forms a resource conflict;

[0015] Select the area to be processed with serious resource conflicts based on the number of resource conflicts in each area;

[0016] Select an empty logic resource not occupied by an instance in the area to be processed, and configure it to form a logic function whose output is equal to the input to form a new signal path and add it to the wiring diagram;

[0017] Based on the updated wiring diagram, the user input netlist is iterated by using the preset wiring algorithm until the number of resource conflicts in all areas is 0.

[0018] Its further technical solution is that when the number of global iterations reaches a predetermined number of iterations, it is determined that the routing iteration process of the user input netlist has reached a predetermined condition, wherein one routing for a net in the user input netlist is a global iteration, and one routing for a net includes initial routing for the net, or removing the existing routing of the net and rewinding it.

[0019] A further technical solution is to select areas with serious resource conflicts to be processed based on the number of resource conflicts in each area, including:

[0020] Determine a number of candidate regions where the number of resource conflicts reaches a conflict number threshold;

[0021] Each to-be-processed region is determined to be a region where a candidate region is located, or a region with a larger area that includes a to-be-processed region.

[0022] A further technical solution is to use all regions whose resource conflicts reach a conflict number threshold as candidate regions, or to use a plurality of regions whose resource conflicts reach the conflict number threshold and are the largest as candidate regions.

[0023] A further technical solution is that the areas of the multiple areas to be processed are the same, or there are at least two areas to be processed that are different in area.

[0024] A further technical solution is that the idle logic resource is a lookup table or a DSP without clock control.

[0025] A further technical solution is to configure a logic function whose output is equal to the input to form a new signal path added to the wiring diagram, including:

[0026] Determine the nodes corresponding to the output ends of the vacant logic resources and the nodes corresponding to several input ends, add a new signal path between the nodes corresponding to each input end of the vacant logic resources and the nodes corresponding to the output ends, and set a path cost for each new signal path. The path costs of multiple new signal paths formed by an vacant logic resource configuration are the same, or there are at least two new signal paths with different path costs.

[0027] A further technical solution is to select all vacant logic resources in the area to be processed to form a new signal path, or to randomly select some vacant logic resources in the area to be processed to form a new signal path, or to select some vacant logic resources at a predetermined position in the area to be processed to form a new signal path.

[0028] A further technical solution is that, in the process of routing a wire net based on a wiring diagram including a newly added signal path, the number of times the wire net passes through the newly added signal path does not exceed a predetermined number threshold.

[0029] A further technical solution is that the predetermined number thresholds corresponding to different wire nets are the same or different, and the predetermined number thresholds corresponding to the same wire net in different routing iteration processes are the same or different.

[0030] A further technical solution is that, in the process of routing a wire net based on a wiring diagram including a newly added signal path, the timing critical path of the wire net does not pass through the newly added signal path.

[0031] The beneficial technical effects of the present invention are:

[0032] The present application discloses an FPGA wiring method for improving wiring efficiency by utilizing vacant logic resources. The method adds an intervention step in the conventional wiring iteration process. For a pending area that is determined to be difficult to resolve resource conflicts, a new signal path is formed by the vacant logic resources in the area and added to the wiring diagram. That is, the vacant logic resources whose input and output ends were originally not connected on the wiring diagram are converted into wiring resources with connected paths. If it is unrealistic to continue iterating in this way, the wire network in the candidate area can have more optional paths, making resource conflicts easier to resolve, improving wiring efficiency, and speeding up wiring completion. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a flowchart of FPGA routing using the existing congestion negotiation algorithm.

[0034] Figure 2 It is a flowchart of the FPGA wiring method of the present application.

[0035] Figure 3 It is a schematic diagram of the area to be processed that has been selected from the area divided inside the FPGA. DETAILED DESCRIPTION

[0036] The specific implementation of the present invention will be further described below in conjunction with the accompanying drawings.

[0037] This application discloses an FPGA wiring method that utilizes idle logic resources to improve wiring efficiency. Please refer to Figure 2 As shown in the flowchart, before the FPGA is wired, the positions of all the endpoints of each original net can be determined based on the layout results of the FPGA. The net endpoints include the source point (Source) and several destination points (Target) connected to it. Then, a wiring diagram is established based on the wiring resources inside the FPGA. The wiring diagram represents the programmable logic resources on the FPGA in a flat manner and forms In the form of, the wiring diagram includes at least several nodes and the lines between the nodes, each node represents the port of the wiring resource or resource module in the FPGA, the lines between the nodes represent the switches passed by the directed edges between the two nodes, and for the purpose of distinction, the present application records the lines in the wiring diagram initially established according to the wiring resources inside the FPGA as the original signal path.

[0038] Then, based on the layout results and in combination with the wiring diagram, the preset wiring algorithm can be used to implement wiring for each wire net in the user input netlist. The conventional practice is as described in the background technology section, and it is continuously iterated until the conflict is eliminated. The difference between this application and the conventional practice is mainly that the iterative process of conventional wiring is intervened, so the wiring method of this application is implemented based on the existing preset wiring algorithm, which can be considered as an improvement on the existing preset wiring algorithm. The more typical existing preset wiring algorithms include the congestion negotiation wiring algorithm and the Lee's maze wiring algorithm.

[0039] Regardless of the wiring process of the preset wiring algorithm, the FPGA wiring method of the present application, in the process of wiring each wire net in the user input netlist based on the wiring diagram using the preset wiring algorithm, triggers the intervention operation of the present application when the wiring iteration process of the user input netlist reaches a predetermined condition.

[0040] Among them, when the number of global iterations reaches the predetermined number of iterations, it is determined that the routing iteration process of the user input netlist meets the predetermined conditions, triggering the intervention operation of the present application. In the present application, a global iteration is defined as a routing of a net in the user input netlist. A routing implemented on a net includes the process of performing initial routing on the net, or the process of removing the existing routing of the net and rewinding the wires. When the number of global iterations reaches the predetermined number of iterations, at least the initial routing of all nets has been completed. Since when routing an FPGA, all nets are generally routed initially first, and then the conflicting nets are rewound, the predetermined number of iterations is at least the number of nets. There are three common situations: (1) The predetermined number of iterations is the number of nets, that is, after the initial routing of all nets is completed, the intervention operation is triggered in each subsequent global iteration process. (2) The predetermined number of iterations is greater than the number of wire nets but less than the predetermined iteration threshold. Generally, a predetermined iteration threshold is set during FPGA routing. If the conflict is still not resolved when the global iteration number reaches the iteration threshold, the iteration will not continue but the routing will be determined to have failed. The predetermined number of iterations can be set to any appropriate value that does not reach the predetermined iteration threshold, and the intervention operation is triggered in each subsequent global iteration process. (3) When the predetermined number of iterations is the predetermined iteration threshold, as in case (2), the conventional global iteration number reaches the predetermined iteration threshold and the routing is still not completed, then the routing is determined to have failed. However, in this application, after the global iteration number reaches the predetermined iteration threshold, by triggering the intervention operation, it is still possible to resolve the conflict in the future, so that the routing can be successful. In this case, it can be considered that the subsequent process of triggering the intervention operation and iterating is the process after the end of the conventional routing process, and it is usually also necessary to set another threshold for the number of iterations.

[0041] Regardless of the specific conditions under which it is triggered, the intervention operations triggered by this application are as follows:

[0042] 1. Determine the number of resource conflicts in each area of ​​the FPGA based on the current connection tree of each network. Each area contains a number of routing resource nodes. Divide the FPGA into several areas in advance. Each area contains a number of programmable logic resources inside the FPGA, such as CLBs with several rows and columns. The size of each area and the number and type of programmable logic resources contained can be the same or different. Figure 3 As shown, the FPGA is divided into four areas. Figure 3 As indicated by the dotted box, region 1 includes 2 rows and 2 columns of CLBs, region 2 includes 4 rows and 2 columns of CLBs, region 3 includes 4 rows and 4 columns of CLBs, and region 4 includes 2 rows and 4 columns of CLBs.

[0043] As described in the background technology section, in the iterative routing process, after obtaining a connection tree of a wire net, the number of shared conflicts of the routing resource nodes (programmable logic resources) involved in the connection tree will be updated, so that the number of shared conflicts of each programmable logic resource is known. The number of resource conflicts of all programmable logic resources in a region can be used to determine the number of resource conflicts in the region. The number of resource conflicts in the region reflects the situation in which each routing resource node in the current region is shared by multiple wire nets and resource conflicts are formed. The larger the number of resource conflicts in the region and the more serious the resource conflicts in the region, the more difficult it is to resolve the conflicts through congestion negotiation. The sum of the number of shared conflicts of all programmable logic resources in a region is taken as the number of resource conflicts in the region, or the maximum value / average value / median value of the number of shared conflicts of all programmable logic resources in a region can be taken as the number of resource conflicts in the region.

[0044] 2. Select the areas with serious resource conflicts to be processed based on the number of resource conflicts in each area. Specifically:

[0045] (1) Determine several candidate regions where the number of resource conflicts reaches the conflict number threshold. Each candidate region is the region initially delineated for the FPGA, and the conflict number thresholds corresponding to each region are equal or different. All regions where the number of resource conflicts reaches the conflict number threshold can be used as candidate regions, or several regions where the number of resource conflicts reaches the conflict number threshold and the number of resource conflicts is the largest can be used as candidate regions. For example Figure 3 In the example, assuming that the number of resource conflicts in regions 1, 2, 3, and 4 all reaches the conflict number threshold, and the number of resource conflicts is region 1, region 4, region 2, and region 3 from large to small, then all four regions can be used as candidate regions, or only region 1 and region 4 can be selected as candidate regions.

[0046] (2) Determine that each area to be processed is the area where a candidate area is located, that is, the area to be processed is the candidate area itself and is the same size as the candidate area. Alternatively, it is an area with a larger area that contains an area to be processed, that is, the area to be processed contains the candidate area and its peripheral part, has an area larger than the candidate area, and contains more programmable logic resources than the candidate area. The sizes of the areas expanded by different areas to be processed relative to their corresponding candidate areas may be the same or different. Thus, it is determined that the areas of the multiple areas to be processed are the same, or there are at least two areas to be processed that have different areas. Moreover, there may be overlapping parts between different areas to be processed, that is, some programmable logic resources may be shared. For example Figure 3 In the figure, it is assumed that region 1 and region 4 are candidate regions, the shaded portion at region 1 represents the region to be processed corresponding to region 1, and its area is the same as that of region 1; and the shaded portion at region 4 represents the region to be processed corresponding to region 4, and its area is larger than that of region 4, and contains more programmable logic resources than region 4, and the sizes of the two regions to be processed and the numbers of the contained programmable logic resources are different.

[0047] The following step 4 is performed for each selected area to be processed. When multiple areas to be processed are selected, the areas to be processed can generally be processed in order from the largest to the smallest number of resource conflicts.

[0048] 3. Select an empty logic resource that is not occupied by an instance in the area to be processed. The empty logic resource selected in this step can be implemented by any logic function that can be configured as an output or input, that is, a logic resource that implements a buffer function. Typically, the empty logic resource is a lookup table or a DSP without clock control.

[0049] The selected vacant logic resources not occupied by the instance are configured to form a logic function whose output is equal to the input to form a newly added signal path and added to the wiring diagram. In one embodiment, all vacant logic resources are selected in the area to be processed to form a newly added signal path. Or in another embodiment, some vacant logic resources are randomly selected in the area to be processed to form a newly added signal path. Or in another embodiment, some vacant logic resources at predetermined positions are selected in the area to be processed to form a newly added signal path, that is, only vacant logic resources at certain positions can form a newly added signal path, which is conducive to optimizing performance and reducing delay increase.

[0050] For each selected vacant logic resource to form a new signal path, one vacant logic resource can be configured to form multiple new signal paths. The specific method is: determine the node corresponding to the output end of the vacant logic resource and the nodes corresponding to several input ends, and add a new signal path from the node corresponding to each input end of the vacant logic resource to the node corresponding to the output end. Each new signal path is a directed edge in the wiring diagram indicating that the input end points to the output end. For example, the node corresponding to the output end of an empty lookup table is Y, and the nodes corresponding to the input end are A1, A2, A3, A4, A5 and A6, respectively. Then, the 6 new signal paths formed by the configuration of the vacant lookup table include (A1, Y), (A2, Y), (A3, Y), (A4, Y), (A5, Y), (A6, Y), where (A1, Y) represents the directed edge from A1 to Y.

[0051] When adding a new signal path to the wiring diagram, it is also necessary to set a path cost for each new signal path, just like a conventional directed edge. Then, the path costs of multiple new signal paths formed by an empty logic resource configuration are the same, or there are at least two new signal paths with different path costs, that is, the costs of passing through multiple new signal paths can be differentiated. For example, the path cost of (A1, Y) in the above example is set to cost1, the path cost of (A2, Y) can also be set to cost1, and the path cost of (A3, Y) can be set to cost2, and the others are similar.

[0052] After selecting vacant logic resources for all areas to be processed to form a new signal path and adding it to the wiring diagram, an updated wiring diagram is obtained, and the following step 4 is executed.

[0053] 4. Based on the updated wiring diagram, the user input netlist is iterated by using the preset wiring algorithm until the number of resource conflicts in all areas is 0. Since the new signal path is added to the wiring diagram, the nets in the area to be processed can have more optional wiring paths through the new signal path in the next wiring iteration, thereby reducing the wiring congestion in the area to be processed.

[0054] Therefore, when the routing iteration process of the user input netlist reaches the predetermined conditions, the wiring diagram includes the original signal path and the newly added signal path. In one embodiment, when a wire net is rewound based on the wiring diagram, the wiring path can be determined only according to the path cost of the signal path, that is, no additional attribute distinction is made between the original signal path and the newly added signal path. In another embodiment, in addition to considering the path cost of the signal path, there will be additional routing restrictions on the newly added signal path, because the newly added signal path often increases the path delay. A typical practice is that in the process of routing a wire net based on a wiring diagram containing a newly added signal path, the number of newly added signal paths passed by the wire net is set not to exceed a predetermined number threshold. The predetermined number thresholds corresponding to different wire nets are the same or different, and the predetermined number thresholds corresponding to the same wire net in different routing iterations are the same or different. Another typical practice is that in the process of routing a wire net based on a wiring diagram containing a newly added signal path, the timing critical path of the wire net does not pass through the newly added signal path.

Claims

1. An FPGA wiring method for improving wiring efficiency by utilizing idle logic resources, characterized in that: The method comprises: In the process of implementing routing for each net in the user input netlist based on the routing diagram using a preset routing algorithm, when the routing iteration process of the user input netlist reaches a predetermined condition, the number of resource conflicts for each region in the FPGA is determined according to the current connection tree of each net, each region includes a number of routing resource nodes, and the number of resource conflicts for the region reflects the situation that each routing resource node in the current region is shared by multiple nets to form a resource conflict; Select the area to be processed with serious resource conflicts based on the number of resource conflicts in each area; Selecting vacant logic resources not occupied by instances in the area to be processed, and configuring a logic function whose output is equal to the input to form a newly added signal path to be added to the wiring diagram; Based on the updated wiring diagram, the preset wiring algorithm is used to iterate the wiring of the user input netlist until the number of resource conflicts in all regions is 0; The configuration forms a logical function in which the output is equal to the input, and forms a new signal path that is added to the wiring diagram, including: determining the node corresponding to the output end of the vacant logic resource and the nodes corresponding to several input ends, adding a new signal path between the node corresponding to each input end of the vacant logic resource and the node corresponding to the output end, and setting a path cost for each new signal path, the path costs of multiple new signal paths formed by an vacant logic resource configuration are the same, or there are at least two new signal paths with different path costs.

2. The method according to claim 1, characterized in that When the number of global iterations reaches a predetermined number of iterations, it is determined that the routing iteration process of the user input netlist has reached a predetermined condition, wherein a routing operation for a net in the user input netlist is a global iteration, and a routing operation for a net includes initial routing for the net, or removing the existing routing for the net and rewinding the wiring.

3. The method according to claim 1, characterized in that The selecting of the area to be processed with serious resource conflicts based on the number of resource conflicts in each area includes: Determine a number of candidate regions where the number of resource conflicts reaches a conflict number threshold; Each area to be processed is determined to be an area where a candidate area is located, or to be an area with a larger area that includes an area to be processed.

4. The method according to claim 3, characterized in that All regions whose resource conflicts reach a conflict number threshold are taken as candidate regions, or several regions whose resource conflicts reach a conflict number threshold and are the largest are taken as candidate regions.

5. The method according to claim 1, characterized in that The areas of the plurality of regions to be processed are all the same, or at least two regions to be processed have different areas.

6. The method according to claim 1, characterized in that The idle logic resource is a lookup table or a DSP without clock control.

7. The method according to claim 1, characterized in that All vacant logic resources are selected in the area to be processed to form a new signal path, or some vacant logic resources are randomly selected in the area to be processed to form a new signal path, or some vacant logic resources at predetermined positions are selected in the area to be processed to form a new signal path.

8. The method according to claim 1, characterized in that In a process of routing a wire net based on a routing diagram including a newly added signal path, the number of times the wire net passes through the newly added signal path does not exceed a predetermined number threshold.

9. The method according to claim 8, characterized in that The predetermined number thresholds corresponding to different wire nets are the same or different, and the predetermined number thresholds corresponding to the same wire net in different routing iteration processes are the same or different.

10. The method according to claim 1, characterized in that In a process of routing a wire net based on a wiring diagram including a newly added signal path, a timing critical path of the wire net does not pass through the newly added signal path.

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