Calibration control circuit and storage device comprising a calibration control circuit

Abstract

A memory device includes a calibration circuit configured to perform a ZQ calibration operation in accordance with a calibration command signal and a calibration supply voltage, and a calibration control circuit configured to determine the calibration command signal based on a comparison result obtained by comparing the calibration supply voltage level to at least one reference voltage level.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0083438, filed on July 7, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] Embodiments of the present inventive concept relate to a calibration control circuit, and more particularly, to a calibration control circuit outputting a calibration command signal and a memory device including the same. BACKGROUND

[0004] Semiconductor memory devices widely used in high-performance electronic systems are increasing in capacity and speed. Examples of the memory devices include dynamic random access memory (DRAM). DRAM is a volatile memory and determines data according to an electric charge stored in a capacitor.

[0005] To prevent distortion of a signal transmitted between a memory controller and a memory device, an on-die termination (ODT) circuit and / or an off chip driver (OCD) circuit can be included in the memory device. Resistance (or impedance) of the ODT / OCD circuit is controlled by a control code generated in a calibration circuit. The calibration circuit performs a ZQ calibration operation in which a pull-up code and a pull-down code are generated as the control code, which varies according to conditions such as process, voltage, and temperature (PVT). SUMMARY

[0006] Embodiments of the present inventive concept provide a calibration control circuit outputting a calibration command signal according to a level of a power supply voltage input to a calibration circuit, a memory device including the same, and an operating method of the memory device.

[0007] According to one or more embodiments, a memory device includes a calibration circuit configured to perform a ZQ calibration operation according to a calibration command signal and a calibration power supply voltage, and a calibration control circuit configured to determine the calibration command signal based on a comparison result obtained by comparing a level of the calibration power supply voltage with a level of at least one reference voltage.

[0008] According to one or more embodiments, a calibration control circuit includes a comparator configured to obtain a comparison result by comparing a calibration power supply voltage input to a calibration circuit configured to perform a ZQ calibration operation with at least one reference voltage, and a command signal output unit configured to output a calibration command signal for determining whether the calibration circuit performs the ZQ calibration operation based on the comparison result.

[0009] According to one or more embodiments, a method of operating a memory device includes comparing a calibration power supply voltage input to a calibration circuit configured to perform a ZQ calibration operation with at least one reference voltage, and determining a logic state of a calibration command signal for determining whether the calibration circuit is to perform the ZQ calibration operation based on a comparison result obtained by comparing the calibration power supply voltage with the at least one reference voltage. BRIEF DESCRIPTION OF DRAWINGS

[0010] Embodiments of the inventive concept will now be described, by way of example, with reference to the accompanying drawings, in which:

[0011] Figure 1 is a block diagram of a memory system according to an embodiment;

[0012] Figure 2 is a block diagram of an example of a memory device of Figure 1

[0013] Figure 3 is a block diagram of an example of outputting an existing calibration command signal;

[0014] Figure 4 is a block diagram of another example of outputting an existing calibration command signal;

[0015] Figure 5A and Figure 5B is a timing diagram of signals input to Figure 3 and Figure 4 a memory device of

[0016] Figure 6 shows an example of a calibration control circuit including a counter;

[0017] Figure 7 is a timing diagram of signals input to a calibration control circuit of Figure 6

[0018] Figure 8 and Figure 9 shows other examples of a calibration control circuit including a counter;

[0019] Figure 10 ​​is a flowchart of operations of an operation method of a memory device;

[0020] Figure 11 is a flowchart of operations of an operation method of an example of a calibration control circuit according to Figures 6 to 9

[0021] Figure 12 An example of a calibration control circuit including a hysteresis comparator is shown;

[0022] Figure 13 is a timing diagram of signals input to Figure 12 a calibration control circuit;

[0023] Figure 14 and Figure 15 An example of a calibration control circuit including a hysteresis comparator is shown;

[0024] Figure 16 is a flowchart of operations of an operation method of an example of a calibration control circuit including a hysteresis comparator according to Figures 12 to 15

[0025] is an example of a calibration control circuit including a counter and a hysteresis comparator; and Figure 17

[0026] Figure 18 is a timing diagram of signals input to Figure 17 a calibration control circuit. DETAILED DESCRIPTION

[0027] Embodiments of the inventive concept will hereinafter be described in conjunction with the appended drawings. Throughout the drawings, like reference numerals can refer to like elements.

[0028] It will be understood that the terms “first,” “second,” “third,” etc. as used herein are used to distinguish one element from another, and do not imply a limitation on the elements. Thus, a “first” element in one embodiment could be described as a “second” element in another embodiment.

[0029] As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0030] ​​As used herein, the term "about" includes the recited value, and refers to a range of values that a person of ordinary skill in the art would consider acceptable when considering the issues of measurement and error associated with measuring a particular quantity (e.g., limitations of the measurement system). For example, "about" can mean within one or more standard deviations as understood by a person of ordinary skill in the art. Further, it is to be understood that although a parameter can be described herein as being "about" a particular value according to an embodiment, the parameter can be exactly the particular value or close to the particular value within a measurement error as understood by a person of ordinary skill in the art.

[0031] Figure 1 is a block diagram of a memory system according to an embodiment.

[0032] Referring to Figure 1 The memory system can include a memory controller 100 and a memory device 200. The memory controller 100 transmits various signals to the memory device 200 and controls a storage operation such as a write operation and a read operation. For example, the memory controller 100 can include a memory interface 110 and can receive data DATA from a memory cell array 210 by providing a command CMD and an address ADDR to the memory device 200.

[0033] The command CMD can include a command for a normal storage operation (e.g., a write operation and a read operation). The memory controller 100 can provide a command CMD for various control operations in the memory device 200, and the memory controller 100 can provide, for example, a calibration command CMD_ZQ to the memory device 200. The memory device 200 can set a termination resistance value of an on-die termination (ODT) circuit in the memory device 200 or can set a resistance value of an output driver (e.g., an off-chip driver (OCD) circuit) by performing a calibration operation during an initial operation or in response to the calibration command CMD_ZQ.

[0034] The memory controller 100 can access the memory device 200 according to a request from a host device. The memory controller 100 can communicate with the host device according to various protocols. For example, the memory controller 100 can communicate with the host device according to an interface protocol such as a peripheral component interconnect express (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), or a serial attached SCSI (SAS). In addition to the above-described interface protocols, other interface protocols such as a universal serial bus (USB), a multimedia card (MMC), an enhanced small disk interface (ESDI), and an integrated drive electronics (IDE) can also be used as a protocol between the host device and the memory controller 100. However, embodiments of the inventive concept are not limited thereto.

[0035] The memory device 200 can include various types of memory. Examples of the memory device 200 include, but are not limited to, dynamic random access memory (DRAM), such as double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate (LPDDR) SDRAM, graphics double data rate (GDDR) SDRAM, or Rambus dynamic random access memory (RDRAM). However, embodiments of the inventive concept are not limited thereto. For example, according to embodiments, the memory device 200 can include non-volatile memory such as magnetic RAM (MRAM), ferroelectric RAM (FRAM), phase change RAM (PRAM), or resistive RAM (ReRAM).

[0036] The memory device 200 can communicate with the memory controller 100 via an interface according to various standards. For example, the memory controller 100 and the memory device 200 can communicate via an interface according to low power double data rate 4 (LPDDR4), LPDDR4X, LPDDR5, and other standards.

[0037] The memory device 200 can include a storage cell array 210, an OCD / ODT circuit 220, a calibration circuit 230, and a calibration control circuit 240. According to embodiments, the memory device 200 can include an OCD circuit and an ODT circuit. However, embodiments of the inventive concept are not limited thereto. In embodiments, the OCD circuit and the ODT circuit can be separated from each other in the memory device 200. For example, in embodiments, the OCD circuit and the ODT circuit can be implemented by different hardware modules in the memory device 200. Alternatively, according to embodiments, the OCD circuit can include a pull-up circuit and a pull-down circuit, and any one of the pull-up circuit and the pull-down circuit can be used as the ODT circuit. For example, in an operation of outputting data DATA, the OCD circuit can perform a signal output operation using the pull-up circuit and the pull-down circuit, and in an operation of receiving data DATA, the pull-up circuit of the OCD circuit can be used as the ODT circuit to provide a termination resistance to a line of the input data DATA. The OCD / ODT circuit 220 can adjust a resistance (or impedance) of the OCD / ODT circuit 220 to prevent or reduce distortion of a signal transmitted between the memory controller 100 and the memory device 200.

[0038] The calibration circuit 230 can perform a ZQ calibration operation of generating a pull-up code or a pull-down code to adjust the resistance of the OCD / ODT circuit 220. The calibration circuit 230 can generate a control code for adjusting the resistance value of the OCD / ODT circuit 220. The calibration circuit 230 can perform the calibration operation when it periodically or at an initial stage of the memory device 200 enters a ZQ calibration mode. In the ZQ calibration operation, the control code can be generated based on a feedback operation. For example, the calibration circuit 230 can include a resistance circuit having the same characteristics as the pull-up resistance and / or the pull-down resistance included in the OCD / ODT circuit 220. The calibration circuit 230 can generate a pull-up code for adjusting the resistance value of the pull-up circuit of the OCD / ODT circuit 220, or can generate a pull-down code for adjusting the resistance value of the pull-down circuit of the OCD / ODT circuit 220. The generated pull-up code and / or pull-down code can be set or stored in the memory device 200, and then can be used to provide an on-chip termination resistance in an operation of writing and reading data DATA, or to adjust the resistance value (or output strength) of the OCD circuit (or output driver circuit).

[0039] The calibration control circuit 240 can determine the logic level of the calibration command signal based on a result of comparing the level of the reference voltage with the level input to the calibration circuit 230 or the calibration power voltage. For example, when the calibration power voltage is higher than the reference voltage, the calibration control circuit 240 can transmit the calibration command signal having a logic high level to the calibration circuit 230. The calibration command signal of the logic high level is a signal that commands the calibration circuit 230 to perform the ZQ calibration operation, and the calibration circuit 230 can generate various control codes to perform the ZQ calibration operation.

[0040] Figure 2 is Figure 1 a block diagram of an example of the memory device 200.

[0041] The memory device 200 can include a storage cell array 210, an OCD / ODT circuit 220, a calibration circuit 230, a calibration control circuit 240, a command decoder 250, and an address buffer 260. The memory device 200 can further include various components for writing data to or reading data from a storage cell of the storage cell array 210 corresponding to an address. For example, the memory device 200 can further include a row decoder 211 for selecting a row of the storage cell array 210, a column decoder 214 for selecting a column, an input / output sense amplifier 212, and an input / output gating unit 213 for performing gating of input / output data.

[0042] The command decoder 250 can decode control signals regarding a storage operation by receiving a command CMD from the memory controller 100 or a host device, and can also provide various control signals to components included in the memory device 200. According to an embodiment, the command decoder 250 can receive a command signal CMD regarding a data write / erase / read operation, and can perform an operation in response to the received command signal CMD. The address buffer 260 can receive an address ADDR provided from the memory controller 100. The address ADDR can include a row address ROW_ADDR for indicating a row of the memory cell array 210 and a column address COL_ADDR for indicating a column of the memory cell array 210. For example, the command decoder 250 can receive a command signal CMD for controlling data write from the memory controller 100, and the address buffer 260 can receive an address ADDR indicating at which memory cell of the memory cell array 210 data is to be written. The memory device 200 can determine which operation is to be performed on which memory cell in response to the command signal CMD and the address ADDR.

[0043] The input / output gating unit 213 can provide data read from the memory cell array 210 to a device outside the memory device 200 through the OCD / ODT circuit 220. In addition, an input buffer can be provided inside or outside the OCD / ODT circuit 220, and in a data write operation, data can be provided to the memory cell array 210 through the input buffer and the input / output gating unit 213.

[0044] The command decoder 250 can receive a calibration command CMD_ZQ from the memory controller 100 or a host device, and can control operations related to calibration according to the received calibration command CMD_ZQ. The command decoder 250 can receive a command CMD and a calibration command CMD_ZQ regarding data write / erase / read, the command CMD and the calibration command CMD_ZQ being a code including a series of bits. However, embodiments of the inventive concept are not limited thereto. The command decoder 250 can receive a command CMD and a calibration command CMD_ZQ, the command CMD and the calibration command CMD_ZQ being separate codes. The calibration command CMD_ZQ can include signals associated with a calibration start signal ZQ_Start, a calibration inhibit signal, and a calibration latch signal ZQ_Latch, and the command decoder 250 can decode the above signals, and thus can provide a command signal to at least one of the calibration control circuit 240 and the calibration circuit 230. The calibration control circuit 240 can receive at least one signal from the command decoder 250, and can determine a logic state of a calibration command signal ZQ_CTR provided to the calibration circuit 230 in response to the received signal. The calibration control circuit 240 will be described below with reference to FIG. 2B. Figures 6 to 18A detailed description of the determination of the calibration command signal by the calibration control circuit 240 is provided.

[0045] The calibration circuit 230 can receive power supply voltages related to voltage levels, and each power supply voltage can be related to a type of calibration operation. For example, a high power supply voltage level VDDQ_HIGH of about 0.5V can be a level of a power supply voltage indicating that a calibration operation is performed, and a low power supply voltage level VDDQ_LOW of about 0.3V can be a level of a power supply voltage indicating that a calibration operation is not performed. The power supply voltage VDDQ can be received by the calibration circuit 230, and can also be referred to herein as a calibration power supply voltage.

[0046] Figure 3 is a block diagram of an example of the output calibration command signal ZQ_CTR.

[0047] Referring to Figure 3 , the command decoder 350 of the memory device can receive a calibration command CMD_ZQ from a memory controller or a host device. Certain aspects of the command decoder 350 can be the same as or similar to certain aspects of the command decoder 250 described previously with reference to Figure 2 . Further description of these aspects can be omitted for the sake of explanation. The command decoder 350 can generate a calibration start signal ZQ_Start_CMD and a calibration latch signal ZQ_Latch by decoding the calibration command CMD_ZQ. In embodiments described herein, the reference designations ZQ_Start_CMD and ZQ_Start can be used interchangeably.

[0048] The command decoder 350 can output the calibration start signal ZQ_Start_CMD to perform a ZQ calibration operation, and compare a calibration enable signal ZQ_EN received from the memory controller or the host device with the calibration start signal ZQ_Start_CMD, thereby determining a logic state of the calibration command signal ZQ_CTR. For example, when both the calibration enable signal ZQ_EN and the calibration start signal ZQ_Start_CMD are high logic level signals, whereby these signals indicate that a ZQ calibration operation is performed, the memory device can output the calibration command signal ZQ_CTR as a logic high. Alternatively, when at least one of the calibration enable signal ZQ_EN and the calibration start signal ZQ_Start_CMD is a low logic level signal, the memory device can determine that a ZQ calibration operation is unnecessary, and thus can output the calibration command signal ZQ_CTR as a logic low.

[0049] The command decoder 350 can send the calibration latch signal ZQ_Latch to the calibration circuit 330 when a certain period of time elapses after the memory device starts performing a ZQ calibration operation. Certain aspects of the calibration circuit 330 can be the same as or similar to certain aspects of the calibration circuit 230 described previously with reference to Figure 1 andFigure 2 Certain aspects of the described calibration circuit 230 are the same or similar. Further description of these aspects can be omitted for ease of explanation. When the calibration latch signal ZQ_Latch is received, the calibration circuit 330 can load the ZQ code. The ZQ code can be provided by the calibration circuit 330 to the OCD / ODT circuit to allow the memory device to perform a ZQ calibration operation, and the memory device can determine whether to continue performing the ZQ calibration operation when the calibration circuit 330 loads the ZQ code in response to the calibration latch signal ZQ_Latch.

[0050] Figure 4 is a block diagram of another example of an output calibration command signal.

[0051] Figure 3 Embodiments of show the calibration command signal ZQ_CTR generated when a command for performing a ZQ calibration operation is received from a memory controller or a host device, while Figure 4 Embodiments of show that the background calibration start signal ZQ_Start_BG is periodically generated from the feedback circuit 440 including a timer when the calibration enable signal ZQ_EN is input from the memory controller and / or the host device.

[0052] When the calibration enable signal ZQ_EN is received from the memory controller or the host device, the memory device according to embodiments can output the calibration command signal ZQ_CTR according to the logic state of the calibration enable signal ZQ_EN and the logic state of the background calibration start signal ZQ_Start_BG. The timer of the feedback circuit 440 can output the background calibration start signal ZQ_Start_BG whose logic state is the same as that of the calibration command signal ZQ_CTR after a certain time elapses after receiving the calibration command signal ZQ_CTR. Then, the memory device can output the calibration command signal ZQ_CTR according to the logic state of the background calibration start signal ZQ_Start_BG and the logic state of the calibration enable signal ZQ_EN.

[0053] For example, when the calibration command signal ZQ_CTR outputting a high logic level, the timer of the feedback circuit 440 can output the background calibration start signal ZQ_Start_BG of a logic high level. Then, when the calibration enable signal ZQ_EN inputting a logic high level, the memory device can output the calibration command signal ZQ_CTR of a logic high level again. However, when the calibration enable signal ZQ_EN inputting a low logic level, although the background calibration start signal ZQ_Start_BG outputting a high logic level, the memory device can output the calibration command signal ZQ_CTR of a low logic level since it is determined that the ZQ calibration operation is not required.

[0054] Figure 4Certain aspects of the illustrated calibration circuit 430 and command decoder 450 can be the same or similar to those previously described with reference to the calibration circuit 230 and command decoder 250 described with reference to FIG. 2. Further description of these aspects can be omitted for the sake of brevity. Reference is made to the description of the calibration circuit 230 and command decoder 250 of FIG. 2 for further details. Figure 1 and Figure 2 are the same or similar to those previously described with reference to the calibration circuit 230 and command decoder 250 described with reference to FIG. 2. Further description of these aspects can be omitted for the sake of brevity. Reference is made to the description of the calibration circuit 230 and command decoder 250 of FIG. 2 for further details. Figure 3 A description is provided of the calibration circuit 430 loading the ZQ code when the command decoder 450 outputs the calibration latch signal ZQ_Latch. Thus, further detailed description thereof will be omitted for the sake of brevity.

[0055] Figure 5A and Figure 5B are timing diagrams of signals input to the memory device. Figure 3 and Figure 4 are timing diagrams of signals input to the memory device.

[0056] Figure 5A It is shown that, in an ideal case where a command and a supply voltage for a ZQ calibration operation are provided from a memory controller or a host device (e.g., in a case where the memory device operates in accordance with a Joint Electron Device Engineering Council (JEDEC) specification), the calibration circuit receives a calibration start signal ZQ_Start and / or a calibration enable signal ZQ_EN corresponding to a state of the supply voltage VDDQ. For example, a high supply voltage level VDDQ_HIGH corresponds to a high logic level of the calibration start signal ZQ_Start and the calibration enable signal ZQ_EN, while a low supply voltage level VDDQ_LOW corresponds to a low logic level of the calibration start signal ZQ_Start and the calibration enable signal ZQ_EN. The high supply voltage level VDDQ_HIGH is set to have a level higher than an average voltage of the supply voltage VDDQ, while the low supply voltage level VDDQ_LOW is set to have a level lower than the average voltage level of the supply voltage VDDQ. For example, the high supply voltage level VDDQ_HIGH can be about 0.5V, while the low supply voltage level VDDQ_LOW can be about 0.3V or more. Thus, the memory device can generate the calibration command signal ZQ_CTR corresponding to the supply voltage VDDQ in the ideal case.

[0057] In contrast, Figure 5B is a timing diagram corresponding to a case where the memory device violates the JEDEC specification or the supply voltage VDDQ fails to synchronize with the timing of the calibration command signal ZQ_CTR. When the low supply voltage level VDDQ_LOW is applied, the calibration start signal ZQ_Start and the calibration enable signal ZQ_EN should be generated as Figure 5AThe illustrated low logic level calibration command signal ZQ CTR controls the memory device not to perform the ZQ calibration operation. However, the high logic level calibration start signal ZQ Start and the calibration enable signal ZQ EN are still applied, and the calibration circuit generates the high logic level calibration command signal ZQ CTR. As a result, the calibration circuit can perform the ZQ calibration operation, which results in unnecessary power consumption.

[0058] Figures 6 to 8 An example of a calibration control circuit including a counter is shown.

[0059] As Figures 3 to 5B shown in embodiments, to prevent unnecessary power consumption due to unnecessarily performing the ZQ calibration operation, embodiments described herein can include a calibration control circuit 640 that compares a level of a power supply voltage VDDQ to a level of a reference voltage V REF Some aspects of the calibration control circuit 640 can be the same as or similar to some aspects of the calibration control circuit 240 described with reference to Figure 1 and Figure 2 When a certain period of time has elapsed after the memory device starts to perform the ZQ calibration operation, the command decoder 650 can send a calibration latch signal ZQ Latch to the calibration circuit 630. Some aspects of the command decoder 650 and the calibration circuit 630 can be similar to or the same as some aspects of the command decoder 250 and the calibration circuit 230 described with reference to Figure 1 and Figure 2 Further description of these aspects can be omitted for the sake of explanation. After receiving the calibration latch signal ZQ Latch, the calibration circuit 630 can load the ZQ code. The ZQ code can be provided by the calibration circuit 630 to the OCD / ODT circuit to allow the memory device to perform the ZQ calibration operation, and the memory device can determine whether to continue to perform the ZQ calibration operation when the calibration circuit 630 loads the ZQ code in response to the calibration latch signal ZQ Latch.

[0060] According to Figure 6The calibration control circuit 640 of the memory device of the embodiment can output a calibration start enable signal ZQ_Start_EN according to a calibration start signal ZQ_Start_CMD and a calibration enable signal ZQ_EN. The calibration control circuit 640 can determine a logic state of the calibration start enable signal ZQ_Start_EN according to a logic level of the calibration start signal ZQ_Start_CMD and a logic level of the calibration enable signal ZQ_EN. For example, when the calibration start signal ZQ_Start_CMD and the calibration enable signal ZQ_EN are both high logic level signals, the calibration control circuit 640 can output the calibration start enable signal ZQ_Start_EN with a logic high level through an AND gate.

[0061] The supply voltage VDDQ can be classified to have a high logic level and a low logic level according to voltage levels, and the voltage levels can correspond to different operation modes of the calibration circuit 630, respectively. For example, a high supply voltage level VDDQ_HIGH can be a level of the supply voltage VDDQ input to the calibration circuit 630 when performing a ZQ calibration operation, and a low supply voltage level VDDQ_LOW can be a level of the supply voltage VDDQ input to the calibration circuit 630 when not performing the ZQ calibration operation.

[0062] The comparator 642 of the calibration control circuit 640 according to the embodiment can compare the supply voltage VDDQ with a reference voltage V REF and thus can generate a comparison signal COMP. For example, the reference voltage V REF may have a level between the high supply voltage level VDDQ_HIGH and the low supply voltage level VDDQ_LOW, and can be an average of the high supply voltage level VDDQ_HIGH and the low supply voltage level VDDQ_LOW. According to the embodiment, the memory device can adjust the level of the reference voltage V REF based on an amount of power consumed to perform the ZQ calibration operation. For example, the memory device can measure the amount of power consumed to perform the ZQ calibration operation, and when it is determined that the measured amount is greater than a threshold power consumption, the level of the reference voltage V REF may be converted to a voltage level higher than the previously set reference voltage.

[0063] The comparator 642 of the calibration control circuit 640 can determine whether the level of the supply voltage VDDQ is a high level or a low level by comparing the level of the reference voltage V REF with the level of the supply voltage VDDQ, and can provide the comparison signal COMP to the counter 641. For example, when the comparator 642 determines that the level of the supply voltage VDDQ is lower than the reference voltage V REFa logic high level when the reference voltage V REF may have a level fixed to a certain level. However, embodiments of the inventive concept are not limited thereto. The reference voltage V REF may have a level changeable according to a request of a host device and / or a user.

[0064] The counter 641 according to an embodiment can generate a count output signal CT_OUT according to a calibration start enable signal ZQ_Start_EN and a comparison signal COMP. The calibration start enable signal ZQ_Start_EN can be a signal associated with a command for a ZQ calibration operation, and can be an enable signal that activates the counter 641.

[0065] The counter 641 can generate a count output signal CT_OUT when receiving the calibration start enable signal ZQ_Start_EN and the comparison signal COMP in a certain logic state for a certain period of time. The comparison signal COMP in the certain logic state can be in a logic high state. However, embodiments of the inventive concept are not limited thereto. For example, in an embodiment, when receiving the calibration start enable signal ZQ_Start_EN in a certain logic state and the comparison signal COMP in a certain logic state, the counter 641 can make a count value plus 1, and when the count value is equal to or greater than a reference count value, the counter 641 can output the count output signal CT_OUT in a logic low level.

[0066] The calibration control circuit 640 according to an embodiment can determine that the calibration command signal ZQ_CTR is a logic high level signal when the count output signal CT_OUT and the calibration start enable signal ZQ_Start_EN are in a logic high level. The calibration control circuit 640 can output the calibration command signal ZQ_CTR in a logic low level when any one of the count output signal CT_OUT and the calibration start enable signal ZQ_Start_EN is a logic low level signal.

[0067] That is, when the calibration start signal ZQ_Start_CMD and the calibration enable signal ZQ_EN are not input to the memory device since the memory controller or the host device determines not to perform the ZQ calibration operation, the calibration control circuit 640 can prevent the generation of the calibration command signal ZQ_CTR. In addition, even if the calibration command CMD_ZQ that controls the execution of the ZQ calibration operation is received from the memory controller or the host device, the ZQ calibration operation should be prevented from being performed when a low power supply voltage is applied to the calibration circuit. When the comparator 642 determines that the power supply voltage VDDQ is lower than the reference voltage V REFAt this time, the calibration control circuit 640 can output the calibration command signal ZQ_CTR of a logic low level, and thus the ZQ calibration operation can be disabled.

[0068] The components included in the calibration control circuit 640, such as the counter 641 and the AND gate outputting the calibration command signal ZQ_CTR to the calibration circuit 630, can be individually or collectively referred to as a command signal output unit (or command signal output circuit).

[0069] Figure 7 is a timing diagram of a signal input to Figure 6 the calibration control circuit.

[0070] Referring to Figure 7 , as shown in the timing diagram of Figure 5B , the power supply voltage VDDQ can have a plurality of levels, but since the calibration start signal ZQ_Start and the calibration enable signal ZQ_EN of a logic high level are input, the memory device can violate the JEDEC specification and perform the ZQ calibration operation.

[0071] Since the high power supply voltage level VDDQ_HIGH higher than the level of the reference voltage V REF is applied in the first section T1, the calibration control circuit according to the embodiment can output the calibration command signal ZQ_CTR of a logic high level. Thus, in the first section T1, the calibration circuit can perform the ZQ calibration operation.

[0072] Then, in the second section T2, in the ideal case where the level of the power supply voltage VDDQ drops to a low level, the calibration start signal ZQ_Start or the calibration enable signal ZQ_EN should be transitioned to a logic low level, but can also remain in a logic high state as in the first section T1.

[0073] In the second section T2, the comparator can compare the level of the power supply voltage VDDQ with the level of the reference voltage V REF , and when it is determined that the level of the power supply voltage VDDQ is lower than the level of the reference voltage V REF , the comparator can output the comparison signal COMP of a high logic level. The counter can start the counting operation by receiving the comparison signal COMP of a high logic level and the calibration start enable signal ZQ_Start_EN of a high logic level. Each time the count pulse CP is generated (i.e., each time the comparison signal COMP is received at one counting timing), the counter can compare the count value with the reference count value by increasing the count value by 1. For example, when the reference count value is 3, the calibration control circuit can output the calibration command signal ZQ_CTR of a high logic level until the counter performs the counting twice in succession. That is, when the level of the power supply voltage VDDQ is lower than the level of the reference voltage V REFWhen the voltage level is low (VDDQ_LOW), the calibration control circuit according to the embodiment does not immediately stop the ZQ calibration operation. Instead, it determines the state of the power supply voltage VDDQ until a specific time period has elapsed after the power supply voltage VDDQ is applied at a low power supply voltage level (VDDQ_LOW). Then, the calibration control circuit can determine whether to block the ZQ calibration operation. Therefore, in the case where the ZQ calibration operation should be performed but the power supply voltage VDDQ experiences a momentary drop, the storage device according to the embodiment can prevent the ZQ calibration operation from being blocked.

[0074] according to Figure 7 In one embodiment, the second part T2 is the part that generates two counting pulses CP. The reference count value is 3. However, embodiments of the present invention are not limited thereto. Additionally, the storage device can adjust the reference count value according to a request from the memory controller or host device. For example, the storage device can measure the power consumption based on the ZQ calibration operation and can adjust the reference count value based on the power consumption. When the power consumption is greater than the reference power, the memory controller or host device can determine to quickly stop the unnecessary ZQ calibration operation, and by reducing the reference count value to be lower than the previous reference count value, the storage device can quickly prevent the execution of the ZQ calibration operation. That is, when the power supply voltage VDDQ is lower than the reference voltage V... REF When the number of times the reference count is equal to or greater than a certain number of consecutive reference counts, the storage device can output a low logic level calibration command signal ZQ_CTR. The storage device can adjust the reference count value based on the power consumed during the ZQ calibration operation.

[0075] In Part T3, since the number of consecutively generated counting pulses CP exceeds the reference count value, the counter can generate a low-logic-level counting output signal CT_OUT. When the low-logic-level counting output signal CT_OUT is generated, the counting output signal CT_OUT and the calibration start enable signal ZQ_Start_EN can be input into an AND gate, and a low-logic-level calibration command signal ZQ_CTR can be output.

[0076] As the supply voltage level VDDQ_LOW increases to the high supply voltage level VDDQ_HIGH, the supply voltage VDDQ becomes higher than the reference voltage V. REF At this point, the storage device can enter section four, T4. In section four, T4, the comparator can output a low logic level comparison signal COMP, and the counter can stop generating counting pulses CP. Therefore, the storage device can generate a high logic level calibration command signal ZQ_CTR, thus allowing the calibration circuit to resume the ZQ calibration operation.

[0077] according to Figure 8The calibration control circuit 840 of the memory device of the embodiment can output a calibration start enable signal ZQ_Start_EN according to a background calibration start signal ZQ_Start_BG and a calibration enable signal ZQ_EN. The timer can determine whether to output the background calibration start signal ZQ_Start_BG by receiving the calibration start enable signal ZQ_Start_EN. Figure 8 Some aspects of the calibration circuit 830, the calibration control circuit 840, and the command decoder 850 shown in FIG. 8 can be the same as or similar to those of the calibration circuit 230, the calibration control circuit 240, and the command decoder 250, respectively, previously described with reference to Figure 1 and Figure 2 For ease of explanation, further description of these aspects can be omitted.

[0078] When the background calibration start signal ZQ_Start_BG and the calibration enable signal ZQ_EN are logic high signals, the calibration start enable signal ZQ_Start_EN of a logic high level can be output through an AND gate included in the calibration control circuit 840. The comparator 842 can generate a comparison signal COMP by comparing the power supply voltage VDDQ with a reference voltage V REF The counter 841 can generate a count output signal CT_OUT according to the calibration start enable signal ZQ_Start_EN and the comparison signal COMP. Referring to Figure 6 The generation of the count output signal CT_OUT by the counter 841 is described, and thus, for ease of explanation, further detailed description thereof will be omitted. When any one of the calibration start enable signal ZQ_Start_EN and the count output signal CT_OUT is a logic low signal, the calibration control circuit 840 can output the calibration command signal ZQ_CTR of a low logic level.

[0079] That is, when the background calibration start signal ZQ_Start_BG and the calibration enable signal ZQ_EN are not input to the memory device because the memory controller or the host device determines not to perform the ZQ calibration operation, the calibration control circuit 840 can prevent the generation of the calibration command signal ZQ_CTR. In addition, even if the calibration command CMD_ZQ to control the execution of the ZQ calibration operation is received from the memory controller or the host device, the ZQ calibration operation is prevented from being performed when a low power supply voltage is applied to the calibration circuit. When the comparator 842 determines that the power supply voltage VDDQ is lower than the reference voltage V REF , the calibration control circuit 840 can output the calibration command signal ZQ_CTR of a low logic level, and thus, the ZQ calibration operation can be disabled.

[0080] Figure 9 The memory device of the embodiment can include a calibration control circuit 940 in which,Figure 6 A portion of the calibration control circuit 640 can be connected to Figure 8 This is part of the calibration control circuit 840. Specifically, it occurs when a calibration start signal ZQ_Start_CMD is received from the command decoder 950, or when a background calibration start signal ZQ_Start_BG is received via its feedback circuit through the feedback calibration start enable signal ZQ_Start_EN. Figure 9 The storage device can output the calibration command signal ZQ_CTR. Figure 9 Certain aspects of the calibration circuit 930, calibration control circuit 940, and command decoder 950 shown may be respectively related to the previously referenced Figure 1 and Figure 2 The calibration circuit 230, calibration control circuit 240, and command decoder 250 described are identical or similar in some aspects. For ease of explanation, further description of these aspects may be omitted.

[0081] When a calibration enable signal ZQ_EN is input from the memory controller or host device, the storage device can receive either a command enable signal ZQ_EN (CMD) or a background enable signal ZQ_EN (BG). The command enable signal ZQ_EN (CMD) is used to activate the execution of the ZQ calibration operation based on a command from the memory controller or host device, while the background enable signal ZQ_EN (BG) can be used to activate the execution of the ZQ calibration operation based on internal feedback from the storage device. That is, when the memory controller or host device determines that a ZQ calibration operation is required, it can provide the storage device with either the background enable signal ZQ_EN (BG) or the command enable signal ZQ_EN (CMD) as the calibration enable signal ZQ_EN.

[0082] According to an embodiment, a background enable signal ZQ_EN(BG) and a command enable signal ZQ_EN(CMD) are not applied to the storage device simultaneously. Furthermore, when the memory controller or host device determines to perform a ZQ calibration operation by directly sending a command, only the command enable signal ZQ_EN(CMD) is sent to the storage device. Conversely, when the memory controller or host device determines to perform a ZQ calibration operation internally within the storage device, only the background enable signal ZQ_EN(BG) may be provided to the storage device. In another embodiment, when the memory controller or host device determines that a ZQ calibration operation is not required, neither the command enable signal ZQ_EN(CMD) nor the background enable signal ZQ_EN(BG) is provided to the storage device.

[0083] Comparator 942 can compare the supply voltage VDDQ with the reference voltage V REFThe comparison signal COMP is generated by comparison, and the counter 941 can generate a count output signal CT_OUT according to the calibration start enable signal ZQ_Start_EN and the comparison signal COMP. When either the count output signal CT_OUT or the calibration start enable signal ZQ_Start_EN is at a high logic level, the calibration control circuit 940 can determine that the calibration command signal ZQ_CTR is a logic high signal. When either the count output signal CT_OUT or the calibration start enable signal ZQ_Start_EN is a logic low signal, the calibration command signal ZQ_CTR can be output at a logic low level.

[0084] That is, when the calibration start signal ZQ_Start and the calibration enable signal ZQ_EN are not input to the memory device because the memory controller or the host device determines not to perform the ZQ calibration operation, the calibration control circuit 940 can prevent the calibration command signal ZQ_CTR from being generated. In addition, even if the calibration command CMD_ZQ to control the execution of the ZQ calibration operation is received from the memory controller or the host device, the ZQ calibration operation is prevented from being performed when a low power supply voltage is applied to the calibration circuit, and when the comparator 942 determines that the power supply voltage VDDQ is lower than the reference voltage V REF , the calibration control circuit 940 can output the calibration command signal ZQ_CTR at a low logic level, so that the ZQ calibration operation can be disabled.

[0085] Figure 10 is a flowchart of operations according to the operation method of the memory device of the embodiment.

[0086] In operation S100, the memory device according to the embodiment can determine whether a calibration start signal ZQ_Start is transmitted. The calibration start signal ZQ_Start can be a signal included in a command received from a memory controller or a host device, or can be a background signal periodically generated in an internal feedback circuit. When the calibration start signal ZQ_Start is transmitted, the memory device can perform operation S200, and when the calibration start signal ZQ_Start is not transmitted, the memory device can end the ZQ calibration operation.

[0087] In operation S200, the memory device according to the embodiment can compare a power supply voltage VDDQ with a reference voltage V REF . When the power supply voltage VDDQ is higher than the reference voltage V REF , the memory device can determine that the power supply voltage VDDQ has a high power voltage level VDDQ_HIGH, and when the power supply voltage VDDQ is lower than the reference voltage V REF , the memory device can determine that the power supply voltage VDDQ has a low power voltage level VDDQ_LOW.

[0088] In operation S300, when the memory device determines that the power supply voltage VDDQ has the high power supply voltage level VDDQ_HIGH, the memory device can output the calibration command signal ZQ_CTR of a high logic level. When the calibration command signal ZQ_CTR of the high logic level is input to the calibration circuit, the calibration circuit can perform a ZQ calibration operation.

[0089] In operation S400, when the memory device determines that the power supply voltage VDDQ has the low power supply voltage level VDDQ_LOW, the memory device can output the calibration command signal ZQ_CTR of a low logic level. When the calibration command signal ZQ_CTR of the low logic level is input to the calibration circuit, the calibration circuit does not perform a ZQ calibration operation, and can again determine whether to input the calibration start signal ZQ_Start to the memory device in operation S100, thus repeating the above-described operations.

[0090] Figure 11 is a flowchart of operations of an operation method of a calibration control circuit according to an embodiment of a counter including Figures 6 to 9

[0091] According to an embodiment, when it is determined that the power supply voltage is lower than the reference voltage V REF , the memory device can increase the count value by 1 at each count timing. In operation S210, when it is determined that the power supply voltage VDDQ is lower than the reference voltage V REF , the memory device can determine whether the count value temporarily stored in the counter is 0 or equal to or greater than 1. When the count value is 0, the counter can determine the count timing corresponding to the generated count pulse as an initial count timing. When the count timing corresponding to the generated count pulse is determined as the initial count timing, the memory device can proceed to operation S220, and when the count timing is not determined as the initial count timing, the memory device can proceed to operation S230.

[0092] In operation S220, the memory device can at least temporarily start storing the count value, and thus can start a count operation. In operation S230, the memory device can increase the count value by 1 based on the count pulse generated corresponding to the count timing.

[0093] In operation S240, the memory device can determine whether the accumulated count value of the counter is greater than a reference count value. The reference count value can be set in advance. However, embodiments of the inventive concept are not limited thereto. The reference count value can be adjustable according to the amount of power consumed. When the accumulated count value is greater than the reference count value, the memory device can generate the calibration command signal ZQ_CTR of a low logic level by proceeding to operation S400, and when the accumulated count value is less than the reference count value, the memory device can proceed to operation S100.

[0094] ​Figures 12 to 14 An embodiment of a calibration control circuit including a hysteresis comparator 1241 is shown.

[0095] According to Figure 12 An embodiment of a calibration control circuit 1240 of a memory device can output a calibration start enable signal ZQ_Start_EN in response to a calibration start signal ZQ_Start_CMD and a calibration enable signal ZQ_EN. The calibration control circuit 1240 can determine a logic state of the calibration start enable signal ZQ_Start_EN in response to the calibration start signal ZQ_Start_CMD and the calibration enable signal ZQ_EN. For example, when the calibration start signal ZQ_Start_CMD and the calibration enable signal ZQ_EN are logic high signals, the calibration control circuit 1240 can output the calibration start enable signal ZQ_Start_EN at a logic high level through an AND gate. Figure 12 Certain aspects of the calibration circuit 1230, the calibration control circuit 1240, and the command decoder 1250 shown in FIG. 12A can be the same as or similar to certain aspects of the calibration circuit 230, the calibration control circuit 240, and the command decoder 250, respectively, previously described with reference to FIG. 2A. Figure 1 and Figure 2 Certain aspects of the calibration circuit 1230, the calibration control circuit 1240, and the command decoder 1250 shown in FIG. 12A can be the same as or similar to certain aspects of the calibration circuit 230, the calibration control circuit 240, and the command decoder 250, respectively, previously described with reference to FIG. 2A.

[0096] A memory device according to an embodiment can classify a level of a power supply voltage VDDQ as a high level and a low level based on a hysteresis comparator 1241 operating in a hysteresis mode. The hysteresis comparator 1241 can be referred to as a Schmitt trigger. In the hysteresis mode, at least two reference voltages are compared with the power supply voltage VDDQ. When the power supply voltage VDDQ is equal to or higher than a first reference voltage V REF1 , the power supply voltage VDDQ can have a high level, and when the power supply voltage VDDQ is equal to or lower than a second reference voltage V REF2 , the power supply voltage VDDQ can have a low level. In this case, the level of the first reference voltage V REF1 may be greater than the level of the second reference voltage V REF2 .

[0097] When the hysteresis comparator 1241 operates in the hysteresis mode, the comparator 1241 can determine whether the power supply voltage VDDQ having a voltage between the first reference voltage V REF1 and the second reference voltage V REF2 has a high logic level or a low logic level based on a previous logic level of the power supply voltage VDDQ. For example, when the power supply voltage VDDQ input to the hysteresis comparator 1241 has a higher logic level than the first reference voltage V REF1a low level, and when a previous level of the supply voltage VDDQ is greater than a first reference voltage V REF1 In contrast, when the supply voltage VDDQ input to the comparator 1241 has a level lower than the first reference voltage V REF1 , or when a previous level of the supply voltage VDDQ is lower than the level of the first reference voltage V REF1 , the comparator 1241 can determine that the supply voltage VDDQ has a low supply voltage level VDDQ_LOW.

[0098] That is, the comparator 1241 can determine which one of the first reference voltage V REF1 and the second reference voltage V REF2 will be compared with the supply voltage VDDQ according to a previous logic state of the calibration command signal ZQ_CTR. When the previous logic state of the calibration command signal ZQ_CTR is a logic high level, the comparator 1241 can compare the first reference voltage V REF1 with the supply voltage VDDQ, and when the previous logic state of the calibration command signal ZQ_CTR is a logic low level, the hysteresis comparator 1241 can compare the second reference voltage V REF2 with the supply voltage VDDQ.

[0099] When it is determined that the supply voltage VDDQ has a high supply voltage level VDDQ_HIGH, the comparator 1241 according to an embodiment can output a comparison signal COMP of a high logic level, and when it is determined that the supply voltage VDDQ has a low level, the comparator 1241 can output a comparison signal COMP of a low logic level.

[0100] The calibration control circuit 1240 of the memory device can provide the calibration command signal ZQ_CTR to the calibration circuit 1230 according to the calibration start enable signal ZQ_Start_EN and the comparison signal COMP. When the calibration start enable signal ZQ_Start_EN and the comparison signal COMP are logic high signals, it can be determined that the calibration command signal ZQ_CTR is logic high, and when any one of the calibration start enable signal ZQ_Start_EN and the comparison signal COMP is a logic low signal, the calibration control circuit 1240 can output a calibration command signal ZQ_CTR of logic low.

[0101] That is, when the calibration start signal ZQ_Start_CMD and the calibration enable signal ZQ_EN are not input to the memory device since the memory controller or the host device determines not to perform the ZQ calibration operation, the calibration control circuit 1240 can block the generation of the calibration command signal. Also, when the comparator 1241 determines that the power voltage VDDQ has a low logic level, the calibration control circuit 1240 can disable the ZQ calibration operation by outputting the calibration command signal ZQ_CTR of a low logic level.

[0102] Figure 13 is a timing diagram of signals input to the calibration control circuit of Figure 12

[0103] In the fifth section T5, the calibration control circuit according to the embodiment can output the calibration command of a high logic level due to the high power voltage level VDDQ_HIGH which is greater than the first reference voltage V REF1 At the point in time when the power voltage VDDQ of the fifth section T5 becomes equal to the first reference voltage V REF1 , the memory device can determine the previous level of the power voltage VDDQ, and refer to Figure 13 Since the previous level of the power voltage VDDQ is a high logic level, the calibration control circuit can continue to determine that the power voltage VDDQ has a high logic level. Therefore, the calibration control circuit can output the calibration command signal ZQ_CTR of a high logic level although the power voltage VDDQ is between the first reference voltage V REF1 and the second reference voltage V REF2 .

[0104] Then, in the sixth section T6, as the level of the power voltage VDDQ drops to a low logic level, the logic state of the calibration start signal ZQ_Start or the calibration enable signal ZQ_EN should ideally be transitioned to a low logic level, but can remain in a logic high state as in the fifth section T5.

[0105] In the sixth section T6, since the level of the power voltage VDDQ becomes lower than the level of the second reference voltage V REF2 , the calibration control circuit can determine that the power voltage VDDQ has a low level, and thus the calibration control circuit can output the comparison signal COMP of a low logic level. The calibration control circuit can compare the logic state of the calibration start enable signal ZQ_Start_EN with the logic state of the comparison signal COMP through, for example, an AND gate, and since the comparison signal COMP is a logic low signal, the calibration control circuit can output the calibration command signal ZQ_CTR of a low logic level.

[0106] At the point in time when the power voltage VDDQ of the sixth section T6 becomes equal to the second reference voltage V REF2 ​At the time point, the memory device can determine the previous level of the power supply voltage VDDQ, and refer to Figure 13 Because the previous level of the power supply voltage VDDQ is the low logic level, the calibration control circuit can continue to determine that the power supply voltage VDDQ has the low logic level. Thus, although the power supply voltage VDDQ is between the first reference voltage V REF1 and the second reference voltage V REF2 , the calibration control circuit can continue to output the calibration command signal ZQ_CTR of the low logic level.

[0107] That is, the calibration control circuit can determine the reference voltage to compare with the power supply voltage VDDQ between the first reference voltage V REF1 and the second reference voltage V REF2 , according to the logic state of the calibration command signal ZQ_CTR. In the fifth part T5, because the calibration command signal ZQ_CTR is the logic high signal, the calibration control circuit can compare the power supply voltage VDDQ with the second reference voltage V REF2 , and in the sixth part T6, because the calibration command signal ZQ_CTR is the logic low signal, the calibration control circuit can compare the power supply voltage VDDQ with the first reference voltage V REF1 .

[0108] In the seventh part T7, because the power supply voltage VDDQ becomes higher than the first reference voltage V REF1 , the calibration control circuit can determine that the power supply voltage VDDQ has the high logic level, and can output the comparison signal COMP of the high logic level. The calibration control circuit can compare the logic state of the calibration start enable signal ZQ_Start_EN with the logic state of the comparison signal COMP by using, for example, an AND gate, and because the logic state of the calibration start enable signal ZQ_Start_EN and the logic state of the comparison signal COMP are the high logic level, the calibration control circuit can output the calibration command signal ZQ_CTR of the high logic level. Thus, the calibration control circuit can resume the ZQ calibration operation by providing the calibration command signal ZQ_CTR of the high logic level to the calibration circuit.

[0109] Figure 14 and Figure 15 An example of the calibration control circuit including a hysteresis comparator is shown.

[0110] According to Figure 14The calibration control circuit 1440 of the memory device of the embodiment can output a calibration start enable signal ZQ_Start_EN according to the background calibration start signal ZQ_Start_BG and the calibration enable signal ZQ_EN. The comparator 1441 can determine whether the supply voltage VDDQ has a high logic level or a low logic level. The comparator 1441 can be a hysteresis comparator 1441 operating in a hysteresis mode. The hysteresis comparator 1441 can output a comparison signal COMP by determining whether the supply voltage VDDQ has a low logic level or a high logic level. Referring to Figure 12 The output of the comparison signal COMP is described, and thus, a further detailed description thereof will be omitted for convenience of explanation. Figure 14 Some aspects of the calibration circuit 1430, the calibration control circuit 1440, and the command decoder 1450 shown in FIG. 14A can be the same as or similar to those of the calibration circuit 230, the calibration control circuit 240, and the command decoder 250, respectively, previously described with reference to Figure 1 and Figure 2 Some aspects of the calibration circuit 230, the calibration control circuit 240, and the command decoder 250 described with reference to FIG. 2A can be the same as or similar to those of the calibration circuit 1430, the calibration control circuit 1440, and the command decoder 1450, respectively. A further description of the aspects will be omitted for convenience of explanation.

[0111] When the calibration start enable signal ZQ_Start_EN and the comparison signal COMP are logic high signals, the calibration control circuit 1440 can determine that the calibration command signal ZQ_CTR is a logic high signal, and when any one of the calibration start enable signal ZQ_Start_EN and the comparison signal COMP is a logic low signal, the calibration control circuit 1440 can output the calibration command signal ZQ_CTR as a low logic level.

[0112] That is, when the background calibration start signal ZQ_Start_BG and the calibration enable signal ZQ_EN are not input to the memory device because the memory controller or the host device determines not to perform the ZQ calibration operation, the calibration control circuit 1440 can prevent the generation of the calibration command signal ZQ_CTR. In addition, when the hysteresis comparator 1441 determines that the supply voltage VDDQ has a low level, the calibration control circuit 1440 can disable the ZQ calibration operation by outputting the calibration command signal ZQ_CTR as a low logic level.

[0113] Figure 15 The memory device of the embodiment can include a calibration control circuit 1540 in which Figure 12 A part of the calibration control circuit 1240 of the embodiment can be connected to Figure 14 A part of the calibration control circuit 1440 of the embodiment. That is, when Figure 15The memory device can output a calibration command signal ZQ_CTR when the memory device receives a calibration start signal ZQ_Start_CMD from the command decoder 1550 or a background calibration start signal ZQ_Start_BG through the feedback circuit that receives the calibration start enable signal ZQ_Start_EN.

[0114] When the memory controller or host device determines to perform a ZQ calibration operation, the calibration enable signal ZQ_EN of any one of the background enable signal ZQ_EN(BG) and the command enable signal ZQ_EN(CMD) can be provided to the memory device. The background enable signal ZQ_EN(BG) and the command enable signal ZQ_EN(CMD) are not applied to the memory device at the same time, and only the command enable signal ZQ_EN(CMD) can be applied to the memory device when it is determined to perform a ZQ calibration operation due to the memory controller or host device directly sending a command to the memory device. Figure 15 Certain aspects of the calibration circuit 1530, the calibration control circuit 1540, and the command decoder 1550 shown in FIG. 15 can be the same as or similar to the calibration circuit 230, the calibration control circuit 240, and the command decoder 250, respectively, previously described with reference to Figure 1 and Figure 2 Certain aspects of the calibration circuit 230, the calibration control circuit 240, and the command decoder 250 described with reference to

[0115] The calibration control circuit 1540 can generate a calibration start enable signal ZQ_Start_EN by receiving a calibration start signal ZQ_Start and a calibration enable signal ZQ_EN. The hysteresis comparator 1541 can generate a comparison signal COMP based on the comparator 1541 operating in a hysteresis mode. Referring to Figure 12 and Figure 13 The generation of the calibration start enable signal ZQ_Start_EN and the comparison signal COMP is described, and further detailed description thereof will be omitted for ease of explanation.

[0116] When either the calibration start enable signal ZQ_Start_EN or the comparison signal COMP is a logic high signal, the calibration control circuit 1540 can determine that the calibration command signal ZQ_CTR is a logic high signal; whereas when either of the calibration start enable signal ZQ_Start_EN or the comparison signal COMP is a logic low signal, the calibration control circuit 1540 can output the calibration command signal ZQ_CTR at a low logic level.

[0117] That is, when the calibration start signal ZQ_Start and the calibration enable signal ZQ_EN are not input to the memory device since the memory controller or the host device determines not to perform the ZQ calibration operation, the calibration control circuit 1540 can prevent the generation of the calibration command signal. Also, when the comparator 1541 determines that the supply voltage VDDQ has a low logic level, the calibration control circuit 1540 can disable the ZQ calibration operation by outputting the calibration command signal ZQ_CTR of a low logic level.

[0118] According to Figure 12 and Figure 15 , when the supply voltage VDDQ has a value between the first comparison voltage and the second comparison voltage, in some cases, the calibration control circuit can maintain the previous voltage level. Thus, the calibration control circuit can prevent an undesired toggling of the logic state of the calibration command signal ZQ_CTR that can be caused by noise in the supply voltage VDDQ. For example, referring to Figure 13 , when the supply voltage VDDQ has a high logic level, the supply voltage VDDQ can decrease below or equal to the first reference voltage V REF1 , while the comparator operating in the hysteresis mode can maintain the logic state of the calibration command signal ZQ_CTR to a logic high state unless the supply voltage VDDQ drops below or equal to the second reference voltage V REF2 .

[0119] Figure 16 is Figures 12 to 15 a flowchart of operations of an operation method of an example of a calibration control circuit according to including a hysteresis comparator.

[0120] In operation S110, when the calibration start signal ZQ_Start is received, the calibration control circuit can determine the current logic state of the calibration command signal ZQ_CTR. When the logic state of the calibration command signal ZQ_CTR is a high logic level, the calibration control circuit can proceed to operation S120. When the logic state of the calibration command signal ZQ_CTR is a low logic level, the calibration control circuit can proceed to operation S130.

[0121] In operation S120, when it is determined that the current logic state of the calibration command signal ZQ_CTR is a high logic level, the calibration control circuit can set the comparison voltage compared with the supply voltage VDDQ to the second reference voltage V REF2 . In operation S130, when it is determined that the current logic state of the calibration command signal ZQ_CTR is a low logic level, the calibration control circuit can set the comparison voltage compared with the supply voltage VDDQ to the first reference voltage V REF1Therefore, when the calibration command signal ZQ_CTR is in a high logic state, the calibration control circuit can continue to output a high logic level calibration command signal ZQ_CTR, regardless of the power supply voltage VDDQ and the first reference voltage V. REF1 What are the results of the comparison? When the calibration command signal ZQ_CTR is at a low logic level, the calibration control circuit can continue to output a low logic level calibration command signal ZQ_CTR, regardless of the power supply voltage VDDQ and the second reference voltage V. REF2 What were the results of the comparison?

[0122] Figure 17 An example of a calibration control circuit including a counter and a hysteresis comparator is shown. Figure 18 Is input to Figure 17 Timing diagram of the signals of the calibration control circuit.

[0123] Figure 17 The calibration control circuit 1740 may include a hysteresis comparator 1742 that operates in hysteresis mode, instead of Figure 8 The comparator 842 of the calibration control circuit shown. Based on the logic state of the calibration command signal ZQ_CTR, it compares the power supply voltage VDDQ with the first reference voltage V... REF1 Second reference voltage V REF2 When comparing one of them, a comparison signal COMP can be generated from the comparator 1742. Figure 17 Certain aspects of the calibration circuit 1730, calibration control circuit 1740, and command decoder 1750 shown may be respectively related to the previously referenced Figure 1 and Figure 2 The calibration circuit 230, calibration control circuit 240, and command decoder 250 described are identical or similar in some aspects. For ease of explanation, further description of these aspects may be omitted.

[0124] In section T8, the calibration command signal ZQ_CTR is in a high logic state, and the calibration control circuit 1740 can compare the power supply voltage VDDQ with the second reference voltage V REF2 A comparison can be made and a comparison signal COMP can be generated. In this case, the hysteresis comparator 1742 can provide the low logic level comparison signal COMP to the counter 1741. The counter 1741 can output a high logic level count output signal CT_OUT without performing a counting operation, and therefore, a high logic level calibration command signal ZQ_CTR can be provided to the calibration circuit 1730.

[0125] In part T9, because the supply voltage VDDQ drops below or equal to the second reference voltage V REF2Therefore, the comparator 1742 can change the logic state of the comparison signal COMP. The comparator 1742 can transition the logic low state of the comparison signal COMP to the logic high state in the ninth portion T9, and the counter 1741 receiving the calibration start enable signal ZQ_Start_EN and the comparison signal COMP of the high logic level can perform a counting operation by generating a count pulse CP. The counter 1741 generates the count pulse CP less than or equal to the reference count value, and thus, the counter 1741 can output the same count output signal CT_OUT as in the eighth portion T8. The calibration control circuit 1740 can continue to provide the calibration command signal ZQ_CTR of the high logic level to the calibration circuit 1730.

[0126] In the tenth portion T10, the counter 1741 can continuously generate the count pulse CP exceeding the reference count value, and thus, the count output signal CT_OUT of the logic low level can be generated. When the count output signal CT_OUT of the low logic level is generated, the count output signal CT_OUT and the calibration start enable signal ZQ_Start_EN can be connected via the AND gate, and the calibration command signal ZQ_CTR of the low logic level can be output.

[0127] When the power voltage VDDQ becomes higher than the first reference voltage V REF1 When the low power voltage level VDDQ_LOW increases to the high power voltage level VDDQ_HIGH, the power voltage VDDQ becomes higher than the first reference voltage V

[0128] Embodiments are described and illustrated in terms of functional blocks, units, and / or modules. Those skilled in the art will appreciate that these blocks, units, and / or modules can be implemented by electronic (or optical) circuitry, such as a logic circuit, discrete components, a microprocessor, a hard-wired circuit, memory elements, wiring connections, and / or the like, which can be formed from any of a number of semiconductor-based or other technologies. When the blocks, units, and / or modules are implemented by microprocessor or similar technology, they can be programmed using software (e.g., microcode) to perform various functions as discussed herein, and the program(s) can be optionally stored in storage devices (e.g., RAM, ROM, EEPROM, flash memory, etc.). Alternatively, each block, unit, and / or module can be implemented by special purpose hardware, or by a combination of special purpose hardware and a processor (e.g., one or more programmed microprocessors and associated circuitry) that performs some functions.

[0129] While the present concepts have been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the present concepts as defined by the appended claims.

Claims

1. A storage device, comprising: A calibration circuit configured to perform a ZQ calibration operation based on a calibration command signal and a calibration power supply voltage; as well as A calibration control circuit configured to determine the logic state of the calibration command signal based on a comparison result obtained by comparing the level of the calibration power supply voltage with the level of at least one reference voltage. The calibration circuit is further configured to determine whether to perform the ZQ calibration operation based on the logic state of the calibration command signal.

2. The storage device according to claim 1, wherein, The calibration control circuit is configured to determine the logic state of the calibration command signal based on a comparison result obtained by comparing the level of the calibration power supply voltage with the level of the at least one reference voltage within a specific time period.

3. The storage device according to claim 2, wherein, The calibration control circuit also includes: A counter, configured to output a signal for determining the logic state of the calibration command signal by receiving the comparison result at each counting time interval.

4. The storage device according to claim 3, wherein, The counter is configured to output the calibration command signal with a high logic level when the comparison result indicates that the level of the calibration power supply voltage is equal to or greater than the level of the at least one reference voltage and the comparison result is received at least once during a counting time.

5. The storage device according to claim 3, wherein, The counter is configured to output the calibration command signal with a low logic level when the comparison result indicates that the level of the calibration power supply voltage is lower than the level of the at least one reference voltage and the number of times the comparison result is received is equal to or greater than a specific number of consecutive times.

6. The storage device according to claim 1, wherein, The calibration control circuit is configured to compare the level of the calibration power supply voltage with different reference voltage levels according to the logic state of the calibration command signal.

7. The storage device according to claim 6, wherein, The calibration control circuit is configured to: when the calibration command signal is a logic high signal, compare the level of the calibration power supply voltage with one of the different reference voltage levels, and when the level of the calibration power supply voltage is less than the one of the different reference voltage levels, change the calibration command signal to a low logic level.

8. The storage device according to claim 6, wherein, The calibration control circuit is configured to: when the calibration command signal is a logic low signal, compare the level of the calibration power supply voltage with one of the different reference voltage levels, and when the level of the calibration power supply voltage is equal to or higher than the one of the different reference voltage levels, change the calibration command signal to a high logic level.

9. A calibration control circuit, comprising: A comparator configured to obtain a comparison result by comparing a calibration supply voltage input to a calibration circuit configured to perform ZQ calibration operations with at least one reference voltage; as well as A command signal output unit is configured to determine the logic state of a calibration command signal based on the comparison result, wherein the logic state of the calibration command signal is used to determine whether the calibration circuit should perform the ZQ calibration operation.

10. The calibration control circuit according to claim 9, wherein, The command signal output unit includes: A counter, configured to receive the comparison result from the comparator at each counting time interval, and output a signal for determining the calibration command signal based on the comparison result within a specific time period.

11. The calibration control circuit according to claim 10, wherein, The counter is configured to output the calibration command signal with a high logic level when the comparison result indicates that the level of the calibration power supply voltage is equal to or higher than the level of the at least one reference voltage and the comparison result is received within at least one counting time.

12. The calibration control circuit according to claim 10, wherein, The counter is configured to output the calibration command signal with a low logic level when the comparison result indicates that the level of the calibration power supply voltage is lower than the level of the at least one reference voltage and the number of times the comparison result is received is equal to or greater than a certain number of consecutive times.

13. The calibration control circuit according to claim 9, wherein, The comparator is configured to compare the calibration power supply voltage with different reference voltages based on the logic state of the calibration command signal.

14. The calibration control circuit according to claim 13, wherein, The calibration control circuit is configured to: when the calibration command signal is a logic high signal, and when the calibration power supply voltage is lower than the at least one reference voltage compared with the calibration power supply voltage, change the calibration command signal to a low logic level.

15. The calibration control circuit according to claim 13, wherein, The calibration control circuit is configured to: when the calibration command signal is a logic low signal, and when the calibration power supply voltage is equal to or higher than the at least one reference voltage compared with the calibration power supply voltage, change the calibration command signal to a high logic level.

16. A method of operating a storage device, the method comprising: The calibration power supply voltage input to the calibration circuit configured to perform ZQ calibration operation is compared with at least one reference voltage. as well as Based on the comparison result obtained by comparing the calibration power supply voltage with the at least one reference voltage, the logic state of the calibration command signal is determined, wherein the logic state of the calibration command signal is used to determine whether the calibration circuit should perform the ZQ calibration operation.

17. The operating method according to claim 16, wherein, The logical state of the calibration command signal is determined by receiving the comparison result at each counting time of the counter within a specific time period.

18. The operating method according to claim 17, wherein, The logical state for determining the calibration command signal includes: When the comparison result indicates that the calibration power supply voltage is lower than the at least one reference voltage and the number of times the comparison result is received is equal to or greater than a certain number of consecutive times, the calibration command signal with a low logic level is output.

19. The operating method according to claim 16, wherein, The comparison includes comparing different reference voltages with the calibration power supply voltage according to the logic state of the calibration command signal.

20. The operating method according to claim 19, wherein, The logical state for determining the calibration command signal includes: When the calibration command signal is a logic high signal, the calibration power supply voltage is compared with a first reference voltage, and when the calibration power supply voltage is lower than the first reference voltage, the calibration command signal is converted to a low logic level; or When the calibration command signal is a logic low signal, the calibration power supply voltage is compared with the second reference voltage, and when the calibration power supply voltage is equal to or higher than the second reference voltage, the calibration command signal is switched to a high logic level.

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