Method for manufacturing semiconductor structure

Abstract

A method for manufacturing a semiconductor structure includes the following operations. A stacking structure is formed on a substrate, the stacking structure including a plurality of semiconductor layers and a plurality of sacrificial layers stacked alternately, wherein the sacrificial layers contain germanium, and the germanium concentration of the sacrificial layers decreases from bottom to top. A virtual gate structure is formed on the stacking structure. Spacers are formed on both sides of the virtual gate structure. The virtual gate structure is removed to form an opening. The sacrificial layers are removed from the opening. A gate structure is formed to cover the semiconductor layers. In another manufacturing method, the stacking structure includes a plurality of semiconductor layers and a plurality of sacrificial layers stacked alternately, wherein the thickness of the semiconductor layers increases from bottom to top, or the thickness of the sacrificial layers increases from bottom to top. The design of the above-mentioned stacking structure can avoid the problem of uneven shape of the semiconductor layers that may occur after removing the sacrificial layers, and make the remaining semiconductor layers consistent in shape, with similar thickness and width.

Description

Technical Field

[0001] The invention relates to a method for manufacturing a semiconductor structure. Background Art

[0002] Semiconductor integrated circuit technology has experienced exponential growth, and multiple generations of integrated circuits have been developed, each with smaller and more complex circuits than the previous generation. In the process of integrated circuit development, functional density is usually increased and geometric dimensions are reduced, thereby increasing process complexity. For example, as integrated circuit technology moves towards smaller technology nodes, multi-gate components have been developed, such as gate-all-around field-effect transistors (GAAFETs). Compared with planar transistors, GAAFETs can better control the channel and reduce short-channel effects.

[0003] However, the etching process used to manufacture GAAFETs can cause uneven channel shapes, which can adversely affect the performance of GAAFETs. Therefore, new manufacturing methods need to be developed to overcome these issues. Summary of the Invention

[0004] The present invention provides a method for fabricating a semiconductor structure, comprising the following operations: forming a stacked structure on a substrate, the stacked structure comprising a plurality of alternating semiconductor layers and a plurality of sacrificial layers, wherein the sacrificial layers contain germanium, and the germanium concentration of the sacrificial layers decreases from bottom to top; forming a dummy gate structure on the stacked structure; forming spacers on both sides of the dummy gate structure; removing the dummy gate structure to form an opening; removing the sacrificial layers from the opening; and forming a gate structure to cover the semiconductor layers.

[0005] In some embodiments, the semiconductor layers include silicon, silicon carbide, or silicon phosphide, and the sacrificial layers include silicon germanium, germanium, or germanium tin.

[0006] In some embodiments, the thickness of the semiconductor layers increases from bottom to top.

[0007] In some embodiments, the thickness of the sacrificial layers increases from bottom to top.

[0008] In some embodiments, forming the stacked structure includes: forming a first sacrificial layer on a substrate; forming a first semiconductor layer on the first sacrificial layer; forming a second sacrificial layer on the first semiconductor layer, wherein a germanium concentration in the second sacrificial layer is lower than a germanium concentration in the first sacrificial layer; and forming a second semiconductor layer on the second sacrificial layer.

[0009] In some embodiments, among any two upper and lower adjacent sacrificial layers, the germanium concentration of the lower sacrificial layer is higher than the germanium concentration of the upper sacrificial layer by 5 at % to 15 at %.

[0010] The present invention provides a method for fabricating a semiconductor structure, comprising the following operations: forming a stacked structure on a substrate, the stacked structure comprising a plurality of alternating semiconductor layers and a plurality of sacrificial layers, wherein the thickness of the semiconductor layers increases from bottom to top, or the thickness of the sacrificial layers increases from bottom to top; forming a dummy gate structure on the stacked structure; forming spacers on both sides of the dummy gate structure; removing the dummy gate structure to form an opening; removing the sacrificial layers from the opening; and forming a gate structure to cover the semiconductor layers.

[0011] In some embodiments, the thickness of the semiconductor layers increases from bottom to top, and forming the stacked structure includes the following operations: forming a first sacrificial layer on a substrate; forming a first semiconductor layer on the first sacrificial layer; forming a second sacrificial layer on the first semiconductor layer; and forming a second semiconductor layer on the second sacrificial layer, wherein the thickness of the second semiconductor layer is greater than the thickness of the first semiconductor layer.

[0012] In some embodiments, the thickness of the sacrificial layers increases from bottom to top, and forming the stacked structure includes the following operations: forming a first sacrificial layer on a substrate; forming a first semiconductor layer on the first sacrificial layer; forming a second sacrificial layer on the first semiconductor layer, wherein the second sacrificial layer is thicker than the first sacrificial layer; and forming a second semiconductor layer on the second sacrificial layer.

[0013] In some embodiments, the semiconductor layers include silicon, silicon carbide, or silicon phosphide, and the sacrificial layers include silicon germanium, germanium, or germanium tin.

[0014] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other aspects, features and other advantages of the present invention will be more clearly understood with reference to the specification and the accompanying drawings, in which:

[0016] Figure 1 、 Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 and Figure 7A is a schematic diagram of a process for manufacturing a semiconductor structure according to various embodiments of the present invention.

[0017] Figure 7B It is along Figure 7A Schematic cross-section along the midline AA.

[0018] Figure 7C It is along Figure 7A Schematic cross-section of the midline BB.

[0019] Figure 8A 、 Figure 9A 、 Figure 10A and Figure 11A According to various embodiments of the present invention Figure 7B A cross-sectional diagram of the process of manufacturing a semiconductor structure.

[0020] Figure 8B 、 Figure 9B 、 Figure 9C 、 Figure 9D 、 Figure 10B and Figure 11B According to various embodiments of the present invention Figure 7C A cross-sectional diagram of the process of manufacturing a semiconductor structure. DETAILED DESCRIPTION

[0021] The following drawings illustrate several embodiments of the present invention. For clarity, many practical details are included in the following description. However, it should be understood that these practical details are not intended to limit the present invention. In other words, in some embodiments of the present invention, these practical details are not essential. Furthermore, to simplify the drawings, some commonly used structures and components are depicted in simplified schematic form.

[0022] Although a series of operations or steps are used below to illustrate the methods disclosed herein, the order in which these operations or steps are shown should not be construed as limiting the present invention. For example, certain operations or steps may be performed in a different order and / or simultaneously with other steps. Furthermore, not all illustrated operations, steps, and / or features must be performed to implement embodiments of the present invention. Furthermore, each operation or step described herein may include several sub-steps or actions.

[0023] The present invention provides a method for manufacturing a semiconductor structure. Figure 1 、 Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 and Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B 、 Figure 9C 、 Figure 9D 、 Figure 10A 、 Figure 10B 、 Figure 11A and Figure 11B In some embodiments, the fabrication method of the present invention can be applied to fabricate nanosheet field-effect transistors (NSFETs), nanowire field-effect transistors (NWFETs), gate-all-around field-effect transistors (GAAFETs), and the like.

[0024] like Figure 1 As shown, a multilayer stack 10A is formed on a substrate 20. The multilayer stack 10A includes a plurality of semiconductor layers 12A and a plurality of sacrificial layers 14A that are alternately stacked. Figure 1 Six semiconductor layers 12A and seven sacrificial layers 14A are shown, but this is merely for illustration. The number of semiconductor layers 12A and sacrificial layers 14A can be adjusted arbitrarily according to design requirements.

[0025] In some embodiments, the semiconductor layers 12A include silicon, silicon carbide, or silicon phosphide, and the sacrificial layers 14A include silicon germanium, germanium, or germanium tin. In some embodiments, the semiconductor layers 12A are doped with a Group V element. For example, the semiconductor layers 12A include phosphorus-doped silicon carbide. In some embodiments, the sacrificial layers 14A are doped with a Group III element. For example, the sacrificial layers 14A include boron-doped silicon germanium.

[0026] In some embodiments, the sacrificial layers 14A contain germanium, and the germanium concentration of the sacrificial layers 14A decreases from bottom to top. Figure 1 The germanium concentrations of the sacrificial layers 14A shown are arithmetically decreasing. For example, the germanium concentration of the bottom sacrificial layer 14A is 90 at%, and the germanium concentration of the top sacrificial layer 14A is 10 at%. The benefits of the germanium concentration of the sacrificial layers 14A decreasing from bottom to top will be further described below. In some embodiments, forming the multilayer stack 10A includes: forming a first sacrificial layer on the substrate 20. Forming a first semiconductor layer on the first sacrificial layer. Forming a second sacrificial layer on the first semiconductor layer, wherein the germanium concentration of the second sacrificial layer is lower than the germanium concentration of the first sacrificial layer. Forming a second semiconductor layer on the second sacrificial layer. Repeating the above operations can form the sacrificial layers 14A with the germanium concentration decreasing from bottom to top.

[0027] In some embodiments, the semiconductor layer 12A and the sacrificial layer 14A in the multilayer stack 10A may be deposited by processes such as vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0028] Each layer in the multilayer stack 10A may have a small thickness, for example, a thickness in the range of about 5 nm to about 30 nm. In some embodiments, the thickness of the semiconductor layer 12A increases from bottom to top. For example, Figure 1 The thickness of these semiconductor layers 12A shown is arbitrarily increased. In some embodiments, forming the multilayer stack 10A includes the following operations: forming a first sacrificial layer on a substrate. Forming a first semiconductor layer on the first sacrificial layer. Forming a second sacrificial layer on the first semiconductor layer. Forming a second semiconductor layer on the second sacrificial layer, wherein the thickness of the second semiconductor layer is greater than the thickness of the first semiconductor layer. Repeating the above operations can form these semiconductor layers 12A with increasing thickness from bottom to top. In other embodiments, the thickness of the sacrificial layer 14A increases from bottom to top. For example, Figure 1 The thicknesses of the sacrificial layers 14A are shown to increase in arithmetic steps. In some embodiments, forming the multilayer stack 10A includes the following operations: forming a first sacrificial layer on a substrate; forming a first semiconductor layer on the first sacrificial layer; forming a second sacrificial layer on the first semiconductor layer, wherein the second sacrificial layer has a thickness greater than that of the first sacrificial layer; and forming a second semiconductor layer on the second sacrificial layer. Repeating the above operations can form the sacrificial layers 14A with increasing thickness from bottom to top. The benefits of the above embodiments will be further described below.

[0029] In some embodiments, substrate 20 is a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The semiconductor substrate may be doped (doped with p-type or n-type dopants) or undoped. Substrate 20 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, an oxide layer, a silicon oxide layer, or the like. In some embodiments, the semiconductor material of substrate 20 includes silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or a combination thereof.

[0030] like Figure 2 As shown, the multilayer stack 10A and the substrate 20 are patterned to form a stacked structure 10B and fins 22. The stacked structure 10B includes a plurality of semiconductor layers 12B and a plurality of sacrificial layers 14B. The fins 22 are semiconductor strips patterned in the substrate 20. The semiconductor layer 12B and the sacrificial layer 14B include the remaining portions of the semiconductor layer 12A and the sacrificial layer 14A, respectively. In some embodiments, the stacked structure 10B is a nanosheet, a nanoribbon, or a nanowire. In some embodiments, the patterning can be performed by processes such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. In some embodiments, the width of the stacked structure 10B is greater than or equal to 25 nm. For example, the width of the stacked structure 10B is 25, 30, 40, 50, 60, 70, 80, 90, 100, 110, or 120 nm.

[0031] like Figure 3 As shown, a shallow trench isolation region (STI region) 300 is formed on the substrate 20 and between adjacent fins 22. The STI region 300 surrounds at least a portion of the fin 22, allowing at least a portion of the stack structure 10B to protrude from the adjacent STI region 300. In some embodiments, the STI region 300 includes an oxide, such as silicon oxide; a nitride, such as silicon nitride, or a combination thereof. In some embodiments, the STI region 300 can be formed by a CVD process, such as high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or a combination thereof.

[0032] like Figure 4 As shown, a dummy gate structure 400 is formed on the stacked structure 10B. The dummy gate structure 400 includes a dummy dielectric layer 410 and a dummy gate 420. For example, the dummy gate structure 400 can be formed by the following steps: Forming the dummy dielectric layer 410 to fully cover the Figure 3 The stacked structure 10B and the STI region 300 shown in FIG. 1 are formed by forming a virtual gate layer on the virtual dielectric layer 410, forming a patterned mask on the virtual gate layer, and transferring the pattern of the patterned mask to the virtual gate layer and the virtual dielectric layer 410 to form a virtual gate layer. Figure 4The dummy dielectric layer 410 and the dummy gate 420 are shown. The dummy gate 420 may have a length direction substantially perpendicular to the length direction of the fin 22. In some embodiments, the dummy gate 420 may be formed of a conductive or non-conductive material, such as amorphous silicon, polysilicon, polycrystalline silicon germanium, metal, metal nitride, metal silicide, metal oxide, etc.

[0033] like Figure 5 As shown, spacers 510 are formed on both sides of the dummy gate structure 400, the portion of the stack structure 10B not covered by the dummy gate structure 400 and the spacers 510 is removed, and the upper portion of the fin 22 is removed to form a recess R. In some embodiments, the spacers 510 include one or more layers of dielectric material. For example, the dielectric material includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, or a combination thereof. In some embodiments, the spacers 510 are formed by a conformal deposition process such as CVD, plasma-enhanced chemical vapor deposition (PECVD), ALD, plasma-enhanced atomic layer deposition (PEALD), etc. In some embodiments, the stack structure 10B is removed by using an anisotropic etching process (such as RIE, NBE, etc.).

[0034] like Figure 6 As shown, a portion of the sacrificial layer 14B in the stacked structure 10B is etched. More specifically, the exposed sidewalls of the sacrificial layer 14B are etched to form a recess between the adjacent semiconductor layers 12B. In some embodiments, the etching is performed using an anisotropic etching process (such as RIE, NBE, etc.).

[0035] Please refer to Figure 7A 、 Figure 7B and Figure 7C . Figure 7B It is along Figure 7A Schematic cross-section along the midline AA. Figure 7C It is along Figure 7A Schematic cross-section of the midline BB.

[0036] like Figure 7A and Figure 7B As shown, an internal spacer 710 is formed in the recess between adjacent semiconductor layers 12B. Since source / drain regions will be formed in the groove R later and the dummy gate structure 400 will be replaced by a gate structure, the internal spacer 710 will serve as an isolation feature between the gate structure and the source / drain regions. In addition, the internal spacer 710 can also prevent the source / drain regions from being damaged during the subsequent etching operation of the sacrificial layer 14B. Figure 7C As shown, the stacked structure 10B is covered by the dummy gate structure 400 .

[0037] See also Figure 8A 、 Figure 9A 、 Figure 10A and Figure 11A , the above diagram describes Figure 7B See Figure 8B 、 Figure 9B 、 Figure 10B and Figure 11B , the above diagram describes Figure 7C subsequent process.

[0038] like Figure 8A As shown, a source / drain region 810 is formed in the groove R, and an interlayer dielectric layer 820 is formed on the source / drain region 810. The source / drain region 810 is disposed on both sides of the stacked structure 10B. In some embodiments, the source / drain region 810 is formed by epitaxial growth. In other embodiments, before forming the interlayer dielectric layer 820 on the source / drain region 810, a contact etch stop layer (not shown) is formed to cover the source / drain region 810 and the spacer 510. Figure 8B As shown, when the source / drain regions 810 and the interlayer dielectric layer 820 are formed, the above elements are not present in Figure 8B sectional diagram of .

[0039] like Figure 9A and Figure 9B As shown, the dummy gate structure 400 is removed to form an opening OP1. In some embodiments, the dummy gate structure 400 is removed by an anisotropic dry etching process. Figure 8A When the dummy gate 420 is formed, the dummy dielectric layer 410 acts as an etch stop layer, and then the dummy dielectric layer 410 is removed. Figure 9B As shown, after the dummy gate structure 400 is removed, the stacked structure 10B is exposed through the opening OP1 .

[0040] like Figure 10A and Figure 10B As shown, the sacrificial layer 14B is removed from the opening OP1, forming an opening OP2 between adjacent semiconductor layers 12B. For example, the sacrificial layer 14B is removed by an etching process. In some embodiments, when the semiconductor layer 12B comprises silicon and the sacrificial layer 14B comprises silicon germanium, a wet etching process such as tetramethylammonium hydroxide (TMAH) or ammonium hydroxide (NH4OH) can be used to remove the sacrificial layer 14B.

[0041] Generally speaking, the etching process has a faster etching rate for the upper part of the stacked structure and a slower etching rate for the lower part of the stacked structure. Therefore, after removing the sacrificial layer, it is easy to cause the upper semiconductor layer to be thinner and smaller in width, while the lower semiconductor layer is thicker and wider. In other words, the shapes of the remaining semiconductor layers are uneven and there is a deformation problem. For stacked structures with a wider width, such as stacked structures with a width of 60nm or 100nm or more, the deformation problem caused by the etching process will be more serious. For example, since high-performance computing (HPC) devices usually require higher currents, a wider stacked structure will need to be formed in the process, so the deformation problem of HPC devices will be more serious. Since the semiconductor layer will serve as a channel layer, the uneven shape and deformation of the semiconductor layer will have an adverse effect on the performance of the final semiconductor structure.

[0042] In some embodiments, as Figure 9A and Figure 9B The sacrificial layers 14B shown contain germanium, and the germanium concentration of the sacrificial layers 14B decreases from bottom to top. For example, the germanium concentration of the sacrificial layers 14B decreases arithmetically. For example, the germanium concentration of the bottom sacrificial layer 14B is 90at%, and the germanium concentration of the top sacrificial layer 14B is 10at%. In some embodiments, in any two of these sacrificial layers 14B adjacent to each other, the germanium concentration of the bottom sacrificial layer 14B is 5at% to 15at% higher than the germanium concentration of the top sacrificial layer 14B. The germanium concentration affects the etching selectivity. The etching process has a faster etching rate for the sacrificial layer 14B with a higher germanium concentration. Conversely, the etching process has a slower etching rate for the sacrificial layer 14B with a lower germanium concentration. The present invention is based on Figure 9B The sacrificial layer 14B shown has a structure with a germanium concentration that decreases from bottom to top, which slows down the etching rate of the upper sacrificial layer 14B and speeds up the etching rate of the lower sacrificial layer 14B. Therefore, the manufacturing method of the present invention can overcome the problem of uneven shape and deformation of the semiconductor layer in the etching process mentioned above, so that the etching rate of the upper and lower sacrificial layers 14B is similar, thereby making the remaining semiconductor layers 12B (i.e. Figure 10B The semiconductor layers 12B shown have uniform shapes, similar thicknesses and widths. Therefore, the semiconductor structure made from these semiconductor layers 12B can have better performance.

[0043] In other embodiments, see Figure 9C , Figure 9C 1 is a schematic cross-sectional view of a semiconductor structure fabricated according to various embodiments of the present invention. Figure 9CAs shown, in the stacked structure 10C, the thickness of the semiconductor layer 12C increases from bottom to top. For example, the thickness of these semiconductor layers 12C increases arithmetic difference. Figure 10A and Figure 10B As shown, the sacrificial layers 14C are removed in the opening OP1. Figure 9A and Figure 9B The implementation of the sacrificial layer 14B will not be described in detail here.

[0044] As previously mentioned, the etching process has a faster etching rate for the upper portion of the stacked structure 10B and a slower etching rate for the lower portion of the stacked structure 10B. The present invention is designed such that the thickness of the semiconductor layer 12C increases from bottom to top to compensate for the uneven shape and deformation of the semiconductor layer caused by the etching process, thereby making the remaining semiconductor layers (i.e. Figure 10B The semiconductor layers 12B shown have uniform shapes, similar thicknesses and widths. Therefore, the semiconductor structure made from these semiconductor layers 12C can have better performance.

[0045] In other embodiments, see Figure 9D , Figure 9D 1 is a schematic cross-sectional view of a semiconductor structure fabricated according to various embodiments of the present invention. Figure 9D As shown, in the stacked structure 10D, the thickness of the sacrificial layer 14D increases from bottom to top. For example, the thickness of these sacrificial layers 14D increases arithmetic difference. Figure 10A and Figure 10B As shown, these sacrificial layers 14D are removed in the opening OP1. For details on the removal method, please refer to the above-mentioned removal method. Figure 9A and Figure 9B The implementation of the sacrificial layer 14B will not be described in detail here.

[0046] As previously mentioned, the etching process has a faster etching rate for the upper portion of the stacked structure 10B and a slower etching rate for the lower portion of the stacked structure 10B. The present invention is designed such that the thickness of the sacrificial layer 14D increases from bottom to top to compensate for the uneven shape and deformation of the semiconductor layer caused by the etching process, thereby making the remaining semiconductor layers (i.e. Figure 10B The semiconductor layers 12B shown have uniform shapes, similar thicknesses and widths. Therefore, the semiconductor structure made from these semiconductor layers 12D can have better performance.

[0047] In other embodiments, the Figure 9B and Figure 9C In some embodiments, in the stacked structure, the germanium concentration of the sacrificial layer decreases from bottom to top and the thickness of the semiconductor layer increases from bottom to top. Figure 9B and Figure 9D In some embodiments, in the stacked structure, the germanium concentration of the sacrificial layer decreases from bottom to top and the thickness of the sacrificial layer increases from bottom to top. Figure 9C and Figure 9D In some embodiments, the thickness of the semiconductor layer and the sacrificial layer increases from bottom to top in the stacked structure. Figure 9B 、 Figure 9C and Figure 9D In the stacked structure, the germanium concentration of the sacrificial layer decreases from bottom to top, and the thicknesses of the semiconductor layer and the sacrificial layer both increase from bottom to top. The above embodiments can compensate for the uneven shape and deformation of the semiconductor layer caused by the etching process.

[0048] like Figure 11A and Figure 11B As shown, a gate dielectric layer 1110 and a gate structure 1120 are formed to cover these semiconductor layers 12B to form a semiconductor structure 1100. The gate dielectric layer 1110 includes a first gate dielectric layer 1112 and a second gate dielectric layer 1114. The first gate dielectric layer 1112 is, for example, an interface layer, and the second gate dielectric layer 1114 is, for example, a high-k dielectric layer. In some embodiments, the gate structure 1120 includes one or more layers of conductive materials, such as a metal layer, a metal nitride layer (for example, titanium nitride, tantalum nitride, etc.), a metal carbide layer (for example, titanium carbide), or a combination thereof. By the aforementioned Figure 9B (The germanium concentration of the sacrificial layer decreases from bottom to top), Figure 9C (the thickness of the semiconductor layer increases from bottom to top), Figure 9D (the thickness of the sacrificial layer increases from bottom to top) can make the remaining Figure 11B Therefore, the semiconductor layer 12B, which serves as a channel of the semiconductor structure 1100 , can allow current to pass uniformly, thereby enabling the semiconductor structure 1100 to have good performance.

[0049] In summary, the present invention provides various methods for fabricating semiconductor structures. These methods can adjust the germanium concentration distribution of multiple sacrificial layers, the thickness distribution of multiple semiconductor layers, and the thickness distribution of multiple sacrificial layers, thereby avoiding the problem of uneven semiconductor layer shape that may occur after etching the sacrificial layers. Since wider stacked structures typically experience more severe deformation after etching, the fabrication methods of the present invention can be applied to wider stacked structures to overcome this deformation problem. Furthermore, the fabrication methods of the present invention are simple and can be easily applied to existing processes and equipment.

[0050] Although the present invention has been described in considerable detail with reference to certain embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0051] It will be apparent to those skilled in the art that various modifications and variations may be made to the structure of the present invention without departing from the scope or spirit of the present invention. In view of the foregoing, the present invention is intended to cover modifications and variations of the present invention that fall within the scope of the appended claims.

[0052]

Explanation of symbols

[0053] 10A: Multi-layer stacking

[0054] 10B, 10C, 10D: stacked structure

[0055] 12A, 12B, 12C, 12D: semiconductor layer

[0056] 14A, 14B, 14C, 14D: Sacrificial layer

[0057] 20:Substrate

[0058] 22: Fins

[0059] 300: shallow trench isolation area (STI area)

[0060] 400: Virtual gate structure

[0061] 410: Virtual dielectric layer

[0062] 420: Virtual Gate

[0063] 510: Spacer

[0064] 710: Internal spacer

[0065] 810: Source / drain region

[0066] 820: interlayer dielectric layer

[0067] 1100:Semiconductor Structure

[0068] 1110: Gate dielectric layer

[0069] 1112: first gate dielectric layer

[0070] 1114: second gate dielectric layer

[0071] AA, BB: line

[0072] OP1, OP2: Opening

[0073] R: Groove.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: A stacked structure is formed on a substrate, wherein the stacked structure includes a plurality of semiconductor layers and a plurality of sacrificial layers stacked alternately, wherein the thickness of the semiconductor layers increases equidistantly from bottom to top. Forming the stacked structure on the substrate includes: An operation of sequentially forming a first sacrificial layer, a first semiconductor layer, a second sacrificial layer, and a second semiconductor layer on the substrate; and Repeating the operation of sequentially forming the first sacrificial layer, the first semiconductor layer, the second sacrificial layer, and the second semiconductor layer on the substrate; forming a dummy gate structure on the stacked structure; forming spacers on both sides of the dummy gate structure; removing the dummy gate structure to form an opening; removing the sacrificial layers from the opening; and A gate structure is formed to cover the semiconductor layers. 2 . The manufacturing method according to claim 1 , wherein the semiconductor layers comprise silicon, silicon carbide, or silicon phosphide, and the sacrificial layers comprise silicon germanium, germanium, or germanium-tin. The manufacturing method according to claim 1 , wherein the semiconductor layers comprise silicon carbide or silicon phosphide. The manufacturing method according to claim 1 , wherein the thickness of the sacrificial layers increases gradually from bottom to top. 5 . The manufacturing method according to claim 1 , wherein the sacrificial layers contain germanium, and the germanium concentration of the sacrificial layers decreases from bottom to top. 6 . The manufacturing method according to claim 1 , wherein in any two upper and lower adjacent sacrificial layers, the germanium concentration of the lower sacrificial layer is 5 at % to 15 at % higher than the germanium concentration of the upper sacrificial layer.

7. A method for manufacturing a semiconductor structure, characterized in that: include: A stacked structure is formed on a substrate, wherein the stacked structure includes a plurality of semiconductor layers and a plurality of sacrificial layers stacked alternately, wherein the thickness of the sacrificial layers increases equidistantly from bottom to top. Forming the stacked structure on the substrate includes: An operation of sequentially forming a first sacrificial layer, a first semiconductor layer, a second sacrificial layer, and a second semiconductor layer on the substrate; and Repeating the operation of sequentially forming the first sacrificial layer, the first semiconductor layer, the second sacrificial layer, and the second semiconductor layer on the substrate; forming a dummy gate structure on the stacked structure; forming spacers on both sides of the dummy gate structure; removing the dummy gate structure to form an opening; removing the sacrificial layers from the opening; and A gate structure is formed to cover the semiconductor layers. The manufacturing method according to claim 7 , wherein the thicknesses of the semiconductor layers increase gradually from bottom to top. 9 . The manufacturing method according to claim 7 , wherein the germanium concentration of the sacrificial layers decreases from bottom to top. 10 . The manufacturing method according to claim 7 , wherein the semiconductor layers comprise silicon, silicon carbide, or silicon phosphide, and the sacrificial layers comprise silicon germanium, germanium, or germanium tin.

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