Semiconductor element and method for producing the same

Abstract

The present disclosure provides a semiconductor element and a method for manufacturing the same. The semiconductor element includes a first die, a first conductive feature, a second die, a first mask layer, a conductive filling layer, a plurality of insulating layers, and a plurality of protective layers. The first conductive feature is in the first die. The second die is on the first die. The first mask layer is on the second die. The conductive filling layer is at the first mask layer and the second die and extends to the first die and contacts the first conductive feature. The insulating layers are between the conductive filling layer and the first die and between the conductive filling layer and the second die. The protective layers are between the conductive filling layer and the first mask layer and cover upper portions of the insulating layers.

Description

Technical Field

[0001] This application claims priority and benefits from U.S. Official Application No. 16 / 926,281, filed July 10, 2020, the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method for fabricating the semiconductor device. In particular, it relates to a semiconductor device having multiple protective layers to reduce metal leakage to silicon, and a method for fabricating the semiconductor device having said protective layers. Background Technology

[0003] Semiconductor components are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components is continuously shrinking to meet the ever-increasing demands for computing power. However, this shrinking process introduces new and increasing problems, both in number and complexity. Therefore, challenges continue to emerge in improving quality, yield, performance, and reliability, while reducing complexity.

[0004] The above description of "prior art" is merely to provide background information and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0005] One embodiment of this disclosure provides a semiconductor device including a first die; a first conductive feature located in the first die; a second die located on the first die; a first masking layer located on the second die; a conductive filling layer located along the first masking layer and the second die, extending to the first die and contacting the first conductive feature; a plurality of insulating layers located between the conductive filling layer and the first die, and between the conductive filling layer and the second die; and a plurality of protective layers located between the conductive filling layer and the first masking layer, and covering the upper portion of the insulating layers.

[0006] In some embodiments of this disclosure, the highest point of the insulating layer is located on a vertical plane, which is a vertical plane flush with a lower surface of the first masking layer.

[0007] In some embodiments of this disclosure, multiple interfaces between the first masking layer and the protective layer are tapered.

[0008] In some embodiments of this disclosure, the angle between an upper surface of the first masking layer and the interface between the first masking layer and the protective layer is between approximately 120 degrees and approximately 135 degrees.

[0009] In some embodiments of this disclosure, the plurality of interfaces located between the protective layer and the conductive filler layer are substantially perpendicular.

[0010] In some embodiments of this disclosure, the conductive filling layer is made of polycrystalline silicon, tungsten, copper, carbon nanotubes, or solder alloy, and the insulating layer is made of silicon oxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate, parylene, epoxy resin, or poly(p-xylene).

[0011] In some embodiments of this disclosure, the semiconductor device further includes a barrier layer located between the insulating layer and the conductive filling layer, wherein the barrier layer is made of tantalum, tantalum nitride, titanium, titanium nitride, rhenium, nickel boride, or a tantalum nitride / tantalum bilayer.

[0012] In some embodiments of this disclosure, the semiconductor device further includes an adhesive layer located between the barrier layer and the conductive filling layer, wherein the adhesive layer is made of titanium, tantalum, titanium tungsten, or manganese nitride.

[0013] In some embodiments of this disclosure, the semiconductor device further includes a seed layer located between the adhesive layer and the conductive fill layer, wherein the seed layer has a thickness between about 10 nm and about 40 nm.

[0014] In some embodiments of this disclosure, the width of the conductive filling layer is between approximately 1 μm and approximately 22 μm.

[0015] In some embodiments of this disclosure, the depth of the conductive filler layer is between approximately 20 μm and approximately 160 μm.

[0016] In some embodiments of this disclosure, the aspect ratio of the conductive filler layer is between approximately 1:2 and approximately 1:35.

[0017] In some embodiments of this disclosure, the interface between the first masking layer and the protective layer is substantially vertical.

[0018] Another embodiment of this disclosure provides a semiconductor device including a first die; a first conductive feature located in the first die; a first masking layer located on the first die; a conductive filling layer located along the first masking layer, extending to the first die and contacting the first conductive feature; a plurality of insulating layers located between the conductive filling layer and the first die, and between the conductive filling layer and the first masking layer; and a plurality of protective layers located between the conductive filling layer and the insulating layers; wherein the lowest point of the protective layer is located on a vertical plane, the vertical plane being a vertical plane lower than a lower surface of the first masking layer.

[0019] In some embodiments of this disclosure, multiple interfaces between the first masking layer and the insulating layer are tapered.

[0020] In some embodiments of this disclosure, the plurality of interfaces located between the conductive filler layer and the protective layer are substantially perpendicular.

[0021] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, including performing a bonding process to bond a second die to a first die; forming a first masking layer on the second die; forming a first opening to pass through the first masking layer and the second die and extend to the first die; forming a plurality of insulating layers on a plurality of sidewalls of the first opening; forming a plurality of protective layers to cover the upper portion of the insulating layers; and forming a conductive filling layer in the first opening.

[0022] In some embodiments of this disclosure, the method for fabricating the semiconductor element further includes performing an etching process to extend the first opening in the first masking layer prior to the step of forming the insulating layer on the sidewall of the first opening.

[0023] In some embodiments of this disclosure, the etching process has an etching rate of the first masking layer on a substrate of the second die, which is between approximately 100:1 and approximately 1.05:1.

[0024] In some embodiments of this disclosure, the protective layer is made of aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, titanium nitride, tungsten nitride, silicon nitride, or silicon oxide.

[0025] Due to the design of the semiconductor device disclosed herein, the protective layer provides additional protection to reduce metal leakage into silicon. Furthermore, due to the geometry of the protective layer, the formation of the conductive filling layer requires no voids. In summary, this improves the manufacturing yield of the semiconductor device.

[0026] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0027] When referring to the drawings in conjunction with the embodiments and claims, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

[0028] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure.

[0029] Figures 2 to 6 This is a cross-sectional schematic diagram of various semiconductor elements according to some embodiments of the present disclosure.

[0030] Figure 7 This is a schematic flowchart of a method for fabricating a semiconductor element according to an embodiment of the present disclosure.

[0031] Figures 8 to 21 This is a cross-sectional schematic diagram of a process for fabricating the semiconductor device according to an embodiment of the present disclosure.

[0032] Figures 22 to 24 This is a cross-sectional schematic diagram of a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

[0033] Figures 25 to 28 This is a cross-sectional schematic diagram of a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

[0034] Figures 29 to 31 This is a cross-sectional schematic diagram of a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

[0035] The reference numerals in the attached figures are explained as follows:

[0036] 1A: Semiconductor components

[0037] 1B: Semiconductor components

[0038] 1C: Semiconductor components

[0039] 1D: Semiconductor components

[0040] 1E: Semiconductor components

[0041] 1F: Semiconductor components

[0042] 10: Method

[0043] 100: First grain

[0044] 101: First basement

[0045] 103: First dielectric layer

[0046] 105: First passivation layer

[0047] 107: First device element

[0048] 109: First electrical conductivity characteristic

[0049] 111: First Virtual Conductivity Feature

[0050] 200: Second grain

[0051] 201: Second basement

[0052] 201BS: Lower Surface

[0053] 203: Second dielectric layer

[0054] 205: Second passivation layer

[0055] 207: Second device element

[0056] 211: Second Virtual Conductivity Feature

[0057] 301: First mask layer

[0058] 301BS: Lower surface

[0059] 301TS: Top surface

[0060] 401: Conductive filler layer

[0061] 403: Insulation layer

[0062] 403B: Lower Section

[0063] 403C: Coverage Segment

[0064] 403S: Side Section

[0065] 403T: Upper Section

[0066] 403TP: Highest point

[0067] 405: Barrier Layer

[0068] 407: Adhesive layer

[0069] 409: Seed layer

[0070] 501: Protective layer

[0071] 501BP: Lowest point

[0072] 501S: Sidewall

[0073] 601: First Opening

[0074] 603: First conductive material

[0075] D1: Depth

[0076] IF01: Interface

[0077] IF03: Interface

[0078] IF07: Interface

[0079] IF09: Interface

[0080] S11: Steps

[0081] S13: Steps

[0082] S15: Steps

[0083] S17: Steps

[0084] S19: Steps

[0085] S21: Steps

[0086] S23: Steps

[0087] T1: Thickness

[0088] W1: Width

[0089] Z: Direction

[0090] α: Angle Detailed Implementation

[0091] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0092] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass not only the orientations shown in the figures but also different orientations of the elements during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0093] It should be understood that when a component is formed on, connected to, and / or coupled to another component, it may include embodiments in which these components are in direct contact, and may also include embodiments in which additional components are formed between these components so that these components are not in direct contact.

[0094] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0095] Unless otherwise specified herein, when referring to orientation, layout, location, shapes, sizes, amounts, or other measures, terms such as "same," "equal," "planar," or "coplanar" as used herein do not necessarily mean an exact identical orientation, layout, location, shape, size, amount, or other measure, but rather mean, within acceptable differences, that the orientation, layout, location, shape, size, amount, or other measure is substantially identical, for example, due to manufacturing processes. The term "substantially" may be used herein to convey this meaning. For example, "substantially the same," "substantially equal," or "substantially planar" means exactly the same, equal, or planar, or it can be the same, equal, or planar within an acceptable range of differences, for example, which can occur due to the manufacturing process.

[0096] It should be understood that the term "about" modifies an ingredient, a quantity of a component, or a reactant of this disclosure, indicating a possible variation in numerical quantity, for example, through typical measurements and liquid handling procedures used to produce concentrates or solutions. Furthermore, variation can arise from unintentional errors in the measurement procedures applied to the manufacture of the compositions or the implementation of the methods or similar methods, differences in manufacturing, source, or purity of the component. In one aspect, the term "about" means within 10% of the reported value. In another aspect, the term "about" means within 5% of the reported value. In yet another aspect, the term "about" means within 10%, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

[0097] In this disclosure, a semiconductor element generally means an element that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the scope of semiconductor elements.

[0098] It should be understood that in the description of this disclosure, "above" (or "up") refers to the direction corresponding to the Z-direction arrow, while "below" (or "down") refers to the relative direction corresponding to the Z-direction arrow.

[0099] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device 1A according to an embodiment of the present disclosure.

[0100] Please refer to Figure 1 The semiconductor device 1A may include a first die 100, a second die 200, a first masking layer 301, a conductive filling layer 401, a plurality of insulating layers 403, a barrier layer 405, an adhesive layer 407, a seed layer 409, and a plurality of protective layers 501.

[0101] Please refer to Figure 1 The first grain 100 may include a first substrate 101, a first dielectric layer 103, a first passivation layer 105, a plurality of first device elements 107, a first conductive feature 109, and a plurality of first virtual conductive features 111.

[0102] Please refer to Figure 1 For example, the first substrate 101 may be made of silicon, germanium, silicon-germanium, silicon-carbon, silicon-germanium-carbon, gallium, gallium arsenide, indium arsenide, indium phosphide, or other group IV-IV, III-V, or II-VI semiconductor materials. In some embodiments, the substrate 101 may include an organic semiconductor or a single-layer semiconductor, such as silicon / silicon-germanium, silicon-on-insulator, or silicon-germanium-on-insulator. When the substrate 101 is made of silicon-on-insulator, the substrate 101 may include an upper semiconductor layer, a lower semiconductor layer, and a buried isolation layer, wherein the upper and lower semiconductor layers are made of silicon, and the buried isolation layer separates the upper and lower semiconductor layers. For example, the buried isolation layer may comprise crystalline silicon or an amorphous silicon oxide, nitride, or a combination thereof.

[0103] Please refer to Figure 1A first dielectric layer 103 may be disposed on a first substrate 101. In some embodiments, the first dielectric layer 106 may be a stacked structure. The first dielectric layer 103 may include a plurality of first isolation sublayers. Each isolation sublayer may have a thickness between approximately 0.5 μm and approximately 3.0 μm. For example, the plurality of isolation sublayers may be made of the following materials: silicon oxide, borophosphosilicate glass, undopedsilicate glass, fluorinated silicate glass, low dielectric constant dielectric material, the like, or combinations thereof. The plurality of first isolation sublayers may be made of different materials, but are not limited thereto. The low dielectric constant dielectric material may have a dielectric constant less than 3.0, or even less than 2.5. In some embodiments, the low dielectric constant dielectric material may have a dielectric constant less than 2.0.

[0104] Please refer to Figure 1 The first passivation layer 105 may be disposed on the first dielectric layer 103. In some embodiments, the first passivation layer 105 may be a multilayer structure, comprising a layer of silicon oxide and a layer of silicon nitride.

[0105] Please refer to Figure 1 The first device element 107 may be disposed in a lower portion of the first dielectric layer 103. In some embodiments, the first device element 107 may be disposed on the first substrate 101 (for clarity, in...). Figure 1 Only three first device elements 107 are shown in the image. For example, the first device element 107 may be a bipolar junction transistor, a metal-oxide-semiconductor field-effect transistor, a diode, flash memory, dynamic random access memory, static random access memory, electrically erasable programmable read-only memory, an image sensor, a micro-electro-mechanical system, an active element, or a passive element.

[0106] Please refer to Figure 1 The first conductive feature 109 may be disposed in the first dielectric layer 103. In the described embodiment, the first conductive feature 109 may be a conductive line. It should be understood that, for example, conductive lines, conductive vias, conductive contact points, and other conductive features of the landing pad are also disposed in the first dielectric layer 103, but for clarity, they are only mentioned in the first dielectric layer 103. Figure 1Not shown in the image. For example, the first conductive feature 109 may be made of aluminum, copper, titanium, the like, or a combination thereof. The first conductive feature 109 may be electrically coupled to the first device element 107.

[0107] Please refer to Figure 1 The first virtual conductive feature 111 may be disposed in the first passivation layer 105. The upper surface of the first virtual conductive feature 111 may be substantially coplanar with the upper surface of the first passivation layer 105. For example, the first virtual conductive feature 111 may be made of aluminum, copper, titanium, the like, or a combination thereof.

[0108] It should be understood that a component considered as a "dummy" component means that when a semiconductor component is operating, no external voltage or current is applied to that component.

[0109] Please refer to Figure 1 The second die 200 may be disposed on the first die 100. In some embodiments, the first die 100 and the second die 200 may provide different functions. For example, the first die 100 may provide a logic function, and the second die 200 may provide a memory function. In some embodiments, the first die 100 and the second die 200 may provide the same function.

[0110] Please refer to Figure 1 In some embodiments, the second die 200 may have a structure similar to that of the first die 100, but placed in an upside-down manner. In particular, the second die 200 may include a second substrate 201, a second dielectric layer 203, a second passivation layer 205, a plurality of second device elements 207, a plurality of second conductive features (not shown), and a plurality of second dummy conductive features 211.

[0111] Please refer to Figure 1 A second passivation layer 205 may be disposed on the first passivation layer 105. A second dielectric layer 203 may be disposed on the second passivation layer 205. A second substrate 201 may be disposed on the second dielectric layer 203. A second device element 207 may be disposed in the second dielectric layer 203 and adjacent to the second substrate 201. The second conductive feature (for clarity, Figure 1 (Not shown) It may be disposed in the second dielectric layer 203. The second virtual conductive feature 211 may be disposed in the second passivation layer 205 and may contact the first virtual conductive feature 111. The second virtual conductive feature 211 and the first virtual conductive feature 111 may facilitate a bonding process between the first die 100 and the second die 200 and may improve the bonding strength between the second die 200 and the first die 100.

[0112] Please refer to Figure 1A first masking layer 301 may be disposed on the second substrate 201. In some embodiments, for example, the first masking layer 301 may be made of silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or the like. In some embodiments, the first masking layer 301 may be made of a material having a higher etch rate than the second substrate 201 of the second grain 200. For example, the etch rate of the first masking layer 301 to the second substrate 201 may be between approximately 100:1 and approximately 1.05:1. As another example, the etch rate of the first masking layer 301 to the second substrate 201 may be between approximately 20:1 and approximately 10:1.

[0113] It should be understood that, in this disclosure, silicon oxynitride refers to a substance comprising silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide refers to a substance comprising silicon, oxygen, and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0114] Please refer to Figure 1 The conductive filler layer 401 may be disposed along the first masking layer 301, the second substrate 201, the second dielectric layer 203, the second passivation layer 205, and the first passivation layer 105, extending to the first dielectric layer 103 and contacting the first conductive feature 109. The conductive filler layer 401 and the first conductive feature 109 are electrically coupled. The upper surface of the conductive filler layer 401 may be substantially coplanar with the upper surface 301TS of the first masking layer 301.

[0115] In some embodiments, the conductive filler layer 401 may have a width W1, which is between approximately 1 μm and approximately 22 μm. In particular, the width W1 of the conductive filler layer 401 may be between approximately 5 μm and approximately 15 μm. In some embodiments, the conductive filler layer 401 may have a depth D1, which is between approximately 20 μm and approximately 160 μm. In particular, the depth D1 of the conductive filler layer 401 may be between approximately 50 μm and approximately 130 μm. In some embodiments, the conductive filler layer 401 may have a depth-to-width ratio, which is between approximately 1:2 and approximately 1:35. In particular, the depth-to-width ratio of the conductive filler layer 401 may be between approximately 1:10 and approximately 1:25. For example, the conductive filler layer 401 may be made of polycrystalline silicon, tungsten, copper, carbon nanotubes, or solder alloys.

[0116] Please refer to Figure 1A seed layer 409 may be disposed on each sidewall and lower surface of the conductive fill layer 401. Each upper surface of the seed layer 409 may be substantially coplanar with the upper surface of the conductive fill layer 401. The seed layer 409 may have a thickness between approximately 10 nm and approximately 40 nm. For example, the seed layer 409 may be made of copper. During the formation of the conductive fill layer 401, the seed layer 409 may reduce the resistivity of an opening.

[0117] Please refer to Figure 1 An adhesive layer 407 may be disposed on each sidewall and lower surface of the seed layer 409. Each upper surface of the adhesive layer 407 may be substantially coplanar with the upper surface of the conductive filling layer 401. For example, the adhesive layer 407 may be made of titanium, tantalum, titanium-tungsten, or manganese nitride. The adhesive layer 407 can improve the adhesion between the seed layer 409 and the barrier layer 405.

[0118] Please refer to Figure 1 The barrier layer 405 can be disposed on each sidewall and lower surface of the adhesive layer 407. Each upper surface of the barrier layer 405 can be substantially coplanar with the upper surface of the conductive filling layer 401. For example, the barrier layer 405 can be made of the following materials: tantalum, tantalum nitride, titanium, titanium nitride, rhenium, nickel boride, or tantalum nitride / tantalum bilayer. The barrier layer 405 can inhibit the diffusion of conductive material from the conductive filling layer 401 into the second dielectric layer 203, the second substrate 201, the second passivation layer 205, the first passivation layer 105, or the first dielectric layer 103.

[0119] Please refer to Figure 1 The insulating layer 403 may be formed on the sidewall of the barrier layer 405. For ease of description, only one insulating layer 403 will be described. The portion of the insulating layer 403 disposed below the lower surface 301BS of the first shielding layer 301 is represented as a side segment 403S of the insulating layer 403.

[0120] Please refer to Figure 1Side segment 403S may be disposed between the conductive filling layer 401 and the second grain 200, and between the conductive filling layer 401 and the first passivation layer 105. In some embodiments, side segment 403S may be disposed between the conductive filling layer 401 and the first dielectric layer 103. The lower end of side segment 403S may contact the first conductive feature 109. In some embodiments, the highest point 403TP of the insulating layer 403 may be located on a vertical plane that is flush with the lower surface 301BS of the first masking layer 301. In some embodiments, the highest point 403TP of the insulating layer 403 may be located on a vertical plane that is lower than the lower surface 301BS of the first masking layer 301 and above the lower surface 201BS of the second substrate 201.

[0121] In some embodiments, the insulating layer 403 may be made of a material having a higher etch rate than the first masking layer 301. For example, the etch rate of the insulating layer 406 to the first masking layer 301 may be between approximately 100:1 and approximately 1.05:1. As another example, the etch rate of the insulating layer 403 to the first masking layer 301 may be between approximately 20:1 and approximately 10:1. In some embodiments, for example, the insulating layer 403 may be made of silicon oxide, silicon nitride, silicon oxynitride, or tetraethyl orthosilicate. The insulating layer 403 may have a thickness between approximately 50 nm and approximately 200 nm. In some embodiments, for example, the insulating layer 403 may be made of parylene, epoxy, or poly(p-xylene). The insulating layer 403 may have a thickness between approximately 1 μm and approximately 5 μm. The insulating layer 403 ensures that the conductive filling layer 401 is electrically insulated from the second grain 200 and the first passivation layer 105.

[0122] The conductive filler layer 401 can reduce the interconnect length between the first die 100 and the second die 200. Therefore, reflection noise, crosstalk noise, simultaneous switching noise, electromagnetic interference, and latency of the semiconductor device 1A can be reduced. Furthermore, since the parasitic capacitance is proportional to the interconnect length, the reduction in parasitic capacitance also reduces the total power consumption in the semiconductor device 1A.

[0123] Please refer to Figure 1The protective layer 501 may be disposed between the barrier layer 405 and the first shielding layer 301, and between the barrier layer 405 and the side section 403S of the insulating layer 403. The protective layer 501 may cover the upper part of the side section 403S. The lowest point 501BP of the protective layer 501 may be located on a vertical plane, which is a vertical plane lower than the highest point 403TP of the insulating layer 403. The upper surface of the protective layer 501 may be approximately coplanar with the upper surface 301TS of the first shielding layer 301.

[0124] Please refer to Figure 1 The plurality of interfaces IF01 located between the first masking layer 301 and the protective layer 501 may be tapered. The angle α between the upper surface 301TS of the first masking layer 301 and the interfaces IF01 located between the first masking layer 301 and the protective layer 501 may be between approximately 120 degrees and approximately 135 degrees. The plurality of interfaces IF03 located between the protective layer 501 and the barrier layer 405 are substantially perpendicular.

[0125] For example, the protective layer 501 may be made of the following materials: aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, titanium nitride, tungsten nitride, silicon nitride, or silicon oxide.

[0126] Without the protective layer 501 described herein, the insulating layer 403 may be damaged during its formation, and a metal-to-silicon leakage may subsequently occur during the formation of the conductive fill layer 401. This could therefore affect the performance / yield of the semiconductor device 1A. Conversely, in the described embodiment, the protective layer 501 forms a barrier to prevent metal diffusion from the conductive fill layer 401 into the second die 200 or the first die 100 during its formation. This improves the performance / reliability of the semiconductor device 1A.

[0127] Figures 2 to 6 The diagram shows cross-sectional views of various semiconductor elements 1B, 1C, 1D, 1E, and 1F according to some embodiments of the present disclosure.

[0128] Please refer to Figure 2In semiconductor device 1B, insulating layer 403 further includes an upper segment 403T, which is the portion of insulating layer 403 disposed above the lower surface 301BS of first masking layer 301. Upper segment 403T may be disposed between protective layer 501 and first masking layer 301. Multiple interfaces IF07 between upper segment 403T and first masking layer 301 may be tapered. Multiple interfaces IF09 between upper segment 403T and protective layer 501 may be tapered. In some embodiments, the interface IF03 between protective layer 501 and barrier layer 405 may be substantially vertical. In some embodiments, the interface IF03 between protective layer 501 and barrier layer 405 may be tapered.

[0129] Please refer to Figure 3 In semiconductor device 1C, the interface IF01 between the first masking layer 301 and the protective layer 501 can be substantially vertical. The interface IF03 between the protective layer 501 and the barrier layer 405 can also be substantially vertical.

[0130] Please refer to Figure 4 In semiconductor device 1D, the interface IF07 between the upper segment 403T and the first masking layer 301 can be substantially perpendicular. The interface IF09 between the upper segment 403T and the protective layer 501 can be substantially perpendicular. The thickness T1 of the protective layer 501 can gradually decrease along the Z direction toward the second grain 200.

[0131] Please refer to Figure 5 In semiconductor device 1E, a first dielectric layer 103 may be disposed on a first passivation layer 105. A first substrate 101 may be disposed on the first dielectric layer 103. A first masking layer 301 may be disposed on the first substrate 101. A conductive filling layer 401 may be disposed to extend along the first masking layer 301 and the first substrate 101, to the first dielectric layer 103, and to contact a first conductive feature 109. The insulating layer 403 may be disposed between the first masking layer 301 and the protective layer 501, and between the first die 100 and the protective layer 501. The interface IF07 between the upper segment 403T and the first masking layer 301 may be tapered. The interface IF09 between the upper segment 403T and the protective layer 501 may be tapered. In some embodiments, the interface IF03 between the protective layer 501 and the barrier layer 405 may be substantially vertical.

[0132] Please refer to Figure 6In semiconductor device 1F, the highest point 403TP of the insulating layer 403 may be located on a vertical plane that is flush with the lower surface 301BS of the first masking layer 301. The protective layer 501 may cover the upper part of the side section 403S. The interface IF01 located between the first masking layer 301 and the protective layer 501 may be tapered. The interface IF03 located between the protective layer 501 and the barrier layer 405 may be substantially vertical.

[0133] It should be understood that the terms “forming,” “formed,” and “form” can refer to and include any method of creating, building, patterning, implanting, or depositing an element, a dopant, or a material. Examples of forming methods may include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, spin coating, diffusion, deposition, growing, implantation, photolithography, dry etching, and wet etching.

[0134] Figure 7 This is a schematic flowchart of a method 10 for fabricating a semiconductor element 1A according to an embodiment of the present disclosure. Figures 8 to 21 This is a cross-sectional schematic diagram of a process for fabricating the semiconductor device 1A according to an embodiment of the present disclosure.

[0135] Please refer to Figures 7 to 10 In step S11, a second grain 200 may be bonded to a first grain 100.

[0136] Please refer to Figure 8 and Figure 9A first die 100 and a second die 200 may be provided separately. The first die 100 may include a first substrate 101, a first dielectric layer 103, a first passivation layer 105, a plurality of first device elements 107, a first conductive feature 109, and a plurality of first dummy conductive features 111. The first dielectric layer 103 may be formed on the first substrate 101. The first device elements 107 and the first conductive features 109 may be formed in the first dielectric layer 103. The first passivation layer 105 may be formed on the first device elements 107. The first dummy conductive features 111 may be formed in the first passivation layer 105. The second die 200 may have a structure similar to that of the first die 100, but arranged in an inverted manner. The second die 200 may be bonded to the first die 100 via a bonding process. The bonding process may include a heat treatment to achieve a hybrid bonding between the elements of the second die 200 and the first die 100. Hybrid bonding can include dielectric-to-dielectric bonding and metal-to-metal bonding. Dielectric-to-dielectric bonding can originate from the bonding between a second passivation layer 205 of the second die 200 and a first passivation layer 105 of the first die 100. Metal-to-metal bonding can originate from the bonding between the first virtual conductive feature 111 of the first die 100 and the second virtual conductive feature 211 of the second die 200. A bonding process temperature can be between approximately 300°C and approximately 450°C.

[0137] Please refer to Figure 10 A thinning process can be performed on a second substrate 201 of the second die 200. The thinning process uses an etching process, a chemical polishing process or a polishing process to reduce the thickness of the second substrate 201.

[0138] Please refer to Figure 7 as well as Figure 11 In step S13, a first masking layer 301 may be formed on the second grain 200.

[0139] Please refer to Figure 11 For example, the first masking layer 301 may be made of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride or other suitable materials.

[0140] Please refer to Figure 7 and Figure 12 In step S15, a first opening 601 is formed along the first masking layer 301 and the second grain 200, and extends to the first grain 100.

[0141] Please refer to Figure 12The first opening 601 can be formed by performing a lithography process and multiple etching processes to sequentially remove the first mask layer 301, the second die 200, the first passivation layer 105, and the first dielectric layer 103. The first conductive feature 109 can be exposed through the first opening 601.

[0142] Please refer to Figure 7 and Figure 13 In step S17, an etching process may be performed to expand the first opening 601 in the first mask layer 301.

[0143] Please refer to Figure 13 The etching ratio of the first masking layer 301 to the second substrate 201 of the second grain can be between approximately 100:1 and 1.05:1. In some embodiments, the etching process can be a wet etching process, which uses a wet etch solution. The wet etch solution can be a hydrofluoric acid solution, which is a buffer oxide etchant with a 6:1 ratio and contains 7% by mass (w / w) hydrofluoric acid, 34% by mass (w / w) ammonium fluoride, and 59% by mass (w / w) water. In some embodiments, the etching process can be a dry etching process, which uses a gas selected from the group consisting of difluoromethane (CH2F2), chloroform (CHF3), and octafluorocyclobutane (C4F8). After the etching process, the width of the first opening 301 in the first masking layer 301 can be widened, while the width of the first opening 601 in the second die 200 or the first die 100 can remain unchanged. Therefore, after the etching process, the sidewall of the first opening 601 in the first masking layer 301 can be tapered. The widened first opening 601 in the first masking layer 301 can promote the formation of the protective layer 501, which will be described later.

[0144] Please refer to Figure 7 , Figure 14 as well as Figure 15 In step S19, multiple insulating layers 403 may be formed in the first opening 601.

[0145] Please refer to Figure 14An insulating layer 403 may be deposited in the first opening 601 and on the upper surface 301TS of the first masking layer 301. The portion of the insulating layer 403 formed on the first conductive feature 109 may be represented as a lower segment 403B. The portions of the insulating layer 403 formed below the lower surface 301BS of the first masking layer 301 and on each sidewall of the first opening 601 may be represented as side segments 403S. The portions of the insulating layer 403 formed above the lower surface 301BS of the first masking layer 301 and below the upper surface 301TS of the first masking layer 301 may be represented as an upper segment 403T. The portion of the insulating layer 403 formed on the upper surface 301TS of the first masking layer 301 may be represented as a covering segment 403C.

[0146] Please refer to Figure 15 A punch etch process can be performed to remove the lower segment 403B, the cover segment 403C, and the upper segment 403T. After the punch etch process, the insulating layer 403 can be divided into multiple portions. The highest point 403TP of the insulating layer 403 can be located on a vertical plane flush with the lower surface 301BS of the first mask layer 301. The etch rate of the insulating layer 403 in the punch etch process can be faster than the etch rate of the first mask layer 301 in the punch etch process to avoid damage to the silicon / hard mask layer interface.

[0147] In some embodiments, the impact etching process may excessively recess the insulating layer 403. The highest point 403TP of the insulating layer 403 may be located on a vertical plane below the lower surface 301BS of the first masking layer 301. In this case, a metal-to-silicon leakage may occur during the formation of a subsequent conductive fill layer 401.

[0148] Please refer to Figure 7 and Figure 16 In step S21, multiple protective layers 501 may be formed to cover the upper part of the insulating layer 403.

[0149] Please refer to Figure 16 The protective layer 501 can be formed by a deposition process, such as atomic layer deposition (ALD), which precisely controls the amount of a first precursor. For example, the protective layer 501 can be made of the following materials: alumina, hafnium oxide, zirconium oxide, titanium oxide, titanium nitride, tungsten nitride, silicon nitride, or silicon oxide.

[0150] In some embodiments, when the protective layer 501 is made of alumina, the first precursor of the atomic layer deposition method may be trimethylaluminum, and the second precursor of the atomic layer deposition method may be water or ozone.

[0151] In some embodiments, when the protective layer 501 is made of hafnium oxide, the first precursor of the atomic layer deposition method may be hafnium tetrachloride, hafnium tert-butoxide, hafnium dimethylamide, hafnium ethylmethylamide, hafnium diethylamide, or hafnium methoxy-t-butoxide, while the second precursor of the atomic layer deposition method may be water or ozone.

[0152] In some embodiments, when the protective layer 501 is made of zirconium oxide, the first precursor of the atomic layer deposition method may be zirconium tetrachloride, and the second precursor of the atomic layer deposition method may be water or ozone.

[0153] In some embodiments, when the protective layer 501 is made of titanium oxide, the first precursor of the atomic layer deposition method may be titanium tetrachloride, tetraethyl titanate, or titanium isopropoxide, and the second precursor of the atomic layer deposition method may be water or ozone.

[0154] In some embodiments, when the protective layer 501 is made of titanium nitride, the first precursor of the atomic layer deposition method may be titanium tetrachloride or ammonia.

[0155] In some embodiments, when the protective layer 501 is made of tungsten nitride, the first precursor of the atomic layer deposition method may be tungsten hexafluoride or ammonia.

[0156] In some embodiments, when the protective layer 501 is made of silicon nitride, the first precursor of the atomic layer deposition method may be silylene, chlorine, ammonia and / or dinitrogen tetrahydride.

[0157] In some embodiments, when the protective layer 501 is made of silicon oxide, the first precursor of the atomic layer deposition method may be silicon tetraisocyanate or CH3OSi(NCO)3, and the second precursor of the atomic layer deposition method may be hydrogen or ozone.

[0158] Because of the tapered sidewalls of the first opening 601 in the first masking layer 301, the sidewalls 501S of the protective layer 501 can be substantially vertical. During subsequent semiconductor manufacturing processes, the protective layer 501 provides additional protection to both the first masking layer 301 and the second die 200. Therefore, metal leakage to silicon during the formation of the conductive filler layer 401 can be avoided. Consequently, the performance / yield of the semiconductor device 1A can be improved.

[0159] Please refer to Figure 7 and Figures 17 to 21 In step S23, a barrier layer 405, an adhesive layer 407, a seed layer 409, and a conductive filling layer 401 may be formed in the first opening 601.

[0160] Please refer to Figure 17 The barrier layer 405 may be conformally formed on the protective layer 501 and in the first opening 601. The barrier layer 405 may cover the upper surface of the protective layer 501, the insulating layer 403, and the first conductive feature 109.

[0161] Please refer to Figures 18 to 19 An adhesive layer 407 may be conformally formed on a barrier layer 405. A seed layer 409 may be conformally formed on an adhesive layer 407.

[0162] Please refer to Figure 20 A first conductive material 603 can be deposited on, for example... Figure 19 The first conductive material 603 is deposited on the intermediate semiconductor element, completely filling the first opening 601. This first conductive material 603 can be deposited using atomic layer deposition, chemical vapor deposition, or other conformal deposition methods. Due to the presence of the protective layer 501, the deposition rate of the first conductive material 603 on each sidewall of the first opening 601 can be reduced. Therefore, the deposition rates of the first conductive material 603 on each sidewall of the first opening 601 and on the lower surface of the first opening 601 can become close to each other. Thus, the first opening 601 can be filled without forming any voids adjacent to the lower surface of the first opening 601. This improves the yield of the semiconductor element 1A.

[0163] Please refer to Figure 21A planarization process, such as chemical mechanical polishing, can be performed until the upper surface 301TS of the first masking layer 301 is exposed to remove excess material, provide a generally flat surface for subsequent processing steps, and simultaneously form a conductive filler layer 401 in the first opening 601.

[0164] Figures 22 to 24 This is a cross-sectional schematic diagram of a process for fabricating a semiconductor device 1B according to an embodiment of the present disclosure.

[0165] Please refer to Figure 22 It can manufacture such as Figure 14 The aforementioned intermediate semiconductor device. The protective layer 501 may be formed on the insulating layer 403 without prior performing a beating etching process on the insulating layer 403. That is, the protective layer 501 may be formed to cover the upper portion of the cover section 403C, the upper section 403T, and the side section 403S.

[0166] Please refer to Figure 23 After the protective layer 501 is formed, a hammer etching process can be performed as follows: Figure 22 On the aforementioned intermediate semiconductor element, the lower segment 403B is removable. Due to the presence of the protective layer 501, excessive recessing of the insulating layer 403 during the blister etching process and metal-to-silicon leakage during the formation of the conductive fill layer 401 are avoided. Please refer to... Figure 24 Other components can be similar to, for example Figures 17 to 21 The process described above is what we have created.

[0167] Figures 25 to 28 This is a cross-sectional schematic diagram of a process for fabricating a semiconductor device 1C according to an embodiment of the present disclosure.

[0168] Please refer to Figure 25 It can manufacture such as Figure 12 An intermediate semiconductor element. An insulating layer 403 may be formed in the first opening 601 without having to previously extend the first opening 601 in the first masking layer 301. The entire sidewall of the first opening 601 may be substantially vertical.

[0169] Please refer to Figure 26 A single, powerful etching process can be similar to... Figure 15 The program shown is being executed. Please refer to it. Figure 27 The protective layer 501 can be similar to, for example: Figure 16 The process described above forms a layer that covers the upper portion of the insulating layer 403. Please refer to [link / reference]. Figure 28 Other components can be similar to, for example Figures 17 to 21 The process described above is what we have created.

[0170] Figures 29 to 31This is a cross-sectional schematic diagram of a process for fabricating a semiconductor device 1F according to an embodiment of the present disclosure.

[0171] Please refer to Figure 29 A first die 100 may be provided. The first die 100 may include a first substrate 101, a first dielectric layer 103, a first passivation layer 105, a plurality of first device elements 107, and a first conductive feature 109. The first dielectric layer 103 is formed on the first substrate 101, the first passivation layer 105 is formed on the first dielectric layer 103, the first device elements 107 are formed in the first dielectric layer 103, and the first conductive feature 109 is formed in the first dielectric layer 103.

[0172] Please refer to Figure 30 The first die 100 can be placed in an upside-down position. The thickness of the first substrate 101 can be thinned by an etching process, a chemical polishing process, or a polishing process. A first masking layer 301 and a first opening 601 can be similar to... Figure 11 and Figure 12 This is formed by the aforementioned procedure. Please refer to [the document / reference]. Figure 31 Other components can be similar to, for example Figures 13 to 21 The process described above is what we have created.

[0173] One embodiment of this disclosure provides a semiconductor device including a first die; a first conductive feature located in the first die; a second die located on the first die; a first masking layer located on the second die; a conductive filling layer located along the first masking layer and the second die, extending to the first die and contacting the first conductive feature; a plurality of insulating layers located between the conductive filling layer and the first die, and between the conductive filling layer and the second die; and a plurality of protective layers located between the conductive filling layer and the first masking layer, and covering the upper portion of the insulating layers.

[0174] Another embodiment of this disclosure provides a semiconductor device including a first die; a first conductive feature located in the first die; a first masking layer located on the first die; a conductive filling layer located along the first masking layer, extending to the first die and contacting the first conductive feature; a plurality of insulating layers located between the conductive filling layer and the first die, and between the conductive filling layer and the first masking layer; and a plurality of protective layers located between the conductive filling layer and the insulating layers; wherein the lowest point of the protective layer is located on a vertical plane, the vertical plane being a vertical plane lower than a lower surface of the first masking layer.

[0175] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, including performing a bonding process to bond a second die to a first die; forming a first masking layer on the second die; forming a first opening to pass through the first masking layer and the second die and extend to the first die; forming a plurality of insulating layers on a plurality of sidewalls of the first opening; forming a plurality of protective layers to cover the upper portion of the insulating layers; and forming a conductive filling layer in the first opening.

[0176] Due to the design of the semiconductor device disclosed herein, the protective layer 501 provides additional protection to reduce metal leakage to silicon. Furthermore, due to the geometry of the protective layer 501, the formation of the conductive filling layer 401 requires no voids. In summary, this improves the manufacturing yield of the semiconductor device 1A.

[0177] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0178] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: The first grain; A first conductive feature is located in the first grain; A second grain is located on the first grain; A first masking layer is located on the second grain; A conductive filler layer is located along the first masking layer and the second grain, extending to the first grain and contacting the first conductive feature; Multiple insulating layers are located between the conductive filling layer and the first grain, and between the conductive filling layer and the second grain; and Multiple protective layers are located between the conductive filler layer and the first masking layer, and cover the upper part of the insulating layer. The multiple interfaces between the first masking layer and the protective layer are tapered. The highest point of the insulating layer is located on a vertical plane, which is flush with the lower surface of the first masking layer. The multiple interfaces between the protective layer and the conductive filler layer are approximately vertical. The shape of the conductive filler layer narrows at the multiple protective layers.

2. The semiconductor device as claimed in claim 1, wherein, The angle between an upper surface of the first masking layer and the interface between the first masking layer and the protective layer is between 120 degrees and 135 degrees.

3. The semiconductor device as claimed in claim 1, wherein, The conductive filling layer is made of polycrystalline silicon, tungsten, copper, carbon nanotubes or solder alloy, and the insulating layer is made of silicon oxide, silicon nitride, silicon oxynitride, tetraethylsilicate, parylene, epoxy resin or parylene.

4. The semiconductor device of claim 3 further includes a barrier layer located between the insulating layer and the conductive filling layer, wherein the barrier layer is made of tantalum, tantalum nitride, titanium, titanium nitride, rhenium, nickel boride, or a tantalum nitride / tantalum bilayer.

5. The semiconductor device of claim 4 further comprises an adhesive layer located between the barrier layer and the conductive filling layer, wherein the adhesive layer is made of titanium, tantalum, titanium tungsten, or manganese nitride.

6. The semiconductor device of claim 5 further comprises a seed layer located between the adhesive layer and the conductive filling layer, wherein the seed layer has a thickness between 10 nm and 40 nm.

7. The semiconductor device as claimed in claim 3, wherein, The width of the conductive filling layer is between 1 μm and 22 μm.

8. The semiconductor device as claimed in claim 3, wherein, The depth of the conductive filler layer is between 20 μm and 160 μm.

9. The semiconductor device as claimed in claim 3, wherein, The aspect ratio of the conductive filler layer is between 1:2 and 1:

35.

10. A semiconductor element, comprising: The first grain; A first conductive feature is located in the first grain; A first masking layer is located on the first grain; A conductive filler layer is located along the first masking layer, extends to the first grain, and contacts the first conductive feature; Multiple insulating layers are located between the conductive filling layer and the first grain, and between the conductive filling layer and the first masking layer; and Multiple protective layers are located between the conductive filler layer and the insulating layer; The lowest point of the protective layer is located on a vertical plane, which is a vertical plane lower than the lower surface of the first masking layer. The plurality of interfaces between the first masking layer and the insulating layer are tapered. The highest point of the insulating layer is located on a vertical plane, which is flush with the lower surface of the first masking layer. The plurality of interfaces between the protective layer and the conductive filling layer are substantially vertical. The shape of the conductive filling layer narrows at the plurality of protective layers.

11. A method for fabricating a semiconductor device, comprising: Perform a bonding process to bond a second die onto a first die; A first masking layer is formed on the second grain; A first opening is formed to pass through the first masking layer and the second grain, and extends to the first grain; Multiple insulating layers are formed on multiple sidewalls of the first opening; Multiple protective layers are formed to cover the upper part of the insulating layer; as well as A conductive filling layer is formed in the first opening, wherein the method for fabricating the semiconductor element further includes: performing an etching process to extend the first opening in the first masking layer into a tapered shape before forming the insulating layer on the sidewall of the first opening, wherein the highest point of the insulating layer is located on a vertical plane, which is flush with a lower surface of the first masking layer, wherein a plurality of interfaces located between the protective layer and the conductive filling layer are substantially vertical, and the shape of the conductive filling layer narrows at the plurality of protective layers.

12. The method for fabricating a semiconductor device as described in claim 11, wherein, The etching process has an etching rate between 100:1 and 1.05:1 for the first masking layer on a substrate of the second grain.

13. The method for fabricating a semiconductor device as described in claim 12, wherein, The protective layer is made of aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, titanium nitride, tungsten nitride, silicon nitride, or silicon oxide.

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