Semiconductor device and method of manufacturing the same

Abstract

Semiconductor devices having different gate structure configurations and methods of manufacturing the same are disclosed. The method includes forming first and second nanostructure channel regions on first and second fin structures; forming a first oxide layer having a first thickness and a second oxide layer having a second thickness; forming a dielectric layer having a first layer portion and a second layer portion on the first and second oxide layers; forming a first cap layer having a first oxygen diffusivity and a second cap layer having a second oxygen diffusivity on the first and second layer portions; growing the first oxide layer to have a third thickness and the second oxide layer to have a fourth thickness; and forming a gate metal fill layer over the dielectric layer. The first and second thicknesses are substantially equal to each other, and the first and second oxide layers surround the first and second nanostructure channel regions. The second oxygen diffusivity is higher than the first oxygen diffusivity. The fourth thickness is greater than the third thickness.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to semiconductor devices and methods of manufacturing the same. BACKGROUND

[0002] As advances in semiconductor technology continue, there is an ever-increasing demand for higher memory capacity, faster processing systems, higher performance, and lower cost. To meet these demands, the semiconductor industry continues to scale down the size of semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), including planar MOSFETs, fin field-effect transistors (finFETs), and gate-all-around FETs (GAA FETs). This scaling has increased the complexity of semiconductor fabrication processes. SUMMARY

[0003] Some embodiments of the present application provide a method of forming a semiconductor device, comprising: forming a first nanowire channel region and a second nanowire channel region on a first fin structure and a second fin structure, respectively; forming a first oxide layer having a first thickness and a second oxide layer having a second thickness, respectively, wherein the first thickness and the second thickness are substantially equal to each other, and wherein the first oxide layer and the second oxide layer surround the first nanowire channel region and the second nanowire channel region, respectively; forming a high-k dielectric layer having a first layer portion and a second layer portion on the first oxide layer and the second oxide layer, respectively; forming a first cap layer having a first oxygen diffusivity and a second cap layer having a second oxygen diffusivity on the first layer portion and the second layer portion, respectively, wherein the second oxygen diffusivity is higher than the first oxygen diffusivity; growing the first oxide layer to have a third thickness and growing the second oxide layer to have a fourth thickness, wherein the fourth thickness is greater than the third thickness; and forming a gate metal fill layer over the high-k dielectric layer.

[0004] Some embodiments of the present application provide a method of forming a semiconductor device, comprising: forming a first nanoscale channel region and a second nanoscale channel region on a first fin structure and a second fin structure, respectively; forming a first gate oxide structure and a second gate oxide structure on the first nanoscale channel region and the second nanoscale channel region, respectively, wherein forming the first gate oxide structure and the second gate oxide structure comprises: forming a first oxide layer and a second oxide layer of a same material having substantially equal thicknesses to each other, forming a first high-k dielectric layer and a second high-k dielectric layer of the same material, forming a first cap layer and a second cap layer having different oxygen diffusivities from each other, growing the first oxide layer and the second oxide layer to have different thicknesses from each other, and removing the first cap layer and the second cap layer; and forming a gate metal fill layer over the first gate oxide structure and the second gate oxide structure.

[0005] Some embodiments of the present application provide a semiconductor device, comprising: a substrate; a first fin structure and a second fin structure disposed on the substrate; a first nanoscale channel region and a second nanoscale channel region disposed on the first fin structure and the second fin structure, respectively, wherein a size of the second nanoscale channel region is smaller than a size of the first nanoscale channel region; a first gate oxide structure and a second gate oxide structure surrounding the first nanoscale channel region and the second nanoscale channel region, respectively, wherein the first gate oxide structure and the second gate oxide structure comprise: a first oxide layer and a second oxide layer of a same material having different thicknesses from each other, a first high-k dielectric layer and a second high-k dielectric layer disposed on the first oxide layer and the second oxide layer, respectively, and a third oxide layer and a fourth oxide layer of different materials having substantially equal thicknesses to each other, wherein the third oxide layer and the fourth oxide layer are disposed on the first high-k dielectric layer and the second high-k dielectric layer, respectively; and a first gate metal fill layer and a second gate metal fill layer disposed over the first gate oxide structure and the second gate oxide structure, respectively. BRIEF DESCRIPTION OF DRAWINGS

[0006] Various aspects of the application can be best understood from the following detailed description when read with the accompanying drawings.

[0007] FIG. 1A An isometric view of a semiconductor device is shown in accordance with some embodiments.

[0008] FIGS. 1B-1H A cross-sectional view of a semiconductor device having different gate oxide structures is shown in accordance with some embodiments.

[0009] FIG. 2 is a flowchart of a method for fabricating a semiconductor device having different gate oxide structures according to some embodiments.

[0010] FIGS. 3A-5B 、 FIGS. 6A-9E 、 FIGS. 10A-12B and FIGS. 13A-14E shows cross-sectional views of a semiconductor device having different gate oxide structures at various stages of its fabrication process according to some embodiments.

[0011] FIG. 15 shows a block diagram of a control system of an atomic layer etching (ALE) system according to some embodiments.

[0012] Illustrative embodiments will now be described with reference to the drawings. In the drawings, like reference numerals generally refer to like, functionally similar, and / or structurally similar elements. The drawings are not necessarily to scale. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Each of the following embodiments can be implemented alone or in combination with one another. Numerous specific details are described to provide a thorough understanding of the embodiments. However, in certain instances, detailed descriptions have been omitted in order to avoid obscuring the embodiments. For example, in the following description, a process for forming a first component over a second component can include embodiments in which the first component and the second component are formed in direct contact, and can also include embodiments in which additional components can be formed between the first component and the second component, such that the first component and the second component can not be in direct contact. As used herein, forming a first component over a second component means forming the first component in direct contact with the second component. In addition, the present disclosure can refer to a component as a“means for” performing a particular function. Such a“means for” component can be constructed as a single component or multiple components, and can be implemented using one or more circuits such as, for example, a general- purpose processor and associated circuitry, a circuit specifically designed to perform the function, a combination of one or more such circuits, or the like.

[0014] For purposes of the description hereinafter, spatial or directional terms, such as, for example, "below," "lower," "bottom," "above," "upper," "top," and the like, can be used with respect to the illustrated orientation of the figures. The spatial or directional terms are used with respect to the orientation of the figures as shown. The spatial or directional terms are used for purposes of illustration and not of limitation. The device can be oriented in other ways (rotated 90 degrees or otherwise) and the spatial or directional terms used herein can be interpreted accordingly.

[0015] It should be noted that references to "one embodiment," "an embodiment," "example embodiments," "exemplary embodiment," "one example," etc., mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily referring to the same embodiment.

[0016] It should be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the specification should be interpreted by those skilled in relevant art in light of the teachings and

[0017] In some embodiments, the terms "about" and "substantially" can indicate a value that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values are merely examples and are not intended to be limiting. The terms "about" and "substantially" can indicate a percentage of a value as interpreted by one of skill in the relevant art in light of the teachings herein.

[0018] The fin structures disclosed herein can be patterned by any suitable method. For example, the fin structures can be patterned using one or more photolithography processes including a double patterning process or a multiple patterning process. Double or multiple patterning processes combine photolithography and self-alignment processes, allowing for the creation of patterns, for example, with a pitch that is less than is obtainable using a single, direct photolithography process. For example, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin structures.

[0019] The present disclosure provides exemplary semiconductor devices having FETs (e.g., finFETs, GAA FETs, or MOSFETs) with different gate structure configurations that provide different power consumption levels. The present disclosure also provides exemplary methods of forming such FETs on the same substrate. The exemplary methods form FET gate structures with different gate oxide structures for forming FETs with different power consumption levels on the same substrate. Compared to other methods of forming FETs with similar power consumption levels on the same substrate, these exemplary methods can be more cost effective (e.g., cost reduction of about 20% to about 30%) and time efficient (e.g., time reduction of about 15% to about 20%) in manufacturing reliable FET gate structures with low and / or ultra-low power consumption levels (e.g., in the range of microwatts, nanowatts, or picowatts). Moreover, compared to other methods of forming FETs with similar power consumption levels, these exemplary methods can form FET gate structures with smaller sizes (e.g., smaller gate lengths) without increasing gate resistance.

[0020] In some embodiments, each of the FET gate oxide structures includes a high-k (HK) gate dielectric layer interposed between a first interface oxide (IO) layer and a second IO layer. The first IO layers can be formed to have different thicknesses from each other to achieve different power consumption levels in different FETs. In some embodiments, the first IO layers of different thicknesses can be formed in two oxidation processes. In a first oxidation process, the first IO layers can be formed to have substantially equal thicknesses from each other. In a second oxidation process, the first IO layers can be grown to have different thicknesses from each other.

[0021] In some embodiments, the second oxidation process can include forming a capping layer on the HK gate dielectric layer and performing an annealing process in an oxidation environment. The capping layers can be formed to have different oxygen diffusivities from each other. As used herein, the term "oxygen diffusivity" refers to the ability of a material and / or layer to allow oxygen atoms to pass through the material and / or layer by diffusion. The capping layers can control the growth of the first IO layers during the annealing process. In some embodiments, the capping layers with different oxygen diffusivities can be formed with materials (e.g., metal nitrides, metal oxides, other suitable materials, or combinations thereof) that are different from each other and have substantially equal thicknesses from each other, or can be formed from the same material with different thicknesses from each other.

[0022] FIG. 1AAn isometric view of a semiconductor device 100 having FETs 102A-102B according to some embodiments is shown. In some embodiments, FETs 102A-102B may represent n-type FETs 102A-102B (NFET 102A-102B) or p-type FETs 102A-102B (PFET 102A-102B). The discussion of FETs 102A-102B applies to both NFETs 102A-102B and PFETs 102A-102B, unless otherwise stated. FIGS. 1B-1C It shows along FIG. 1A Cross-sectional views of FET102A-102B with lines AA and BB. FIGS. 1D-1E It shows along FIG. 1A Cross-sectional views of FET102A-102B with lines CC and DD. FIGS. 1B-1E A cross-sectional view of a semiconductor device 100 with an additional structure is shown; for simplicity, this additional structure is not shown. FIG. 1A As shown in the diagram. The discussion of the components of FET 102A-102B with the same annotations applies to each other unless otherwise stated.

[0023] refer to FIG. 1A FETs 102A-102B may include an array of gate structures 112A-112B disposed on fin structures 106A-106B and an array of S / D regions 110A-110B disposed on portions of fin structures 106A-106B not covered by gate structures 112A-112B. FETs 102A-102B may also include a gate spacer 114, a shallow trench isolation (STI) region 116, an etch stop layer (ESL) 117, and an interlayer dielectric (ILD) layer 118. The ILD layer 118 may be disposed on the ESL 117. In some embodiments, the gate spacer 114, STI region 116, ESL 117, and ILD layer 118 may include insulating materials such as silicon oxide, silicon nitride (SiN), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), silicon germanium oxide, and other suitable insulating materials.

[0024] FETs 102A-102B can be formed on substrate 104. Other FETs and / or structures (e.g., isolation structures) can be formed on substrate 104. Substrate 104 can be a semiconductor material, such as silicon, germanium (Ge), silicon-germanium (SiGe), silicon-on-insulator (SOI) structures, other suitable semiconductor materials, and combinations thereof. Furthermore, substrate 104 can be doped with p-type dopant (e.g., boron, indium, aluminum, or gallium) or n-type dopant (e.g., phosphorus or arsenic). In some embodiments, fin structures 106A-106B can comprise a material similar to substrate 104 and extend along the X-axis.

[0025] Referring to FIGS. 1B-1E FETs 102A and 102B can include: (i) a stack of nanostructure channel regions 120A1-120A2 and 120B1-120B2 disposed on fin structures 106A and 106B, (ii) gate structures 112A and 112B disposed on and wrapping around nanostructure channel regions 120A1-120A2 and 120B1-120B2, and (iii) epitaxial S / D regions 110A and 110B. As used herein, the term "nanostructure" defines a structure, layer, and / or region as having a horizontal dimension (e.g., along the X and / or Y axes) and / or a vertical dimension (e.g., along the Z axis) of less than about 100 nm, e.g., about 90 nm, about 50 nm, about 10 nm, or other values less than about 100 nm are within the scope of the present disclosure. In some embodiments, FETs 102A-102B can be finFETs and can have fin regions (not shown) instead of nanostructure channel regions 120A1-120A2 and 120B1-120B2. Such finFETs 102A-102B can have gate structures 112A-112B disposed on the fin regions.

[0026] Nanowire channel regions 120A1-120A2 and nanowire channel regions 120B1-120B2 can include a semiconductor material similar to or different from substrate 104, and can include a semiconductor material similar to or different from each other. In some embodiments, nanowire channel regions 120A1-120A2 and nanowire channel regions 120B1-120B2 can include Si, silicon arsenide (SiAs), silicon phosphide (SiP), silicon carbide (SiC), silicon carbon phosphide (SiCP), SiGe, silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium tin boron (SiGeSnB), a III-V semiconductor compound, or other suitable semiconductor material. While two nanowire channel regions are shown in each stack, FETs 102A-102B can include any number of nanowire channel regions in each stack. While rectangular cross-sections of nanowire channel regions 120A1-120A2 and nanowire channel regions 120B1-120B2 are shown, nanowire channel regions 120A1-120A2 and nanowire channel regions 120B1-120B2 can have cross-sections of other geometric shapes (e.g., circular, elliptical, triangular, or polygonal). In some embodiments, due to different configurations of gate structures 112A and 112B, nanowire channel regions 120A1-120A2 can have a thickness T1-T2 and a width W1-W2 greater than a thickness T3-T4 and a width W3-W4 of nanowire channel regions 120B1-120B2, as will be described in detail below.

[0027] For NFETs 102A-102B, S / D regions 110A-110B can include epitaxially grown semiconductor material such as Si and n-type dopants such as phosphorous and other suitable n-type dopants. For PFETs 102A-102B, S / D regions 110A-110B can include epitaxially grown semiconductor material such as Si and SiGe and p-type dopants such as boron and other suitable p-type dopants.

[0028] The gate structures 112A-112B can be multi-layer structures and can surround the nanowire channel regions 120A1-120A2 and 120B1-120B2, for which the gate structures 112A-112B can be referred to as “gate-all-around (GAA) structures” or “horizontal gate-all-around (HGAA) structures.” The FETs 102A-102B can be referred to as “GAA FETs 102A-102B.” The gate portions of the gate structures 112A-112B that surround the nanowire channel regions 120A1-120A2 and 120B1-120B2 can be electrically isolated from the adjacent S / D regions 110A-110B by internal spacers 113. The gate portions of the gate structures 112A-112B that are disposed on the stacks of the nanowire channel regions 120A1-120A2 and 120B1-120B2 can be electrically isolated from the adjacent S / D regions 110A-110B by gate spacers 114. The internal spacers 113 and the gate spacers 114 can comprise insulating materials such as SiO2, SiN, SiCN, SiOCN, and other suitable insulating materials.

[0029] In some embodiments, the gate lengths of the gate structures 112A-112B are substantially equal to each other. The gate structures 112A-112B can include: (i) gate oxide structures 127A-127B, (ii) work function metal (WFM) layers 128 disposed on the gates, and (iii) gate metal fill layers 130 disposed on the WFM layers 128. In some embodiments, the gate structures 112A-112B can further include an adhesive layer (not shown) between the WFM layers 128 and the gate metal fill layers 130 for better adhesion of the gate metal fill layers 130 to the WFM layers 128. The adhesive layer can comprise titanium nitride (TiN), tantalum nitride (TaN), molybdenum nitride (MoN), tungsten nitride (WN), or other suitable metal nitride. Although FIGS. 1B-1E All layers of the gate structures 112A-112B are shown to wrap the nanowire channel regions 120A1-120A2 and 120B1-120B2, but the nanowire channel regions 120A1-120A2 and 120B1-120B2 can be wrapped at least by the gate oxide structures 127A-127B. Thus, the nanowire channel regions 120A1-120A2 and 120B1-120B2 can be electrically isolated from each other to prevent shorting between the gate structures 112A-112B and the S / D regions 110A-110B during operation of the FETs 102A-102B.

[0030] For NFETs 102A-102B, WFM layer 128 can include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), Al-doped Ti, Al-doped TiN, Al-doped Ta, Al-doped TaN, other suitable Al-based conductive materials, or combinations thereof. For PFETs 102A-102B, WFM layer 128 can include conductive materials that are substantially free of aluminum (e.g., no Al), such as titanium nitride (TiN), titanium carbonitride (TiCN), titanium silicon nitride (TiSiN), titanium-gold (Ti-Au) alloys, titanium-copper (Ti-Cu) alloys, tantalum nitride (TaN), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum-gold (Ta-Au) alloys, tantalum-copper (Ta-Cu), tungsten nitride (WN), tungsten carbonitride (WCN), other suitable conductive materials that are substantially free of aluminum, and combinations thereof.

[0031] In some embodiments, gate metal fill layer 130 can include conductive materials having a low resistivity (e.g., a resistivity of about 50 μΩ-cm, about 40 μΩ-cm, about 30 μΩ-cm, about 20 μΩ-cm, or about 10 μΩ-cm), such as cobalt (Co), tungsten (W), ruthenium (Ru), iridium (Ir), copper (Cu), molybdenum (Mo), other suitable conductive materials having a low resistivity, and combinations thereof.

[0032] Gate oxide structures 127A-127B can include a first interface oxide (IO) layer 122A-122B, a HK gate dielectric layer 124A-124B disposed on the respective first IO layer 122A-122B, and a second IO layer 126A-126B disposed on the respective HK gate dielectric layer 124A-124B. Because the power consumption level of a FET is inversely proportional to the thickness of the first IO layer, first IO layer 122B can be formed to have a thickness T10-T14 that is greater than the respective thickness T5-T9 of first IO layer 122A to form FET 102B with a lower power consumption level than the power consumption level of FET 102A. In some embodiments, the thickness of HK gate dielectric layers 124A-124B can be similar or different from each other, and the thickness of second IO layers 126A-126B can be similar or different from each other.

[0033] The first IO layer 122A can be formed by oxidizing surfaces of the nanostructured channel regions 120A1-120A2, as described in detail below. Due to different oxidation rates of the surfaces of the nanostructured channel regions 120A1-120A2 along the Z-axis during formation of the first IO layer 122A, the first IO layer 122A can be formed to have different thicknesses T5-T9 from each other. The different oxidation rates also result in different thicknesses of the portions of the surfaces of the nanostructured channel regions 120A1-120A2 that are consumed during formation of the IO layer 122A. As a result, the thicknesses T1-T2 of the nanostructured channel regions 120A1-120A2 can be different from each other, and the widths W1-W2 of the nanostructured channel regions 120A1-120A2 can be different from each other. In some embodiments, the oxidation rates can gradually decrease along the negative Z-axis direction, and thus, the thickness T1 can be less than the thickness T2, the width W1 can be less than the width W2, and the thickness T5 can be greater than the thickness T6, the thickness T6 can be greater than the thickness T7, the thickness T7 can be greater than the thickness T8, and the thickness T8 can be greater than the thickness T9.

[0034] Similarly, the first IO layer 122B can be formed by oxidizing surfaces of the nanostructured channel regions 120B1-120B2, and due to different oxidation rates of the surfaces of the nanostructured channel regions 120B1-120B2 along the Z-axis during formation of the first IO layer 122B, the thicknesses T3-T4, the widths W3-W4, and the thicknesses T10-T14 can be different from each other. In some embodiments, the oxidation rates can gradually decrease along the negative Z-axis direction, and thus, the thickness T3 can be less than the thickness T4, the width W3 can be less than the width W4, and the thickness T10 can be greater than the thickness T11, the thickness T11 can be greater than the thickness T12, the thickness T12 can be greater than the thickness T13, and the thickness T13 can be greater than the thickness T14. Due to the thickness difference between the first IO layers 122A and 122B, the thicknesses T1-T2 of the nanostructured channel regions 120A1-120A2 can be greater than the corresponding thicknesses T3-T4 of the nanostructured channel regions 120B1-120B2. Due to similar reasons, the widths W1-W2 of the nanostructured channel regions 120A1-120A2 can be greater than the corresponding widths W3-W4 of the nanostructured channel regions 120B1-120B2.

[0035] The first IO layer 122A can include an oxide of the semiconductor material in the nanostructure channel region 120A1-120A2, and the first IO layer 122B can include an oxide of the semiconductor material in the nanostructure channel region 120B1-120B2. In some embodiments, each of the first IO layers 122A-122B can include similar materials to each other, if the nanostructure channel region 120A1-120A2 and the nanostructure channel region 120B1-120B2 have the same semiconductor material, or can include different materials to each other, if the nanostructure channel region 120A1-120A2 and the nanostructure channel region 120B1-120B2 have different semiconductor materials to each other. Or in some embodiments, the first IO layers 122A-122B can include silicon oxide (SiO x ), silicon germanium oxide (SiGeO x ), or other suitable oxides of the semiconductor material.

[0036] In some embodiments, the HK gate dielectric layer 124A-124B can include: (i) a HK dielectric material, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), and zirconium silicate (ZrSiO2), and (ii) a HK dielectric material with an oxide of lithium (Li), beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), scandium (Sc), yttrium (Y), zirconium (Zr), aluminum (Al), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), (iii) a combination thereof, or (iv) other suitable HK dielectric materials. As used herein, the term “high-k (HK)” refers to a high dielectric constant. In the field of semiconductor device structures and manufacturing processes, HK refers to a dielectric constant that is greater than that of SiO2(e.g., greater than 3.9).

[0037] In some embodiments, each of the HK gate dielectric layers 124A-124B can include a single HK layer (e.g., a single layer of HfO2, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, or other suitable HK dielectric material). FIGS. 1B-1Eor a stack of two HK layers with different HK materials (not shown) and different dielectric constants. In the stack of two HK layers, the first HK layer can include Hf02with a dopant of lanthanum (La), magnesium (Mg), a rare earth metal, or other suitable dopant, and the second HK layer disposed on the first HK layer can include Zr02or other suitable metal oxide with a higher dielectric constant than the dielectric constant of the first HK layer. In some embodiments, the dopant in the first HK layer can form dipoles with oxygen atoms of the Zr02or other suitable metal oxide of the second HK layer. The dipoles can be used to adjust the threshold voltage of the FETs 102A-102B. Because the dopant concentration in the first HK layer is directly proportional to the dipole concentration, and the dipole concentration is directly proportional to the threshold voltage, the concentration of the dopant can be controlled to adjust the concentration of the dipoles, and thus the threshold voltage of the FETs 102A-102B can be adjusted. In some embodiments, the metal oxide of the second HK layer can be crystallized through an annealing process to reduce leakage through the gate structures 112A-112E.

[0038] The second IO layers 126A-126B can be formed due to oxidation of the capping layers 732A-732B (shown in FIG. 7A) used during formation of the first IO layers 122A-122B (shown in FIG. 6A) and also due to interface reactions between the capping layers 732A-732B and the HK gate dielectric layers 124A-124B, as described in detail below. In some embodiments, in addition to the capping layers 732A-732B, the second IO layers 126A-126B can control the growth of the first IO layers 122A-122B by controlling the diffusion rate of oxygen atoms through the second IO layers 126A-126B. To achieve a first IO layer 122B that is thicker than the first IO layer 122A, the second IO layer 126B can include a material with a higher oxygen diffusivity than the material included in the second IO layer 126A. Because the oxygen diffusivity of a material is directly proportional to the Gibbs energy of the material, the second IO layer 126B can be formed to include a material with a higher Gibbs energy than the Gibbs energy of the material included in the second IO layer 126A. FIGS. 1B-1E FIGS. 7A-8B and FIGS. 13A-14B The second IO layers 126A-126B can be formed due to oxidation of the capping layers 732A-732B (shown in FIG. 7A) used during formation of the first IO layers 122A-122B (shown in FIG. 6A) and also due to interface reactions between the capping layers 732A-732B and the HK gate dielectric layers 124A-124B, as described in detail below. In some embodiments, in addition to the capping layers 732A-732B, the second IO layers 126A-126B can control the growth of the first IO layers 122A-122B by controlling the diffusion rate of oxygen atoms through the second IO layers 126A-126B. To achieve a first IO layer 122B that is thicker than the first IO layer 122A, the second IO layer 126B can include a material with a higher oxygen diffusivity than the material included in the second IO layer 126A. Because the oxygen diffusivity of a material is directly proportional to the Gibbs energy of the material, the second IO layer 126B can be formed to include a material with a higher Gibbs energy than the Gibbs energy of the material included in the second IO layer 126A.

[0039] ​In some embodiments, when the second IO layer 126A-126B is formed on the HK gate dielectric layer 124A-124B with a single layer of Hf02, the second IO layer 126A-126B can include hafnium silicon titanium oxide nitride (TiSiHfON), hafnium titanium oxide nitride (TiHfON), hafnium tantalum oxide nitride (TaHfON), hafnium aluminum oxide nitride (AlHfON), hafnium tungsten oxide nitride (WHfON), or other suitable metal hafnium oxide nitride. In some embodiments, when the second IO layer 126A-126B is formed on the HK gate dielectric layer 124A-124B with a single layer of Zr02or a stack with Hf02and Zr02, the second IO layer 126A-126B can include titanium silicon zirconium oxide nitride (TiSiZrON), titanium zirconium oxide nitride (TiZrON), tantalum zirconium oxide nitride (TaZrON), aluminum zirconium oxide nitride (AlZrON), tungsten zirconium oxide nitride (WZrON), or other suitable metal zirconium oxide nitride. In some embodiments, when the growth of the first IO layer 122A-122B is controlled by different thicknesses of the capping layer 1332A-1332E, the second IO layer 126A-126B can include the same material, as described below with reference to FIGS. 1A-1C. FIGS. 13A-14B described.

[0040] Although the semiconductor device 100 is shown with two FETs 102A-102B, the semiconductor 100 can have two or more FETs with different configurations of gate oxide structures to have FETs with different power consumption levels. In some embodiments, in addition to the FETs 102A-102B, the semiconductor device 100 can include FETs 102C-102E (not shown in FIG. 1A for simplicity) disposed on the substrate 104. Similar to the FETs 102A-102B, the FETs 102C-102E can be formed on the substrate 104 with a gate oxide structure. FIG. 1A FIGS. 1B-1C , FIGS. 1F-1H Cross-sectional views of the FETs 102C-102E along the X-axis are shown. The discussion of elements of the FETs 102A-102E with the same annotations apply to each other unless otherwise noted.

[0041] ​FETs 102C, 102D, and 102E can include: (i) a stack of nanostructure channel regions 120C1-120C2, 120D1-120D2, and 120E1-120E2 disposed on fin structures 106C, 106D, and 106E, (ii) gate structures 112C, 112D, and 112E disposed on and wrapping around nanostructure channel regions 120C1-120C2, 120D1-120D2, and 120E1-120E2, and (iii) epitaxial S / D regions 110C, 110D, and 110E. The discussion of fin structures 106A-106B, nanostructure channel regions 120A1-120A2 and 120B1-120B2, S / D regions 110A-110B, and gate structures 112A-112B applies to fin structures 106C-106E, nanostructure channel regions 120C1-120C2, 120D1-120D2, and 120E1-120E2, S / D regions 110C-110E, and gate structures 112C-112E, unless otherwise noted.

[0042] The gate oxide structures 127C-127E can include a first IO layer 122C-122E, an HK gate dielectric layer 124C-124E disposed on the respective first IO layer 122C-122E, and a second IO layer 126C-126E disposed on the respective HK gate dielectric layer 124C-124E. The discussion of the HK gate dielectric layers 124A-124B applies to the HK gate dielectric layers 124C-124E unless otherwise noted. The first IO layer 122E can be formed to have a thickness T25-T29 that is about 0.1 nm to about 1 nm greater than the respective thickness T20-T24 of the first IO layer 122D. The thickness T20-T24 can be about 0.1 nm to about 1 nm greater than the respective thickness T15-T19 of the first IO layer 122C, which can be about 0.1 nm to about 1 nm greater than the respective thickness T10-T14 of the first IO layer 122B, which can be about 0.1 nm to about 1 nm greater than the respective thickness T5-T9 of the first IO layer 122A. Thus, the FET 102E has a lower power consumption level than the power consumption level of the FET 102D, which has a lower power consumption level than the power consumption level of the FET 102C, which has a lower power consumption level than the power consumption level of the FET 102B, which has a lower power consumption level than the power consumption level of the FET 102A, because the power consumption level of the FET is inversely proportional to the thickness of the first IO layer. If the relative thickness of the first IO layers 122A-122E is less than about 0.1 nm, then there can not be a sufficient difference between the power consumption levels among the FETs 102A-102E. On the other hand, if the relative thickness of the first IO layers 122A-122E is greater than about 1 nm, then the device size is increased and, thus, the device fabrication cost is increased. In some embodiments, the first IO layers 122A-122E can have a thickness in a range of about 1 nm to about 5 nm. Other suitable dimensions for the first IO layers 122A-122E are within the scope of the present disclosure.

[0043] The first IO layers 122C-122E can be formed using the cap layers 732C-732E FIGS. 1F-1H (not shown in FIG. 7B); FIGS. 7C-8E and FIGS. 13C-14Eoxide (as shown in FIG. 1A) and also due to interface reactions between the capping layers 732C-732E and the HK gate dielectric layers 124C-124E, as described in detail below. In some embodiments, to achieve the relative thickness of the first IO layers 122A-122E by controlling the diffusion of oxygen atoms through the second IO layers 126A-126C, the second IO layer 126A, the second IO layer 126B, the second IO layer 126C, the second IO layer 126D, and the second IO layer 126E can include TiSiHfON, TiHfON, TaHfON, AlHfON, and WHfON, respectively, when the second IO layers 126A-126E are formed on the HK gate dielectric layers 124A-124E with a single layer of Hf02. In some embodiments, the second IO layer 126A, the second IO layer 126B, the second IO layer 126C, the second IO layer 126D, and the second IO layer 126E can include TiSiZrON, TiZrON, TaZrON, AlZrON, and WZrON, respectively, when the second IO layers 126A-126E are formed on the HK gate dielectric layers 124A-124E with a single layer of Zr02or a stack with two layers of Hf02and Zr02. The oxygen diffusivity and Gibbs energy of WHfON and WZrON can be higher than the oxygen diffusivity and Gibbs energy of AlHfON and AlZrON, respectively. The oxygen diffusivity and Gibbs energy of AlHfON and AlZrON can be higher than the oxygen diffusivity and Gibbs energy of TaHfON and TaZrON, respectively. The oxygen diffusivity and Gibbs energy of TaHfON and TaZrON can be higher than the oxygen diffusivity and Gibbs energy of TiHfON and TiZrON, respectively. The oxygen diffusivity and Gibbs energy of TiHfON and TiZrON are higher than the oxygen diffusivity and Gibbs energy of TiSiHfON and TiSiZrON, respectively. In some embodiments, the second IO layers 126A-126E can include the same material when the growth of the first IO layers 122A-122E is controlled by different thicknesses of the capping layers 1332A-1332E, as described below with reference to FIG. 13B. FIGS. 13A-14B In some embodiments, the second IO layers 126A-126E can have a thickness in a range from about 0.1 nm to about 1 nm. Other suitable dimensions of the second IO layers 126A-126E are within the scope of the present disclosure.

[0044] FIG. 2 is a flowchart of an exemplary method 200 for fabricating FETs 102A-102E of the semiconductor device 100 in accordance with some embodiments. For purposes of illustration, reference will be made to fabricating FETs 102A-102E of the semiconductor device 100 as shown in FIG. 1A. The method 200 can be performed by a processing system, such as the processing system 1100 shown in FIG. 11A. FIGS. 3A-5B FIGS. 6A-9E FIGS. 10A-12B and FIGS. 13A-14E ​​The exemplary manufacturing process of FET102A-102E is described below. FIG. 2 The operation shown. FIGS. 3A-5B , FIGS. 6A-9E , FIGS. 10A-12B and FIGS. 13A-14E The cross-sectional views along the X-axis of FETs 102A-102E at various manufacturing stages according to the various embodiments can be performed in different sequences or without operation, depending on the specific application. It should be noted that method 200 may not produce complete FETs 102A-102E. Therefore, it should be understood that additional processes can be provided before, during, and after method 200, and only some of these other processes can be briefly described herein. The above describes... FIGS. 3A-5B , FIGS. 6A-9E , FIGS. 10A-12B and FIGS. 13A-14E The ones with FIGS. 1A-1H The components in the same annotation are the same as the components in the annotation.

[0045] In operation 205, a superlattice structure is formed on the fin structure of the FET, and a polycrystalline silicon structure is formed on the superlattice structure. For example, as... FIGS. 3A-3B As shown, polycrystalline silicon structures 312A-312B are formed on corresponding superlattice structures 119A-119B epitaxially formed on corresponding fin structures 106A-106B. Superlattice structure 119A may include nanostructure layers 120A1-120A2 and 122A1-122A2 arranged in an alternating configuration. Similarly, superlattice structure 119B may include nanostructure layers 120B1-120B2 and 122B1-122B2 arranged in an alternating configuration. In some embodiments, nanostructure layers 120A1-120A2 and 120B1-120B2 comprise materials similar to each other, and nanostructure layers 122A1-122A2 and 122B1-122B2 comprise materials similar to each other. During subsequent processing, the polysilicon structures 312A-213B, as well as the nanostructure layers 122A1-122A2 and 122B1-122B2, can be replaced in a gate replacement process to form the gate structure 112A-112B.

[0046] refer to FIG. 2 In operation 210, an S / D region is formed on the fin structure. For example, as referenced... FIGS. 4A-5B As described, S / D regions 110A-110B are formed on the corresponding fin structures 106A and 106B. Forming the S / D regions 110A-110B may include the following sequential operations: (i) forming S / D openings 410 through superlattice structures 119A-119B on the portions of the fin structures 106A-106B that are not located below the non-polycrystalline silicon structures 312A-312B, such as...FIGS. 4A-4B As shown, and (ii) epitaxial growth of semiconductor material inside and outside the S / D opening 410, such as FIGS. 5A-5B As shown. In some embodiments, an internal spacer 113 may be formed between operations (i) and (ii) of the formation process of the epitaxial S / D regions 110A-110B, as... FIGS. 5A-5B As shown. The internal spacer 113 can be formed after the S / D opening 410 is formed, as... FIGS. 5A-5B As shown. After forming the S / D regions 110A-110B, ESL 117 and ILD layers 118 can be formed on the S / D regions 110A-110B to form FIGS. 5A-5B The structure. Although operations 205-210 are shown for FETs 102A-102B, similar operations can be implemented to form the S / D regions 110C-110E of the corresponding FETs 102C-102E, as... FIGS. 6C-7E As shown.

[0047] refer to FIG. 2 In operation 215, gate openings are formed on and within the superlattice structure. For example, as... FIGS. 6A-6E As shown, gate openings 612A-612E are formed. Forming gate openings 612A-612B may include... FIGS. 5A-5B The polysilicon structures 312A-312B and nanostructure layers 122A1-122A2 and 122B1-122B2 are etched. Similar operations can be performed to form gate openings 612C-612E, as shown. FIGS. 6C-6E As shown.

[0048] refer to FIG. 2 In operations 220-230, a gate-all-around (GAA) structure is formed in the gate opening. For example, based on operations 220-230, gate structures 112A-112E can be formed, as shown in the reference. FIGS. 7A-9E , FIGS. 10A-12B and FIGS. 13A-14E Described.

[0049] refer to FIG. 2 In operation 220, a gate oxide structure is formed within the gate opening. For example, as referenced... FIGS. 7A-9E As described, gate oxide structures 127A-127E are formed within gate openings 612A-612E. Forming the gate oxide structures 127A-127E may include the following sequential operations: (i) by... FIGS. 6A-6E The structure implements a first oxidation process to form a first IO layer 722A-722E within the corresponding gate openings 612A-612E, such as... FIGS. 7A-7E As shown, (ii) an HK gate dielectric layer 724 is deposited within gate openings 612A-612E, as...FIGS. 7A-7E As shown, (iii) selectively forming cap layers 732A-732E within the respective gate openings 612A-612E, as FIGS. 7A-7E As shown, (iv) forming first IO layers 122A-122E and second IO layers 126A-126E by performing a second oxidation process on the structure of FIGS. 7A-7E As shown, and (v) removing the cap layers 732A-732E from the structure of FIGS. 8A-8E As shown, and (v) removing the cap layers 732A-732E from the structure of FIGS. 8A-8E As shown, and (v) removing the cap layers 732A-732E from the structure of FIGS. 9A-9E As shown, and (v) removing the cap layers 732A-732E from the structure of

[0050] The first oxidation process can include oxidizing surfaces of the nanowire channel regions 120A1-120A2, the nanowire channel regions 120B1-120B2, the nanowire channel regions 120C1-120C2, the nanowire channel regions 120D1-120D2, and the nanowire channel regions 120E1-120E2 exposed within the gate openings 612A-612E in an oxidation environment. The oxidation environment can include a combination of ozone (O3), ammonium hydroxide, hydrogen peroxide, and water ("SC1 solution") and / or a combination of hydrochloric acid, hydrogen peroxide, water ("SC2 solution"). In some embodiments, the first oxidation process can be performed at a first oxidation temperature in a range of about 30 °C to about 200 °C. Other temperature ranges are within the scope of the present disclosure.

[0051] In the first oxidation process, the oxidation rates of the nanostructured channel regions 120A1-120A2, 120B1-120B2, 120C1-120C2, 120D1-120D2, and 120E1-120E2 can be substantially equal. As a result, the first IO layers 722A-722E grow to substantially equal thicknesses to one another. The first IO layers 722A-722E form the respective first IO layers 122A-122E in a subsequent second oxidation process. During the second oxidation process, the nanostructured channel regions 120A1-120A2, 120B1-120B2, 120C1-120C2, 120D1-120D2, and 120E1-120E2 are further oxidized to grow the first IO layers 722A-722E into the first IO layers 122A-122E having different thicknesses to one another. The oxidation rates of the nanostructured channel regions 120A1-120A2, 120B1-120B2, 120C1-120C2, 120D1-120D2, and 120E1-120E2 are different to one another during the second oxidation process. The second oxidation process can include exposing the structures of FIGS. 7A-7E to a gas mixture of oxygen and nitrogen, steam, or other suitable oxidizing agent substantially simultaneously at a second oxidation temperature in a range of about 800 °C to about 900 °C, which is higher than the first oxidation temperature. Other temperature ranges are within the scope of the present disclosure. In some embodiments, the second oxidation process can be an in-situ process or an ex-situ process.

[0052] In some embodiments, the first IO layers 722A-722E are grown to have respective first IO layers 122A-122E of different thicknesses from one another due to different oxygen diffusivity of the cap layers 732A-732E and / or the second IO layers 126A-126E formed at the interface between the HK gate dielectric layer 724 and the cap layers 732A-732E during the second oxidation process. The different oxygen diffusivity of the cap layers 732A-732E and / or the second IO layers 126A-126E results in different oxidation rates of the nanostructure channel regions 120A1-120A2, the nanostructure channel regions 120B1-120B2, the nanostructure channel regions 120C1-120C2, the nanostructure channel regions 120D1-120D2, and the nanostructure channel regions 120E1-120E2 during the second oxidation process. The oxygen diffusivity of the cap layers 732A-732E and / or the second IO layers 126A-126E is directly proportional to the respective oxidation rates of the nanostructure channel regions 120A1-120A2, the nanostructure channel regions 120B1-120B2, the nanostructure channel regions 120C1-120C2, the nanostructure channel regions 120D1-120D2, and the nanostructure channel regions 120E1-120E2. Accordingly, in some embodiments, to achieve the relative thicknesses of the first IO layers 122A-122E, the cap layer 732E can have a higher oxygen diffusivity than the cap layer 732D, the cap layer 732D can have a higher oxygen diffusivity than the cap layer 732C, the cap layer 732C can have a higher oxygen diffusivity than the cap layer 732B, and the cap layer 732B can have a higher oxygen diffusivity than the cap layer 732A. In some embodiments, the cap layers 732A-732E can include titanium silicon nitride (TiSiN), titanium nitride (TiN), tantalum nitride (TaN), aluminum nitride (AlN), and tungsten nitride (WN), respectively, to achieve the relative thicknesses of the first IO layers 122A-122E. In some embodiments, the cap layers 732A-732E can have substantially equal thicknesses from one another. Selectively forming the cap layers 732A-732E can include using a photolithography process.

[0053] Removing the cap layers 732A-732E can include using tungsten pentachloride (WCl5) or tantalum pentachloride (TaCl5) gas, O2 gas, and argon gas or other suitable gas against the FIGS. 8A-8EThe structure simultaneously performs an atomic layer etching (ALE) process. In some embodiments, each cycle of the ALE process may include the following consecutive cycles: (i) a first etching gas (e.g., WCl5 or TaCl5) stream, (ii) a first purge process using argon, (iii) a second etching gas (e.g., O2) stream, and (iv) a second purge process using argon. In some embodiments, the ALE process may include the following sequential operations: (i) using FIG. 15 The ALE control system 1500 shown uses a training module 1570 to predict an etching scheme, (ii) adjusting the process parameters of an etching apparatus (not shown) using a communication module 1572 based on the predicted etching scheme, (iii) etching capping layers 732A-732E using the etching apparatus based on the adjusted process parameters, (iv) measuring the thickness of the remaining capping layer portion using a measurement system (not shown), (v) sending the measurement data to a memory 1574 of the ALE control system 1500, (vi) analyzing the measurement data using an analysis module 1576 of the ALE control system 1500 to determine whether the thickness of the remaining capping layer portion is equal to approximately zero nanometers, and (vii) if the thickness is equal to approximately zero nanometers, ending the etching process in the etching apparatus using a processor 1578 and / or communication module 1572 of the ALE control system 1500, or repeating operations (i)-(ii) until the thickness is equal to approximately zero nanometers and removing capping layers 732A-732E, as shown. FIGS. 9A-9E As shown. In some embodiments, the training module 1570, communication module 1572, memory 1574, analysis module 1576, and processor 1578 are wired or wirelessly connected to each other. In some embodiments, adjusting the process parameters of the etching apparatus may include adjusting the etching duration, etching gas flow, and / or etching temperature.

[0054] Predicting etching schemes using the ALE control system 1500 may include implementing computational programs to (i) analyze etching process data collected from previous etching processes performed on other structures using etching equipment, and (ii) predict etching process characteristics (e.g., etching rate, etching duration) of the capping layers 732A-732E using different etching process parameters (e.g., ampoule lifetime, temperature and humidity of the etching chamber, light absorption or reflection within the etching chamber, pressure within the etching chamber, carrier gas conditions, length of the etching gas supply pipe, etc.). The computer program may include one or more mathematical operations, pattern recognition programs, big data mining programs, or machine learning programs such as neural network algorithms to analyze etching process data (e.g., ampoule lifetime, etching chamber lifetime, effective etching density, effective etch area size, etching gas parameters, etc.) and predict etching process characteristics. Similarly, analyzing measurement data using the ALE control system 1500 may include implementing computational programs.

[0055] The discussion of HK gate dielectric layers 124A-124E applies to HK gate dielectric layer 724 unless otherwise stated. HK gate dielectric layer 724 is formed in subsequent processes as HK gate dielectric layers 124A-124E. In some embodiments, HK gate dielectric layer 724 can be formed using a hafnium chloride (HfCl4) precursor via an ALD process at a temperature ranging from about 250°C to about 350°C. Other temperature ranges are within the scope of this invention.

[0056] In some embodiments, instead of depositing the HK gate dielectric layer 724 after forming the first IO layers 722A-722B, the HK gate dielectric layer 724 may be deposited after removing the capping layers 732A-732E. That is, in some embodiments, forming the gate oxide structures 127A-127E may include the following sequential operations: (i) by... FIGS. 6A-6E The structure is subjected to a first oxidation process to form a first IO layer 722A-722E within the corresponding gate openings 612A-612E, such as FIGS. 7A-7E As shown, (ii) capping layers 732A-732E are selectively formed on the respective first IO layers 722A-722E, (iii) first IO layers 122A-122E are formed by performing a second oxidation process, (iv) capping layers 732A-732E are removed, and (v) HK gate dielectric layers 724 are deposited on the respective first IO layers 122A-122E.

[0057] refer to FIG. 2 In operation 225, a WFM layer is formed on the gate oxide structure. For example, as... FIGS. 10A-10B As shown, a WFM layer 128 is formed on the gate oxide structures 127A-127B. Depositing the WFM layer 128 may include using titanium tetrachloride (TiCl4) and aluminum titanium ethylene (TEAl) or tantalum chloride (TaCl5) and trimethylaluminum (TMA) as precursors at a temperature in the range of about 350°C to about 450°C, employing an ALD or CVD process. FIGS. 9A-9B A WFM layer 128 of approximately 1 nm to approximately 3 nm thick is deposited on the structure. Other thickness ranges and temperature ranges of the WFM layer 128 are within the scope of this invention. In some embodiments, the WFM layer 128 may be deposited in an ALD process of approximately 4 to approximately 12 cycles, wherein one cycle may include the following consecutive cycles: (i) a first precursor gas (e.g., TiCl4 or TaCl5) stream, (ii) a first gas purge process, (iii) a second precursor gas (e.g., TEA1 or TMA) stream, and (iv) a second gas purge process.

[0058] refer to FIG. 2In operation 230, a gate metal fill layer is deposited on the WFM layer. For example, as... FIGS. 11A-11B As shown, a gate metal fill layer 130 is deposited on the WFM layer 128. The deposited gate metal fill layer 130 may include... FIGS. 10A-10B Simultaneously depositing a fluorine-free metal layer (e.g., a fluorine-free tungsten layer) on the structure. Depositing the fluorine-free metal layer may include depositing the fluorine-free metal layer using WCl5 or WCl6 and H2 as precursors via an ALD process at temperatures ranging from about 400°C to about 500°C. Other temperature ranges are within the scope of this invention. In some embodiments, the fluorine-free metal layer may be deposited in an ALD process of about 160 to about 320 cycles, one cycle of which may include the following consecutive cycles: (i) a first precursor gas (e.g., WCl5 or WCl6) stream, (ii) a first gas purification process, (iii) a second precursor gas (e.g., H2) stream, and (iv) a second gas purification process.

[0059] After depositing the gate metal fill layer 130, the HK gate dielectric layer 724, the second IO layers 126A-126B, the WFM layer 128, and the gate metal fill layer 130 can be polished using a chemical mechanical polishing (CMP) process to make the top surfaces of the HK gate dielectric layer 724, the second IO layers 126A-126B, the WFM layer 128, and the gate metal fill layer 130 substantially coplanar with the top surface of the ILD layer 118, such as... FIGS. 12A-12B As shown. In some embodiments, a contact structure may be formed after the CMP process.

[0060] Although it shows the FIGS. 9A-9B The structural implementation operation is 225-230, but it is also possible to... FIGS. 9C-9E The structure is implemented in operations 225-230 to form FET 102C-102E, such as... FIGS. 1F-1H As shown.

[0061] In some embodiments, in operation 220, instead of selectively forming capping layers 732A-732E of different materials, a photolithography process can be used to selectively form capping layers 1332A-133E of the same material with different thicknesses on the HK gate dielectric layer 724, such as... FIGS. 13A-13E As shown. In some embodiments, to achieve the relative thickness of the first IO layers 122A-122E, the cover layer 1332E may be thicker than the cover layer 1332D, the cover layer 1332D may be thicker than the cover layer 1332C, the cover layer 1332C may be thicker than the cover layer 1332B, and the cover layer 1332B may be thicker than the cover layer 1332A. This can be achieved by... FIGS. 13A-13E The structure rather than FIGS. 7A-7Eto grow the first IO layers 722A-722E to have respective first IO layers 122A-122E with different thicknesses from one another, as shown in FIGS. 14A-14E FIGS. 14A-14E The second IO layers 126A-126E can have the same material.

[0062] The present disclosure provides exemplary semiconductor devices (e.g., semiconductor device 100) having FETs (e.g., FETs 102A-102E) with different gate structure configurations that provide different power levels. The present disclosure also provides exemplary methods (e.g., method 200) of forming such FETs on the same substrate (e.g., substrate 104). The exemplary methods form FET gate structures (e.g., gate structures 112A-112E) with different gate oxide structures (e.g., gate oxide structures 127A-127E) for forming FETs with different power consumption levels on the same substrate. Compared to other methods of forming FETs with similar power consumption levels (e.g., in the range of microwatts, nanowatts, or picowatts) on the same substrate, these exemplary methods can be more cost effective (e.g., cost reduction of about 20% to about 30%) and time efficient (e.g., time reduction of about 15% to about 20%) in manufacturing reliable FET gate structures with low and / or ultra-low power consumption levels. In addition, compared to other methods of forming FETs with similar power consumption levels, these exemplary methods can form FET gate structures with smaller sizes (e.g., smaller gate lengths) without increasing gate resistance.

[0063] In some embodiments, each of the FET gate oxide structures includes a HK gate dielectric layer (e.g., HK gate dielectric layer 124) between the first and second IO layers (e.g., first IO layers 122A-122E and second IO layers 126A-126E). The first IO layers can be formed to have different thicknesses from one another to achieve different power consumption levels in different FETs. In some embodiments, the first IO layers of different thicknesses can be formed in two oxidation processes. In a first oxidation process, the first IO layers can be formed to have substantially equal thicknesses from one another. In a second oxidation process, the first IO layers can be grown to have different thicknesses from one another.

[0064] ​In some embodiments, the second oxidation process can include forming a capping layer (e.g., capping layers 732A-732E or capping layers 1332A-1332E) on the HK gate dielectric layer and performing an in-situ anneal process or an ex-situ anneal process in an oxidation environment. The capping layers can be formed to have different oxygen diffusivities from each other. The capping layers can control growth of the first IO layer during the in-situ anneal process or the ex-situ anneal process. In some embodiments, the capping layers having different oxygen diffusivities can be formed with materials (e.g., metal nitrides, metal oxides, other suitable materials, or combinations thereof) that are different from each other and have substantially equal thicknesses to each other, or can be formed from the same material having different thicknesses from each other.

[0065] In some embodiments, a method includes forming first and second nanostructure channel regions on first and second fin structures, respectively; forming first and second oxide layers having first and second thicknesses, respectively; forming a high-k dielectric layer having first and second layer portions on the first and second oxide layers, respectively; forming first and second capping layers having first and second oxygen diffusivities on the first and second layer portions, respectively; growing the first oxide layer to have a third thickness and growing the second oxide layer to have a fourth thickness; and forming a gate metal fill layer over the high-k dielectric layer. The first and second thicknesses are substantially equal to each other, and the first and second oxide layers surround the first and second nanostructure channel regions, respectively. The second oxygen diffusivity is higher than the first oxygen diffusivity. The fourth thickness is greater than the third thickness.

[0066] In some embodiments, a method includes forming first and second nanostructure channel regions on first and second fin structures, respectively; forming first and second gate oxide layer structures on the first and second nanostructure channel regions, respectively; and forming a gate metal fill layer over the first and second gate oxide structures. Forming the first and second gate oxide layer structures includes forming first and second oxide layers of a same material having substantially equal thicknesses to each other, forming first and second high-k dielectric layers of the same material, forming first and second capping layers having different oxygen diffusivities from each other, growing the first and second oxide layers to have different thicknesses from each other, and removing the first and second capping layers.

[0067] In some embodiments, a semiconductor device includes: a substrate; a first fin structure and a second fin structure disposed on the substrate; a first nanostructure channel region and a second nanostructure channel region disposed on the first fin structure and the second fin structure, respectively; a first gate oxide structure and a second gate oxide structure surrounding the first nanostructure channel region and the second nanostructure channel region, respectively; and a first gate metal fill layer and a second gate metal fill layer disposed above the first gate oxide structure and the second gate oxide structure, respectively. The second nanostructure channel region has a size smaller than a size of the first nanostructure channel region. The first gate oxide structure and the second gate oxide structure include: first and second oxide layers of a same material having different thicknesses from each other; first and second high-k dielectric layers disposed on the first and second oxide layers, respectively; and third and fourth oxide layers of different materials having substantially equal thicknesses from each other. The third and fourth oxide layers are disposed on the first and second high-k dielectric layers, respectively.

[0068] Some embodiments of the present application provide a method of forming a semiconductor device, including: forming a first nanostructure channel region and a second nanostructure channel region on a first fin structure and a second fin structure, respectively; forming a first oxide layer having a first thickness and a second oxide layer having a second thickness, wherein the first thickness and the second thickness are substantially equal to each other, and wherein the first oxide layer and the second oxide layer surround the first nanostructure channel region and the second nanostructure channel region, respectively; forming a high-k dielectric layer having a first layer portion and a second layer portion on the first oxide layer and the second oxide layer, respectively; forming a first cap layer having a first oxygen diffusivity and a second cap layer having a second oxygen diffusivity on the first layer portion and the second layer portion, respectively, wherein the second oxygen diffusivity is higher than the first oxygen diffusivity; growing the first oxide layer to have a third thickness and growing the second oxide layer to have a fourth thickness, wherein the fourth thickness is greater than the third thickness; and forming a gate metal fill layer above the high-k dielectric layer.

[0069] In some embodiments, the method further includes forming a first interface layer between the first capping layer and the first layer portion, and forming a second interface layer between the second capping layer and the second layer portion. In some embodiments, forming the first oxide layer and the second oxide layer includes oxidizing exposed surfaces of the first nanostructured channel region and the second nanostructured channel region at substantially equal oxidation rates. In some embodiments, growing the first oxide layer and the second oxide layer includes oxidizing the first nanostructured channel region and the second nanostructured channel region through the first capping layer and the second capping layer at a first oxidation rate and a second oxidation rate, respectively, and wherein the second oxidation rate is greater than the first oxidation rate. In some embodiments, forming the first capping layer and the second capping layer includes depositing a first nitride layer having a first thickness and a second nitride layer having a second thickness, respectively, and wherein the first thickness and the second thickness are substantially equal to each other. In some embodiments, forming the first capping layer and the second capping layer includes depositing a first nitride layer having a first thickness and a second nitride layer having a second thickness, respectively, and wherein the second thickness is greater than the first thickness. In some embodiments, forming the first capping layer and the second capping layer includes depositing first and second layers of material that are different from each other and have substantially equal thicknesses to each other. In some embodiments, forming the first capping layer and the second capping layer includes depositing first and second layers of the same material having different thicknesses to each other. In some embodiments, the method further includes forming a third oxide layer between the first capping layer and the first layer portion, and forming a fourth oxide layer between the second capping layer and the second layer portion, wherein the third oxide layer and the fourth oxide layer have different materials from each other. In some embodiments, the method further includes forming a third oxide layer having a first oxygen diffusivity between the first capping layer and the first layer portion, and forming a fourth oxide layer having a second oxygen diffusivity between the second capping layer and the second layer portion, wherein the second oxygen diffusivity is higher than the first oxygen diffusivity.

[0070] Some embodiments of the present disclosure provide a method of forming a semiconductor device, comprising: forming a first nanoscale channel region and a second nanoscale channel region on a first fin structure and a second fin structure, respectively; forming a first gate oxide structure and a second gate oxide structure on the first nanoscale channel region and the second nanoscale channel region, respectively, wherein forming the first gate oxide structure and the second gate oxide structure comprises forming a first oxide layer and a second oxide layer of a same material having substantially equal thicknesses to each other, forming a first high-k dielectric layer and a second high-k dielectric layer of the same material, forming a first cap layer and a second cap layer having different oxygen diffusivities to each other, growing the first oxide layer and the second oxide layer to have different thicknesses to each other, and removing the first cap layer and the second cap layer; and forming a gate metal fill layer over the first gate oxide structure and the second gate oxide structure.

[0071] In some embodiments, forming the first gate oxide structure and the second gate oxide structure comprises forming a third oxide layer and a fourth oxide layer having different oxygen diffusivities to each other. In some embodiments, forming the first gate oxide structure and the second gate oxide structure comprises forming a third oxide layer and a fourth oxide layer having different Gibbs energies to each other. In some embodiments, forming the first oxide layer and the second oxide layer comprises oxidizing the first nanoscale channel region and the second nanoscale channel region at a first oxidation temperature, and wherein growing the first oxide layer and the second oxide layer comprises oxidizing the first nanoscale channel region and the second nanoscale channel region at a second oxidation temperature higher than the first oxidation temperature. In some embodiments, the method further comprises forming a work function metal layer between the first gate oxide structure and the second gate oxide structure and the gate metal fill layer. In some embodiments, removing the first cap layer and the second cap layer comprises etching the first cap layer and the second cap layer using an atomic layer etching process.

[0072] Yet some embodiments of the present application provide a semiconductor device, comprising: a substrate; a first fin structure and a second fin structure disposed on the substrate; a first nanostructure channel region and a second nanostructure channel region disposed on the first fin structure and the second fin structure, respectively, wherein a size of the second nanostructure channel region is smaller than a size of the first nanostructure channel region; a first gate oxide structure and a second gate oxide structure surrounding the first nanostructure channel region and the second nanostructure channel region, respectively, wherein the first gate oxide structure and the second gate oxide structure comprise: first and second oxide layers of a same material having different thicknesses from each other, first and second high-k dielectric layers disposed on the first and second oxide layers, respectively, and third and fourth oxide layers of different materials having substantially equal thicknesses from each other, wherein the third and fourth oxide layers are disposed on the first and second high-k dielectric layers, respectively; and first and second gate metal fill layers disposed above the first and second gate oxide structures, respectively.

[0073] In some embodiments, the third and fourth oxide layers have different oxygen diffusivities from each other. In some embodiments, the third and fourth oxide layers have different Gibbs energies from each other. In some embodiments, the first and second high-k dielectric layers comprise dopants of rare earth metals.

[0074] The foregoing summary of features of several embodiments has been presented for the purposes of illustration and description. It is therefore contemplated that persons of ordinary skill in the art will readily appreciate that the application is not limited to the embodiments specifically described and illustrated, and that they could readily use the teachings of the present application as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments described herein without departing from the spirit and scope of the application. It is therefore expressly intended that the claims be interpreted as including all equivalents, modifications and alternatives that would be within the spirit and scope of the present application.

Claims

1. A method for manufacturing a semiconductor device, comprising: A first nanostructure channel region and a second nanostructure channel region are formed on the first fin structure and the second fin structure, respectively. A first oxide layer having a first thickness and a second oxide layer having a second thickness are formed respectively, wherein the first thickness and the second thickness are substantially equal to each other, and wherein the first oxide layer and the second oxide layer surround the first nanostructure channel region and the second nanostructure channel region respectively. High-k dielectric layers having a first layer portion and a second layer portion are formed on the first oxide layer and the second oxide layer, respectively. A first capping layer having a first oxygen diffusivity and a second capping layer having a second oxygen diffusivity are formed on the first layer portion and the second layer portion, respectively, wherein the second oxygen diffusivity is higher than the first oxygen diffusivity; A third oxide layer is formed between the first cover layer and a portion of the first layer; A fourth oxide layer is formed between the second cover layer and a portion of the second layer; The first oxide layer is grown to have a third thickness, and the second oxide layer is grown to have a fourth thickness, wherein the fourth thickness is greater than the third thickness; and A gate metal fill layer is formed above the high-k dielectric layer.

2. The method according to claim 1, further comprising: A first interface layer is formed between the first cover layer and the first layer portion; as well as A second interface layer is formed between the second cover layer and the second layer portion.

3. The method according to claim 1, wherein, Forming the first oxide layer and the second oxide layer involves oxidizing the exposed surfaces of the first nanostructure channel region and the second nanostructure channel region at substantially equal oxidation rates.

4. The method according to claim 1, wherein, Growing the first oxide layer and the second oxide layer includes oxidizing the first nanostructure channel region and the second nanostructure channel region respectively through the first capping layer and the second capping layer at a first oxidation rate and a second oxidation rate, and Wherein, the second oxidation rate is greater than the first oxidation rate.

5. The method according to claim 1, wherein, Forming the first capping layer and the second capping layer includes depositing a first nitride layer having a first thickness and a second nitride layer having a second thickness, respectively. The first thickness and the second thickness are substantially equal to each other.

6. The method according to claim 1, wherein, Forming the first capping layer and the second capping layer includes depositing a first nitride layer having a first thickness and a second nitride layer having a second thickness, respectively. The second thickness is greater than the first thickness.

7. The method according to claim 1, wherein, Forming the first and second capping layers involves depositing a first layer and a second layer of materials that are different from each other and have substantially equal thicknesses.

8. The method according to claim 1, wherein, Forming the first capping layer and the second capping layer involves depositing a first layer and a second layer of the same material having different thicknesses from each other.

9. The method according to claim 1, wherein, The third oxide layer and the fourth oxide layer are made of different materials.

10. The method according to claim 1, wherein, The third oxide layer has: and The fourth oxide layer has a second oxygen diffusivity. The second oxygen diffusivity is higher than the first oxygen diffusivity.

11. A method for manufacturing a semiconductor device, comprising: A first nanostructure channel region and a second nanostructure channel region are formed on the first fin structure and the second fin structure, respectively. A first gate oxide structure and a second gate oxide structure are formed on the first nanostructure channel region and the second nanostructure channel region, respectively, wherein forming the first gate oxide structure and the second gate oxide structure includes: A first oxide layer and a second oxide layer of the same material with substantially equal thickness are formed. Forming a first high-k dielectric layer and a second high-k dielectric layer of the same material, A first capping layer and a second capping layer with different oxygen diffusivity are formed. A third oxide layer is formed between the first capping layer and the first high-k dielectric layer, and a fourth oxide layer is formed between the second capping layer and the second high-k dielectric layer. The first oxide layer and the second oxide layer are grown to have different thicknesses than each other, and Remove the first cover layer and the second cover layer; and A gate metal fill layer is formed over the first gate oxide structure and the second gate oxide structure.

12. The method according to claim 11, wherein, The third oxide layer and the fourth oxide layer have different oxygen diffusivity.

13. The method according to claim 11, wherein, The third oxide layer and the fourth oxide layer have different Gibbs energies.

14. The method according to claim 11, wherein, Forming the first oxide layer and the second oxide layer includes oxidizing the first nanostructure channel region and the second nanostructure channel region at a first oxidation temperature, and The growth of the first oxide layer and the second oxide layer includes oxidizing the first nanostructure channel region and the second nanostructure channel region at a second oxidation temperature higher than the first oxidation temperature.

15. The method of claim 11, further comprising: A functional metal layer is formed between the first gate oxide structure and the second gate oxide structure and the gate metal fill layer.

16. The method according to claim 11, wherein, Removing the first and second cover layers includes etching the first and second cover layers using an atomic layer etching process.

17. A semiconductor device, comprising: Substrate; The first fin structure and the second fin structure are disposed on the substrate; A first nanostructure channel region and a second nanostructure channel region are respectively disposed on the first fin structure and the second fin structure, wherein the size of the second nanostructure channel region is smaller than the size of the first nanostructure channel region. A first gate oxide structure and a second gate oxide structure are respectively surrounding the first nanostructure channel region and the second nanostructure channel region, wherein the first gate oxide structure and the second gate oxide structure include: The first oxide layer and the second oxide layer are made of the same material, but have different thicknesses. A first high-k dielectric layer and a second high-k dielectric layer are respectively disposed on the first oxide layer and the second oxide layer, and A third oxide layer and a fourth oxide layer, made of different materials, have substantially equal thicknesses, wherein the third oxide layer and the fourth oxide layer are respectively disposed on the first high-k dielectric layer and the second high-k dielectric layer; and A first gate metal fill layer and a second gate metal fill layer are respectively disposed above the first gate oxide structure and the second gate oxide structure.

18. The semiconductor device according to claim 17, wherein, The third oxide layer and the fourth oxide layer have different oxygen diffusivity.

19. The semiconductor device according to claim 17, wherein, The third oxide layer and the fourth oxide layer have different Gibbs energies.

20. The semiconductor device according to claim 17, wherein, The first high-k dielectric layer and the second high-k dielectric layer include rare-earth metal dopants.

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