Electroless plating method for metal gate fill

Abstract

This application relates to electroless plating methods for metal gate fill. In a gate replacement process for nanosheet FinFET devices, embodiments employ an electrochemical process to deposit a metal gate electrode in a gate opening. Promoters and inhibitors can be used to achieve bottom-up deposition for the fill material of the metal gate electrode.

Description

Technical Field

[0001] This disclosure generally relates to chemical plating methods for metal gate fillers. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] According to a first aspect of this disclosure, a method for forming a semiconductor device is provided, comprising: etching a dummy gate of a transistor to remove the dummy gate and form a first opening; etching to remove a first nanostructure and extend the first opening to expose a second nanostructure of the transistor; depositing a first dielectric layer in the first opening, the first dielectric layer surrounding the second nanostructure; depositing a first work function layer in the first opening, the first work function layer surrounding the second nanostructure and the first dielectric layer; depositing an adhesive layer in the first opening, the adhesive layer surrounding the second nanostructure; and immersing the first opening in an electrochemical plating solution to plate metal into the first opening, the metal filling the first opening.

[0005] According to a second aspect of this disclosure, a method for forming a semiconductor device is provided, comprising: growing an epitaxial source / drain region in a fin recess located on either side of a gate; performing a gate replacement process, the gate replacement process comprising: removing a dummy gate structure between two gate spacers of the gate to form an opening between the two gate spacers; depositing a first gate dielectric layer in the opening, the first gate dielectric layer covering a channel region of the gate; depositing a work function layer in the opening, the work function layer covering the first gate dielectric layer; and depositing a conductive filler in the opening by a chemical plating process, the chemical plating process depositing the conductive filler at the bottom of the opening at a plating rate 10 to 25 times that at the sidewalls of the opening.

[0006] According to a third aspect of this disclosure, a method for forming a semiconductor device is provided, comprising: forming a first nanostructure field-effect transistor gate structure, the forming comprising: forming a plurality of nanostructure channel regions; depositing a gate dielectric layer around the plurality of nanostructure channel regions; depositing a gate work function layer around the gate dielectric layer; and depositing a gate filler around the gate work function layer and the gate, the depositing of the gate filler comprising: providing a plating solution in an opening corresponding to the gate filler; providing a promoter and an inhibitor in the plating solution; and reducing a metal from the plating solution to deposit the metal at the bottom of the opening; and forming a first epitaxial source / drain region and a second epitaxial source / drain region disposed on either side of the first nanostructure field-effect transistor gate structure, wherein the plurality of nanostructure channel regions extend from the first source / drain region to the second source / drain region. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood by reading in conjunction with the accompanying drawings through the following detailed description. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 An example of a nanostructured field-effect transistor (nano-FET) according to some embodiments is shown in a three-dimensional view.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 11C , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 19A , Figure 19B , Figure 19C , Figure 19D , Figure 20A , Figure 20B , Figure 20C , Figure 20D , Figure 23A , Figure 23B , Figure 23C , Figure 23D , Figure 24A , Figure 24B , Figure 24C , Figure 24D , Figure 25A , Figure 25B , Figure 25C , Figure 25D , Figure 26A , Figure 26B , Figure 26C , Figure 26D , Figure 27A , Figure 27B , Figure 27C , Figure 27D , Figure 28A , Figure 28B , Figure 29A , Figure 29B , Figure 29C , Figure 30A , Figure 30B , Figure 30C , Figure 31A , Figure 31B and Figure 31C This is a cross-sectional view of an intermediate stage in the fabrication of a nanostructured FET according to some embodiments.

[0010] Figure 21 An electrochemical bath according to some embodiments is shown.

[0011] Figure 22A , Figure 22B , Figure 22C and Figure 22D Various cross-sectional views of intermediate stages of a plating process according to some embodiments are shown.

[0012] Figure 32A , Figure 32B and Figure 32C This is a cross-sectional view of a nanostructured FET according to some embodiments.

[0013] Figure 33 An example of a fin field-effect transistor (finFET) according to some embodiments is shown in a three-dimensional view.

[0014] Figures 34A to 34E This is a cross-sectional view of an intermediate stage in the fabrication of a finFET according to some embodiments. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] In addition, spatially related terms (e.g., "below," "under," "down," "above," "up") may be used herein to facilitate the description of the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly.

[0017] Nanostructured FET devices utilize multiple nanostructures as gate channel regions. In the fabrication of nanostructured FETs, a gate replacement process can be used to replace a dummy gate used as a temporary structure with a replacement gate. The replacement gate can be, for example, a metal gate and can comprise multiple layers, including a work function adjustment layer, as discussed in more detail below. The dummy gate is removed by forming a recess at the location of the dummy gate, exposing the nanostructured channel region of the nanostructured FET. After exposing the channel region of the nanostructured FET, the individual layers of the replacement gate are deposited in the recess. After the individual layers of the replacement gate are deposited in the recess, the remaining recess is filled with gate electrode filler, completing the replacement gate deposition. The embodiment process uses electroless plating (also known as electrochemical plating) to deposit the gate electrode filler, rather than using a combined ALD / CVD process. The recess can have a large aspect ratio, and conventional deposition techniques may leave voids or seams in the recess, where the deposition technique interrupts the connection to the underlying region. These gaps or seams can severely hinder the design operations of the subsequently formed gate. The embodiment process employs electrochemical plating techniques, along with promoters and inhibitors, to achieve bottom-up deposition of the gate electrode filler. That is, the recesses are filled primarily from bottom to top, rather than being filled all at once on all surfaces.

[0018] The following describes embodiments of dies including nanostructured FETs in a specific context. However, various embodiments can be applied to dies including other types of transistors (e.g., FinFETs, planar transistors, etc.) that replace or are combined with nanostructured FETs.

[0019] Figure 1An example of a nanostructured FET (e.g., nanowire FET, nanosheet FET (NSFET), etc.) according to some embodiments is shown in a three-dimensional view. The nanostructured FET includes nanostructures 55 (e.g., nanosheets, nanowires, etc.) on a substrate 50 (e.g., a semiconductor substrate) above fins 66, wherein the nanostructures 55 act as channel regions of the nanostructured FET. The nanostructures 55 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Isolation regions 68 are disposed between adjacent fins 66, which may protrude above the isolation regions 68. Although the isolation regions 68 are shown / described as separated from the substrate 50, as used herein, the term "substrate" may refer to a single semiconductor substrate or a combination of a semiconductor substrate and isolation regions. Furthermore, although the bottom portions of the fins 66 are shown as being of a single continuous material with the substrate 50, the bottom portions of the fins 66 and / or the substrate 50 may include a single material or multiple materials. In this context, fin 66 refers to the portion extending between adjacent isolation regions 68.

[0020] A gate dielectric layer 110 is located above the top surface of the fin 66 and along the top, sidewalls, and bottom surface of the nanostructure 55. A gate electrode 112 is located above the gate dielectric layer 110. An epitaxial source / drain region 92 is disposed on the fin 66, on the opposite side of the gate dielectric layer 110 and the gate electrode 112.

[0021] Figure 1 The reference cross sections used in the following figures are further illustrated. Cross section A-A' is along the longitudinal axis of the gate electrode 98 and in a direction perpendicular to, for example, the direction of current flow between the epitaxial source / drain regions 92 of the nanostructure FET. Cross section B-B' is perpendicular to cross section A-A' and parallel to the longitudinal axis of the fin 66 of the nanostructure FET, and in, for example, the direction of current flow between the epitaxial source / drain regions 92 of the nanostructure FET. Cross section C-C' is parallel to cross section A-A' and extends through the epitaxial source / drain regions of the nanostructure FET. Cross section D-D' is a horizontal cross section parallel to the substrate 50 between the nanostructures 55. Cross section E-E' is parallel to cross section D-D' and passes through the nanostructure 55. For clarity, the following figures refer to these reference cross sections.

[0022] Some embodiments discussed herein are discussed in the context of nanostructured FETs formed using a post-gate process. In other embodiments, a pre-gate process may be used. Furthermore, some embodiments are contemplated for use in planar devices (e.g., planar FETs) or in FinFETs.

[0023] Figures 2 to 32C This is a cross-sectional view of an intermediate stage in the fabrication of a nanostructured FET according to some embodiments. Figures 2 to 5 , Figure 6A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 23A , Figure 24A , Figure 25A , Figure 26A , Figure 27A , Figure 28A , Figure 29A , Figure 30A , Figure 31A and Figure 32A It shows Figure 1 The reference section A-A' is shown. Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 11C , Figure 12B , Figure 12D , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 23B , Figure 24B , Figure 25B , Figure 26B , Figure 27B , Figure 28B , Figure 29B , Figure 30B , Figure 31B and Figure 32B It shows Figure 1 The reference section B-B' is shown. Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 12C , Figure 13C , Figure 29C , Figure 30C , Figure 31C and Figure 32C It shows Figure 1 The reference section C-C' is shown. Figure 17C , Figure 18C , Figure 19C , Figure 23C , Figure 24C , Figure 25C , Figure 26Cand Figure 27C It shows Figure 1 The reference section D-D' is shown. Figure 17D , Figure 18D , Figure 19D , Figure 23D , Figure 24D , Figure 25D , Figure 26D and Figure 27D It shows Figure 1 The cross section E-E' is shown. Figure 21 The chemical plating bath is shown, and Figure 22A , Figure 22B , Figure 22C and Figure 22D The chemical plating process for filling the opening is shown.

[0024] exist Figure 2 In this embodiment, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof.

[0025] Substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, like an n-type nanostructure FET, and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, like a p-type nanostructure FET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by separator 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be provided between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0026] Further in Figure 2In this process, a multilayer stack 64 is formed on a substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-C (collectively referred to as second semiconductor layers 53). For illustrative purposes and as discussed in more detail below, in the p-type region 50P, the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form the channel region of the nanostructured FET. Furthermore, in the n-type region 50N, the first semiconductor layer 51 is removed and the second semiconductor layer 53 is patterned to form the channel region of the nanostructured FET. However, in some embodiments, in the n-type region 50N, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form the channel region of the nanostructured FET, and in the p-type region 50P, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form the channel region of the nanostructured FET.

[0027] In some other embodiments, in both the n-type region 50N and the p-type region 50P, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form the channel region of the nanostructured FET. In other embodiments, in both the n-type region 50N and the p-type region 50P, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form the channel region of the nanostructured FET. In such embodiments, the channel regions in both the n-type region 50N and the p-type region 50P may have the same material composition (e.g., silicon or another semiconductor material) and may be formed simultaneously. Figure 32A , Figure 32B and Figure 32C The structure resulting from such an embodiment is shown, wherein, for example, the channel regions in both the p-type region 50P and the n-type region 50N comprise silicon.

[0028] For illustrative purposes, the multilayer stack 64 is shown as a three-layer stack comprising each of a first semiconductor layer 51 and a second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for a p-type nanostructure FET, such as silicon germanium, etc., and the second semiconductor layer 53 may be formed of a second semiconductor material suitable for an n-type nanostructure FET, such as silicon, silicon carbon, etc. For illustrative purposes, the multilayer stack 64 is shown as having a bottom semiconductor layer suitable for a p-type nanostructure FET. In some embodiments, the multilayer stack 64 may be formed such that the bottom layer is a semiconductor layer suitable for an n-type nanostructure FET.

[0029] The first semiconductor material and the second semiconductor material can be materials with high etch selectivity relative to each other. Thus, in the n-type region 50N, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the n-type nanostructure FET. Similarly, in the p-type region 50P, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the p-type nanostructure FET.

[0030] Now for reference Figure 3 According to some embodiments, fins 66 are formed in substrate 50, and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50, respectively, by etching trenches in multilayer stack 64 and substrate 50. Etching can be any acceptable etching, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. Etching can be anisotropic. Forming nanostructures 55 by etching multilayer stack 64 can further define first nanostructures 52A-C (collectively referred to as first nanostructures 52) from first semiconductor layer 51 and second nanostructures 54A-C (collectively referred to as second nanostructures 54) from second semiconductor layer 53. First nanostructures 52 and second nanostructures 54 can be further collectively referred to as nanostructure 55.

[0031] The fin 66 and nanostructure 55 can be patterned using any suitable method. For example, one or more photolithography processes can be used to pattern the fin 66 and nanostructure 55, including dual patterning or multiple patterning processes. Typically, dual or multiple patterning processes combine photolithography and self-alignment processes, allowing patterns to be created with, for example, smaller spacing than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin 66.

[0032] For illustrative purposes, Figure 3 The fins 66 in the n-type region 50N and the p-type region 50P are shown to have substantially equal widths. In some embodiments, the width of the fin 66 in the n-type region 50N may be larger or thinner than the width of the fin 66 in the p-type region 50P. Furthermore, while each of the fins 66 and nanostructures 55 is shown to always have a consistent width, in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls such that the width of each of the fins 66 and / or nanostructures 55 increases continuously in the direction toward the substrate 50. In such embodiments, each nanostructure 55 may have a different width and be trapezoidal.

[0033] exist Figure 4 In the nanostructure 55, a shallow trench isolation (STI) region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material on the substrate 50, the fin 66, and the nanostructure 55, and between adjacent fins 66. The insulating material can be an oxide (e.g., silicon oxide), a nitride, or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In the embodiment, the insulating material is formed such that an excess of insulating material covers the nanostructure 55. Although the insulating material is shown as a single layer, some embodiments may employ multiple layers. For example, in some embodiments, a liner (not shown separately) can be formed first along the surfaces of the substrate 50, the fin 66, and the nanostructure 55. Subsequently, a filler material such as described above can be formed on the liner.

[0034] Then, a removal process is applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etching back, or combinations thereof may be employed. This planarization process exposes the nanostructure 55 such that, after the planarization process is completed, the top surface of the nanostructure 55 and the insulating material are flush.

[0035] The insulating material is then recessed to form STI regions 68. The insulating material is recessed such that the upper portions of the fins 66 in the n-type region 50N and p-type region 50P protrude between adjacent STI regions 68. Furthermore, the top surface of the STI regions 68 can have a flat surface (as shown), a convex surface, a concave surface (e.g., dish-shaped), or a combination thereof. The top surface of the STI regions 68 can be formed as flat, convex, and / or concave by appropriate etching. The STI regions 68 can be recessed using an acceptable etching process, such as an etching process selective for the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of the fins 66 and nanostructures 55). For example, it can be removed using an oxide employing, for example, diluted hydrofluoric acid (dHF).

[0036] The above about Figures 2 to 4 The described process is merely one example of how the fins 66 and nanostructures 55 can be formed. In some embodiments, the fins 66 and / or nanostructures 55 can be formed using masking and epitaxial growth processes. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structure protrudes from the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structure can include alternating semiconductor materials as described above, such as a first semiconductor material and a second semiconductor material. In some embodiments in which the epitaxial structure is epitaxially grown, the epitaxially grown material can be in-situ doped during growth, which can avoid prior and / or subsequent implantation, but in-situ doping and implantation doping can be used together.

[0037] Furthermore, for illustrative purposes only, the first semiconductor layer 51 (and the resulting first nanostructure 52) and the second semiconductor layer 53 (and the resulting second nanostructure 54) are shown and discussed herein as comprising the same material in the p-type region 50P and the n-type region 50N. Thus, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials in the p-type region 50P and the n-type region 50N, or may be formed in a different order.

[0038] Further in Figure 4In this process, suitable wells (not shown separately) can be formed in fin 66, nanostructure 55, and / or STI region 68. In embodiments with different well types, different implantation steps for n-type region 50N and p-type region 50P can be implemented using photoresist or other masks (not shown separately). For example, in n-type region 50N and p-type region 50P, photoresist can be formed over fin 66 and STI region 68. The photoresist is patterned to expose p-type region 50P. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in p-type region 50P, and the photoresist can act as a mask to substantially prevent n-type impurities from being implanted into n-type region 50N. The n-type impurity can be phosphorus, arsenic, antimony, etc., implanted into the region at a concentration of about 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 Within the specified range. After implantation, the photoresist is removed, for example, through an acceptable ashing process.

[0039] After or before implantation in the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the fin 66, nanostructure 55, and STI region 68 in both the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can act as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurity can be boron, boron fluoride, indium, etc., implanted into the region at a concentration of approximately 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 Within the specified range. After injection, the photoresist can be removed, for example, by an acceptable ashing process.

[0040] Following implantation into the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped during growth, which can avoid implantation, but in-situ doping and implantation doping can be used together.

[0041] exist Figure 5In this process, a dummy dielectric layer 70 is formed on the fin 66 and / or nanostructure 55. The dummy dielectric layer 70 can be, for example, silicon oxide, silicon nitride, combinations thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed on the dummy dielectric layer 70, and a mask layer 74 is formed on the dummy gate layer 72. The dummy gate layer 72 can be deposited on the dummy dielectric layer 70 and then planarized, for example, by CMP. The mask layer 74 can be deposited on the dummy gate layer 72. The dummy gate layer 72 can be a conductive or non-conductive material and can be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 72 can be made of other materials that have high etch selectivity relative to the etching of the isolation region. The mask layer 74 can include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed on the n-type region 50N and the p-type region 50P. Note that, for illustrative purposes only, the dummy dielectric layer 70 is shown to cover only the fin 66 and the nanostructure 55. In some embodiments, the dummy dielectric layer 70 can be deposited such that the dummy dielectric layer 70 covers the STI region 68, thereby extending the dummy dielectric layer 70 between the dummy gate layer 72 and the STI region 68.

[0042] Figures 6A to 18C Various additional steps in manufacturing the embodiment device are shown. Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 12C , Figure 13A , Figure 13C , Figure 14A , Figure 15A and Figure 18C The characteristics of the n-type region 50N or the p-type region 50P are shown. Figure 6A and Figure 6B In this process, acceptable photolithography and etching techniques can be used to pattern the mask layer 74 (see [link]). Figure 5A mask 78 is formed. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form dummy gate 76 and dummy gate dielectric 71, respectively. The dummy gate 76 covers the corresponding channel region of the fin 66. The pattern of the mask 78 can be used to physically separate each dummy gate 76 from adjacent dummy gates 76. The dummy gate 76 may also have a longitudinal direction substantially perpendicular to the longitudinal direction of the corresponding fin 66.

[0043] exist Figure 7A and Figure 7B In, respectively in Figure 6A and Figure 6B A first spacer layer 80 and a second spacer layer 82 are formed on top of the structure shown. The first spacer layer 80 and the second spacer layer 82 will then be patterned to act as spacers for forming self-aligned source / drain regions. Figure 7A and Figure 7B In this configuration, a first spacer layer 80 is formed on the top surface of the STI region 68; on the top surface and sidewalls of the fin 66, nanostructure 55, and mask 78; and on the sidewalls of the dummy gate 76 and dummy gate dielectric 71. A second spacer layer 82 is deposited on the first spacer layer 80. The first spacer layer 80 can be formed from silicon oxide, silicon nitride, silicon oxynitride, etc., using techniques such as thermal oxidation, or deposited by CVD, ALD, etc. The second spacer layer 82 can be formed from a material having a different etch rate than the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, etc., and can be deposited by CVD, ALD, etc.

[0044] After the formation of the first spacer layer 80 and before the formation of the second spacer layer 82, implantation for lightly doped source / drain (LDD) regions (not shown separately) can be performed. In embodiments with different device types, similar to the above... Figure 4 The implantation discussed earlier can involve forming a mask, such as a photoresist, over the n-type region 50N while exposing the p-type region 50P. An impurity of an appropriate type (e.g., p-type) can then be implanted into the exposed fins 66 and nanostructures 55 within the p-type region 50P. The mask can then be removed. The n-type impurity can be any of the previously discussed n-type impurities, and the p-type impurity can be any of the previously discussed p-type impurities. The lightly doped source / drain regions can have a doping density of approximately 1 × 10⁻⁶. 15 atoms / cm 3 To approximately 1×10 19 atoms / cm3 The impurity concentration is within a certain range. Annealing can be used to repair injection damage and reactivate the injected impurities.

[0045] exist Figure 8A and Figure 8B In this process, a first spacer layer 80 and a second spacer layer 82 are etched to form a first spacer 81 and a second spacer 83. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 serve to enable self-alignment of the subsequently formed source / drain regions and to protect the sidewalls of the fin 66 and / or nanostructure 55 during subsequent processing. The first spacer layer 80 and the second spacer layer 82 can be etched using a suitable etching process, such as an isotropic etching process (e.g., wet etching process), an anisotropic etching process (e.g., dry etching process), etc. In some embodiments, the material of the second spacer layer 82 has a different etch rate than the material of the first spacer layer 80, such that the first spacer layer 80 can act as an etch stop layer when the second spacer layer 82 is patterned, and that the second spacer layer 82 can act as a mask when the first spacer layer 80 is patterned. For example, the second spacer layer 82 can be etched using an anisotropic etching process, wherein the first spacer layer 80 acts as an etch stop layer, and the remaining portion of the second spacer layer 82 forms the second spacer 83, such as... Figure 8A As shown. Subsequently, the second spacer 83 acts as a mask during the etching of the exposed portion of the first spacer layer 80, thereby forming the first spacer 81, as... Figure 8A As shown.

[0046] like Figure 8A As shown, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or the nanostructure 55. Figure 8B As shown, in some embodiments, the second spacer layer 82 can be removed from the first spacer layer 80 adjacent to the mask 78, dummy gate 76, and dummy gate dielectric 71, and the first spacer 81 is disposed on the sidewalls of the mask 78, dummy gate 76, and dummy gate dielectric 71. In other embodiments, a portion of the second spacer layer 82 may remain on the first spacer layer 80 adjacent to the mask 78, dummy gate 76, and dummy gate dielectric 71.

[0047] Note that the above disclosure generally describes the process for forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be used (e.g., the first spacer 81 can be patterned before depositing the second spacer layer 82), additional spacers can be formed and removed, etc. Furthermore, different structures and steps can be used to form n-type devices and p-type devices.

[0048] exist Figure 9Aand Figure 9B In some embodiments, a first recess 86 is formed in the fin 66, nanostructure 55, and substrate 50. An epitaxial source / drain region is then formed in the first recess 86. The first recess 86 may extend through the first nanostructure 52 and the second nanostructure 54, and into the substrate 50. Figure 9A As shown, the top surface of the STI region 68 can be flush with the bottom surface of the first recess 86. In various embodiments, the fin 66 can be etched such that the bottom surface of the first recess 86 is set below the top surface of the STI region 68. The first recess 86 can be formed by etching the fin 66, nanostructure 55, and substrate 50 using anisotropic etching processes such as RIE, NBE, etc. The first spacer 81, the second spacer 83, and the mask 78 mask portions of the fin 66, nanostructure 55, and substrate 50 during the etching process for forming the first recess 86. Each layer of the nanostructure 55 and / or the fin 66 can be etched using a single etching process or multiple etching processes. A timed etching process can be used to stop etching the first recess 86 after it has reached a desired depth.

[0049] exist Figure 10A and Figure 10B In the n-type region 50N, the portion of the sidewall of the layer formed by the first semiconductor material (e.g., the first nanostructure 52) in the multilayer stack 64 exposed by the first recess 86 is etched to form a sidewall recess 88, and the portion of the sidewall of the layer formed by the second semiconductor material (e.g., the second nanostructure 54) in the multilayer stack 64 exposed by the first recess 86 is etched to form the sidewall recess 88 in the p-type region 50P. Although in Figure 10BThe sidewalls of the first nanostructure 52 and the second nanostructure 54 in the sidewall recess 88 are shown as straight, but these sidewalls can be concave or convex. Isotropic etching processes, such as wet etching, can be used to etch the sidewalls. A mask (not shown) can be used to protect the p-type region 50P while an etchant selective for the first semiconductor material is used to etch the first nanostructure 52, such that in the n-type region 50N, the second nanostructure 54 and the substrate 50 remain relatively unetched compared to the first nanostructure 52. Similarly, a mask (not shown) can be used to protect the n-type region 50N while an etchant selective for the second semiconductor material is used to etch the second nanostructure 54, such that in the p-type region 50P, the first nanostructure 52 and the substrate 50 remain relatively unetched compared to the second nanostructure 54. In embodiments in which the first nanostructure 52 comprises, for example, SiGe and the second nanostructure 54 comprises, for example, Si or SiC, the sidewalls of the first nanostructure 52 in the n-type region 50N can be etched using a dry etching process employing tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., and the sidewalls of the second nanostructure 54 in the p-type region 50P can be etched using a wet or dry etching process employing hydrogen fluoride, another fluorine-based etchant, etc.

[0050] exist Figures 11A-11C In the middle, a first internal spacer 90 is formed in the sidewall recess 88. This can be achieved by... Figure 10A and Figure 10B An internal spacer layer (not shown separately) is deposited on the structure shown to form a first internal spacer 90. The first internal spacer 90 serves as an isolation feature between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed in the first recess 86, and the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P will be replaced with corresponding gate structures.

[0051] The internal spacer layer can be deposited using conformal deposition processes such as CVD or ALD. The internal spacer layer may include materials such as silicon nitride or silicon oxynitride, but any suitable material can be used, for example, a low-k material with a k-value less than about 3.5. The internal spacer layer can then be anisotropically etched to form a first internal spacer 90. Although the outer walls of the first internal spacer 90 are shown flush with the sidewalls of the second nanostructure 54 in the n-type region 50N and the first nanostructure 52 in the p-type region 50P, the outer walls of the first internal spacer 90 may extend beyond or be recessed from the sidewalls of the second nanostructure 54 and / or the first nanostructure 52, respectively.

[0052] Furthermore, despite Figure 11B The outer wall of the first internal spacer 90 is shown to be straight, but the outer wall of the first internal spacer 90 can be concave or convex. For example, Figure 11C An embodiment is shown in which, in the n-type region 50N, the sidewalls of the first nanostructure 52 are concave, the outer sidewalls of the first internal spacer 90 are concave, and the first internal spacer is recessed from the sidewalls of the second nanostructure 54. An embodiment is also shown in which, in the p-type region 50P, the sidewalls of the second nanostructure 54 are concave, the outer sidewalls of the first internal spacer 90 are concave, and the first internal spacer is recessed from the sidewalls of the first nanostructure 52. The internal spacer layer can be etched using anisotropic etching processes such as RIE, NBE, etc. The first internal spacer 90 can be used to prevent subsequent etching processes (e.g., etching processes for forming the gate structure) from affecting the subsequently formed source / drain regions (e.g., as discussed below). Figures 12A-12C The discussion focuses on the damage to the epitaxial source / drain region (92).

[0053] exist Figures 12A-12C In this embodiment, an epitaxial source / drain region 92 is formed in the first recess 86. In some embodiments, the epitaxial source / drain region 92 can apply stress to the second nanostructure 54 in the n-type region 50N and the first nanostructure 52 in the p-type region 50P, thereby improving performance. Figure 12B As shown, epitaxial source / drain regions 92 are formed in the first recess 86 such that each dummy gate 76 is disposed between corresponding adjacent pairs of epitaxial source / drain regions 92. In some embodiments, a first spacer 81 is used to separate the epitaxial source / drain regions 92 from the dummy gate dielectric 71 by an appropriate lateral distance, and a first internal spacer 90 is used to separate the epitaxial source / drain regions 92 from the nanostructure 55 by an appropriate lateral distance, such that the epitaxial source / drain regions 92 are not shorted with the subsequently formed gate of the resulting nanostructure FET.

[0054] The epitaxial source / drain region 92 in the n-type region 50N (e.g., an NMOS region) can be formed by masking the p-type region 50P (e.g., a PMOS region). The epitaxial source / drain region 92 is then epitaxially grown in the first recess 86 in the n-type region 50N. The epitaxial source / drain region 92 can comprise any acceptable material suitable for an n-type nanostructure FET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can comprise a material on which tensile strain is applied, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon-phosphorus, etc. The epitaxial source / drain region 92 can have a surface protruding from the corresponding upper surface of the nanostructure 55 and can have a facet.

[0055] The epitaxial source / drain region 92 in the p-type region 50P (e.g., a PMOS region) can be formed by masking the n-type region 50N (e.g., an NMOS region). The epitaxial source / drain region 92 is then epitaxially grown in the first recess 86 in the p-type region 50P. The epitaxial source / drain region 92 can comprise any acceptable material suitable for a p-type nanostructure FET. For example, if the first nanostructure 52 is silicon-germanium, the epitaxial source / drain region 92 can comprise a material on which compressive strain is applied, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 92 can also have a multilayer stack 64 (see...). Figure 2 The corresponding surface of the ) is raised and can have small planes.

[0056] The epitaxial source / drain region 92, the first nanostructure 52, the second nanostructure 54, and / or the substrate 50 can be implanted with dopants to form the source / drain region, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The impurity concentration of the source / drain region can be approximately 1 × 10⁻⁶. 19 atoms / cm 3 1×10 21 atoms / cm 3 Between. The n-type and / or p-type impurities used for the source / drain regions can be any of the previously discussed impurities. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0057] As a result of the epitaxial process used to form epitaxial source / drain regions 92 in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source / drain regions 92 has small facets that extend laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same nanostructure FET to merge, such as... Figure 12A As shown. In other embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed, as... Figure 12C As shown. In Figure 12A and Figure 12C In the illustrated embodiment, a first spacer 81 may be formed on the top surface of the STI region 68 to prevent epitaxial growth. In some other embodiments, the first spacer 81 may cover portions of the sidewalls of the nanostructure 55 to further prevent epitaxial growth. In some other embodiments, the spacer etching used to form the first spacer 81 may be adjusted to remove spacer material to allow the epitaxial growth region to extend to the surface of the STI region 68.

[0058] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of different semiconductor materials and may be doped with different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration less than that of the second semiconductor material layer 92B and greater than that of the third semiconductor material layer 92C. In embodiments in which the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited on the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited on the second semiconductor material layer 92B.

[0059] Figure 12D An embodiment is shown in which the sidewalls of the first nanostructure 52 in the n-type region 50N and the sidewalls of the second nanostructure 54 in the p-type region 50P are concave, the outer sidewall of the first internal spacer 90 is concave, and the first internal spacer 90 is recessed from the sidewalls of the second nanostructure 54 and the first nanostructure 52, respectively. Figure 12D As shown, the epitaxial source / drain region 92 can be formed to contact the first internal spacer 90 and can extend through the sidewall of the second nanostructure 54 in the n-type region 50N and through the sidewall of the first nanostructure 52 in the p-type region 50P.

[0060] exist Figures 13A-13C In, respectively in Figure 6A , Figure 12B and Figure 12A The first interlayer dielectric (ILD) 96 is deposited on the structure shown. Figures 7A-12D The process will not change. Figure 6A(See the cross-section shown). The first ILD 96 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain region 92, the mask layer 74, and the first spacer 81. The CESL 94 may include a dielectric material having an etch rate different from that of the overlying first ILD 96, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0061] exist Figures 14A-14B In this process, a planarization process such as CMP can be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 76 or the mask 78. This planarization process may also remove the mask 78 on the dummy gate 76, as well as a portion of the first spacer 81 along the sidewall of the mask 78. After this planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 96 are flush within the process variation. Therefore, the top surface of the dummy gate layer 72 is exposed through the first ILD 96. In some embodiments, the mask 78 may be retained, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0062] exist Figure 15A and Figure 15B In one or more etching steps, the dummy gate layer 72 and mask layer 74 (if present) are removed to form the second recess 98. A portion of the dummy gate dielectric 71 in the second recess 98 is also removed. In some embodiments, the dummy gate layer 72 and dummy gate dielectric 71 are removed by an anisotropic dry etching process. For example, this etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate layer 72 at a faster rate than the first ILD 96 or the first spacer 81. Each second recess 98 exposes and / or overlays a portion of the nanostructure 55 that serves as a channel region in the subsequently completed nanostructure FET. The portion of the nanostructure 55 that serves as a channel region is disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy gate dielectric 71 can be used as an etch stop layer as the dummy gate layer 72 is etched. The dummy gate dielectric 71 can then be removed after the removal of the dummy gate layer 72.

[0063] exist Figure 16A and Figure 16B In this embodiment, the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P are removed, causing the second recess 98 to extend. The first nanostructure 52 can be removed by forming a mask (not shown) over the p-type region 50P and performing an isotropic etching process, such as wet etching, using an etchant selective for the material of the first nanostructure 52, while the second nanostructure 54, the substrate 50, and the STI region 68 remain relatively unetched compared to the first nanostructure 52. In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructures 54A-54C comprise, for example, Si or SiC, the first nanostructure 52 in the n-type region 50N can be removed using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc.

[0064] The second nanostructure 54 in the p-type region 50P can be removed by forming a mask (not shown) over the n-type region 50N and performing an isotropic etching process, such as wet etching, using an etchant selective for the material of the second nanostructure 54, while the first nanostructure 52, substrate 50, and STI region 68 remain relatively unetched compared to the second nanostructure 54. In embodiments where the second nanostructure 54 comprises, for example, SiGe and the first nanostructure 52 comprises, for example, Si or SiC, hydrogen fluoride, another fluorine-based etchant, etc., can be used to remove the second nanostructure 54 in the p-type region 50P.

[0065] In other embodiments, the channel regions in the n-type region 50N and the p-type region 50P can be formed simultaneously, for example, by removing the first nanostructure 52 from both the n-type region 50N and the p-type region 50P, or by removing the second nanostructure 54 from both the n-type region 50N and the p-type region 50P. In such embodiments, the channel regions of the n-type nanostructure FET and the p-type nanostructure FET can have the same material composition, such as silicon, silicon germanium, etc. Figure 32A , Figure 32B and Figure 32C A structure resulting from such an embodiment is shown, wherein the channel region in both the p-type region 50P and the n-type region 50N is provided by a second nanostructure 54, and includes, for example, silicon.

[0066] exist Figure 17A , Figure 17B , Figure 17C and Figures 17D to 27A , Figure 27B , Figure 27C and Figure 27D The gate formation process is shown below. Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 19A , Figure 19B , Figure 19C , Figure 19D , Figure 20A , Figure 20B , Figure 20C , Figure 20D , Figure 23A , Figure 23B , Figure 23C , Figure 23D , Figure 24A , Figure 24B , Figure 24C , Figure 24D , Figure 25A , Figure 25B , Figure 25C , Figure 25D , Figure 26A , Figure 26B , Figure 26C , Figure 26D , Figure 27A , Figure 27B , Figure 27C and Figure 27D Each shows an intermediate view of the gate formation process. Figure 17A , Figure 18A , Figure 19A , Figure 23A , Figure 24A and Figure 26A It shows Figure 16A Enlarged view of the dashed box in the n-type region 50N. Figure 25A and Figure 27A It shows Figure 16A Enlarged view of the dashed box in the p-shaped region 50P. Figure 17B , Figure 18B , Figure 19B , Figure 23B , Figure 24B and Figure 26B It shows Figure 16B Enlarged view of the dashed box in the n-type region 50N. Figure 25B and Figure 27B It shows Figure 16B Enlarged view of the dashed box in the p-shaped region 50P. Figure 17C , Figure 18C , Figure 19C , Figure 23C , Figure 24C and Figure 26C It shows along Figure 1 A horizontal cross-sectional view of the second nanostructures 54B and 54A between lines D-D'. Figure 17D , Figure 18D, Figure 19D , Figure 23D , Figure 24D and Figure 26D It shows along Figure 1 A horizontal cross-sectional view of line E-E' passing through the second nanostructure 54B. Figure 25C and Figure 27C It shows along Figure 1 A horizontal cross-sectional view of line D-D' passing through nanostructure 52B. Figure 25D and Figure 27D It shows along Figure 1 A horizontal cross-sectional view of the nanostructures 52B and 52A between lines E-E'. Figure 21 The chemical plating bath is shown, and Figure 22A , Figure 22B , Figure 22C and Figure 22D The chemical plating process for filling the opening is shown.

[0067] refer to Figure 17A , Figure 17B , Figure 17C and Figure 17D Once the first nanostructure 52 is removed from the n-type region 50N and / or the second nanostructure 54 is removed from the p-type region 50P, a process for forming a replacement gate is initiated by depositing a series of layers in the second recess 98, the replacement gate comprising a gate dielectric layer 110, a work function layer 106, and a gate electrode filler 112. In an embodiment, the series of layers of the gate dielectric layer 110 may include an interface layer 102 and a dielectric layer 104. The series of layers of the work function layer 106 may include one or more layers of work function metal and a stack of any intermediate layers deposited between the work function metals. The gate electrode filler 112 may then be filled in the remainder of the second recess 98. The gate electrode may be considered to comprise the work function layer 106 and the gate electrode filler 112. In the n-type region 50N, the gate dielectric layer 110 can be conformally formed on the top surface and sidewalls of the substrate 50, and on the top surface, sidewalls, and bottom surface of the second nanostructure 54. Similarly, in the p-type region 50P, the gate dielectric layer 110 can be conformally formed on the top surface and sidewalls of the substrate 50, and on the top surface, sidewalls, and bottom surface of the first nanostructure 52. The gate dielectric layer 110 can also be deposited on the top surfaces of the first ILD 96, CESL 94, the first spacer 81, and the STI region 68.

[0068] In some embodiments, the interface layer 102 may be a material such as silicon dioxide formed by a process such as in-situ vapor generation (ISSG), but other processes may also be used. In other embodiments, the interface layer 102 may include a high-k dielectric material, and in these embodiments, the interface layer 102 may have a k value greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, Ta2O5, which are conformally deposited in the second recess 98 to about Peace Treaty The thickness of the interface layer 102 can vary, but any suitable deposition process or thickness can be used. The interface layer 102 can be deposited using any suitable process, such as molecular beam deposition (MBD), ALD, PECVD, or combinations thereof. However, any suitable material, formation process, or thickness can be used for the interface layer 102.

[0069] refer to Figure 18A , Figure 18B , Figure 18C and Figure 18D Once the interface layer 102 is formed, a dielectric layer 104 can be formed on top of the interface layer 102. In an embodiment, the dielectric layer 104 is made of a high-k material and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, and Ta2O5, which are conformally deposited in the second recess 98 on the interface layer 102 for approximately [number missing]. Peace Treaty The thickness of the interface layer 102 can be varied, but any suitable deposition process or thickness can be used. The interface layer 102 can be deposited using any suitable process, such as MBD, ALD, PECVD, or combinations thereof. However, the dielectric layer 104 can be made of any suitable material, forming process, or thickness. The structure of the gate dielectric layer 110 can be the same or different in the n-type region 50N and the p-type region 50P.

[0070] refer to Figure 19A , Figure 19B , Figure 19C and Figure 19DThe work function layer 106 can be formed in the second recess 98 on top of the dielectric layer 104. The work function layer 106 may include any number of liner layers and any number of work function adjustment layers. For example, in some embodiments, the work function layer 106 may include a barrier layer deposited on the gate dielectric layer 110. In such embodiments, the barrier layer may be formed of a metallic material, such as TaN, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal nitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations thereof, etc. The barrier layer may be deposited using deposition processes such as MBD, ALD, PECVD, etc., or combinations thereof, to approximately [amount missing]. Peace Treaty The thickness can be between [thickness range], but any suitable deposition process or thickness can also be used.

[0071] The work function layer 106 may further include a work function adjustment layer, such as a p-metal work function adjustment layer, which may be deposited over the barrier layer (if used) and the gate dielectric layer 110. In some embodiments, the material of the p-metal work function adjustment layer may include a tungsten-based metal, such as tungsten, tungsten nitride (WN). x ), Tungsten carbonitride (WC) x N y ), tungsten oxide (WO) x (and combinations thereof). In another embodiment, the p-metal work function adjustment layer can be a molybdenum-based metal, such as molybdenum, molybdenum nitride (MoN), etc. x In another embodiment, the p-metal work function adjustment layer can be a material such as titanium nitride (TiN). In yet another embodiment, the p-metal work function adjustment layer can be a material such as gold, platinum, palladium, or combinations thereof. However, any suitable material can be used. Furthermore, the p-metal work function adjustment layer can be deposited to approximately [value missing] using deposition processes such as MBD, ALD, PECVD, etc. Peace Treaty The thickness can be between [thickness range], but any suitable deposition process or thickness can also be used.

[0072] The work function layer 106 may further include, for example, an n-metal work function adjustment layer, which may be deposited over the barrier layer (if used) and the gate dielectric layer 110. In some embodiments, the n-metal work function adjustment layer may be a material such as Ti, Ag, Al, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. Furthermore, the n-metal work function adjustment layer may be deposited using deposition processes such as MBD, ALD, PECVD, etc. Peace Treaty The thickness can be between [thickness range], but any suitable deposition process or thickness can also be used.

[0073] Embodiments may employ multiple work function adjustment layers, including one or more p-metal work function adjustment layers and / or one or more n-metal work function adjustment layers deposited in any order as described above. In some embodiments, the work function layers 106 may be merged together among the second nanostructures 54, such as... Figure 19A , Figure 19B and Figure 19C As shown. In other embodiments, the work function layer 106 may maintain its respective surrounding each second nanostructure 54 (e.g., Figure 26A , Figure 26B and Figure 26C As shown below.

[0074] exist Figure 20A , Figure 20B , Figure 20C and Figure 20D In this process, a glue layer 108 is deposited on top of the work function layer 106. The glue layer 108 can be formed to assist in adhering the upper gate electrode filler 112 to the lower work function layer 106, and to provide a nucleation layer for forming the gate electrode filler 112. In embodiments, the glue layer 108 can be a material such as titanium nitride, or a material similar to an n-metal work function adjustment layer (as described above), and can be formed using processes such as MBE, ALD, or PECVD. Peace Treaty The thickness can vary, but any suitable deposition process or thickness can be used. However, any suitable materials and processes can be employed.

[0075] Figure 21 and Figure 22A , Figure 22B , Figure 22C and Figure 22DA chemical plating (or electrochemical plating) bath and process are shown for filling openings (e.g., the remainder of the second recess 98 after the deposition of the adhesive layer 108). This process, which is then applied to the second recess 98, will be discussed in detail herein. Figure 23A , Figure 23B , Figure 23C and Figure 23D As shown.

[0076] Figure 21 An electrochemical bath 140 is shown. The electrochemical bath 140 includes an aqueous plating solution 138 containing metal ions 134 of a source material and a chemical reducing agent 136, which acts as a catalyst for reducing the metal ions 134. The deposition of the metal can be represented by the following equation:

[0077] M + +R→M+ oxide byproducts

[0078] Among them, M + Metal ions 134 represent the source metal to be deposited, and R is a reducing agent 136 (electron source). Additives are added to an electrochemical bath 140, which includes a promoter 132 and an inhibitor 130. The promoter 132 is a small molecule that diffuses more quickly to the bottom of the opening to be filled and promotes bottom-up deposition. The inhibitor 130 is a large molecule that accumulates on the sidewalls of the opening to be filled, which slows down the deposition rate.

[0079] Figures 22A to 22D An example plating process is shown to fill an opening 153 in surrounding material 150 using a bottom-up fill process. Instead of depositing a conformal layer of material on the exposed surface, this bottom-up fill process deposits material in layers that are much thicker at the bottom of the opening or recess than at the sidewalls. For openings with a high aspect ratio (i.e., openings with a height much greater than their width), bottom-up deposition, rather than conventional deposition, helps reduce or eliminate voids formed in the deposition. This deposition effect can be achieved by depositing material and then performing an etch-back process using a fluorinated etchant to remove material at the top of the opening at a greater rate than the material at the bottom of the opening. However, in the process described below, bottom-up deposition is achieved using a promoter and inhibitor in an electrochemical bath without performing an etch-back process. Figures 22A to 22D In this context, the surrounding material 150 may include an insulating material, and the opening 153 may be lined with any number of lining layers, such as a barrier layer and an adhesive or bonding layer, which in this example are considered part of the surrounding material 150. The opening 153 may, for example, correspond to the second recess 98 (see, for example, see...). Figure 20A , Figure 20B , Figure 20C and Figure 20D ).

[0080] exist Figure 22A In this process, the opening is immersed in an electrochemical bath, such as electrochemical bath 140. The promoter 132 diffuses more readily to the bottom of the opening 153, and the inhibitor 130 accumulates more on the sidewalls of the opening 153, although some promoter 132 may also be present on the sidewalls. For example, the ratio of promoter 132 to inhibitor 130 at the bottom of the opening 153 can be between 10:1 and 100:1. The ratio of inhibitor 130 to promoter 132 on the sidewalls of the opening (at the midpoint between the top and bottom of the opening 153) can be between 10:1 and 50:1.

[0081] In some embodiments, plating bath 138 may employ bis(3-sulfopropyl) disulfide (SPS) as accelerator 132 and polyethylene glycol (PEG) as inhibitor 130, but other accelerators and inhibitors may also be used. In one example, the concentration of SPS may be between about 0.0001 wt% and about 0.001 wt%, and the concentration of PEG may be between about 0.0001 wt% and about 0.001 wt%. In some embodiments, the ratio of accelerator 132 to inhibitor 130 may be between 10:1 and 1:10, for example, between 5:1 and 1:5 or between 2:1 and 1:2. The plating may be performed with the plating bath at a temperature between about 10°C and about 50°C. The duration of the electrochemical plating may be between about 10 minutes and about 4 hours. By using appropriate concentrations of appropriate accelerator 132 and inhibitor 130, accelerator 132 may accumulate at the bottom of opening 153 (see Figures 22A to 22C The sidewalls of opening 135 are controlled by inhibitor 130. Therefore, more plating occurs at the bottom of opening 135, while plating on the sidewalls of opening 135 is suppressed.

[0082] The metal used for the metal filler 155 can be a metal ion (e.g., metal ion 134) or a metal salt of a conductive material (e.g., Al, Cu, W, Ti, Ta, Mn, Zr, Co, Ni, combinations thereof, etc.), and can be combined with other materials to deposit Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations thereof, etc. The reducing agent 136 used to react with the metal to produce the metal filler 155 can include, for example, NH3, H2, SiH4, etc., or combinations thereof.

[0083] exist Figure 22BIn the process, metal ions (e.g., metal ion 134) react with a reducing agent (e.g., reducing agent 136) to form a metal filler 155 in the opening 153. Due to the inhibitor 130 on the sidewalls of the opening 153 and the promoter 132 at the bottom of the opening 153 and at the corner where the bottom of the opening 153 contacts the sidewalls of the opening 153, the deposition rate of the metal filler 155 is greater at the bottom of the opening 153 than at the sidewalls of the opening 153. In some embodiments, the deposition rate at the bottom of the opening 153 may be 5 to 50 times greater than the deposition rate at the sidewalls of the opening 153. The metal filler 155 comprises a metal formed when metal ions or salts react with the reducing agent 136. The metal filler 155 may also include some of the following: oxidation byproducts from the reaction, unreacted metal ions 134, unreacted reducing agent 136, promoter 132, and / or inhibitor 130, which may become embedded and dispersed in the metal deposit. Oxidation byproducts may include, for example, metal oxides of metal ions 134, oxidation of one or more elements of reducing agent 136, oxidation of one or more elements of promoter 132, and / or oxidation of one or more elements of inhibitor 130. However, since a back-etching process is not used to form metal filler 155, metal filler 155 may be fluorine-free.

[0084] exist Figure 22C In the process, the deposition of metal filler 155 continues in a bottom-up manner, so that the bottom of opening 153 is filled faster than the sidewalls of opening 153.

[0085] exist Figure 22D In this process, the deposition of the metal filler 155 is completed, and a void-free metal filler 155 is formed from bottom to top in the openings of the surrounding material 150. Subsequent processes may include planarizing the metal filler 155 to remove excess material deposited on the surrounding material 150.

[0086] Figure 23A , Figure 23B , Figure 23C and Figure 23D A view is shown showing the formation of the gate electrode filler 112 at the midpoint of the electroless plating process used to fill the remaining portion of the second recess 98. (See diagram) Figure 23A , Figure 23B , Figure 23C and Figure 23D As shown (especially) Figure 23A ), using inhibitors and accelerators as mentioned above, using... Figure 21 , Figure 22A , Figure 22B , Figure 22C and Figure 22D The top-down electroless plating process is used to provide the gate electrode filler 112. This process provides a seamless gate electrode filler 112.

[0087] The individual layers of the work function layer 106 can make it difficult to fill the second recess 98 using other processes such as ALD / CVD without creating voids or seams around the irregular shape of the work function layer 106. Furthermore, after depositing the work function layer 106, Figure 23B The overall height-to-width aspect ratio of the second recess 98 can be between approximately 5:1 and 20:1, for example, between 10:1 and 20:1. A high aspect ratio may make it difficult to use another process (e.g., an ALD / CVD process) to deposit the gate electrode filler 112 at a sufficiently uniform rate (so that the bottom of the second recess 98 is filled with the gate electrode filler 112 before pinch-off), thus leaving voids. A high aspect ratio will tend to result in a lower deposition rate at the bottom of the second recess 98 than towards the top of the second recess 98. However, using the bottom-up gate electrode filler 112 advantageously provides a much larger deposition rate at the bottom of the second recess 98, so that the second recess 98 can be filled with the gate electrode filler 112 without voids or with a reduced number of voids.

[0088] By using the above information Figure 21 , Figure 22A , Figure 22B , Figure 22C and Figure 22D Another advantage of the described electroless plating process includes greater flexibility in forming the work function layer 106. Since the gate electrode filler 112 is formed from bottom to top, the remaining portion of the second recess 98 around the work function layer 106 can be small, yet still achieve a void-free fill for the gate electrode filler 112. For example, the remaining width of the second recess 98 around the work function layer 106 (around the second nanostructure 54) can be approximately... Peace Treaty The specific values ​​depend on the design of the work function layer 106. Because the chemical plating process used can fill such a small opening with a high aspect ratio, the design of the work function layer 106 is very flexible, providing work function adjustment to achieve a variety of threshold voltages for gate functions.

[0089] Figure 24A , Figure 24B , Figure 24C and Figure 24D A view showing the formation of the gate electrode filler 112 after a chemical plating process for filling the remaining portion of the second recess 98.

[0090] Figure 25A , Figure 25B , Figure 25C and Figure 25DA view is shown of the gate dielectric layer 110, work function layer 106, adhesive layer 108, and gate electrode filler 112 in the p-type region 50P. (Using the above...) Figure 17A , Figure 17B , Figure 17C , Figures 17D to 24A , Figure 24B , Figure 24C and Figure 24D The processes discussed in the n-type region 50N are similar to those used in the p-type region 50P, where the aforementioned items are deposited in the second recess 98 and on and around the first nanostructure 52 (see [link to relevant documentation]). Figure 16A and Figure 16B ).

[0091] In some embodiments, the formation of the gate dielectric layer 110 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 110 in each region is formed of the same material; the formation of the work function layer 106 can occur simultaneously, such that the work function layer 106 is formed of the same material; the formation of the adhesive layer 108 can occur simultaneously, such that the adhesive layer 108 is formed of the same material; and the formation of the gate electrode filler 112 can occur simultaneously, such that the gate electrode filler 112 in each region is formed of the same material. In other embodiments, the gate dielectric layer 110 in each region can be formed using different processes, such that the gate dielectric layer 110 can be made of different materials and / or have different numbers of layers; the work function layer 106 in each region can be formed using different processes, such that the work function layer 106 can be made of different materials and / or have different numbers of layers; the adhesive layer 108 in each region can be formed using different processes, such that the adhesive layer 108 can be made of different materials and / or have different numbers of layers; and / or the gate electrode filler 112 in each region can be formed using different processes, such that the gate electrode filler 112 can be made of different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate regions. Any combination of layers comprising the work function layer 106 and the gate electrode filler 112 can be deposited between adjacent second nanostructures 54 and between the second nanostructure 54A and the substrate 50 in the n-type region 50N, and can be deposited between adjacent first nanostructures 52 in the p-type region 50P.

[0092] Figure 26A , Figure 26B , Figure 26C and Figure 26D A view is shown of the gate dielectric layer 110, work function layer 106, adhesive layer 108, and gate electrode filler 112 in the n-type region 50N. However, in Figure 26A , Figure 26B , Figure 26C and Figure 26D In the illustrated embodiment, the work function layer 106 is not merged between the second nanostructures 54 (e.g., between second nanostructure 54A and second nanostructure 54B). Thus, the second recess 98 includes a small gap between the adhesive layers 108 of one second nanostructure 54 and the other. The distance D1 between two adjacent adhesive layers 108 can be... Peace Treaty Between. Because the gate electrode filler 112 is used with the above-mentioned... Figure 21 , Figure 22A , Figure 22B , Figure 22C and Figure 22D The electroless plating process described allows the gaps between these adjacent adhesive layers 108 to be filled without creating voids between them. For example, since the promoter 132 is smaller and denser than the inhibitor 130, the promoter 132 will more easily enter the gaps between adjacent adhesive layers 108 surrounding the second nanostructure 54 than the inhibitor 130, thereby promoting the complete filling of the gaps by the gate electrode filler 112.

[0093] Figure 27A , Figure 27B , Figure 27C and Figure 27D A view is shown of the gate dielectric layer 110, work function layer 106, adhesive layer 108, and gate electrode filler 112 in the p-type region 50P. However, in Figure 27A , Figure 27B , Figure 27C and Figure 27D In the illustrated embodiment, the work function layer 106 is not merged between the first nanostructures 52 (e.g., between the first nanostructure 52A and the first nanostructure 52B), similar to Figure 26A , Figure 26B , Figure 26C and Figure 26D Regarding the second nanostructure 54, the second recess 98 includes a small gap between the adhesive layers 108 of one first nanostructure 52 and another first nanostructure 52. The distance D1 between two adjacent adhesive layers 108 can be... Peace Treaty Between. Since the gate electrode filler 112 uses the above reference... Figure 21 , Figure 22A , Figure 22B , Figure 22C and Figure 22DThe electroless plating process described herein allows the gaps between these adjacent adhesive layers 108 to be filled without creating voids between them. For example, since the promoter 132 is smaller and denser than the inhibitor 130, the promoter 132 will more easily enter the gaps between adjacent adhesive layers 108 surrounding the first nanostructure 52 than the inhibitor 130, thereby promoting complete filling of the gaps by the gate electrode filler 112.

[0094] Figure 28A and Figure 28B This illustrates the n-type region 50N and p-type region 50P following the deposition of the gate dielectric layer 110, work function layer 106, and gate electrode filler 112. Figure 16A and Figure 16B (In a similar view). It should be noted that, for simplicity, details relating to interface layer 102, dielectric layer 104, work function layer 106, and adhesive layer 108 have been omitted in the remaining figures. Instead, gate dielectric layer 110 and gate electrode filler 112 are shown as representing the additional layers previously described. Figure 28A and Figure 28B As shown, the deposition of the gate dielectric layer 110, the work function layer 106, and the gate electrode filler 112 can overfill the second recess 98 (see Figure 112). Figure 16A and Figure 16B ).

[0095] exist Figure 29A , Figure 29B and Figure 29C In the process of filling the second recess 98, a planarization process such as CMP can be performed to remove the material of the gate electrode filler 112 and excess portions of the gate dielectric layer 110 above the top surface of the first ILD 96. The remaining material of the gate electrode filler 112 and the gate dielectric layer 110 thus form the replacement gate structure of the resulting nanostructured FET. The gate electrode filler 112 and the gate dielectric layer 110 can be collectively referred to as the "gate structure".

[0096] The gate structure (including gate dielectric layer 110, work function layer 106, and corresponding overlying gate electrode filler 112) is recessed such that a recess is formed between the gate structure directly above and the opposite portion of the first spacer 81. A gate mask 114 comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled into the recess, and then a planarization process is performed to remove excess dielectric material extending over the first ILD 96. The subsequently formed gate contacts (e.g., referred to below) Figure 32A and Figure 32B The gate contact 124 discussed penetrates the gate mask 114 and contacts the top surface of the recessed gate electrode filler 112.

[0097] like Figures 29A-29C As further shown, the second ILD 116 is deposited over the first ILD 96 and the gate mask 114. In some embodiments, the second ILD 116 is a flowable film formed by FCVD. In some embodiments, the second ILD 116 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD, PECVD, etc.

[0098] exist Figures 30A-30C In this process, the second ILD 116, the first ILD 96, CESL 94, and the gate mask 114 are etched to form a third recess 118, which exposes the surface of the epitaxial source / drain region 92 and / or the gate structure. The third recess 118 can be formed by etching using an anisotropic etching process (e.g., RIE, NBE, etc.). In some embodiments, the third recess 118 can be etched through the second ILD 116 and the first ILD 96 using a first etching process; it can be etched through the gate mask 114 using a second etching process; and it can then be etched through the CESL 94 using a third etching process. A mask (e.g., photoresist) can be formed on and patterned over the second ILD 116 to mask portions of the second ILD 116 from the first and second etching processes. In some embodiments, the etching process may over-etch, so that the third recess 118 extends into the epitaxial source / drain region 92 and / or gate structure, and the bottom of the third recess 118 may be flush with (e.g., at the same level, or having the same distance from the substrate) or below (e.g., closer to the substrate) the epitaxial source / drain region 92 and / or gate structure. Although Figure 30BThe third recess 118 is shown as exposing the epitaxial source / drain region 92 and the gate structure in the same cross section. However, in various embodiments, the epitaxial source / drain region 92 and the gate structure may be exposed in different cross sections, thereby reducing the risk of short-circuiting subsequently formed contacts. After forming the third recess 118, a silicide region 120 is formed over the epitaxial source / drain region 92. In some embodiments, the silicide region 120 is formed by first depositing a metal (not shown) capable of reacting with the underlying semiconductor material (e.g., silicon, silicon-germanium, germanium) of the epitaxial source / drain region 92 to form a silicide region or a germanide region, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof, over the exposed portion of the epitaxial source / drain region 92, and then performing a thermal annealing process to form the silicide region 120. Unreacted portions of the deposited metal are then removed, for example, by an etching process. Although the silicide region 120 is referred to as a silicide region, the silicide region 120 may also be a germanide region, or a silicon-germanide region (e.g., a region comprising both silicide and germanide). In an embodiment, the silicide region 120 comprises TiSi and has a thickness in the range of about 2 nm to about 10 nm.

[0099] Next, in Figures 31A-31C In the third recess 118, contacts 122 and 124 (also referred to as contact plugs) are formed. Contacts 122 and 124 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, contacts 122 and 124 each include a barrier layer and a conductive material, and are electrically coupled to underlying conductive features (e.g., gate electrode filler 112 and / or silicide region 120 in the gate structure of the illustrated embodiment). Gate contact 124 is electrically coupled to gate electrode filler 112 and may be referred to as a gate contact, and contact 122 is electrically coupled to silicide region 120 and may be referred to as a source / drain contact. The barrier layer of contacts 122 / 124 may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material of contacts 122 / 124 may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 116.

[0100] Figures 32A-32C A cross-sectional view of a device according to some alternative embodiments is shown. Figure 32A It shows Figure 1 The reference section A-A' is shown. Figure 32B It shows Figure 1 The reference section B-B' is shown. Figure 32C It shows Figure 1 The reference section C-C' is shown. Figures 32A-32C In the figures, the same reference numerals indicate that they are connected by the same reference numerals. Figures 31A-31C The same components are formed using the same process and structure. However, in Figures 32A-32C In this configuration, the channel regions in the n-type region 50N and the p-type region 50P comprise the same material. For example, a second nanostructure 54 comprising silicon provides the channel region for the p-type nanostructure FET in the p-type region 50P and the n-type nanostructure FET in the n-type region 50N. Figures 32A-32C The structure can be formed by simultaneously removing the first nanostructure 52 from both the p-type region 50P and the n-type region 50N; depositing a gate dielectric layer 110 and a gate electrode 112P (e.g., a work function layer 106 and gate electrode filler 112 suitable for a p-type NSFET) around the second nanostructure 54 in the p-type region 50P; and depositing a gate dielectric layer 110 and a gate electrode 112N (e.g., a work function layer 106 and gate electrode filler 112 suitable for an n-type NSFET) around the second nanostructure 54 in the n-type region 50N. In such an embodiment, the material of the epitaxial source / drain region 92 in the n-type region 50N can be different from that in the p-type region 50P, as described above.

[0101] Figure 33 as well as Figures 34A-34E Various views of a gate replacement process for a FinFET device according to some embodiments are shown. Figure 33 An example of a FinFET according to some embodiments is shown in a three-dimensional view. The FinFET includes a fin 252 on a substrate 250 (e.g., a semiconductor substrate). Isolation regions 256 are disposed in the substrate 250, and the fin 252 protrudes from and above adjacent isolation regions 256. Although the isolation regions 256 are described / shown as being separated from the substrate 250, as used herein, the term "substrate" may be used to refer to a semiconductor substrate alone, or a semiconductor substrate including the isolation regions. Furthermore, although the fin 252 is shown as being of a single continuous material with the substrate 250, the fin 252 and / or the substrate 250 may comprise a single material or multiple materials. In this context, fin 252 refers to the portion extending between adjacent isolation regions 256.

[0102] A gate dielectric layer 292 runs along the sidewall of fin 252 and is above the top surface of fin 252, and a gate electrode 294 is above the gate dielectric layer 292. Source / drain regions 282 are disposed on opposite sides of fin 252 with respect to the gate dielectric layer 292 and the gate electrode 294. A cross-section GG runs along the longitudinal axis of fin 252 and in the direction of current flow between the source / drain regions 282 of a FinFET.

[0103] Figures 34A to 34E The gate replacement process for FinFET devices is illustrated. Figures 34A to 34E The view in is through Figure 33 These views are obtained from the GG cross-section. These views can be applied to n-type regions similar to the aforementioned n-type region 50N, or p-type regions similar to the aforementioned p-type region 50P. Gate replacement can be performed simultaneously in both regions, or through different processes, by employing various masks as described above.

[0104] exist Figure 34A In the process, a dummy gate is removed in one or more etching steps, thereby forming a recess 290 between the gate sealing spacer 280 and the gate spacer 286. In some embodiments, the dummy gate is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate while etching little or no of the surrounding first ILD (not shown) or gate spacer 286. Each recess 290 exposes and / or covers a channel region 258 of the corresponding fin 252. Each channel region 258 is disposed between adjacent pairs of epitaxial source / drain regions 282. During removal, the dummy dielectric layer may be used as an etch stop layer as the dummy gate is etched. The dummy dielectric layer may then be optionally removed after the dummy gate has been removed.

[0105] Next, layers 294A and 294B are formed for the gate dielectric layer 292 and the gate electrode 294 (see [link]). Figure 34D This is used to replace the gate. The gate dielectric layer 292 includes one or more layers deposited in the recess 290, for example, on the top surface and sidewalls of the fin 252 and on the sidewalls of the gate sealing spacer 280 / gate spacer 286. The gate dielectric layer 292 may also be formed on the top surface of the first ILD surrounding the gate spacer 286. In some embodiments, the gate dielectric layer 292 includes one or more dielectric layers, for example, one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, etc. For example, in some embodiments, the gate dielectric layer 292 includes an interface layer of silicon oxide formed by thermal oxidation or chemical oxidation, and an overlying high-k dielectric material, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The gate dielectric layer 292 may include a dielectric layer with a k value greater than about 7.0. Methods for forming the gate dielectric layer 292 may include molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments in which some portions of the dummy gate dielectric are retained in the recess 290, the gate dielectric layer 292 comprises the material of the dummy gate dielectric (e.g., SiO2).

[0106] The liner layer 294A and work function adjustment layer 294B of the gate electrode 294 are respectively deposited on the gate dielectric layer 292 and, together with the fill material 294C, fill the remaining portion of the recess 290. The gate electrode 294 may include a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, the gate electrode 294 may include any number of liner layers 294A, any number of work function adjustment layers 294B, and fill material 294C, such as… Figure 34D As shown.

[0107] After depositing the liner layer 294A and the work function adjustment layer 294B, use, for example, the above-mentioned Figure 21 , Figure 22A , Figure 22B , Figure 22C and Figure 22D The aforementioned materials and processes utilize a chemical plating process (i.e., an electrochemical plating process) to form the filler material 294C. Figure 34A In the process, the recess 290 is immersed in a plating solution, wherein the accelerator 132 and the inhibitor 130 are dispersed in a manner such that the concentration of the accelerator 132 at the bottom of the recess 290 is greater than the concentration on the sidewalls of the recess 290. Similarly, the inhibitor 130 is dispersed in a manner such that the concentration of the inhibitor 130 on the sidewalls of the recess 290 is greater than the concentration at the bottom of the recess 290.

[0108] exist Figure 34B In the process, filler material 294C begins to fill recess 290. Since the concentration of accelerator 132 is higher at the bottom of recess 290, filler material 294C is deposited in a manner that causes the bottom of recess 290 to be filled with filler material 294C faster than the sidewalls of recess 290, thereby forming a seamless and void-free filler.

[0109] exist Figure 34C In the process, the electrochemical plating process continues to fill the recess 290 in a bottom-up manner. Figure 34D In the process, the electrochemical plating process continues to fill the recess 290 until the filling material 294C overfills the recess 290.

[0110] exist Figure 34DIn the process of filling the recess 290, a planarization process such as CMP can be performed to remove excess material from the gate electrode 294 and the gate dielectric layer 292 above the top surface of the ILD surrounding the gate spacer 286. The remaining material from the gate electrode 294 and the gate dielectric layer 292 thus form the replacement gate of the resulting FinFET. The gate electrode 294 and the gate dielectric layer 292 can be collectively referred to as the “gate stack”. The gate and the gate stack can extend along the sidewalls of the channel region 258 of the fin 252.

[0111] The embodiments advantageously employ a gate replacement process for nanostructured FETs or FinFETs, utilizing electroless plating to achieve bottom-up filling. Electroless plating enables the replacement gate to be filled while reducing voids and eliminating seams in the filler of the gate electrode of the nanostructured FET. Promoters and inhibitors can be added to the plating bath to suppress sidewall deposition of the gate electrode material while promoting bottom deposition, thereby enabling electrode material to be deposited in small openings and around the nanostructures forming the channels of the nanostructured FET.

[0112] One embodiment is a method including etching a dummy gate of a transistor to remove the dummy gate and form a first opening. The method further includes etching to remove a first nanostructure and extend the first opening to expose a second nanostructure of the transistor. The method further includes depositing a first dielectric layer in the first opening, the first dielectric layer surrounding the second nanostructure. The method further includes depositing a first work function layer in the first opening, the first work function layer surrounding the second nanostructure and the first dielectric layer. The method further includes depositing an adhesive layer in the first opening, the adhesive layer surrounding the second nanostructure. The method further includes immersing the first opening in an electrochemical plating solution to plate metal into the first opening, the metal filling the first opening. In one embodiment, the electrochemical plating solution includes metal ions or metal salts, a reducing agent, an inhibitor, and a promoter. In one embodiment, during metal plating, the promoter is more densely distributed at the bottom of the first opening than at the sidewalls of the first opening, and the inhibitor is more densely distributed at the sidewalls of the first opening than at the bottom of the first opening. In one embodiment, the method may include: planarizing a metal, an adhesive layer, a first work function metal, and a first dielectric layer such that the upper surfaces of the metal, the adhesive layer, the first work function metal, and the first dielectric layer are flush with each other. In one embodiment, the method may include: depositing an interface layer in the first opening, the interface layer surrounding the second nanostructure, before depositing the first dielectric layer in the first opening. In one embodiment, depositing the metal includes: depositing the metal using a bottom-up process. In one embodiment, depositing the metal includes: filling spaces vertically between the second nanostructures. In one embodiment, a first work function layer surrounding a first second nanostructure in the second nanostructure is merged with a first work function layer surrounding a second second nanostructure in the second nanostructure.

[0113] Another embodiment is a method comprising growing an epitaxial source / drain region in a fin recess located on either side of a gate. The method further includes performing a replacement gate process comprising removing a dummy gate structure between two gate spacers of the gate to form an opening between the two gate spacers. The method further includes depositing a first gate dielectric layer in the opening, the first gate dielectric layer covering a channel region of the gate. The method further includes depositing a work function layer in the opening, the work function layer covering the first gate dielectric layer. The method further includes plating a conductive filler in the opening by a chemical plating process, the chemical plating process plating the conductive filler at the bottom of the opening at a plating rate 10 to 25 times that at the sidewalls of the opening. In one embodiment, plating may include immersing the opening in a plating bath comprising metal ions and a reducing agent. In one embodiment, the plating bath may include a promoter and an inhibitor, the promoter to inhibitor ratio being between 10:1 and 100:1 at the bottom of the opening. In one embodiment, the total weight ratio of promoter to inhibitor in the plating bath is between 1:5 and 5:1. In one embodiment, the method may include planarizing the gate so that the upper surfaces of the first gate dielectric layer, the work function layer, and the conductive filler are flush with each other. In one embodiment, the work function layer fills the space between the two nanostructures in the channel region.

[0114] Another embodiment is a method comprising forming a first nanostructured field-effect transistor (nano-FET) gate structure, the formation comprising: forming a plurality of nanostructured channel regions; depositing a gate dielectric layer surrounding the plurality of nanostructured channel regions; depositing a gate work function layer surrounding the gate dielectric layer; and depositing a gate filler surrounding the gate work function layer and the gate, the gate filler deposition comprising: providing a plating solution in an opening corresponding to the gate filler; providing a promoter and an inhibitor in the plating solution; and reducing a metal from the plating solution to deposit the metal at the bottom of the opening. The method further comprises forming a first epitaxial source / drain region and a second epitaxial source / drain region disposed on either side of the first nano-FET gate structure, wherein the plurality of nanostructured channel regions extend from the first source / drain region to the second source / drain region. In one embodiment, the gate filler comprises oxidation of an inhibitor or oxidation of a promoter, and the gate filler is fluorine-free. In one embodiment, the gate filler comprises an oxide of a metal or a byproduct of a reducing agent. In one embodiment, the metal comprises tungsten, cobalt, or nickel. In one embodiment, in a cross-section passing through the first epitaxial source / drain region and the second epitaxial source / drain region, the height-to-width ratio of the gate filler is between 10:1 and 20:1. In one embodiment, the gate work function layer includes a p-metal work function adjustment layer.

[0115] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0116] Example

[0117] Example 1. A method for forming a semiconductor device, comprising: etching a dummy gate of a transistor to remove the dummy gate and form a first opening; etching to remove a first nanostructure and extend the first opening to expose a second nanostructure of the transistor; depositing a first dielectric layer in the first opening, the first dielectric layer surrounding the second nanostructure; depositing a first work function layer in the first opening, the first work function layer surrounding the second nanostructure and the first dielectric layer; depositing an adhesive layer in the first opening, the adhesive layer surrounding the second nanostructure; and immersing the first opening in an electrochemical plating solution to plate metal into the first opening, the metal filling the first opening.

[0118] Example 2. The method according to Example 1, wherein the electrochemical plating solution comprises metal ions or metal salts, reducing agents, inhibitors, and accelerators.

[0119] Example 3. The method according to Example 2, wherein, during the plating of the metal, the promoter is more densely distributed at the bottom of the first opening than at the sidewall of the first opening, and wherein, during the plating of the metal, the inhibitor is more densely distributed at the sidewall of the first opening than at the bottom of the first opening.

[0120] Example 4. The method according to Example 1 further includes: planarizing the metal, the adhesive layer, the first work function metal and the first dielectric layer so that the upper surfaces of the metal, the adhesive layer, the first work function metal and the first dielectric layer are flush with each other.

[0121] Example 5. The method according to Example 1 further includes: depositing an interface layer in the first opening, the interface layer surrounding the second nanostructure, prior to depositing the first dielectric layer in the first opening.

[0122] Example 6. The method according to Example 1, wherein plating the metal comprises: depositing the metal using a bottom-up process.

[0123] Example 7. The method according to Example 1, wherein coating the metal comprises: filling the space vertically between the second nanostructures.

[0124] Example 8. The method according to Example 1, wherein the first work function layer surrounding the first second nanostructure in the second nanostructure is merged with the first work function layer surrounding the second second nanostructure in the second nanostructure.

[0125] Example 9. A method for forming a semiconductor device, comprising: growing an epitaxial source / drain region in a fin recess located on either side of a gate; performing a gate replacement process, the gate replacement process comprising: removing a dummy gate structure between two gate spacers of the gate to form an opening between the two gate spacers; depositing a first gate dielectric layer in the opening, the first gate dielectric layer covering a channel region of the gate; depositing a work function layer in the opening, the work function layer covering the first gate dielectric layer; and depositing a conductive filler in the opening by a chemical plating process, the chemical plating process depositing the conductive filler at the bottom of the opening at a plating rate 10 to 25 times that at the sidewalls of the opening.

[0126] Example 10. The method according to Example 9, wherein the plating comprises: immersing the opening in a plating solution comprising metal ions and a reducing agent.

[0127] Example 11. The method according to Example 10, wherein the plating solution further includes an accelerator and an inhibitor, and at the bottom of the opening, the ratio of the accelerator to the inhibitor is between 10:1 and 100:1.

[0128] Example 12. The method according to Example 11, wherein the total weight ratio of the accelerator to the inhibitor in the plating solution is 1:5 to 5:1.

[0129] Example 13. The method according to Example 9 further includes: planarizing the gate so that the upper surfaces of the first gate dielectric layer, the work function layer and the conductive filler are flush with each other.

[0130] Example 14. The method according to Example 9, wherein the work function layer fills the space between the two nanostructures in the channel region.

[0131] Example 15. A method for forming a semiconductor device, comprising: forming a first nanostructure field-effect transistor gate structure, the forming comprising: forming a plurality of nanostructure channel regions; depositing a gate dielectric layer around the plurality of nanostructure channel regions; depositing a gate work function layer around the gate dielectric layer; and depositing a gate filler around the gate work function layer and the gate, the gate filler deposition comprising: providing a plating solution in an opening corresponding to the gate filler; providing a promoter and an inhibitor in the plating solution; and reducing a metal from the plating solution to deposit the metal at the bottom of the opening; and forming a first epitaxial source / drain region and a second epitaxial source / drain region disposed on either side of the first nanostructure field-effect transistor gate structure, wherein the plurality of nanostructure channel regions extend from the first source / drain region to the second source / drain region.

[0132] Example 16. The method according to Example 15, wherein the gate filler comprises oxidation of the inhibitor or oxidation of the promoter, and wherein the gate filler is fluorine-free.

[0133] Example 17. The method according to Example 15, wherein the gate filler comprises an oxide of the metal or a byproduct of a reducing agent.

[0134] Example 18. The method according to Example 15, wherein the metal comprises tungsten, cobalt, or nickel.

[0135] Example 19. The method according to Example 15, wherein, in a cross section passing through the first epitaxial source / drain region and the second epitaxial source / drain region, the height-to-width ratio of the gate filler is between 10:1 and 20:1.

[0136] Example 20. The method according to Example 15, wherein the gate work function layer includes a p-metal work function adjustment layer.

Claims

1. A method for forming a semiconductor device, comprising: The dummy gate of the transistor is etched to remove the dummy gate and form a first opening; Etching is performed to remove the first nanostructure and extend the first opening, thereby exposing the second nanostructure of the transistor; A first dielectric layer is deposited in the first opening, the first dielectric layer surrounding the second nanostructure; A first work function layer is deposited in the first opening, the first work function layer surrounding the second nanostructure and the first dielectric layer; An adhesive layer is deposited in the first opening, the adhesive layer surrounding the second nanostructure; as well as The first opening is immersed in an electrochemical plating solution to plate metal into the first opening, the metal filling the first opening, wherein the electrochemical plating solution includes an accelerator, and wherein, during the plating of the metal, the accelerator is more densely distributed at the bottom of the first opening than at the sidewalls of the first opening.

2. The method according to claim 1, wherein, The electrochemical plating solution also includes metal ions or metal salts, reducing agents, and inhibitors.

3. The method according to claim 2, wherein, During the metal plating process, the inhibitor is distributed more densely on the sidewalls of the first opening than on the bottom of the first opening.

4. The method according to claim 1, further comprising: The metal, the adhesive layer, the first work function layer, and the first dielectric layer are planarized so that the upper surfaces of the metal, the adhesive layer, the first work function layer, and the first dielectric layer are flush with each other.

5. The method according to claim 1, further comprising: Before depositing the first dielectric layer in the first opening, an interface layer is deposited in the first opening, the interface layer surrounding the second nanostructure.

6. The method according to claim 1, wherein, The metal being plated includes: The metal is deposited using a bottom-up process.

7. The method according to claim 1, wherein, The metal being plated includes: It fills the space vertically between the second nanostructures.

8. The method according to claim 1, wherein, The first work function layer surrounding the first second nanostructure in the second nanostructure merges with the first work function layer surrounding the second second nanostructure in the second nanostructure.

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