Wafer-level packaging structure and preparation method

Abstract

The present invention provides a wafer-level packaging structure and preparation method. The wafer-level packaging structure includes a wafer with TSVs, a first rewiring layer, a second rewiring layer, a bonding pad, a chip, a protective layer, and a packaging layer. The wafer with TSVs and the first and second rewiring layers located on opposite sides of the wafer form a wafer-level packaging structure with high three-dimensional stacking density and small dimensions. This reduces the manufacturing difficulty of a single RDL, thereby reducing process complexity and production costs. Interconnection through TSVs allows for good conductivity between the top and bottom surfaces of the wafer with TSVs, significantly increasing chip speed and reducing power consumption, resulting in a wafer-level packaging structure with excellent electrical and thermal performance and high-efficiency transmission performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to a wafer-level packaging structure and a preparation method thereof. Background Art

[0002] As integrated circuits become more powerful, perform higher and more integrated, and new types of integrated circuits emerge, packaging technology plays an increasingly important role in integrated circuit products and accounts for an increasingly larger proportion of the value of the entire electronic system.

[0003] Wafer-level packaging (WLP) technology has become an important packaging method for high-demand electronic devices such as mobile / wireless networks due to its advantages of miniaturization, low cost, high integration, better performance and higher energy efficiency. It is currently one of the most promising packaging technologies.

[0004] In wafer-level packaging technology, the redistribution layer (RDL) can rearrange the solder pad locations of the chip, allowing the new solder pads to meet the minimum solder ball spacing requirements and be arranged in an array. However, for high-I / O chip packaging structures, multiple layers of stacked metal wires are required in the RDL. Within a limited form factor and package size, smaller RDL metal wire widths and spacing translate to more power rails. However, the manufacturing of RDL metal wires is the most expensive part of the entire WLP process, requiring numerous process steps and complex manufacturing processes. Consequently, the manufacturing process difficulty and development costs for highly integrated RDLs are increasing.

[0005] Therefore, it is necessary to provide a novel wafer-level packaging structure and preparation method. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a wafer-level packaging structure and preparation method, which is used to solve the problems of multiple process steps, high process difficulty and high production cost caused by the preparation of highly integrated RDL in wafer-level packaging technology to improve the power supply track of RDL.

[0007] To achieve the above-mentioned and other related objectives, the present invention provides a wafer-level packaging structure, comprising:

[0008] A wafer comprising a first surface and a second surface opposite to each other, and comprising a plurality of TSVs, wherein the first surface of the wafer exposes first ends of the TSVs, and the second surface of the wafer exposes second ends of the TSVs;

[0009] a first redistribution layer, the first redistribution layer being located on a first surface of the wafer and electrically connected to a first end of the TSV;

[0010] a second redistribution layer, the second redistribution layer being located on the second surface of the wafer and electrically connected to the second end of the TSV;

[0011] a bonding pad, the bonding pad being located on the second redistribution layer and electrically connected to the second redistribution layer;

[0012] a chip, the chip being located on the second redistribution layer and electrically connected to the bonding pad via a chip pad;

[0013] a protection layer, the protection layer being located between the chip and the second redistribution layer and filling a gap between the chip and the second redistribution layer;

[0014] The packaging layer is located on the second redistribution layer and covers the chip and the second redistribution layer.

[0015] Optionally, the TSV includes one of a copper TSV, a nickel TSV, a tin TSV, and a silver TSV.

[0016] Optionally, the encapsulation layer includes one of an epoxy resin layer, a polyimide layer and a silicone layer.

[0017] Optionally, the protective layer includes one of an epoxy resin layer, a polyimide layer and a silicone layer.

[0018] Optionally, the first rewiring layer and the second rewiring layer both include a patterned dielectric layer and a patterned metal wiring layer stacked in sequence, wherein the dielectric layer includes one or a combination of an epoxy resin layer, a silicone layer, a PI layer, a PBO layer, a BCB layer, a silicon oxide layer, a phosphosilicate glass layer and a fluorine-containing glass layer, and the metal wiring layer includes one or a combination of a copper layer, an aluminum layer, a nickel layer, a gold layer, a silver layer and a titanium layer.

[0019] Optionally, the chip includes one or a combination of active components and passive components, the active components include one or a combination of a transceiver chip and a power management chip, and the passive components include one or a combination of resistors, capacitors and inductors.

[0020] The present invention also provides a method for preparing a wafer-level packaging structure, comprising the following steps:

[0021] Providing a wafer, wherein the wafer includes a first side and a second side opposite to each other, and the wafer includes a plurality of TSVs;

[0022] forming a first redistribution layer, wherein the first redistribution layer covers the first surface of the wafer and is electrically connected to the first end of the TSV;

[0023] providing a supporting substrate, and bonding the first rewiring layer to the supporting substrate via a separation layer;

[0024] thinning the wafer to expose the second end of the TSV;

[0025] forming a second redistribution layer, wherein the second redistribution layer covers the second surface of the wafer and is electrically connected to the second end of the TSV;

[0026] forming a bonding pad, the bonding pad being located on the second redistribution layer and electrically connected to the second redistribution layer;

[0027] Providing a chip, wherein the chip is located on the second redistribution layer, and the chip is electrically connected to the bonding pad via a chip pad;

[0028] forming a protection layer, wherein the protection layer is located between the chip and the second redistribution layer and fills a gap between the chip and the second redistribution layer;

[0029] forming a packaging layer, wherein the packaging layer is located on the second redistribution layer and covers the chip and the second redistribution layer;

[0030] The separation layer and the supporting substrate are removed to expose the first redistribution layer.

[0031] Optionally, the supporting substrate includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate.

[0032] Optionally, the separation layer comprises one of an adhesive tape and a polymer layer.

[0033] Optionally, the method for forming the encapsulation layer includes one of compression molding, transfer molding, liquid sealing molding, vacuum lamination and spin coating; and before removing the separation layer and the supporting substrate, it also includes a step of thinning the encapsulation layer.

[0034] As described above, the wafer-level packaging structure and preparation method of the present invention can form a wafer-level packaging structure with high three-dimensional stacking density and small external dimensions through a wafer with TSV and a first rewiring layer and a second rewiring layer located on opposite sides of the wafer, and can reduce the manufacturing difficulty of a single RDL, thereby reducing process complexity and production costs; interconnection through TSV can make the upper and lower surfaces of the wafer with TSV well conductive, thereby greatly improving the speed of the chip and reducing power consumption, so as to form a wafer-level packaging structure with good electrothermal performance and high-efficiency transmission performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Shown is a schematic diagram of the process flow for preparing a wafer-level packaging structure in the present invention.

[0036] Figures 2 to 9 Shown is a schematic structural diagram of each step of preparing a wafer-level packaging structure in the present invention.

[0037] Component number description

[0038] 100 wafers

[0039] 200 TSV

[0040] 300 First Rewiring Layer

[0041] 400 separation layer

[0042] 500 support base

[0043] 600 Second rewiring layer

[0044] 700 Bond Pad

[0045] 800 chip pads

[0046] 900 chips

[0047] 110 protective layer

[0048] 120 encapsulation layer DETAILED DESCRIPTION

[0049] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0050] See also Figures 1 to 9 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0051] See Figure 9The present invention provides a wafer-level packaging structure, which includes: a wafer 100 having TSVs 200, a first redistribution layer 300, a second redistribution layer 600, a bonding pad 700, a chip 900, a protective layer 110, and a packaging layer 120. The wafer 100 includes a first surface and a second surface opposite to each other, the first surface of the wafer 100 exposes the first end of the TSVs 200, and the second surface of the wafer 100 exposes the second end of the TSVs 200; the first redistribution layer 300 is located on the first surface of the wafer 100 and is electrically connected to the first end of the TSVs 200; the second redistribution layer 600 is located on the second surface of the wafer 100 and is electrically connected to the second end of the TSVs 200; the bonding pad 700 is located on the second redistribution layer 300. 600 and is electrically connected to the second rewiring layer 600; the chip 900 is located on the second rewiring layer 600, and the chip 900 is electrically connected to the bonding pad 700 through the chip pad 800; the protective layer 800 is located between the chip 900 and the second rewiring layer 600, and fills the gap between the chip 900 and the second rewiring layer 600; the packaging layer 120 is located on the second rewiring layer 600, and covers the chip 900 and the second rewiring layer 600.

[0052] In this embodiment, the wafer 100 having the TSVs 200 and the first and second redistribution layers 300 and 600 located on opposite sides of the wafer 100 can form a wafer-level packaging structure with high three-dimensional stacking density and small dimensions. Because the TSVs 200 are used for interconnection in this embodiment, when the chip 900 is electrically led out, a multi-layer structure can be interconnected through the first redistribution layer 300, TSVs 200, and second redistribution layer 600, thereby reducing the manufacturing difficulty of a single RDL, reducing process complexity and production costs. Furthermore, interconnection through the TSVs 200 allows for good electrical conductivity between the top and bottom surfaces of the wafer 100 having the TSVs, thereby significantly improving the speed of the chip 900 and reducing power consumption, thereby forming a wafer-level packaging structure with good electrical and thermal performance and high-efficiency transmission performance.

[0053] As an example, the TSV 200 includes one of a copper TSV, a nickel TSV, a tin TSV, and a silver TSV.

[0054] As an example, the encapsulation layer 120 includes one of an epoxy resin layer, a polyimide layer, and a silicone layer; the protection layer 110 includes one of an epoxy resin layer, a polyimide layer, and a silicone layer.

[0055] As an example, the first rewiring layer 300 and the second rewiring layer 600 both include a patterned dielectric layer and a patterned metal wiring layer stacked in sequence, wherein the dielectric layer includes one or a combination of an epoxy resin layer, a silicone layer, a PI layer, a PBO layer, a BCB layer, a silicon oxide layer, a phosphosilicate glass layer and a fluorine-containing glass layer, and the metal wiring layer includes one or a combination of a copper layer, an aluminum layer, a nickel layer, a gold layer, a silver layer and a titanium layer.

[0056] As an example, the chip 900 includes one or a combination of active components and passive components, the active components include one or a combination of a transceiver chip and a power management chip, and the passive components include one or a combination of resistors, capacitors and inductors.

[0057] See Figure 1 This embodiment also provides a method for preparing a wafer-level packaging structure. This method can be used to form the above-mentioned wafer-level packaging structure, but the method for preparing the wafer-level packaging structure is not limited thereto. For a specific preparation process, please refer to Figures 2 to 9 .

[0058] First, see Figure 2 , a wafer 100 is provided. The wafer 100 includes a first surface and a second surface opposite to each other, and the wafer 100 includes a plurality of TSVs 200 .

[0059] Specifically, the material of the TSVs 200 can be one of copper, nickel, tin, and silver, but is not limited thereto. To reduce process complexity, the wafer 100 having the TSVs 200 can be directly purchased as an intermediate connection structure, but is not limited thereto. The wafer 100 can also be etched and deposited on a silicon substrate to form the TSVs 200. The size, morphology, and number of the TSVs 200 can be selected and designed based on specific needs.

[0060] Next, the first redistribution layer 300 is formed on the first surface of the wafer 100 . The first redistribution layer 300 covers the first surface of the wafer 100 and is electrically connected to the first end of the TSV 200 .

[0061] Specifically, a portion of the wafer 100 may be removed by CMP to expose the first end of the TSV 200 and provide a flat surface to facilitate the formation of a high-quality first redistribution layer 300. The formation of the first redistribution layer 300 may include the following steps:

[0062] A dielectric layer is formed on the wafer 100 by using a physical vapor deposition process or a chemical vapor deposition process, and the dielectric layer is etched to form a patterned dielectric layer;

[0063] A metal wiring layer is formed on the patterned dielectric layer by adopting a physical vapor deposition process, a chemical vapor deposition process, an evaporation process, a sputtering process, an electroplating process or an electroless plating process, and the metal wiring layer is etched to form a patterned metal wiring layer.

[0064] In the first redistribution layer 300, the dielectric layer and the metal wiring layer can each be a single layer or multiple layers. The dielectric layer can be made of one or a combination of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass. The metal wiring layer can be made of one or a combination of copper, aluminum, nickel, gold, silver, and titanium. The thickness of the first redistribution layer 300 can range from 10 μm to 20 μm. The number of layers, material, thickness, and distribution of the first redistribution layer 300 can be selected based on specific needs and are not excessively limited herein.

[0065] Next, see Figure 3 , providing a supporting substrate 500 , and bonding the first rewiring layer 300 to the supporting substrate 500 through a separation layer 400 .

[0066] As an example, the supporting substrate 500 may include one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate; and the separation layer 400 may include one of an adhesive tape and a polymer layer.

[0067] Specifically, the support base 500 can provide support for subsequent processes to reduce the risk of deformation and fragmentation. The thickness of the support base 500 can be millimeter-level, such as 1 mm, 2 mm, etc., and can be selected according to specific needs. In order to further reduce damage, improve product quality and improve operational convenience, the separation layer 400 is preferably first formed on the supporting substrate 500. In this embodiment, the supporting substrate 500 is preferably a glass substrate, and the separation layer 400 is preferably a polymer layer, such as an LTHC light-to-heat conversion layer, wherein the LTHC light-to-heat conversion layer can be coated on the surface of the supporting substrate 500 by a spin coating process, and then cured and formed by an ultraviolet curing or thermal curing process. In the subsequent separation process, the LTHC light-to-heat conversion layer can be heated based on a laser to separate the supporting substrate 500 from the LTHC light-to-heat conversion layer, so as to provide operational convenience and reduce damage to the wafer-level packaging structure. However, the selection of materials for the supporting substrate 500 and the separation layer 400 is not limited to this, and the selection of specific materials and the formation method are not overly restricted here.

[0068] Next, see Figure 4 , thinning the wafer 100 to expose the second end of the TSV 200 .

[0069] Specifically, the method for thinning the wafer 100 may adopt a CMP method in order to provide a flat surface, but is not limited thereto, and an etching method may also be adopted. By thinning, the second end of the TSV 200 may be exposed, and the thickness of the wafer-level packaging structure formed subsequently may be further reduced by thinning. In this embodiment, due to the supporting function of the supporting substrate 500, damage to the wafer 100 may be reduced during the thinning process, and since the thinning process is performed before the chip 900 is formed, damage to the chip 900 may be avoided during the thinning process of the wafer 100, thereby improving the quality of the wafer-level packaging structure finally formed. Among them, the height range of the TSV 200 after thinning is preferably 500μm to 800μm, such as 600μm, 750μm, etc. The specific thickness of the TSV 200 may be selected as needed, and no excessive restrictions are imposed here.

[0070] Next, see Figure 5 , forming a second redistribution layer 600. The second redistribution layer 600 covers the second surface of the wafer 100 and is electrically connected to the second end of the TSV 200. The material, preparation method, structure, and distribution of the second redistribution layer 600 can be found in the first redistribution layer 300 and are not further described here.

[0071] Specifically, the wafer 100 having the TSVs 200 and the first redistribution layer 300 and the second redistribution layer 600 located on opposite sides of the wafer 100 can form a wafer-level packaging structure with high three-dimensional stacking density and small dimensions. The TSVs 200 can transform a single RDL into a multi-layer structure interconnected by the first redistribution layer 300, TSVs 200, and the second redistribution layer 600, thereby reducing the manufacturing difficulty of a single RDL, reducing process complexity and production costs. Furthermore, the interconnection through the TSVs 200 can ensure good conductivity between the top and bottom surfaces of the wafer 100 having the TSVs, thereby greatly improving the speed of the chip 900 and reducing power consumption, thereby forming a wafer-level packaging structure with good electrical and thermal performance and high-efficiency transmission performance.

[0072] Next, a bonding pad 700 is formed, which is located on the second redistribution layer 600 and electrically connected to the second redistribution layer 600. The bonding pad 700 can be made of one or a combination of tin, silver, gold, and copper, and the specific preparation process is not limited here.

[0073] Next, see Figure 6, providing a chip 900 , wherein the chip 900 is located on the second redistribution layer 600 , and the chip 900 is electrically connected to the bonding pad 700 through a chip pad 800 .

[0074] Specifically, the chip pad 800 and the bonding pad 700 can be connected by a reflow soldering process, but are not limited thereto. For example, a conductive adhesive can also be used for curing connection. The chip 900 can include one or a combination of active components and passive components. For example, the active component can include one or a combination of a transceiver chip and a power management chip, and the passive component can include one or a combination of a resistor, a capacitor, and an inductor. However, the type, number, and distribution of the chips can be selected as needed and are not excessively limited here.

[0075] Next, a protection layer 110 is formed. The protection layer 110 is located between the chip 900 and the second re-distribution layer 600 , and the protection layer 110 fills the gap between the chip 900 and the second re-distribution layer 600 .

[0076] Specifically, the protective layer 110 may be made of one of epoxy resin, polyimide, and silicone. The protective layer 110 may be formed in the gap between the chip 900 and the second redistribution layer 600 by dispensing or molding. The protective layer 110 can effectively protect the chip 900, for example, preventing moisture from entering the chip 900 and the second redistribution layer 600. The protective layer 110 can also serve as a buffer structure to further improve the stability of the wafer-level packaging structure, such as preventing damage caused by impact.

[0077] Next, see Figure 7 , forming a packaging layer 120 , wherein the packaging layer 120 is located on the second redistribution layer 600 and covers the chip 900 and the second redistribution layer 600 .

[0078] Specifically, the material of the encapsulation layer 120 may include one of epoxy resin, polyimide and silicone, and the method of forming the encapsulation layer 120 may include one of compression molding, transfer molding, liquid sealing molding, vacuum lamination and spin coating. Figure 8 After forming the packaging layer 120, a step of thinning the packaging layer 120 may also be included, such as using a CMP method to act on the surface of the packaging layer 120 to provide a flat packaging layer 120, so as to further reduce the thickness of the wafer-level packaging structure formed subsequently.

[0079] Next, see Figure 9 , the separation layer 400 and the supporting substrate 500 are removed to expose the first rewiring layer 300 .

[0080] Specifically, since in this embodiment, the separation layer 400 adopts the LTHC light-to-heat conversion layer, the LTHC light-to-heat conversion layer can be heated based on a laser to separate the supporting substrate 500 from the LTHC light-to-heat conversion layer to expose the first rewiring layer 300, so that the prepared wafer-level packaging structure can be electrically connected to a substrate or other chips, wafers, etc. based on the first rewiring layer 300.

[0081] In summary, the wafer-level packaging structure and preparation method of the present invention can form a wafer-level packaging structure with high three-dimensional stacking density and small external dimensions through a wafer with TSV and a first rewiring layer and a second rewiring layer located on opposite sides of the wafer, and can reduce the manufacturing difficulty of a single RDL, thereby reducing process complexity and production costs; interconnection through TSV can make the upper and lower surfaces of the wafer with TSV well conductive, thereby greatly improving the speed of the chip and reducing power consumption, so as to form a wafer-level packaging structure with good electrothermal performance and high-efficiency transmission performance.

[0082] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for preparing a wafer-level packaging structure, characterized in that: The following steps are involved: Providing a wafer, wherein the wafer includes a first side and a second side opposite to each other, and the wafer includes a plurality of TSVs; forming a first redistribution layer, wherein the first redistribution layer covers the first surface of the wafer and is electrically connected to the first end of the TSV; Providing a supporting substrate, bonding the first rewiring layer to the supporting substrate via a separation layer, wherein the separation layer includes an LTHC light-to-heat conversion layer; thinning the wafer to expose the second end of the TSV; forming a second redistribution layer, wherein the second redistribution layer covers the second surface of the wafer and is electrically connected to the second end of the TSV; forming a bonding pad, the bonding pad being located on the second redistribution layer and electrically connected to the second redistribution layer; Providing a chip, wherein the chip is located on the second redistribution layer, and the chip is electrically connected to the bonding pad via a chip pad; forming a protection layer, wherein the protection layer is located between the chip and the second redistribution layer and fills a gap between the chip and the second redistribution layer; forming a packaging layer, wherein the packaging layer is located on the second redistribution layer and covers the chip and the second redistribution layer; The separation layer and the supporting substrate are removed to expose the first redistribution layer.

2. The method for preparing a wafer-level packaging structure according to claim 1, wherein: The supporting substrate includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate.

3. The method for preparing a wafer-level packaging structure according to claim 1, wherein: The separation layer includes one of an adhesive tape and a polymer layer.

4. The method for preparing a wafer-level packaging structure according to claim 1, wherein: The method for forming the encapsulation layer includes one of compression molding, transfer molding, liquid sealing molding, vacuum lamination and spin coating; before removing the separation layer and the supporting substrate, it also includes a step of thinning the encapsulation layer.

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