Semiconductor device and method for manufacturing semiconductor device

Abstract

The object of the present invention is to provide a semiconductor device with built-in buffer circuit that can miniaturize a power conversion circuit assembled with a semiconductor device and can be flexibly applied to various electrical devices. The semiconductor device 100 involved in the present invention includes: a semiconductor substrate 110; a source electrode 120; a drain electrode 130; a plurality of grooves 140; a first electrode 150, which is arranged in the grooves through a gate insulating film 172 formed on the side walls of the plurality of grooves 140; a second electrode 160, which is formed above the first electrode 150 in a state separated from the first electrode 150; a first insulating region 170; and a second insulating region 174, wherein the grooves 140, the first electrode 150 and the second electrode 160 are formed in a stripe shape from a plane view, and at least any one of the plurality of second electrodes 160 is connected to the drain electrode 130.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] Conventionally, a trench gate semiconductor device is known (for example, refer to Patent Document 1).

[0003] The semiconductor device 900 described in Patent Document 1 is a trench gate type semiconductor device. Fig. 22 As shown, it includes: a semiconductor substrate 910 having an n-type drift layer 912, a p-type base region 913 formed on the surface of the drift layer 912, and an n-type source region 914 formed on the surface of the base region 913; a source electrode 920 formed on one surface side of the semiconductor substrate 910; a drain electrode (not shown) formed on the other surface side of the semiconductor substrate 910; a plurality of trenches 940 formed on one surface of the semiconductor substrate 910 and having a bottom 942 adjacent to the drift layer 912, and side walls 944 adjacent to the drift layer 912, the base region 913 and the source region 914; and a gate electrode 950, which is arranged in the trench 940 via a gate insulating film 972 formed on the side walls 944 of the plurality of trenches 940, and whose side faces are opposite to the base region 913.

[0004] Conventionally, it is also known that when the semiconductor device 900 described above is incorporated into a power conversion circuit, a snubber circuit must be separately provided to absorb switching noise (for a conventional power conversion circuit, see, for example, Patent Document 2).

[0005] In the power conversion circuit 9 described in Patent Document 2, as Fig.23 As shown, a half-bridge circuit is formed by connecting two switching elements (semiconductor devices) in series, and a snubber circuit in which a resistor and a capacitor are connected in series is connected in parallel to each switching element.

[0006] Prior art literature

[0007] [Patent Document 1] Specification of U.S. Patent No. 6429481

[0008] [Patent Document 2] International Publication No. 2018 / 012122

[0009] However, when a snubber circuit is separately mounted when a semiconductor device is incorporated into a power conversion circuit, it is necessary to ensure an area for mounting the snubber circuit, which makes it difficult to miniaturize the power conversion circuit and, in turn, the electric device.

[0010] In addition, although it is conceivable to adopt a semiconductor device with a built-in snubber circuit in which a snubber circuit is incorporated into the semiconductor device, in this case, it is necessary to design and manufacture a semiconductor device in which the snubber capacitor of the snubber circuit is changed according to the electrical device, so it is difficult to make a semiconductor device with a built-in snubber circuit that can be flexibly applied to various electrical devices.

[0011] In view of the above problems, an object of the present invention is to provide a semiconductor device with a built-in snubber circuit that can reduce the size of a power conversion circuit in which the semiconductor device is incorporated and can be flexibly applied to various electric devices. Summary of the invention

[0012] The semiconductor device according to the present invention is characterized by comprising:

[0013] A semiconductor substrate having a drift layer of a first conductivity type, a base region of a second conductivity type formed on a surface of the drift layer, and a source region of the first conductivity type formed on a surface of the base region;

[0014] A source electrode formed on one surface side of the semiconductor substrate;

[0015] a drain electrode formed on the other surface side of the semiconductor substrate;

[0016] a plurality of trenches formed on a surface of the semiconductor substrate and having a bottom adjacent to the drift layer and sidewalls adjacent to the drift layer, the base region and the source region;

[0017] a plurality of first electrodes, arranged in the trenches via gate insulating films respectively formed on the side walls of the plurality of trenches, and having side surfaces facing the base region;

[0018] a plurality of second electrodes, formed above each of the first electrodes in a state of being separated from the first electrodes;

[0019] a first insulating region formed between the bottom of the trench and the first electrode to separate the first electrode from the bottom of the trench; and

[0020] a second insulating region extending between the second electrode and the first electrode to separate the second electrode from the first electrode, and extending between the second electrode and the sidewall of the trench to separate the second electrode from the sidewall of the trench,

[0021] The groove, the first electrode and the second electrode are formed in stripe shapes when viewed from a plane.

[0022] At least any one of the plurality of second electrodes is connected to the drain electrode.

[0023] The method for manufacturing a semiconductor device according to the present invention is used to manufacture the semiconductor device according to the present invention, and is characterized in that it comprises, in sequence:

[0024] A semiconductor substrate preparation step of preparing a semiconductor substrate having a drift layer of a first conductivity type;

[0025] A groove forming step of forming a plurality of grooves that appear to be stripes when viewed from a plane;

[0026] A first insulating film forming step, wherein a first insulating film is formed at the bottom and sidewalls of each of the plurality of trenches, thereby forming a first insulating region at the bottom of each of the plurality of trenches and a gate insulating film at the sidewalls of each of the plurality of trenches;

[0027] A first electrode forming step of forming a first electrode in the trench via the gate insulating film;

[0028] a second insulating film forming step of forming a second insulating film on a surface of the first insulating film on a side wall of the trench and on a surface of the first electrode;

[0029] a second electrode forming step of forming a second electrode above the first electrode in a state of being separated from the first electrode via the second insulating film; and

[0030] The source electrode / drain electrode forming step includes a step of forming a source electrode on one surface side of the semiconductor substrate and a step of forming a drain electrode on the other surface side of the semiconductor substrate.

[0031] Effects of the Invention

[0032] According to the semiconductor device and the method for manufacturing the semiconductor device of the present invention, since a plurality of second electrodes are formed above the first electrode in a state separated from the first electrode, and at least one of the plurality of second electrodes is connected to the drain electrode, the parasitic capacitance between the second electrode and the source region can be used as (a part of) a capacitor, thereby forming a buffer circuit using the internal resistance of the second electrode itself as a resistor. In this way, when the semiconductor device is assembled into the power conversion circuit, it is not necessary to install a buffer circuit separately. As a result, it is not necessary to ensure an area for setting the buffer circuit, thereby miniaturizing the power conversion circuit.

[0033] In addition, according to the semiconductor device and the method for manufacturing the semiconductor device of the present invention, since the second electrode is formed in a stripe shape when viewed from a plane, and at least one of the plurality of second electrodes is connected to the drain electrode, the snubber capacitance (the resistance value of the resistor of the snubber circuit and the electrostatic capacitance of the capacitor) can be adjusted according to the electrical device by limiting the length and cross-sectional area of ​​the second electrode and limiting the number of strips connected to the drain electrode. In this way, it is not necessary to redesign and manufacture the semiconductor device after changing the snubber capacitance of the snubber circuit according to the electrical device, and thus it is a snubber circuit built-in semiconductor device that can be flexibly applied to various electrical devices.

[0034] In addition, according to the method for manufacturing a semiconductor device of the present invention, since the first insulating film forming step (see Figure 4 (c)), so that the gate insulating film can be formed directly on the side wall of the trench before forming other insulating films. In this way, a gate insulating film that meets the film thickness uniformity requirements can be formed with high precision. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 1 is a diagram for explaining a semiconductor device 100 according to the first embodiment. Figure 1 (a) is a plan cross-sectional view of the semiconductor device 100. Figure 1 (b) Yes Figure 1 AA cross-section view of (a).

[0036] Figure 2 1 is a diagram for explaining the peripheral portion of the semiconductor device 100 according to the first embodiment. Figure 2 (a) Yes Figure 1 (a) BB cross-section diagram, Figure 2 (b) Yes Figure 1 (a) CC cross-section view.

[0037] Figure 3 1 is a diagram for explaining a buffer circuit in a semiconductor device 100 according to the first embodiment. Figure 3 (a) is a diagram showing the parasitic electrostatic capacitance of the semiconductor device 100. Figure 3 (b) is a diagram showing the relationship between the semiconductor device 100 and the electrostatic capacitance. Figure 3 (c) is an equivalent circuit diagram showing a semiconductor device and a buffer circuit. Figure 3 (d) is the resistance and electrostatic capacitance C of each buffer electrode DS1 formula.

[0038] Figure 4 1 is a diagram showing a method for manufacturing a semiconductor device 100 according to the first embodiment. Figure 4 (a)~ Figure 4 (d) is the process diagram ( Figure 5 and Figure 6 (The same is true).

[0039] Figure 5 FIG. 1 is a diagram showing a method for manufacturing the semiconductor device 100 according to the first embodiment.

[0040] Figure 6 FIG. 1 is a diagram showing a method for manufacturing the semiconductor device 100 according to the first embodiment.

[0041] Figure 7 1 is a diagram showing a method for manufacturing a semiconductor device 100 according to the first embodiment. Figure 7 (a)~ Figure 7 (c) is the process diagram.

[0042] Figure 8 FIG. 8 is a diagram showing a semiconductor device 800 according to a comparative example.

[0043] Fig. 9 is a diagram showing a method for manufacturing a semiconductor device 800 according to a comparative example. Fig. 9 (a)~ Fig. 9 (d) is the process diagram ( Fig.10 and Fig.11 Also, symbol M1 in the figure represents a mask.

[0044] Fig.10 It is a diagram showing a method for manufacturing a semiconductor device 800 according to a comparative example.

[0045] Fig.11 It is a diagram showing a method for manufacturing a semiconductor device 800 according to a comparative example.

[0046] Fig.12 This is a diagram for explaining a semiconductor device 101 according to a second embodiment.

[0047] Fig.13 1 is a diagram for explaining a semiconductor device 102 according to a first modification. Fig.13 (a) is a plan view of the semiconductor device 102. Fig.13 (b) Yes Fig.13 (a) DD cross-sectional view.

[0048] Fig.14 1 is a diagram for explaining a semiconductor device 102a according to a second modification example. Fig.14 (a) is a plan view of the semiconductor device 102a. Fig.14 (b) Fig.14 (a) EE cross-section diagram.

[0049] Fig.15 This is a diagram for explaining a semiconductor device 103 according to a third embodiment.

[0050] Fig.16 This is a diagram for explaining a semiconductor device 104 according to a fourth embodiment.

[0051] Fig.17 FIG. 1 is a diagram for explaining a semiconductor device 105 according to a third modification. Fig.17 In the figure, the drain finger DF, the drain pad DP, and the source electrode 120 are omitted (in Fig.18 The same is true in ).

[0052] Fig.18 It is a diagram for explaining a semiconductor device 106 according to a fourth modification.

[0053] Fig.19 This is a diagram for explaining a semiconductor device 107 according to a fifth modification.

[0054] Fig. 20 It is a diagram for explaining a semiconductor device 108 according to a sixth modification.

[0055] Fig.21 1 is a diagram for explaining a semiconductor device 109 according to a seventh modification. Fig.21 (a) is a plan view of the semiconductor device 109, Fig.21 (b) Yes Fig.21 (a) FF cross-section diagram.

[0056] Fig. 22 This is a diagram for explaining a semiconductor device 900 described in Patent Document 1. In the figure, reference numeral 911 denotes a low-resistance semiconductor layer, reference numeral 917 denotes a contact region, and reference numeral 976 denotes an interlayer insulating film.

[0057] Fig.23 This is a circuit diagram of a power conversion circuit (half-bridge circuit) 9 in Patent Document 2. DETAILED DESCRIPTION

[0058] Hereinafter, the semiconductor device and the method for manufacturing the semiconductor device of the present invention will be described according to the embodiments shown in the accompanying drawings. In addition, each of the accompanying drawings is a schematic diagram and does not necessarily strictly reflect the actual size. The embodiments described below do not limit the invention involved in the claims of the present invention. In addition, the elements and their combinations described in each embodiment are not all necessary for the solution of the present invention. In each embodiment, the same structures, elements (including structural elements that are not completely the same in shape, etc.) as the basic structure, features, functions, etc. are used in the embodiments. The same symbols are used and repeated descriptions are omitted.

[0059] [Implementation Method 1]

[0060] 1. Structure of Semiconductor Device 100 According to Embodiment 1

[0061] like Figure 1 As shown in (a), the semiconductor device 100 involved in the first embodiment is a trench gate semiconductor device (MOSFET) having a unit area A1 and a peripheral area A2 divided into parts surrounding the unit area. The unit area A1 is an area where the source electrode 120 is arranged on one side of the semiconductor substrate 110. The peripheral area A2 is an area where the drain finger DF, the drain pad DP, the gate finger GF and the gate pad GP are arranged at a position surrounding the unit area A1. In the first embodiment, when viewed from a plane, the semiconductor substrate 110 is rectangular in shape, and a gate pad GP is formed on one side of the rectangular shape. In addition, from one side adjacent to the side where the gate pad GP is formed to the other side ( Figure 1 The stripe-shaped gate electrode 150 and the buffer electrode 160 extending from the upper side to the lower side in (a) are formed in a stripe shape so as to vertically cross the cell region A1.

[0062] In the peripheral region A2 of the semiconductor device 100 according to the first embodiment, there is a drain lead-out wiring 162 (see Figure 2 )、Drain pad DP (refer to Figure 1 (a)), drain finger DF, gate lead wiring 152 (refer to Figure 2 )、gate pad GP (refer to Figure 1 ), and the gate finger GF. In the outer edge portion of the peripheral region A2, the base region 113 of the semiconductor substrate 110 is not formed. In this specification, the n-type layer in the region where the base region 113 is formed is referred to as the drift layer 112, and the n-type layer in the region where the base region 113 is not formed is referred to as the n-type semiconductor layer 117 (see Figure 2 (b)).

[0063] The drain lead wiring 162 is formed at both ends of the buffer electrode 160 which is strip-shaped in plan view (see FIG. Figure 2 (a)) The drain lead-out wiring 162 is made of polysilicon containing impurities at the same concentration as that of the buffer electrode 160 described later.

[0064] The drain pad DP is formed on the third insulating region 176 (interlayer insulating film) described later. A contact hole is formed in the third insulating region 176 directly below the drain pad DP, and the drain pad DP is connected to the n-type semiconductor layer 117 of the semiconductor substrate 110 via the metal plug Pg in the contact hole (see Figure 2 (b)).

[0065] The drain finger DF is formed so as to surround the cell area A1 from the drain pad DP in a plan view (see Figure 1 ) and formed on the third insulating region 176 (refer to Figure 2 (a) A contact hole is formed in the third insulating region 176 directly below the drain finger DF, and the drain finger DF is connected to the drain lead-out wiring 162 via the metal plug Pg in the contact hole.

[0066] The gate lead wiring 152 is formed at both ends of the gate electrode 150 which is strip-shaped when viewed from a plane (see FIG. Figure 2 (a)) The gate lead wiring 152 is made of polysilicon containing impurities at the same concentration as that of the gate electrode 150 described later.

[0067] The gate pad GP is connected to a gate terminal for external connection (not shown) and is formed on the third insulating region 176 .

[0068] In a plan view, the gate finger GF is formed to surround the cell region A1, the drain pad DP, and the drain finger DF from the gate pad GP (see Figure 1 (a)) and is formed on the third insulating region 176. A contact hole is formed on the third insulating region 176 directly below the gate finger GF, and the gate finger GF is connected to the gate lead wiring 152 via the metal plug Pg in the contact hole (see Figure 2 (a)).

[0069] In the semiconductor device 100 according to the first embodiment, in the cell area A1, as shown in FIG. Figure 1 As shown in (b), it has a semiconductor substrate 110, a source electrode 120, a drain electrode 130, a plurality of trenches 140, a gate electrode 150 (first electrode), a buffer electrode 160 (second electrode), a first insulating region 170, a gate insulating film 172, a second insulating region 174, and a third insulating region 176.

[0070] The semiconductor substrate 110 includes: an n+ type low resistance semiconductor layer 111, an n- type drift layer 112 formed on the low resistance semiconductor layer 111 and having a lower impurity concentration than the low resistance semiconductor layer 111, a p-type base region 113 formed on the surface of the drift layer 112, and an n-type source region 114 formed on the surface of the base region 113 and having a higher impurity concentration than the drift layer 112.

[0071] The thickness of the low resistance semiconductor layer 111 is 50 μm to 500 μm (for example, 350 μm), and the impurity concentration of the low resistance semiconductor layer 111 is 1×10 18 cm -3 ~1×10 21 cm -3 (For example, 1×10 19 cm -3The thickness of the drift layer 112 in the region where the trench 140 is not formed is 3 μm to 50 μm (for example, 15 μm), and the impurity concentration of the drift layer 112 is 1×10 14 cm -3 ~1×10 19 cm -3 (For example, 1×10 15 cm -3 ). The thickness of the base region 113 is 0.5 μm to 10 μm (e.g., 5 μm), and the impurity concentration of the base region 113 is 1×10 16 cm -3 ~1×10 19 cm -3 (For example, 1×10 17 cm -3 ).

[0072] The source electrode 120 is formed on one surface side of the semiconductor substrate 110 across the third insulating region 176, and contacts the source region 114 and the base region 113 through the metal plug Pg formed in the contact hole of the third insulating region 176. The source electrode 120 is, for example, composed of an Al film or an Al alloy film (e.g., an AlSi film), and its thickness is 1 μm to 10 μm (e.g., 3 μm). The drain electrode 130 is formed on the other surface side of the semiconductor substrate 110 (on the surface of the low-resistance semiconductor layer 111). The drain electrode 130 is composed of a stacked film stacked in the order of Ti, Ni, and Au (or Ag), and its thickness is 0.2 μm to 1.5 μm (e.g., 1 μm).

[0073] A plurality of trenches 140 are formed on one surface of the semiconductor substrate 110. The plurality of trenches 140 respectively have a bottom 142 adjacent to the drift layer 112 and a sidewall 144 adjacent to the drift layer 112, the base region 113, and the source region 114. The bottom of the trench 140 is located deeper than the position of the pn junction between the drift layer 112 and the base region 113.

[0074] The gate electrode 150 is arranged in each trench 140 via a gate insulating film 172 formed on the side walls 144 (the lower side of the side walls) of the plurality of trenches 140, and its side faces the base region 113. The upper surface of the gate electrode 150 is located at a depth shallower than the deepest part of the source region 114, and the lower surface of the gate electrode 150 is located at a depth position that is the same as or deeper than the depth position of the pn junction surface between the base region 113 and the drift layer 112. The gate electrode 150 is formed in a strip shape when viewed from a plane, and each buffer electrode is formed in a strip shape. A gate lead wiring 152 (see Figure 2a) The gate electrode 150 is connected to an external gate terminal through the gate lead wiring 152, the metal plug Pg, the gate finger GF and the gate pad GP.

[0075] The buffer electrode 160 is made of polysilicon containing an impurity of a predetermined concentration, and is disposed in the trench 140 above the gate electrode 150 in a state of being separated by the second insulating region 174. The depth position of the lower surface of the buffer electrode 160 is shallower than the depth position of the lowest portion of the contact surface of the source region 114 with the trench 140. The depth position of the upper surface of the buffer electrode 160 may be the same as the height position of the surface of the semiconductor substrate 110 in the region where the trench 140 is not formed, may be located at a depth position deeper than the height (depth) position of the surface of the semiconductor substrate 110, or may be located at a height higher than the height (depth) position of the surface of the semiconductor substrate 110.

[0076] The buffer electrode 160 is formed in a stripe shape (belt shape) when viewed from a plane. The width of the buffer electrode 160 ( Figure 1 The lateral width in the cross-sectional view of (b) is narrower than the width of the gate electrode 150. A drain lead wiring 162 (see Figure 2 (a) The buffer electrode 160 is electrically connected to the drain electrode 130 via the drain lead-out wiring 162 , the metal plug Pg, the drain finger DF, the drain pad DP, the metal plug Pg, the n-type semiconductor layer 117 , and the low-resistance semiconductor layer 111 .

[0077] The first insulating region 170 is formed between the bottom 142 of the trench 140 and the gate electrode 150, and separates the gate electrode 150 from the bottom 142 of the trench 140. The gate insulating film 172 is formed on the surface of the lower side wall of the side wall 144 of the trench 140, and separates the gate electrode 150 from the side wall 144 of the trench 140. In the first embodiment, the first insulating region 170 and the gate insulating film 172 are formed together, and the film thickness is the same as that of the gate insulating film 172, but it can also be thicker than the gate insulating film 172. The first insulating region 170 and the gate insulating film 172 are thermal oxide films, but they can also be CVD oxide films.

[0078] The second insulating region 174 extends between the gate electrode 150 and the buffer electrode 160 to separate the buffer electrode 160 from the gate electrode 150, and extends between the buffer electrode 160 and the sidewall 144 of the trench 140 to separate the buffer electrode 160 from the sidewall 144 of the trench 140. The film thickness t of the second insulating region 174 between the sidewall 144 of the trench 140 and the buffer electrode 160 is t оx1 Than the film thickness t of the gate insulating film 172 оx2 thicker than the film thickness t of the first insulating region 170 оx3The film thickness of the second insulating region 174 between the buffer electrode 160 and the gate electrode 150 is greater than the film thickness of the second insulating region 174 between the buffer electrode 160 and the sidewall 144 of the trench 140. оx1 The second insulating region 174 is a CVD oxide film formed by a CVD method, and may also be a thermal oxide film.

[0079] The third insulating region 176 extends between the source electrode 120 and the buffer electrode 160 to separate the source electrode 120 from the buffer electrode 160. The third insulating region 176 is used to reduce the influence of vibration and heat on the buffer electrode 160 and the gate electrode 150 when bonding a wire or the like to the source electrode 120 during mounting.

[0080] The plurality of trenches 140 , the gate electrodes 150 in the trenches 140 , the buffer electrodes 160 , and the source regions 114 are formed in a stripe shape when viewed in a plan view.

[0081] 2. Buffer Circuit in Semiconductor Device 100 According to Embodiment 1

[0082] As described above, the buffer electrode 160 is formed on the semiconductor device 100 according to the first embodiment, and the buffer electrode 160 is connected to the drain electrode 130. In addition, the semiconductor device 100 includes the second insulating region 174, which extends between the buffer electrode 160 and the gate electrode 150 to separate the buffer electrode 160 from the gate electrode 150, and extends between the buffer electrode 160 and the sidewall 144 of the trench 140 to separate the buffer electrode 160 from the sidewall 144 of the trench 140.

[0083] By doing so, Figure 3 As shown in (a), there is an electrostatic capacitance C between the buffer electrode 160 and the source region 114. DS1 .like Figure 1 As shown in (a), since a plurality of buffer electrodes 160 are formed in a stripe shape, an electrostatic capacitance C exists in each buffer electrode 160. DS1 In addition, there is also an electrostatic capacitance C between the base region 113 and the drift layer 112. DS2 Therefore, if Figure 3 As shown in (b), an electrostatic capacitor C is configured between the source electrode 120 and the drain electrode 130. DS1 (The electrostatic capacitance C between each buffer electrode 160 and the source region 114 DS1 The combined capacitance) and electrostatic capacitance C DS2 These electrostatic capacitances (parasitic capacitances) constitute a capacitor C between the source electrode 120 and the drain electrode 130 (see Figure 3 (c)).

[0084] The buffer electrode 160 is made of polycrystalline silicon containing impurities at a predetermined concentration, and is formed in a stripe shape when viewed from above (see FIG. Figure 1 (a)), so there is an internal resistance in the buffer electrode 160. The combined resistance of the internal resistances of the buffer electrodes 160 constitutes the resistance between the capacitor C and the drain electrode 130 (see Figure 3 (c)).

[0085] Therefore, the semiconductor device 100 is a semiconductor device (MOSFET) having a built-in RC snubber circuit including a capacitor C and a resistor R connected in series.

[0086] When the resistivity is set to ρ, the cross-sectional area of ​​the buffer electrode 160 is set to S1, and the length of the buffer electrode 160 (the length along the current path) is set to l, as shown in FIG. Figure 3 As shown in (d), the internal resistance R1 of each buffer electrode 160 is proportional to the resistivity ρ and the length l of the buffer electrode 160, and inversely proportional to the cross-sectional area S1 of the buffer electrode 160. Therefore, by adjusting the film thickness of the second insulating region 174, the cross-sectional area S1 of the buffer electrode 160 can be adjusted. Figure 1 (b) lateral width × height). In addition, the length l of the strip-shaped buffer electrode 160 can also be adjusted. In this way, the resistance value of each strip-shaped buffer electrode 160 can be adjusted relatively easily, and the resistance R of the buffer circuit can be adjusted relatively easily. Since the resistivity ρ also depends on the impurity concentration introduced into the polysilicon, from this point of view, the resistance value of the buffer electrode 160 can also be adjusted.

[0087] In addition, regarding the capacitor of the buffer circuit, when the dielectric constant of the second insulating region 174 is ε, and the length between the buffer electrode 160 and the source region 114, that is, the thickness of the second insulating region 174 is t оx1 , when the surface of the buffer electrode 160 facing the source region 114 is set as S2, as Figure 3 As shown in (d), each electrostatic capacitor C DS1 It is inversely proportional to the film thickness tоx1 of the second insulating region 174 , and is proportional to the area S2 of the region where the buffer electrode 160 faces the source region 114 .

[0088] Since the film thickness t of the second insulating region 174 can be adjusted relatively easily оx1 , and the area S2 of the region where the buffer electrode 160 faces the source region 114 is proportional to the height of the buffer electrode 160. Therefore, by adjusting the film thickness of the second insulating region 174, the area S2 of the region where the buffer electrode 160 faces the source region 114 can be adjusted. In this way, the electrostatic capacitance C between each stripe-shaped buffer electrode 160 and the source region 114 can be easily adjusted. DS1, and thus the electrostatic capacitance of the buffer circuit can be adjusted relatively easily.

[0089] As described above, since the resistance value and the electrostatic capacitance of the buffer circuit in the semiconductor device 100 according to the first embodiment can be easily adjusted, the semiconductor device 100 is a semiconductor device with high flexibility.

[0090] 3. Method for manufacturing semiconductor device according to embodiment 1

[0091] The semiconductor device 100 according to the first embodiment can be manufactured according to the following steps. Figure 4 to Figure 7 As shown, it includes in sequence: a semiconductor substrate preparation step; a trench forming step, a first insulating film forming step; a gate electrode forming step (a first electrode forming step); a second insulating film forming step; a buffer electrode forming step; and a source region and a base region forming step.

[0092] (1) Semiconductor substrate preparation process

[0093] First, a semiconductor substrate 110 having an n+ type low resistance semiconductor layer 111 and an n type drift layer 112 formed on the low resistance semiconductor layer 111 is prepared (see Figure 4 (a)).

[0094] (2) Groove Formation Process

[0095] Next, a plurality of trenches 140 (see FIG. 1 ) which are stripe-shaped when viewed from above are formed on the drift layer 112. Figure 4 (b)).

[0096] (3) First Insulating Film Formation Step

[0097] Next, a first insulating film 170′ (see FIG. 1 ) is formed on one surface of the semiconductor substrate 110 (the surface on the drift layer 112 side, including the inner surface of the trench 140). Figure 4 (c)). In this way, the first insulating region 170 is formed on the bottom 142 of each of the plurality of trenches 140, and the gate insulating film 172 is formed on the sidewall 144 of each of the plurality of trenches. The first insulating film 170' is formed by, for example, thermal oxidation.

[0098] (4) Gate electrode forming step (first electrode forming step)

[0099] Next, the gate electrode 150 is formed in the trench 140 via the first insulating region 170 and the gate insulating film 172. Specifically, first, polysilicon 150' having a predetermined impurity concentration is formed on the entire region of one surface side of the semiconductor substrate 110 (see Figure 4(d)). At this time, a gate lead wiring 152 is formed in the peripheral region A2. Then, the gate electrode 150 is formed by etching the polysilicon 150' (see Figure 5 (a)). The polysilicon 150' may be formed by ion implanting p-type impurities (such as boron) after forming polysilicon, or may be formed by growing polysilicon in a p-type impurity atmosphere (doped polysilicon).

[0100] (5) Second Insulating Film Formation Step

[0101] Next, a second insulating film 174' is formed on the sidewall 144 of the trench 140, the surface of the first insulating film 170' formed on the surface of the semiconductor substrate 110, and the surface of the gate electrode 150 (see Figure 5 (b)). In this way, the second insulating film 174' on the gate electrode 150 forms the second insulating region 174 on the side of the gate electrode 150 (see Figure 5 (d)), at the same time, the first insulating film 170' and the second insulating film 174' stacked on the surface of the upper side wall (upper side wall) of the trench 140 form a second insulating region 174 on the side wall 144 of the trench 140 (see Figure 5 (d)) The second insulating film 174' is formed by a CVD method, but a thermal oxide film formed by a thermal oxidation method may also be used.

[0102] (6) Buffer Electrode Forming Step (Second Electrode Forming Step)

[0103] Then, the buffer electrode 160 is formed on the gate electrode 150 in a state separated from the gate electrode 150. Specifically, first, polysilicon 160' (see Figure 5 (c)). At this time, a drain lead wiring 162 is formed in the peripheral area A2. Next, etching is performed so that the upper surface of the polysilicon 160' is at the same depth as the surface of the semiconductor substrate 110 or at a depth deeper than the surface of the semiconductor substrate 110, and at the same time, the first insulating film 170' and the second insulating film 174' on the surface of the semiconductor substrate 110 are removed by etching (see Figure 5 (d)).

[0104] (7) Source Region and Base Region Formation Step

[0105] Next, p-type impurity (e.g., boron) ions are implanted from one surface side of the semiconductor substrate 110 to a predetermined depth (see Figure 6 (a)). Next, the p-type impurity is activated to form a base region 113. Next, n-type impurity (for example, phosphorus) is ion-implanted from the surface side of the semiconductor substrate 110 to a predetermined depth (see Figure 6 Next, the n-type impurities are activated to form a source region 114 .

[0106] (8) Third Insulating Film Formation Step

[0107] Next, a third insulating film (third insulating region 176) is formed on the surface of the semiconductor substrate 110, the second insulating region 174, and the buffer electrode 160 (see Figure 6 (c) The third insulating film is formed by, for example, a CVD method.

[0108] (9) Contact Hole Forming Step

[0109] Next, a contact hole is formed between adjacent trenches 140 so as to penetrate the third insulating region 176 and the source region 114 and reach the base region 113 (see FIG. Figure 6 (d)). At this time, in the peripheral area A2, a contact hole for making the gate lead wiring 152 formed at the end of the gate electrode 150 contact the gate finger; a contact hole for making the drain lead wiring 162 formed at the end of the buffer electrode 160 contact the drain finger (drain pad); and a contact hole for making the drain pad DP contact the n-type semiconductor layer 117 are formed.

[0110] Next, a barrier metal (not shown) is formed on the inner peripheral surface of each contact hole by sputtering, and a tungsten film is formed through the barrier metal (see Figure 7 (a)). Then, by CMP, only tungsten is left in each contact hole, and metal plugs Pg are formed respectively (refer to Figure 7 (b)).

[0111] (10) Source Electrode and Drain Electrode Formation Step

[0112] Next, an Al-Cu metal film is formed on the surface of the third insulating region 176 and the metal plug Pg by sputtering, and a source electrode 120, a drain pad DP and a drain finger DF, and a gate pad GP and a gate finger GF are formed (see FIG. Figure 7 (b)). In this way, the source electrode 120 is electrically connected to the source region 114 and the base region 113 via the metal plug Pg, the drain electrode DF and the drain pad DP are electrically connected to the buffer electrode 160 via the metal plug Pg, and the gate electrode GF and the gate pad GP are connected to the gate electrode via the metal plug Pg. In addition, a multilayer metal film such as Ti-Ni-Au (or Ag) is formed on the surface of the low resistance semiconductor layer 111, and a drain electrode 130 is formed (see Figure 7(c)). In the peripheral region, the drain electrode 130 is connected to the drain pad DP via the n-type semiconductor layer 117 and the metal plug Pg. Therefore, by forming the drain electrode 130, the buffer electrode 160 is connected to the drain electrode 130 via the drain lead-out wiring 162, the drain finger DF, the drain pad DP, and the semiconductor substrate 110 (drift layer 112).

[0113] Through the above steps, the semiconductor device according to the first embodiment can be manufactured.

[0114] 4. Comparison between the semiconductor device of the present invention and a semiconductor device having a shielded gate structure

[0115] However, as a semiconductor device in which two or more electrodes are arranged in a trench, a semiconductor device with a shielded gate structure is known (for example, the semiconductor device 800 according to the comparative example, the semiconductor device 800 according to the reference example, Figure 8 ).

[0116] like Figure 8 As shown, the semiconductor device 800 according to the comparative example includes a semiconductor substrate 810 , a trench 840 , a gate electrode 850 , a gate insulating film 872 , a shield electrode 890 , an insulating region 878 , a source electrode 820 , a drain electrode 830 , and an interlayer insulating film 876 .

[0117] The semiconductor substrate 810 includes an n-type low-resistance semiconductor layer 811 , an n-type drift layer 812 adjacent to the low-resistance semiconductor layer 811 , a p-type base region 813 adjacent to the drift layer 812 , and an n-type source region 814 adjacent to the base region 813 .

[0118] The gate electrode 850 is disposed in the trench 840. A side wall portion of the gate electrode 850 faces the base region 813 via a gate insulating film 872.

[0119] The shield electrode 890 is disposed within the trench 840 and is located at a lower side of the gate electrode 850 .

[0120] The insulating region 878 extends between the gate electrode 850 and the shield electrode 890 and along the sidewalls and bottom of the trench 840 , thereby isolating the shield electrode 890 from the sidewalls and bottom.

[0121] The semiconductor device 800 according to the comparative example can be manufactured by, for example, the following method.

[0122] That is, the method for manufacturing the conductor device according to the comparative example 1 comprises, in order:

[0123] In the first step, a semiconductor substrate 810 is prepared (see Fig. 9 (a));

[0124] In the second step, a plurality of grooves 840 (see FIG. 1 ) which are stripe-shaped when viewed from a plane are formed on the semiconductor substrate 810. Fig. 9 (b));

[0125] In the third step, a first insulating film 878′ is formed on the bottom surface and sidewall of each of the plurality of trenches 840 (see Fig. 9 (c));

[0126] In the fourth step, polysilicon 890' is formed on the entire surface of the semiconductor substrate 810 (see Fig. 9 (d)), and after a portion of the polysilicon 890' in the trench 840 is retained, etching is performed to form a shield electrode 890 in the trench 840 via the first insulating film 878' (see Fig.10 (a));

[0127] In the fifth step, a second insulating film 870' is formed on the entire semiconductor substrate 810 (see Fig.10 (b));

[0128] In the sixth step, only the portion on the shielding electrode 890 is retained, and the first insulating film 878' and the second insulating film 870' are etched (refer to Fig.10 (c));

[0129] In the seventh step, an insulating film 872' is formed on one surface of the semiconductor substrate 810 (including the inner surface of the trench 840), thereby forming a gate insulating film 872 on the sidewall of the upper portion of the trench 840 (see Fig.10 (d));

[0130] In the eighth step, polysilicon 850' is formed on one surface of the semiconductor substrate 810 (including the inner surface of the trench 840) (see Fig.11 (a)), only the portion inside the trench 840 is left and etched to form a gate electrode 850 (see Fig.11 (b));

[0131] Ninth step, forming an interlayer insulating film 876 (refer to Fig.11 (c)); and

[0132] The tenth step is to form a source electrode 820 and a drain electrode 830 (see Fig.11 (d)).

[0133] Since the gate insulating film that determines the threshold voltage of the device requires high precision, in the manufacturing method of the semiconductor device according to the comparative example, the first insulating film 878' (see Fig. 9 (c)), in the fifth step, a second insulating film 870' is formed (see Fig.10(b)) After that, in the sixth step, the first insulating film 878' and the second insulating film 870' are etched (over-etched, see Fig.10 (c)), in the seventh step, a gate insulating film 872 is formed (see Fig.10 (d)) However, in the sixth step, since the insulating film may be over-etched, it is difficult to etch the first insulating film 878' and the second insulating film 870' with high accuracy, and it is difficult to form the gate insulating film 872 with high accuracy.

[0134] On the other hand, according to the method for manufacturing a semiconductor device according to the first embodiment, since the gate insulating film is formed before forming other insulating films (see Figure 4 (c)), the gate insulating film can be directly formed on the side wall of the trench before forming other insulating films. In this way, the gate insulating film can be formed with high precision.

[0135] 5. Effects of the Semiconductor Device 100 and the Manufacturing Method Thereof According to the First Embodiment

[0136] According to the semiconductor device 100 and the method for manufacturing the semiconductor device according to the first embodiment, since the buffer electrode 160 is formed above the gate electrode 150 in a state separated from the gate electrode 150 and at least one of the plurality of buffer electrodes 160 (all of the buffer electrodes 160 in the first embodiment) is connected to the drain electrode 130, a buffer circuit can be formed in which the parasitic capacitance between the buffer electrode 160 and the source region 114 is used as (a part of) the capacitor and the internal resistance of the buffer electrode 160 itself is used as the resistor. Thus, when the semiconductor device is assembled into the power conversion circuit, it is not necessary to install the buffer circuit. As a result, it is no longer necessary to ensure an area for providing the buffer circuit, and the power conversion circuit can be miniaturized.

[0137] Furthermore, according to the semiconductor device 100 and the method for manufacturing the semiconductor device according to the first embodiment, since the buffer electrode 160 is formed in a stripe shape when viewed from a plane, and at least one of the plurality of buffer electrodes is connected to the drain electrode 130, the length of the buffer electrode 160 can be adjusted. Figure 1 (a) and the cross-sectional area, and further, by selecting whether to use each buffer electrode 160 as a drain potential, the buffer capacitance can be adjusted according to the electrical device. In this way, there is no need to redesign and manufacture a semiconductor device with a buffer capacitance of a buffer circuit changed according to the electrical device, and a semiconductor device with a built-in buffer circuit that can be flexibly applied to various electrical devices.

[0138] Furthermore, according to the method for manufacturing a semiconductor device according to the first embodiment, since the first insulating film forming step (see FIG. 1 ) is included in which the gate insulating film 172 is formed after the trench forming step and before the other insulating films are formed, Figure 4 (c)), the gate insulating film 172 can be formed directly on the sidewall 144 of the trench 140 before forming other insulating films. In this way, the gate insulating film 172 will not be affected by the etching accuracy of other insulating films, so that the gate insulating film 172 that meets the film thickness uniformity requirement can be formed with high accuracy.

[0139] However, when a buffer electrode is formed in a semiconductor device, an area for forming a buffer circuit must be separately prepared, which makes it difficult to miniaturize the semiconductor device itself. In contrast, according to the semiconductor device 100 of the first embodiment, since the buffer electrode 160 is provided in the trench 140, it is not necessary to separately prepare an area for forming a buffer circuit. As a result, although it is a semiconductor device of a built-in buffer circuit type, the semiconductor device itself can still be miniaturized.

[0140] Furthermore, according to the semiconductor device 100 according to the first embodiment, since the buffer electrode 160 is disposed at a position facing the source region 114 with the second insulating region 174 interposed therebetween, an electrostatic capacitor C can be formed between the buffer electrode 160 and the source region 114. DS1 , and the electrostatic capacitance C can be adjusted relatively easily by adjusting the thickness of the second insulating region 174 between the buffer electrode 160 and the sidewall 144 of the trench 140 DS1 As described above, the semiconductor device 100 according to the first embodiment can easily adjust the snubber capacity according to the electric device, and is a snubber circuit built-in semiconductor device that can be flexibly applied to various electric devices.

[0141] In addition, according to the semiconductor device 100 involved in the first embodiment, since the thickness of the second insulating region 174 between the side wall 144 of the trench 140 and the buffer electrode 160 is thicker than the thickness of the gate insulating film 172, the second insulating region 174 between the side wall 144 of the trench 140 and the buffer electrode 160 can be used as an electrolyte with a specified electrostatic capacitance suitable for constituting a buffer circuit.

[0142] According to the semiconductor device 100 of the first embodiment, the buffer electrode 160 is made of polysilicon containing impurities at a predetermined concentration. Therefore, the resistance value of the buffer electrode 160 can be adjusted by adjusting the impurity concentration, thereby making the resistance value of the buffer circuit within a desired range.

[0143] In addition, according to the semiconductor device 100 according to the first embodiment, since the depth position of the bottom surface of the buffer electrode 160 is shallower than the depth position of the lowest portion of the contact surface with the trench 140 in the source region 114, the entire side surface of the buffer electrode 160 faces the source region 114. In this way, since the area S2 of the region where the buffer electrode 160 faces the source region 114 can be increased, the electrostatic capacitance C between the buffer electrode 160 and the source region 114 can be increased. DS1 , thereby ensuring the electrostatic capacitance required to form a buffer circuit.

[0144] [Implementation Method 2]

[0145] The semiconductor device 101 according to the second embodiment basically has the same structure as the semiconductor device 100 according to the first embodiment, but the number of buffer electrodes connected to the drain electrode is different from that of the semiconductor device 100 according to the first embodiment. That is, in the semiconductor device 101 according to the second embodiment, not all buffer electrodes 160 are connected to the drain electrode 130 as in the first embodiment, but at least one (a predetermined number) of the buffer electrodes 160 among the plurality of buffer electrodes 160 is connected to the drain electrode 130.

[0146] In the second embodiment, half of the plurality of buffer electrodes 160 (the buffer electrodes 160 in every other stripe) are connected to the drain finger DF (see Fig.12 The remaining buffer electrodes 160 are not connected to the drain finger DF. In the second embodiment, half of the plurality of buffer electrodes 160 are in contact with each other, but the number of buffer electrodes 160 in contact may be more than half or less than half, so that the buffer capacitance (resistance value and electrostatic capacitance) of the buffer circuit can be easily adjusted.

[0147] As described above, although the number of buffer electrodes connected to the drain in the semiconductor device 101 according to the second embodiment is different from that of the semiconductor device 100 according to the first embodiment, since at least one of the plurality of buffer electrodes 160 (half of the number in the second embodiment) is connected to the drain electrode, the semiconductor device is a semiconductor device with a built-in buffer circuit, and can be used as a miniaturized power conversion circuit. In addition, by selecting the length and cross-sectional area of ​​the buffer electrode 160 and whether to set each buffer electrode 160 to the drain potential, the buffer capacitance corresponding to the electrical device can be adjusted, and thus the semiconductor device is a semiconductor device with a built-in buffer circuit that can be flexibly applied to various electrical devices.

[0148] Furthermore, according to the semiconductor device 101 of the second embodiment, only a predetermined buffer electrode 160 among the plurality of buffer electrodes 160 is connected to the drain electrode 130. Therefore, the resistance value and electrostatic capacitance of the buffer circuit can be adjusted by adjusting the number of buffer electrodes 160 connected to the drain electrode 130. Therefore, the semiconductor device 101 of the second embodiment is a semiconductor device having a built-in buffer circuit that can be used in various electrical devices.

[0149] The semiconductor device 101 according to the second embodiment has the same structure as the semiconductor device 100 according to the first embodiment except that the number of buffer electrodes connected to the drain electrode is different, and thus also has the same effects as the semiconductor device 100 according to the first embodiment.

[0150] [Variation 1]

[0151] The semiconductor device 102 according to the first modification example basically has the same structure as the semiconductor device 101 according to the second embodiment, but is different from the semiconductor device 101 according to the second embodiment in the structure of the source region (see Fig.13 (a) and Fig.13 (b)). That is, in the first modification, in the trench 140 (see Fig.13 (b) The source region 114 is not formed around the trench 140 on the right side, but the trench 140 (see FIG. 1 ) includes a buffer electrode 160 in contact with the drain electrode DF (drain electrode). Fig.13 (b) A source region 114 is formed around the trench 140 on the left side.

[0152] As described above, although the semiconductor device 102 according to the first modification is different from the semiconductor device 101 according to the second embodiment in the structure of the source region, it is a semiconductor device with a built-in buffer circuit because at least one of the plurality of buffer electrodes 160 (half of them in the first modification) is connected to the drain, similarly to the semiconductor device 102 according to the second embodiment, and can be used as a miniaturized power conversion circuit. In addition, the semiconductor device 102 according to the first modification does not need to be redesigned and manufactured in accordance with the electrical device, and is a semiconductor device with a built-in buffer circuit that can be flexibly applied to various electrical devices.

[0153] In addition, in the trench 140 having the buffer electrode 160 connected to the drain electrode 130, although the depletion layer extends in a direction deeper than the trench 140, even in the trench 140 having the buffer electrode 160 not connected to the drain electrode 130 (see Fig.13(b) In the trench on the right side, the depletion layer can also be maintained at a deeper depth, so although it does not function as a gate trench, it still functions as a so-called virtual trench.

[0154] [Variation 2]

[0155] The semiconductor device 102a according to the second modification example basically has the same structure as the semiconductor device 102 according to the first modification example, but is different from the semiconductor device 102 according to the first modification example in the number of buffer electrodes in contact with the drain. That is, in the second modification example, all the buffer electrodes 160 are connected to the drain fingers DF (see Fig.14 (a)). At this time, the trench 140 is not formed around the source region 114 (see Fig.14 The trench on the right side of (b) does not function as a gate trench, but functions as a buffer circuit and a so-called dummy trench. In addition, in the second modification, the number of buffer electrodes connected to the drain fingers and the number of trenches without a source region formed around them can also be arbitrarily adjusted.

[0156] As described above, the semiconductor device 102a according to the second modification is different from the semiconductor device 102 according to the first modification in the number of buffer electrodes in contact with the drain. However, like the semiconductor device 102 according to the first modification, since at least one of the plurality of buffer electrodes 160 (all in the second modification) is connected to the drain, it is a semiconductor device with a built-in buffer circuit and can be used as a miniaturized power conversion circuit. In addition, the semiconductor device 102 according to the first modification does not need to be redesigned and manufactured in accordance with the electrical device, and is therefore a semiconductor device with a built-in buffer circuit that can be flexibly applied to various electrical devices.

[0157] [Implementation Method 3]

[0158] The semiconductor device 103 according to the third embodiment basically has the same structure as the semiconductor device 100 according to the first embodiment or the semiconductor device 101 according to the second embodiment (hereinafter referred to as the semiconductor device 100 according to the first embodiment, etc.), but is different from the semiconductor device 100 according to the first embodiment, etc. in that it has a shielded gate structure. That is, the semiconductor device 103 according to the third embodiment includes a shield electrode 190 (see FIG. 1 ) that is separated from the trench 140 and the source electrode 120 and connected to the source electrode 120 (which may also be a gate electrode) between the gate electrode 150 in the trench 140 and the bottom of the trench 140. Fig.15In addition, although the shield electrode 190 is connected to the source electrode in the third embodiment, it may be connected to the gate electrode. In this case, the shield electrode 190 and the gate electrode 150 are separated from each other in the trench 140 and are electrically connected via the gate finger GF outside the trench 140.

[0159] In the third embodiment, the fourth region 178 is included. The fourth region 178 extends between the shield electrode 190 and the gate electrode 150 to separate the gate electrode 150 from the shield electrode 190 , and extends between the gate electrode 150 and the sidewall 144 of the trench 140 to separate the gate electrode 150 from the sidewall 144 of the trench 140 .

[0160] As described above, although the semiconductor device 103 of the third embodiment is different from the semiconductor device 100 of the first embodiment in that it does not have a shielded gate structure, it is a semiconductor device with a built-in buffer circuit because at least one of the plurality of buffer electrodes 160 (half of them in the second embodiment) is connected to the drain electrode, similarly to the semiconductor device 100 of the first embodiment, and can be used as a miniaturized power conversion circuit. In addition, by selecting the length and cross-sectional area of ​​the buffer electrode 160 and whether to set each buffer electrode 160 to the drain potential, the buffer capacitance corresponding to the electrical device can be adjusted, and thus the semiconductor device with a built-in buffer circuit can be flexibly applied to various electrical devices.

[0161] In addition, according to the semiconductor device 103 of the third embodiment, since the shield electrode 190 is provided between the gate electrode 150 in the trench 140 and the bottom of the trench 140, the shield electrode 190 is isolated from the bottom 142 of the trench 140, the sidewall 144 of the trench 140, and the gate electrode 150 and connected to the gate electrode 150 or the source electrode 120, the capacitance C between the gate and the drain can be reduced. GD This reduces the gate charge current and gate discharge current, thereby increasing the switching speed.

[0162] In addition, since the fourth insulating region 178 is provided, the fourth insulating region 178 extends between the shielding electrode 190 and the gate electrode 150 to separate the gate electrode 150 from the shielding electrode 190, and extends between the gate electrode 150 and the side wall 144 of the groove 140 to separate the gate electrode 150 from the side wall 144 of the groove 140. Therefore, the distance from the corner of the groove 140 that is prone to cause electric field concentration to the gate electrode 150 can be extended, and the electric field can be further alleviated at the fourth insulating region 178, thereby improving the withstand voltage.

[0163] The semiconductor device 103 according to the third embodiment has the same structure as the semiconductor device 100 according to the first embodiment, except that it does not have a shield gate structure, and thus has the same effects as the semiconductor device 100 according to the first embodiment.

[0164] [Implementation method 4]

[0165] The semiconductor device 104 according to the fourth embodiment basically has the same structure as the semiconductor device 100 according to the first embodiment, but is different from the semiconductor device 100 according to the first embodiment in that it has a super junction structure (hereinafter referred to as an SJ structure). That is, in the semiconductor device 104 according to the fourth embodiment, the semiconductor substrate 110 further has: a plurality of p-type column regions 116 (second conductive column regions) formed at predetermined intervals in a region deeper than the bottom of the base region 113, wherein the drift layer between adjacent p-type column regions 116 constitutes an n-type column region 115 (first conductive column region), and the n-type column region 115 and the p-type column region 116 constitute an SJ structure (see Fig.16 ). In addition, in the fourth embodiment, in order to form the n-type column region 115 below the trench 140 and form the source region 114 and the channel, a structure in which the width of the channel is wider than the width of the trench 140 is adopted, but any suitable structure may be used as long as it is an SJ structure and can form the source region 114 and the channel.

[0166] As described above, although the semiconductor device 104 according to the fourth embodiment is different from the semiconductor device 100 according to the first embodiment in that it has an SJ structure, it is a semiconductor device with a built-in buffer circuit because at least one of the plurality of buffer electrodes 160 is connected to the drain electrode, and can be used as a miniaturized power conversion circuit. In addition, by selecting the length and cross-sectional area of ​​the buffer electrode 160 and whether to set each buffer electrode 160 to the drain potential, the buffer capacitance corresponding to the electrical device can be adjusted, and thus the semiconductor device with a built-in buffer circuit can be flexibly applied to various electrical devices.

[0167] Furthermore, according to the semiconductor device 104 according to the fourth embodiment, since the n-type column region 115 and the p-type column region 116 form an SJ structure, it is a semiconductor device that can maintain a withstand voltage while having a low on-resistance.

[0168] The semiconductor device 104 according to the fourth embodiment has the same structure as the semiconductor device 100 according to the first embodiment, etc. except for having the SJ structure, and thus has the same effects as the semiconductor device 100 according to the first embodiment, etc.

[0169] As mentioned above, although the present invention has been described based on the above-mentioned embodiment, the present invention is not limited to the above-mentioned embodiment. It can be implemented in various forms within the scope not departing from the gist thereof, and for example, the following modifications are also possible.

[0170] (1) The shapes, positions, sizes, etc. described in the above-mentioned embodiments (including various modified examples, the same below) are merely examples and may be changed within the scope that does not impair the effects of the present invention.

[0171] Furthermore, each embodiment and modification example may be combined.

[0172] (2) In the above-mentioned embodiments, the gate fingers GF are arranged only at the periphery of the semiconductor substrate, but the present invention is not limited thereto. In addition to the periphery, the gate fingers GF may be further arranged so as to cross the semiconductor substrate 110 from the gate pad GP toward the opposite side (see Fig.17 ). In this case, the source electrode (not shown) is divided into two regions surrounded by gate fingers, and the drain electrode and the drain pad (not shown) are arranged to surround the respective source electrodes (two in total).

[0173] (3) In the above-mentioned embodiments, the trench, gate electrode, and buffer electrode are formed in a manner that the semiconductor substrate is vertically cut in a plan view, but the present invention is not limited thereto. A long buffer electrode may be divided into two or more short strips for configuration (see the case where the buffer electrode is divided into two strips). Fig.18 Symbol 160a. Or the semiconductor device 106 in the fourth modification), the gate electrode 150 can also be short-divided into two or more pieces for configuration, and the buffer electrode and the gate electrode can also be short-divided into two or more pieces for configuration.

[0174] (4) In the above-mentioned embodiments, the buffer electrode 160 is formed in the groove 140, but the present invention is not limited thereto. The buffer electrode may be formed entirely outside the groove, that is, the buffer electrode may be formed at a position higher than the height position of the surface of the semiconductor substrate 110 in the region where the groove is not formed (see Fig.19 The buffer electrode 160b) may also be partially formed in the trench and the other part may be formed at a position higher than the surface height of the semiconductor substrate 110.

[0175] (5) In the above-mentioned embodiments, although the metal plug Pg is used to make the source electrode 120 contact the source region and the base region, the present invention is not limited to this. A high-concentration p-type diffused semiconductor region can also be formed on the semiconductor substrate to make the source electrode 120 contact the source region and the base region. In this case, in the contact region forming step, the semiconductor substrate can be etched without etching, and p-type impurities can be introduced into the semiconductor substrate (for example, ion implantation, epitaxial growth, etc.) to form a p-type diffused semiconductor region, or the p-type diffused semiconductor region can be formed without intentionally forming the p-type diffused semiconductor region. In addition, in the above-mentioned embodiments, although n-type impurities are ion-implanted into a region of an entire surface of the semiconductor substrate, a mask can also be used to selectively ion-implant n-type impurities into the semiconductor substrate.

[0176] (6) In the above-mentioned embodiments, although the buffer electrode 160 is connected to the drain electrode in the peripheral region via the metal plug Pg and the n-type semiconductor layer 117 formed in a manner penetrating the third insulating region 176, the present invention is not limited thereto. The buffer electrode 160 may also be connected to the drain electrode 130 via a side portion of the semiconductor substrate or a channel stopper electrode (not shown). In addition, a circuit substrate 200 having an insulating substrate 210 and a wiring 220 arranged on the insulating substrate 210 may be prepared, and a semiconductor device 109 (having the same structure as the semiconductor device 100 involved in the first embodiment) may be arranged on the wiring 220 of the circuit substrate 200 via a conductive bonding material S (such as solder, etc.), and the drain electrode 130 is electrically connected to the wiring 220, and the wiring 220 is further connected to the drain pad DP via a connecting member such as a bonding wire W, thereby connecting the drain pad DP to the drain electrode 130 (refer to Fig.21 ). In addition, in this case, in order to connect the drain pad DP and the drain electrode 130 in the semiconductor substrate, it is not necessary to connect the drain pad DP and the semiconductor substrate 110 using the metal plug Pg.

[0177] (7) In each of the above-mentioned embodiments, a drain pad is formed, but the present invention is not limited to this. The drain pad may not be formed.

[0178] (8) In the above embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is not limited thereto. The first conductivity type may be p-type and the second conductivity type may be n-type.

[0179] Explanation of symbols

[0180] 100, 101, 102, 102a, 103, 104, 105, 106, 107, 108, 109…semiconductor device; 110…semiconductor substrate; 112…drift layer; 113…base region; 114…source region; 115…n-type column region; 116…p-type column region; 120…source electrode; 130…drain electrode; 140…trench; 142…bottom; 144…sidewall; 150…gate electrode; 160…buffer electrode; 170…first insulating region, 170'…first insulating film, 172…gate insulating film; 174…second insulating region; 174'…second insulating film, 190…shielding electrode.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor substrate having a drift layer of a first conductivity type, a base region of a second conductivity type formed on a surface of the drift layer, and a source region of the first conductivity type formed on a surface of the base region; A source electrode formed on one surface side of the semiconductor substrate; a drain electrode formed on the other surface side of the semiconductor substrate; a plurality of trenches formed on a surface of the semiconductor substrate and having a bottom adjacent to the drift layer and sidewalls adjacent to the drift layer, the base region and the source region; a plurality of first electrodes, arranged in the trenches via gate insulating films respectively formed on the side walls of the plurality of trenches, and having side surfaces facing the base region; a plurality of second electrodes formed above each of the first electrodes in a state of being separated from the first electrodes; a first insulating region formed between the bottom of the trench and the first electrode to separate the first electrode from the bottom of the trench; as well as a second insulating region extending between the second electrode and the first electrode to separate the second electrode from the first electrode, and extending between the second electrode and the sidewall of the trench to separate the second electrode from the sidewall of the trench, The groove, the first electrode and the second electrode are formed in stripe shapes when viewed from a plane. At least one of the plurality of second electrodes is connected to the drain electrode, The second electrode is disposed in the groove, The first electrode is a gate electrode, The second electrode is a buffer electrode and is arranged at a position opposite to the source region via the second insulating region to form a buffer circuit using a parasitic capacitance between the second electrode and the source region as a capacitor and an internal resistance of the second electrode itself as a resistor.

2. The semiconductor device according to claim 1, wherein: in, The thickness of the second insulating region between the sidewall of the trench and the second electrode is thicker than the thickness of the gate insulating film.

3. The semiconductor device according to claim 1, wherein: in, At least a portion of the second electrode is disposed above a height position of the one surface of the semiconductor substrate where the trench is not formed.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that: Further including: A shielding electrode is located between the first electrode in the trench and the bottom of the trench, separated from the bottom of the trench, the sidewall of the trench and the first electrode, and electrically connected to the source electrode or the first electrode.

5. The semiconductor device according to any one of claims 1 to 3, characterized in that: in, The semiconductor substrate further includes: a plurality of second conductive type pillar regions formed at predetermined intervals in a region deeper than the bottom of the base region, The drift layer between adjacent second conductive type column regions constitutes a first conductive type column region, The first conductive type column region and the second conductive type column region form a super junction structure.

6. The semiconductor device according to any one of claims 1 to 3, characterized in that: in, The second electrode is made of polycrystalline silicon containing impurities at a predetermined concentration.

7. The semiconductor device according to any one of claims 1 to 3, characterized in that: in, The depth position of the lower surface of the second electrode is shallower than the depth position of the lowest portion of the contact surface with the trench in the source region.

8. A method for manufacturing a semiconductor device, for manufacturing the semiconductor device according to any one of claims 1 to 7, characterized in that: Contains: A semiconductor substrate preparation step of preparing a semiconductor substrate having a drift layer of a first conductivity type; A groove forming step of forming a plurality of grooves that appear to be stripes when viewed from a plane; A first insulating film forming step, wherein a first insulating film is formed at the bottom and sidewalls of each of the plurality of trenches, thereby forming a first insulating region at the bottom of each of the plurality of trenches and a gate insulating film at the sidewalls of each of the plurality of trenches; A first electrode forming step of forming a first electrode in the trench via the gate insulating film, wherein the first electrode is a gate electrode; a second insulating film forming step of forming a second insulating film on a surface of the first insulating film on a side wall of the trench and on a surface of the first electrode; a second electrode forming step of forming a second electrode above the first electrode in a state of being separated from the first electrode via the second insulating film, wherein the second electrode is a buffer electrode, is arranged in the trench, and is arranged at a position opposite to the source region via the second insulating region, so as to form a buffer circuit in which a parasitic capacitance between the second electrode and the source region is used as a capacitor and an internal resistance of the second electrode itself is used as a resistor; as well as The source electrode / drain electrode forming step includes a step of forming a source electrode on one surface side of the semiconductor substrate and a step of forming a drain electrode on the other surface side of the semiconductor substrate.

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