A cross-connection device and a clock keeping method and system thereof

Abstract

The cross-connection device and clock keeping method and system provided by the embodiment of the present invention detect the frequency deviation between the local reference clock and the system reference clock in the normal state; adjust the frequency of the local reference clock according to the frequency deviation, so that the local reference clock tracks the system reference clock, and record the adjustment parameters of the frequency adjustment and the corresponding adjustment time; when in the holding state, adjust the local reference clock according to the recorded adjustment parameters and the corresponding adjustment time, and output the local reference clock; it can be seen that when in the holding state, each service board can adjust the frequency with reference to the system reference clock, thereby improving the synchronization of the local reference clocks of each service board, and the service is not easily interrupted.

Description

Technical Field

[0001] The embodiments of the present invention relate to, but are not limited to, the field of communications, and specifically, relate to, but are not limited to, a cross-connection device and a clock keeping method and system thereof. Background Art

[0002] Centralized cross-connect systems, such as OTN (Optical Transmission Net) centralized cross-connect systems, require that all service boards in the same subframe must use the same system clock and the same phase 8K frame header (8000 clock pulses per second), otherwise the service will be interrupted. In the prior art, usually under normal circumstances, each service board uses the same external input clock as the reference clock. When the external clock cannot be received, the local clock is used as the reference clock. Although the local clock of each service board has the same frequency as the external clock, due to factors such as deviations in the local clock frequency of each service board, inconsistent stability of the local clock of each service board, and environmental influences, the local clocks of each service board are usually unable to be synchronized, resulting in large deviations in the 8K signals of each service board, which can easily cause service interruptions. Summary of the invention

[0003] The cross-connection device and the clock keeping method and system provided by the embodiment of the present invention mainly solve the technical problem that after the system reference clock is lost, the use of the local reference clock is likely to cause service interruption.

[0004] In order to solve the above technical problems, an embodiment of the present invention provides a clock holding method, comprising:

[0005] Get the system reference clock;

[0006] Generating a local reference clock having the same frequency as the system reference clock;

[0007] In a normal state, detecting a frequency deviation between the local reference clock and the system reference clock;

[0008] Adjusting the frequency of the local reference clock according to the frequency deviation so that the local reference clock tracks the system reference clock, and recording adjustment parameters of the frequency adjustment and their corresponding adjustment time;

[0009] In the hold state, the local reference clock is adjusted according to the adjustment parameter and its corresponding adjustment time, and the local reference clock is output.

[0010] The embodiment of the present invention further provides a clock holding system, comprising:

[0011] A local clock generating circuit, used for generating a local reference clock having the same frequency as the system reference clock;

[0012] A state control circuit, used for determining the state of the clock holding system, wherein the state of the clock holding system includes a normal state and a holding state;

[0013] A frequency deviation detection circuit, used for detecting the frequency deviation between the local reference clock and the system reference clock in the normal state, and obtaining an adjustment parameter for adjusting the frequency of the local reference clock according to the frequency deviation, so that the local reference clock tracks the system reference clock;

[0014] A frequency adjustment recording circuit, used for recording the adjustment parameters of the frequency adjustment and the corresponding adjustment time in the normal state; and outputting the adjustment parameters according to the adjustment parameters and the corresponding adjustment time in the holding state;

[0015] The local clock generating circuit is further used to adjust the frequency of the local reference clock according to the adjustment parameter output by the frequency deviation detecting circuit in the normal state; and to adjust the frequency of the local reference clock according to the adjustment parameter output by the frequency adjustment recording circuit in the hold state;

[0016] The clock source selection circuit is used to obtain the system reference clock and the local reference clock output by the local clock generation circuit, output the system reference clock in the normal state, and output the local reference clock in the holding state.

[0017] An embodiment of the present invention further provides a cross-connection device, including:

[0018] A main clock board is provided with a main system clock source, and the main system clock source is used to output a main system clock and a main system second pulse signal;

[0019] A backup clock board is provided with a backup system clock source, and the backup system clock source is used to output a backup system clock and a backup system second pulse signal;

[0020] One or more service boards for processing services are provided with the clock holding system as described above, wherein the clock source selection circuit of the clock holding system is further used to select one of the main system clock and the backup system clock as the system reference clock, and select one of the main system second pulse signal and the backup system second pulse signal as the system reference second pulse signal;

[0021] Cross-connect board, used for data cross-connection.

[0022] An embodiment of the present invention further provides a cross-connection device, including a processor, a memory, and a communication bus;

[0023] The communication bus is used to realize the connection and communication between the processor and the memory;

[0024] The processor is used to execute one or more computer programs stored in the memory to implement the steps of the clock keeping method as described above.

[0025] An embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores one or more computer programs, and the one or more computer programs can be executed by one or more processors to implement the steps of the clock keeping method as described above.

[0026] According to the cross-connection device and its clock holding method and system provided by the embodiment of the present invention, in normal state, the frequency deviation between the local reference clock and the system reference clock is detected; the frequency of the local reference clock is adjusted according to the frequency deviation, so that the local reference clock tracks the system reference clock, and the adjustment parameters of the frequency adjustment and the corresponding adjustment time are recorded; in the holding state, the local reference clock is adjusted according to the adjustment parameters and the corresponding adjustment time, and the local reference clock is output; it can be seen that in the holding state, each service board can adjust the frequency with reference to the system reference clock, thereby improving the synchronization of the local reference clocks of each service board, and the service is not easily interrupted.

[0027] Other features and corresponding beneficial effects of the present invention are described in the latter part of the specification, and it should be understood that at least part of the beneficial effects become obvious from the description in the specification of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Provide a block diagram of the existing clock keeping system;

[0029] Figure 2 This is a flowchart of a clock holding method according to a first embodiment of the present invention;

[0030] Figure 3 for Figure 2 Flowchart of step 4 in ;

[0031] Figure 4 A schematic diagram of signal flow in a normal state in a clock holding system according to a second embodiment of the present invention;

[0032] Figure 5 A schematic diagram of signal flow in a holding state in a clock holding system according to a second embodiment of the present invention;

[0033] Figure 6 The figure is a schematic diagram of signal transmission between a clock board and a service board in the cross-connection device of the present invention. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the following is a further detailed description of the embodiments of the present invention through specific implementation methods combined with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0035] like Figure 1 As shown, in the prior art, the system provides the main system clock source SCK_A and the main second pulse synchronization signal 1PPS_A to all slot line cards through the main clock board, and the backup clock board provides the backup system clock source SCK_B signal and the backup second pulse synchronization signal 1PPS_B signal to all slot line cards. At the same time, each line card will also generate a local clock source L_CLK and a local second pulse synchronization signal 1PPS_L. Each line card selects one as the system reference clock source SCK and the system reference second pulse signal 1PPS according to the status of the main clock board and the backup clock board. Each line card uses the selected system reference clock source SCK signal to generate the required system clock: system clock SYSCLK_A and system clock SYSCLK_B. The system clock SYSCLK_A is used for line card OTN framing and lower backplane signal processing. The system clock SYSCLK_B and the system reference second pulse signal 1PPS jointly generate the 8K frame header signal required by the line card.

[0036] When the master clock board / backup clock board is normal, each line card will give priority to the system reference clock source (SCK_A / SCK_B) and system reference 1PPS second pulse signal (1PPS_A / 1PPS_B) provided by the master clock board / backup clock board to ensure that each line card generates a system clock with the same source as the clock cross board and an 8K frame header signal with the same phase. When the line card detects that the master clock board / backup clock board of the system is lost, the line card needs to use the local clock source to generate the local system clock and 8K frame header signal. At this time, because the accuracy and stability of the local clock source are not as good as the master clock board / backup clock board, the local system clock and 8K frame header signal of the line card are not from the same source as the clock cross board clock in the system, so the instability of the local system clock is easy to cause service interruption.

[0037] The cross-connection device and the clock keeping method and system provided by the present invention obtain the frequency relationship between the local reference clock LCK and the system reference clock SCK by tracking the system reference clock. After the system reference clock is lost, the local reference clock LCK is adjusted according to this frequency relationship. The adjusted local reference clock LCK is closer to the system reference clock SCK, more stable, and more able to meet business needs, thereby realizing the clock keeping function. The specific process is described by the following embodiments.

[0038] Embodiment 1:

[0039] In order to improve the consistency of the local reference clocks of each service board, an embodiment of the present invention provides a clock maintenance method, which can be applied in application scenarios where a local clock is required to provide a clock signal when an external clock source is interrupted, such as in various centralized cross-connection systems, especially OTN electrical cross-connection equipment.

[0040] See also Figure 2 and Figure 4 , Figure 2 The flowchart of a clock holding method of an embodiment includes steps 1 to 9. The order of these steps is not limited to the order from 1 to 9. The order between some steps can be adjusted without affecting the clock holding. The following is a specific description:

[0041] Step 1, obtain the system reference clock and the system reference second pulse signal. For example, receive the main system clock SCK_A and the main system second pulse signal 1PPS_A output by the main system clock source, receive the backup system clock SCK_B and the backup system second pulse signal 1PPS_B output by the backup system clock source; select one of the signals output by the main system clock source (main system clock and main system second pulse signal) and the signals output by the backup system clock source (backup system clock and backup system second pulse signal) as the system reference clock SCK and the system reference second pulse signal 1PPS. Usually, when both clock sources are normal, the main system clock SCK_A can be selected as the system reference clock SCK and the main system second pulse signal 1PPS_A can be selected as the system reference second pulse signal 1PPS. When the main system clock source is abnormal, for example, when the clock signal output by the main system clock source cannot be received, the signal output by the backup system clock source is used as the system reference clock SCK and the system reference second pulse signal 1PPS. The system reference clock is also the system reference clock signal.

[0042] Step 2: Generate a local reference clock LCK with the same frequency as the system reference clock SCK, that is, the frequency of the generated local reference clock LCK is theoretically the same as the frequency of the system reference clock SCK. For example, a local clock p_clk with the same nominal (theoretical) frequency as the system reference clock SCK is generated by a local high stability clock (High Stability LocalClock) and a frequency synthesizer, and the local clock p_clk is adjusted, such as fine-tuned, to obtain the local reference clock LCK, which is nominally the same frequency as the system reference clock SCK, but in fact has a frequency closer to the system reference clock SCK than the local clock p_clk.

[0043] Step 3, the clock holding system has two states, one is the normal state and the other is the holding state, and it switches between these two states. In the normal state, the system reference clock SCK and the system reference second pulse signal 1PPS are output, and the frequency deviation between the local reference clock LCK and the system reference clock SCK is detected. Although the local reference clock LCK and the system reference clock SCK are theoretically the same frequency, in fact, the system reference clock SCK and the local reference clock LCK are not absolutely stable, so LCK needs to be fine-tuned according to the frequency deviation between the two. For example, Figure 3 As shown, step 3 may specifically include the following steps:

[0044] Step 31: Generate a local pulse per second signal LCK_1PPS according to the local reference clock LCK. For example, the local reference clock LCK is divided by a counter to generate the local pulse per second signal LCK_1PPS.

[0045] Step 32, based on the system reference clock SCK, the system reference pulse second signal 1PPS and the local pulse second signal LCK_1PPS, calculate the relative position of the phase between the local pulse second signal LCK_1PPS and the system reference pulse second signal 1PPS. For example, a reference counter PPS_STAMP_CNT is generated using the system reference clock SCK and the system reference pulse second signal 1PPS. The reference counter accumulates 1 at each rising edge of the system reference clock SCK and is cleared at the rising edge of the second pulse of the system reference pulse second signal 1PPS. The maximum count value of the reference counter PPS_STAMP_CNT within a 1-second period, that is, the number of system reference clock pulse signals within 1s of the system reference pulse second signal 1PPS, is recorded as MAX. In the frequency deviation detection process, the reference counter PPS_STAMP_CNT is used to measure the phase difference and phase difference change between the local reference clock LCK and the system reference clock SCK.

[0046] At the rising edge of each local pulse-per-second signal LCK_1PPS, the value of the reference counter PPS_STAMP_CNT is recorded as TIME_STAMP, and the value is used to record the relative position between the phases of the local pulse-per-second signal LCK_1PPS and the system reference pulse-per-second signal 1PPS.

[0047] Furthermore, in order to more clearly record the relative phase position between the local pulse-per-second signal LCK_1PPS and the system reference pulse-per-second signal 1PPS, a symbol number may be used to represent the phase advance or phase lag, which is recorded as TIME_STAMP_SIGN. If TIME_STAMP is less than (MAX+1) / 2, TIME_STAMP_SIGN takes the value of (+TIME_STAMP), indicating that the phase of the local pulse-per-second signal LCK_1PPS lags behind the system reference pulse-per-second signal 1PPSTIME_STAMP system reference clock cycles; if TIME_STAMP is not less than (MAX+1) / 2, TIME_STAMP takes the value of {-(MAX+1-TIME_STAMP)}, indicating that the phase of the local pulse-per-second signal LCK_1PPS leads the system reference pulse-per-second signal 1PPS by (MAX+1-TIME_STAMP) system reference clock cycles.

[0048] Step 33, obtain the reference relative position, and obtain the change of the relative position relative to the reference relative position according to the relative position and the reference relative position. To obtain the reference relative position, a relative position can be selected as the reference relative position after the frequency of the local reference clock is adjusted. For example, in this embodiment, the initial reference relative position can be any value. After the frequency of the local reference clock is adjusted, the first relative position is selected as the reference relative position, and the phase relative position TIME_STAMP_SIGN between the current local pulse second signal LCK_1PPS and the system reference pulse second signal 1PPS is compared with the selected reference relative position TIME_STAMP_SIGN_INIT to obtain the change TIME_STAMP_SIGN_OFFSET of the relative position of the current local pulse second signal LCK_1PPS relative to the reference relative position.

[0049] Step 34, calculate the time interval between the moment of selecting the reference relative position and the moment of the relative position corresponding to the current change, divide the current change by the time interval, and obtain the frequency deviation between the current local reference clock and the system reference clock. For example, the system reference clock SCK and the local second pulse signal LCK_1PPS are used to drive the second counter MEAR_CNT, and under the system reference clock SCK, 1 is accumulated at each rising edge of the local second pulse signal LCK_1PPS, and it is cleared after each update of the reference relative position TIME_STAMP_SIGN_INIT. The second counter MEAR_CNT is used to record the time interval between the phase relative position latching moment of the current local second pulse signal LCK_1PPS and the moment when the reference relative position is generated, in seconds (S). Calculate the frequency deviation between the local reference clock LCK and the system reference clock SCK: Freq_Offset = TIME_STAMP_SIGN_OFFSET / MEAR_CNT.

[0050] Step 4, adjust the frequency of the local reference clock according to the frequency deviation, so that the local reference clock tracks the system reference clock. There are many ways to trigger the frequency adjustment of the local reference clock, for example, determine whether the frequency deviation exceeds a preset deviation threshold, if so, adjust the frequency of the local reference clock, otherwise do not adjust the frequency of the local reference clock, the deviation threshold can be set according to actual needs. For another example, because the change in the relative position of the phase between LCK_1PPS and 1PPS reflects the frequency deviation between the local reference clock and the system reference clock, it is also possible to determine whether the change in the relative position exceeds a preset change threshold, if so, adjust the frequency of the local reference clock, otherwise do not adjust the frequency of the local reference clock, the change threshold can be set according to actual needs.

[0051] Furthermore, a frequency fine-tuning circuit such as a Sigma-Delta frequency fine-tuning circuit may be used to adjust the frequency of the local reference clock, and the frequency fine-tuning may be performed in the following manner:

[0052] By adjusting the parameter M (adjustment parameter) of the Sigma-Delta frequency fine-tuning circuit, the frequency adjustment of the local reference clock LCK is achieved. Further, the method of adjusting the parameter M is as follows:

[0053] According to the nominal frequency relationship between the local reference clock LCK and the system reference clock SCK, the nominal value is taken as the initial value of the parameter M. For example, the local high stability clock (High Stability Local Clock) outputs a clock signal HS_LCK, the frequency synthesizer receives HS_LCK and outputs a local clock p_clk with the same frequency as the system reference clock nominally. Initially, the Sigma-Delta frequency fine-tuning circuit uses the initial value of the adjustment parameter M to fine-tune p_clk so that the local reference clock LCK output by it is closer to the system reference clock SCK.

[0054] When the adjustment parameter M needs to be modified, calculate M_DIFF = B × Freq_Offset = B × (TIME_STAMP_SIGN_OFFSET / MEAR_CNT), where M_DIFF is the adjustment amount of the adjustment parameter M, B is the proportional constant, and the sign bit of M_DIFF is the same as the sign bit of TIME_STAMP_SIGN_OFFSET. The initial value of the adjustment parameter M is usually a theoretical value, and the subsequent adjustment belongs to fine-tuning, which generally does not exceed the preset range. In order to ensure that the adjustment amount of the adjustment parameter M is within the set range, if the absolute value of M_DIFF is less than the preset adjustment amount threshold, the current M is subtracted from M_DIFF as the new M. If the absolute value of M_DIFF is not less than the preset adjustment amount threshold, M takes the initial value. The adjustment amount threshold can be set according to actual needs. Since in this embodiment, the frequency adjustment of the local reference clock belongs to fine-tuning, the frequency adjustment range of the local reference clock can be limited. For example, (f 理LCK -f 实LCK ) divided by the absolute value of f 理LCK Less than or equal to 20 PPM (parts per million), in this embodiment, (f 理LCK -f 实LCK ) divided by the absolute value of f 理LCK Less than or equal to 10PPM. 理LCK is the theoretical frequency of the local reference clock LCK; f 实LCK is the actual frequency of the local reference clock LCK; the setting range of the adjustment amount, the adjustment amount threshold, etc. can be set accordingly according to this limitation.

[0055] After obtaining the adjustment parameter M, the Sigma-Delta frequency fine-tuning circuit adjusts the frequency of the local reference clock LCK according to the adjustment parameter M. Specifically, the Sigma-Delta frequency fine-tuning circuit uses the adjustment parameter M to adjust the local clock p_clk, obtains the corresponding local reference clock LCK and outputs it.

[0056] Step 5, record the frequency adjustment adjustment parameter M and its corresponding adjustment time. In this embodiment, the frequency adjustment adjustment parameter M and its corresponding adjustment time within the first preset time period before entering the hold state are recorded. The first preset time period can be set as needed, for example, it can be 1 hour, that is, the frequency adjustment adjustment parameter M and its corresponding adjustment time within 1 hour before entering the hold state (normal state) are recorded, or it can be 30 hours, or it can be a time between 1 hour and 30 hours, or a time of more than 30 hours. Specifically, each time the parameter M of the Sigma-Delta frequency fine-tuning circuit is adjusted, the adjustment parameter M is recorded, and the counter MEAR_CNT is cleared to record the next time the local reference clock LCK frequency is adjusted relative to this time. That is, each time the LCK frequency adjustment is completed according to the set frequency deviation threshold condition, the reference relative position TIME_STAMP_SIGN_INIT is updated, and the currently recorded relative position TIME_STAMP_SIGN is used as the new reference relative position.

[0057] Further, the method for adjusting the parameter M cache is as follows:

[0058] Under normal conditions, when a new adjustment parameter M is calculated, the value of the adjustment parameter M and the adjustment time of M need to be cached for adjusting the frequency of the local reference clock in the hold state. For example, the adjustment parameter for frequency adjustment and the corresponding elapsed seconds are stored, and the elapsed seconds are updated so that the elapsed seconds are the time interval from the moment of adjusting the adjustment parameter to the current moment, until the hold state is entered or the time interval is equal to the second preset time period. Specifically, a memory M_TABLE is reserved in the FPGA, and each address of M_TABLE stores two fields, adjustment parameter M and elapsed seconds. The elapsed seconds are the time interval from the moment of adjusting the local reference clock frequency to the current moment, and the maximum value of the elapsed seconds corresponding to the same adjustment parameter is the time interval from the moment of adjusting the local reference clock frequency to the moment of entering the hold state. Each time the adjustment parameter M is adjusted, the value of the adjustment parameter M is written in the write pointer address, 1 is written in the elapsed seconds field, and the write pointer address is increased by 1. At the rising edge of LCK_1PPS, the elapsed seconds fields of all addresses are checked. If the elapsed seconds field of a certain address is not 0, the elapsed seconds field is incremented by 1 and then written into the elapsed seconds field of the address to complete the update of each elapsed seconds field; when the elapsed seconds field of a certain address is equal to the number of seconds in the second preset time period, the elapsed seconds field of the address is written to 0. In this way, when entering the hold state, the elapsed seconds field records the number of seconds between the time when M is adjusted in the second preset time period in the normal state and the time when the hold state is entered.

[0059] Step 6: Determine the system status of the clock maintenance system.

[0060] There are many specific ways, one of which is: determine the system state according to the received control instruction (such as a message), for example, when a message for entering the holding state is received, control the clock holding system to enter the holding state and enter step 7; when no message for entering the holding state is received, maintain the original state, that is, the clock holding system maintains a normal state, and enters step 3. The control instruction can be issued by the main clock board or the standby clock board, or by other devices.

[0061] The other is: when the system reference clock and the system reference second pulse signal can be obtained, it is determined to be in a normal state, that is, the control clock keeps the system in a normal state, and enters step 3; when the system reference clock and the system reference second pulse signal cannot be obtained, it is determined to be in a holding state, that is, the control clock keeps the system in a holding state, and enters step 7. For example, the main system clock SCK_A and the main system second pulse signal 1PPS_A can be received, that is, the system reference clock and the system reference second pulse signal can be obtained, and it is determined to be in a normal state; the backup system clock SCK_B and the backup system second pulse signal 1PPS_B can be received, that is, the system reference clock and the system reference second pulse signal can be obtained, and it is determined to be in a normal state; if SCK_A, 1PPS_A, SCK_B and 1PPS_B cannot be received, the system reference clock and the system reference second pulse signal cannot be obtained, and it is determined to be in a holding state.

[0062] Another method is: when the obtained system reference clock and system reference second pulse signal are normal, it is determined to be a normal state, that is, the control clock holding system enters a normal state, and enters step 3; when the obtained system reference clock and system reference second pulse signal are abnormal, it is determined to be a holding state, that is, the control clock holding system enters a holding state, and enters step 7. In the above method, failure to obtain SCK and 1PPS is essentially an abnormality, so it will not be repeated.

[0063] Make sure that the system state is not affected by other steps, that is, the order of step 6 is not limited. Figure 2 The location in is just an example.

[0064] Step 7: In the hold state, the local reference clock is adjusted according to the adjustment parameters and the corresponding adjustment moments. In this embodiment, the adjustment parameters and the corresponding adjustment moments within the first preset time period are recorded, and the local reference clock is adjusted according to the adjustment parameters and the corresponding adjustment moments recorded within the second preset time period, and the local reference clock is output, that is, the adjusted local reference clock is output. The second preset time period can also be set according to actual needs, for example, 24 hours, and the second preset time period can be the same as or different from the first preset time period. For example, the adjustment parameters M and the adjustment moments within the first preset time period before entering the hold state are recorded, and the frequency is adjusted using the adjustment parameters and the adjustment moments within the second preset time period before entering the hold state. Among the adjustment parameters and the corresponding adjustment moments recorded within the second preset time period, the adjustment parameters are selected in sequence to adjust the local reference clock in the order of the adjustment moments corresponding to the adjustment parameters from near to far, wherein the duration of adjustment using the adjustment parameters can be the time interval between the adjustment moment corresponding to the current adjustment parameter and the adjustment moment corresponding to the next adjustment parameter. Assuming that under normal conditions, the adjustment moments corresponding to two adjacent adjustment parameters M1 and M2 (the moments when M1 and M2 are used to adjust the frequency) are t1 and t2 respectively, and the holding state is entered at moment t3 after t2, then M2 is used to adjust the local reference clock, and the duration is the time interval from t2 to t3, and then M1 is used to adjust the local reference clock, and the duration is the time interval from t1 to t2.

[0065] Specifically, in the hold state, all service boards adjust the parameter M of the sigma_delta frequency fine-tuning circuit according to the adjustment parameter M and the elapsed seconds field in M_TABLE. When entering the hold state, the read address pointer of M_TABLE is equal to the write address pointer in the normal state. At the rising edge of HOLD_1PPS (local second pulse signal in the hold state), it is determined whether the elapsed seconds field of the current read pointer address is 1. If the elapsed seconds field is 1, the adjustment parameter M at the current read pointer address is used to replace the parameter M of the sigma_delta frequency fine-tuning circuit, and then the read pointer address is reduced by 1; at the same time, the elapsed seconds field of all addresses in M_TABLE is checked. If the elapsed seconds field of a certain address is not 0, the elapsed seconds field is reduced by 1 and then written into the elapsed seconds field of the address to complete the update of all elapsed seconds fields. In this way, the M recorded in the second preset time period in the normal state in M_TABLE is used to adjust the frequency of HOLD_CLK (local reference clock in the hold state) in the hold state.

[0066] Since the system reference clock and system reference second pulse signal output in the normal state are stable and reliable and can meet the index requirements, and the adjustment of the local reference clock in the hold state adopts the adjustment parameters corresponding to the normal state, the local reference clock output by each service board in the hold state is also stable and reliable, with good consistency. The clock retention performance meets the index requirements, allowing the service to be maintained long enough without being affected, thereby meeting user needs.

[0067] In the normal state, the target clock signal is generated and output according to the system reference clock SCK and the system reference second pulse signal 1PPS. The target clock signal can be an 8K frame header. For example, an 8K clock counter HOLD_8K_CNT is generated using the system reference clock. When the counter counts to the threshold value HOLD_8K_CNT_MAX, it is cleared to 0 and a HOLD_8K signal is generated. Each time HOLD_8K_CNT counts to the maximum value, the HOLD_8K clock signal phase flip is triggered. In the normal state, HOLD_8K_CNT is cleared to 0 at the rising edge of the system reference second pulse signal 1PPS to ensure that the generated HOLD_8K frame header is in phase with the system reference frame header.

[0068] In the hold state, the target clock signal is generated and output according to the local reference clock. For example, when the clock enters the hold state, HOLD_8K_CNT is no longer cleared to 0 using the system reference pulse per second signal 1PPS, and the counter HOLD_8K_CNT is kept in a free oscillation state, and is only cleared to 0 when the maximum threshold value HOLD_8K_CNT_MAX is counted, so that the output HOLD_8K frame header will be maintained within a stable range.

[0069] A pulse includes a rising edge and a falling edge. The above process uses the rising edge, and the falling edge can also be used to replace the above rising edge, which will not be elaborated here.

[0070] To sum up, the clock holding method provided by the present invention enables each service board to enter the clock holding state after the system clock source is lost, and the clock holding performance meets the index requirements, allowing the service to be maintained for a sufficiently long time without being affected, thereby meeting the needs of users.

[0071] Embodiment 2:

[0072] Please refer to Figure 4 and Figure 5 , Figure 4The structure block diagram of a clock holding system of an embodiment includes a local clock generating circuit 10, a clock source selecting circuit 30, a target signal generating circuit 40, a local second pulse generating circuit 60, a frequency deviation detecting circuit 70, a frequency adjustment recording circuit 80 and a state control circuit 90. The local clock generating circuit 10 is connected to an input end of the clock source selecting circuit 30 and an input end of the local second pulse generating circuit 60; the output end of the clock source selecting circuit 30 is connected to the framer 50 through the target signal generating circuit 40. The output end of the local second pulse generating circuit 60 is connected to the frequency adjustment recording circuit 80 through the frequency deviation detecting circuit 70, and the frequency adjustment recording circuit 80 is connected to the local clock generating circuit 10 and the clock source selecting circuit 30 through the state control circuit 90. Most functions of the clock holding system can be realized by logic coding in the FPGA device.

[0073] The local clock generation circuit 10 is used to generate a local reference clock SCK with nominally the same frequency as the system reference clock. In this embodiment, the local clock generation circuit 10 includes a frequency synthesizer, a local high-stability clock and a frequency fine-tuning circuit 20. The local high-stability clock can use a high-stability crystal oscillator. The crystal oscillator generates a clock signal HS_LCK, the frequency synthesizer receives HS_LCK and outputs a local clock p_clk with nominally the same frequency as the system reference clock, and the frequency fine-tuning circuit 20 fine-tunes p_clk according to the received adjustment parameter M (including m and m_auto). It fine-tunes p_clk according to the initial value of the adjustment parameter M at the beginning to obtain a local reference clock LCK that is closer to the system reference clock. The frequency fine-tuning circuit 20 can use a Sigma-Delta frequency fine-tuning circuit.

[0074] The clock source selection circuit 30 is used to obtain the system reference clock and the system reference second pulse signal. For example, the input end of the clock source selection circuit 30 is connected to the main system clock source and the backup system clock source. The clock source selection circuit 30 receives the main system clock SCK_A and the main system second pulse signal 1PPS_A output by the main system clock source, and receives the backup system clock SCK_B and the backup system second pulse signal 1PPS_B output by the backup system clock source. When at least one of the main system clock source and the backup system clock source is normal, for example, when at least one of the output signals can be received, one of the signals output by the main system clock source (main system clock and main system second pulse signal) and the signals output by the backup system clock source (backup system clock and backup system second pulse signal) is selected as the system reference clock SCK and the system reference second pulse signal 1PPS. Usually, when both clock sources are normal, the main system clock SCK_A is preferentially selected as the system reference clock SCK and the main system second pulse signal 1PPS_A is preferentially selected as the system reference second pulse signal 1PPS. When the main system clock source is abnormal, for example, when the clock signal output by the main system clock source cannot be received, the signal output by the backup system clock source is used as the system reference clock SCK and the system reference second pulse signal 1PPS. The system reference clock is also the system reference clock signal.

[0075] like Figure 4 As shown, the clock source selection circuit 30 outputs the system reference clock SCK and the system reference pulse per second signal IPPS in a normal state, for example, when at least one of the main system clock source and the backup system clock source is available.

[0076] like Figure 5 As shown, the clock source selection circuit 30 outputs the local reference clock HOLD_CLK in the hold state.

[0077] The state control circuit 90 is used to determine the state of the clock holding system, and the state of the clock holding system includes a normal state and a holding state. There are many specific ways, one of which is: the state control circuit 90 determines the system state according to the received control instruction (such as a message), and outputs the signal state of the system state to the clock source selection circuit 30, the frequency adjustment recording circuit 80 and 70, etc. For example, when a message entering the holding state is received, the clock holding system is controlled to enter the holding state, and the holding state signal is output to the clock source selection circuit 30, the frequency adjustment recording circuit 80 and 70, etc.; when no message entering the holding state is received, the original state is maintained, that is, the clock holding system maintains a normal state, and the normal state signal is output to the clock source selection circuit 30, the frequency adjustment recording circuit 80 and 70, etc. The control instruction can be issued by the main clock board or the standby clock board, or by other devices.

[0078] The other is: when the clock source selection circuit 30 can obtain the system reference clock and the system reference second pulse signal, the state control circuit 90 determines it as a normal state, that is, controls the clock to keep the system into a normal state, and outputs the system state signal to 30, 80 and 70, etc.; when the clock source selection circuit 30 cannot obtain the system reference clock and the system reference second pulse signal, it is determined to be a holding state, that is, controls the clock to keep the system into a holding state, and outputs the holding state signal to 30, 80 and 70, etc. For example, the clock source selection circuit 30 can receive the main system clock SCK_A and the main system second pulse signal 1PPS_A, that is, it can obtain the system reference clock and the system reference second pulse signal, and is determined to be in a normal state; the clock source selection circuit 30 can receive the backup system clock SCK_B and the backup system second pulse signal 1PPS_B, that is, it can obtain the system reference clock and the system reference second pulse signal, and is determined to be in a normal state; if SCK_A, 1PPS_A, SCK_B and 1PPS_B are all not received, then the system reference clock and the system reference second pulse signal cannot be obtained, and it is determined to be in a holding state.

[0079] Another method is: when the system reference clock and system reference second pulse signal obtained by the clock source selection circuit 30 are normal, the state control circuit 90 determines that it is in a normal state, that is, the control clock holding system enters a normal state; when the system reference clock and system reference second pulse signal obtained by the clock source selection circuit 30 are abnormal, it is determined to be a holding state, that is, the control clock holding system enters a holding state. In the above method, failure to obtain SCK and 1PPS is essentially an abnormality, so it will not be described in detail.

[0080] In the normal state, the clock source selection circuit 30 outputs the system reference clock and the system reference second pulse signal. In the hold state, the clock source selection circuit 30 outputs the local reference clock. The frequency adjustment recording circuit 80 records the adjustment parameter M and the adjustment time in the normal state. In the hold state, the recorded adjustment parameter M is output according to the recorded adjustment time. In this embodiment, the frequency adjustment recording circuit 80 records the adjustment parameter M and the adjustment time in the first preset time period before entering the hold state in the normal state; in the hold state, the adjustment parameter M recorded in the second preset time period is output according to the recorded adjustment time. The first preset time period can be set as needed, for example, it can be 1 hour, that is, the frequency adjustment recording circuit 80 records the frequency adjustment adjustment parameter M and its corresponding adjustment time within 1 hour before entering the hold state (normal state), which can also be 30 hours, or a time between 1 hour and 30 hours, or a time of more than 30 hours. The state control circuit 90 outputs the adjustment parameter M calculated by the frequency deviation detection circuit 70 in real time in the normal state, and outputs the adjustment parameter M output by the frequency adjustment recording circuit 80 in the hold state. Figure 4In order to facilitate distinction, the adjustment parameters are represented by m_auto, m and M according to different output circuits; for the convenience of description, the adjustment parameter M (including m_auto, m) is used in the text content for general description.

[0081] The frequency deviation detection circuit 70 is used to detect the frequency deviation between the local reference clock LCK and the system reference clock SCK in a normal state, and obtain an adjustment parameter for adjusting the frequency of the local reference clock according to the frequency deviation, so that the local reference clock tracks the system reference clock.

[0082] Specifically, the local pulse per second generation circuit 60 generates the local pulse per second signal LCK_1PPS according to the local reference clock LCK. For example, the local pulse per second generation circuit 60 uses the second frequency division circuit to generate the local pulse per second signal LCK_1PPS by using the local reference clock LCK through a counter frequency division method.

[0083] The frequency deviation detection circuit 70 calculates the relative position of the phase between the local second pulse signal LCK_1PPS and the system reference second pulse signal 1PPS according to the system reference clock SCK output by the clock source selection circuit 30, the system reference second pulse signal 1PPS and the local second pulse signal LCK_1PPS output by the local second pulse generation circuit 60. For example, the frequency deviation detection circuit 70 generates a reference counter PPS_STAMP_CNT using the system reference clock SCK and the system reference second pulse signal 1PPS. The reference counter accumulates 1 at each rising edge of the system reference clock SCK and is cleared at the rising edge of the second pulse of the system reference second pulse signal 1PPS. The maximum count value of the reference counter PPS_STAMP_CNT within a 1-second period, that is, the number of system reference clock pulse signals within 1s of the system reference second pulse signal 1PPS, is recorded as MAX. In the process of frequency deviation detection, the reference counter PPS_STAMP_CNT is used to measure the phase difference and phase difference change between the local reference clock LCK and the system reference clock SCK.

[0084] The frequency deviation detection circuit 70 records the value of the reference counter PPS_STAMP_CNT as TIME_STAMP at the rising edge of each local pulse per second signal LCK_1PPS, and uses this value to record the relative position between the phases of the local pulse per second signal LCK_1PPS and the system reference pulse per second signal 1PPS.

[0085] Furthermore, in order to more clearly record the relative phase position between the local pulse-per-second signal LCK_1PPS and the system reference pulse-per-second signal 1PPS, a symbol number may be used to represent the phase advance or phase lag, which is recorded as TIME_STAMP_SIGN. If TIME_STAMP is less than (MAX+1) / 2, TIME_STAMP_SIGN takes the value of (+TIME_STAMP), indicating that the phase of the local pulse-per-second signal LCK_1PPS lags behind the system reference pulse-per-second signal 1PPS by TIME_STAMP system reference clock cycles; if TIME_STAMP is not less than (MAX+1) / 2, TIME_STAMP takes the value of {-(MAX+1-TIME_STAMP)}, indicating that the phase of the local pulse-per-second signal LCK_1PPS leads the system reference pulse-per-second signal 1PPS by (MAX+1-TIME_STAMP) system reference clock cycles.

[0086] The frequency deviation detection circuit 70 obtains the reference relative position, and obtains the variation of the relative position relative to the reference relative position according to the relative position and the reference relative position. To obtain the reference relative position, a relative position can be selected as the reference relative position after the frequency of the local reference clock is adjusted. For example, in this embodiment, the initial reference relative position can be any value, and after the frequency of the local reference clock is adjusted, the first relative position is selected as the reference relative position, and the phase relative position TIME_STAMP_SIGN between the current local pulse-per-second signal LCK_1PPS and the system reference pulse-per-second signal 1PPS is compared with the selected reference relative position TIME_STAMP_SIGN_INIT to obtain the variation TIME_STAMP_SIGN_OFFSET of the relative position of the current local pulse-per-second signal LCK_1PPS relative to the reference relative position.

[0087] The frequency deviation detection circuit 70 calculates the time interval between the moment of selecting the reference relative position and the moment of the relative position corresponding to the current change, and divides the current change by the time interval to obtain the frequency deviation between the current local reference clock and the system reference clock. For example, the system reference clock SCK and the local second pulse signal LCK_1PPS are used to drive the second counter MEAR_CNT, and under the system reference clock SCK, 1 is accumulated at each rising edge of the local second pulse signal LCK_1PPS, and it is cleared after each update of the reference relative position TIME_STAMP_SIGN_INIT. The second counter MEAR_CNT is used to record the time interval between the phase relative position latching moment of the current local second pulse signal LCK_1PPS and the moment when the reference relative position is generated, in seconds (S). The frequency deviation between the local reference clock LCK and the system reference clock SCK is calculated: Freq_Offset = TIME_STAMP_SIGN_OFFSET / MEAR_CNT.

[0088] The frequency deviation detection circuit 70 is also used to generate an adjustment parameter for frequency adjustment of the local reference clock according to the frequency deviation, so that the local reference clock tracks the system reference clock. There are many ways to trigger the frequency deviation detection circuit 70 to generate the adjustment parameter. For example, the frequency deviation detection circuit 70 determines whether the frequency deviation exceeds a preset deviation threshold. If it exceeds, the adjustment parameter is generated according to the frequency deviation. Otherwise, the adjustment parameter is not generated, that is, the frequency adjustment of the local reference clock is not performed. The deviation threshold can be set according to actual needs. For another example, because the change in the relative position of the phase between LCK_1PPS and 1PPS reflects the frequency deviation between the local reference clock and the system reference clock, the frequency deviation detection circuit 70 can also determine whether the change in the relative position exceeds a preset change threshold. If it exceeds, the adjustment parameter is generated according to the frequency deviation. Otherwise, the frequency adjustment of the local reference clock is not performed. The change threshold can be set according to actual needs.

[0089] Under normal conditions, the frequency deviation detection circuit 70 outputs the adjustment parameter to the frequency fine-tuning circuit 20 through the state control circuit 90, so that the frequency fine-tuning circuit 20 adjusts the frequency of the local reference clock.

[0090] Further, the frequency fine-tuning circuit 20 adopts Sigma-Delta modulation to adjust the frequency of the local reference clock LCK by changing the parameter M (adjustment parameter) that affects the frequency. Further, the frequency fine-tuning circuit 20 fine-tunes p_clk according to the received adjustment parameter M to obtain the adjusted local clock LCK (local reference clock), so that the local reference clock LCK is closer to the system reference clock SCK, and outputs the local reference clock LCK.

[0091] When the adjustment parameter M needs to be modified, the frequency deviation detection circuit 70 calculates M_DIFF=B×Freq_Offset=B×(TIME_STAMP_SIGN_OFFSET / MEAR_CNT), where M_DIFF is the adjustment amount of the adjustment parameter M, B is the proportional constant, and the sign bit of M_DIFF is the same as the sign bit of TIME_STAMP_SIGN_OFFSET. The initial value of the adjustment parameter M is usually a theoretical value, and the subsequent adjustment belongs to fine-tuning, which generally does not exceed a preset range. In order to ensure that the adjustment amount of the adjustment parameter M is within the set range, if the absolute value of M_DIFF is less than the preset adjustment amount threshold, the current M is subtracted from M_DIFF as the new M. If the absolute value of M_DIFF is not less than the preset adjustment amount threshold, M takes the initial value. The adjustment amount threshold can be set according to actual needs. Since in this embodiment, the frequency adjustment of the local reference clock belongs to fine-tuning, the frequency adjustment range of the local reference clock can be limited. For example, (f 理LCK -f 实LCK ) divided by the absolute value of f 理LCK Less than or equal to 20 PPM (parts per million), in this embodiment, (f 理LCK -f 实LCK ) divided by the absolute value of f 理LCK Less than or equal to 10PPM. 理LCK is the theoretical frequency of the local reference clock LCK; f 实LCK is the actual frequency of the local reference clock LCK; the setting range of the adjustment amount, the adjustment amount threshold, etc. can be set accordingly according to this limitation.

[0092] The frequency adjustment recording circuit 80 is used to record the adjustment parameters of the frequency adjustment and their corresponding adjustment moments. Specifically, each time the parameter M of the Sigma-Delta frequency fine-tuning circuit is adjusted, for example, each time the frequency deviation detection circuit 70 outputs the adjustment parameter M, the frequency adjustment recording circuit 80 records the adjustment parameter M and clears the counter MEAR_CNT to record the next time the local reference clock LCK frequency is adjusted relative to this time. That is, each time the LCK frequency adjustment is completed according to the set frequency deviation threshold condition, the reference relative position TIME_STAMP_SIGN_INIT is updated, and the currently recorded relative position TIME_STAMP_SIGN is used as the new reference relative position.

[0093] Under normal conditions, when the frequency deviation detection circuit 70 calculates a new adjustment parameter M, the frequency adjustment recording circuit 80 needs to cache the value of the adjustment parameter M and the time of adjusting M, and output it to the frequency fine-tuning circuit 20 in the hold state to adjust the frequency of the local reference clock. For example, the frequency adjustment recording circuit 80 stores the adjustment parameter of the frequency adjustment and the corresponding elapsed seconds, and updates the elapsed seconds so that the elapsed seconds are the time interval from the moment of adjusting the adjustment parameter to the current moment, until the hold state is entered or the time interval is equal to the second preset time period. Specifically, a memory M_TABLE is reserved in the FPGA, and each address of M_TABLE stores two fields, the adjustment parameter M and the elapsed seconds. The elapsed seconds are the time interval from the moment of adjusting the local reference clock frequency to the current moment, and the maximum value of the elapsed seconds corresponding to the same adjustment parameter is the time interval from the moment of adjusting the local reference clock frequency to the moment of entering the hold state. Each time the adjustment parameter M is adjusted, the value of the adjustment parameter M is written in the write pointer address, 1 is written in the elapsed seconds field, and the write pointer address is increased by 1. At the rising edge of LCK_1PPS, the elapsed seconds fields of all addresses are checked. If the elapsed seconds field of a certain address is not 0, the elapsed seconds field is incremented by 1 and then written into the elapsed seconds field of the address to complete the update of each elapsed seconds field; when the elapsed seconds field of a certain address is equal to the number of seconds in the first preset time period, the elapsed seconds field of the address is written to 0. In this way, when entering the hold state, the elapsed seconds field records the number of seconds between the time when M is adjusted in the second preset time period of the normal state and the time when the hold state is entered.

[0094] When the frequency fine-tuning circuit 20 is in the hold state, the local reference clock is adjusted according to the adjustment parameters and the corresponding adjustment moments recorded by the frequency adjustment recording circuit 80. In this embodiment, the frequency adjustment recording circuit 80 records the adjustment parameters and the corresponding adjustment moments within the first preset time period, and the frequency fine-tuning circuit 20 adjusts the local reference clock according to the adjustment parameters and the corresponding adjustment moments recorded therein within the second preset time period, and outputs the local reference clock LCK to the clock source selection circuit 30. The second preset time period can also be set according to actual needs, for example, 24 hours, and the second preset time period can be the same as or different from the first preset time period. For example, the frequency adjustment recording circuit 80 records the adjustment parameters M and the adjustment moments within the first preset time period before entering the hold state, and the frequency adjustment recording circuit 80 outputs the adjustment parameters within the second preset time period before entering the hold state to the frequency fine-tuning circuit 20. Among the adjustment parameters and the corresponding adjustment moments recorded within the second preset time period, the frequency fine-tuning circuit 20 selects the adjustment parameters in sequence to adjust the local reference clock in the order of the adjustment moments corresponding to the adjustment parameters from near to far, wherein the duration of adjustment using the adjustment parameters can be the time interval between the adjustment moment corresponding to the current adjustment parameter and the adjustment moment corresponding to the next adjustment parameter. Assuming that under normal conditions, the adjustment moments corresponding to two adjacent adjustment parameters M1 and M2 (the moments when M1 and M2 are used to adjust the frequency) are t1 and t2 respectively, and the holding state is entered at moment t3 after t2, then M2 is used to adjust the local reference clock, and the duration is the time interval from t2 to t3, and then M1 is used to adjust the local reference clock, and the duration is the time interval from t1 to t2.

[0095] Specifically, in the hold state, all service boards adjust the parameter M of the sigma_delta frequency fine-tuning circuit according to the adjustment parameter M and the elapsed seconds field in M_TABLE. When entering the hold state, the read address pointer of M_TABLE is equal to the write address pointer in the normal state. At the rising edge of HOLD_1PPS (local second pulse signal in the hold state), it is determined whether the elapsed seconds field of the current read pointer address is 1. If the elapsed seconds field is 1, the adjustment parameter M at the current read pointer address is used to replace the parameter M of the sigma_delta frequency fine-tuning circuit, and then the read pointer address is reduced by 1; at the same time, the elapsed seconds field of all addresses in M_TABLE is checked. If the elapsed seconds field of a certain address is not 0, the elapsed seconds field is reduced by 1 and then written into the elapsed seconds field of the address to complete the update of all elapsed seconds fields. In this way, the M recorded in the first preset time period in the normal state in M_TABLE is used to adjust the frequency of HOLD_CLK (local reference clock in the hold state) in the hold state.

[0096] The target signal generating circuit 40 is used to generate and output the target clock signal according to the signal output by the clock source selecting circuit 30. Specifically, in the normal state, the clock source selecting circuit 30 outputs the system reference clock SCK and the system reference second pulse signal 1PPS, and the target signal generating circuit 40 generates and outputs the target clock signal according to the system reference clock SCK and the system reference second pulse signal 1PPS output by the clock source selecting circuit 30. The target signal generating circuit 40 includes two clock chips and a first frequency dividing circuit. One clock chip generates the clock signal SYSCLK_A required by the framer 50 according to the system reference clock SCK, and the other clock chip generates the clock signal SYSCLK_B required by the first frequency dividing circuit according to the system reference clock SCK. The target clock signal can be an 8K frame header. The first frequency division circuit generates an 8K clock counter HOLD_8K_CNT according to the clock signal SYSCLK_B. The counter is cleared to 0 when it counts to the threshold value HOLD_8K_CNT_MAX, and a HOLD_8K signal is generated. Each time HOLD_8K_CNT counts to the maximum value, the HOLD_8K clock signal phase flip is triggered. Under normal conditions, HOLD_8K_CNT is cleared to 0 at the rising edge of the system reference second pulse signal 1PPS, ensuring that the generated HOLD_8K frame header is in phase with the system reference frame header.

[0097] In the hold state, the clock source selection circuit 30 outputs the local reference clock HOLD_CLK (the adjusted local reference clock LCK output by the frequency fine-tuning circuit 20), and the target signal generation circuit 40 generates and outputs the target clock signal according to the local reference clock HOLD_CLK output by the clock source selection circuit 30. Similarly, one clock chip generates the clock signal SYSCLK_A required by the framer 50 according to the local reference clock HOLD_CLK, and another clock chip generates the clock signal SYSCLK_B required by the first frequency division circuit according to the local reference clock HOLD_CLK. HOLD_8K_CNT is no longer cleared to 0 using the system reference second pulse signal 1PPS, and the counter HOLD_8K_CNT is kept in a free oscillation state, and is only cleared to 0 when the maximum threshold value HOLD_8K_CNT_MAX is counted, so that the output HOLD_8K frame header will be maintained within a stable range.

[0098] A pulse includes a rising edge and a falling edge. The above process uses the rising edge, and the falling edge can also be used to replace the above rising edge, which will not be elaborated here.

[0099] In summary, when there is a system clock source (SCK_A / SCK_B / 1PPS_A / 1PPS_B), according to the master-slave state, a system clock source is selected as the system reference clock source SCK and the system reference second pulse signal 1PPS through the clock source selection circuit 30. The system reference second pulse signal 1PPS can be used to synchronize various service boards. A local clock with the same frequency as the system reference clock source SCK is generated by the frequency synthesizer and the high stability local clock source (High Stability Local Clock). The frequency fine-tuning circuit 20 fine-tunes the local clock to obtain the local reference clock LCK. The frequency deviation detection circuit 70 detects the frequency deviation between the local reference clock LCK and the system reference clock source SCK. According to the frequency detection result, the frequency fine-tuning circuit 20 fine-tunes the local reference clock LCK so that the local reference clock LCK tracks the system reference clock source SCK. While fine-tuning the local reference clock LCK, the adjustment time and adjustment value of each adjustment are recorded, and the adjustment value is represented by the parameter M in the frequency fine-tuning circuit 20. By recording each adjustment time and adjustment value within a sufficiently long period of time, that is, recording the frequency relationship between the local reference clock LCK and the system reference clock SCK within this period of time, when the system reference clock source is lost, according to the recorded frequency relationship between the local reference clock LCK and the system reference clock SCK, a holding reference clock HOLD_CLK and a holding 1PPS second pulse signal HOLD_1PPS with performance indicators meeting the requirements can be generated through the local reference clock LCK and the frequency fine-tuning circuit 20, thereby realizing the clock holding function.

[0100] Compared with the existing methods of maintaining the crystal output clock using a maintenance algorithm obtained from the aging characteristics of the crystal, and generating a synchronous clock according to a prediction equation using a digital phase-locked loop, the method adopted by the present invention not only has the clock maintenance performance meeting the index requirements and the service maintenance time meeting the customer needs, but also has the advantages of simple implementation, low cost, and online upgrade of the function. It is applicable to but not limited to OTN centralized cross-connection systems.

[0101] Embodiment three:

[0102] The embodiment of the present invention also provides a cross-connection device, such as an electrical cross-connection device, such as Figure 6 As shown, including:

[0103] The main clock board 100 is provided with a main system clock source, and the main system clock source is used to output a main system clock SCK_A and a main system second pulse signal 1PPS_A.

[0104] The standby clock board 300 is provided with a standby system clock source, and the standby system clock source is used to output a standby system clock SCK_B and a standby system second pulse signal 1PPS_B.

[0105] One or more service boards 200 for processing services, the service boards 200 can be used to convert data, such as format conversion. The service board 200 is provided with the clock holding system as described above, wherein the clock source selection circuit 30 of the clock holding system is also used to select one of the main system clock and the backup system clock as the system reference clock, and select one of the main system second pulse signal and the backup system second pulse signal as the system reference second pulse signal.

[0106] The cross-connection board (not shown in the figure) is used for data cross-connection. Since the improvement of the cross-connection equipment of the present invention lies in the clock holding system, which has been described in detail in the above embodiment, it will not be repeated in this embodiment.

[0107] Embodiment 4:

[0108] This embodiment also provides a cross-connection device, which includes a processor, a memory and a communication bus. The communication bus is used to realize the connection and communication between the processor and the memory. The processor is used to execute one or more computer programs stored in the memory to implement at least one step of the clock holding method in the above-mentioned embodiment 1. In this embodiment, the functions and connection relationships of the processor, the memory and the communication bus are all implemented by FPGA (programmable gate array). That is, the cross-connection device includes FPGA, which stores one or more computer programs and has the following features: Figure 4 and Figure 5 The circuit shown in FIG. FPGA is used to execute one or more computer programs stored therein to implement at least one step of the clock keeping method in the above-mentioned embodiment 1. Of course, in other embodiments, the processor may also be a CPU, an MCU, etc.

[0109] The present embodiment also provides a computer-readable storage medium, which includes volatile or non-volatile, removable or non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, computer program modules or other data). Computer-readable storage media include, but are not limited to, RAM (Random Access Memory), ROM (Read-Only Memory), EEPROM (Electrically Erasable Programmable read only memory), flash memory or other memory technology, CD-ROM (Compact Disc Read-Only Memory), digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer.

[0110] The computer-readable storage medium in this embodiment can be used to store one or more computer programs, and the one or more computer programs stored therein can be executed by a processor such as an FPGA to implement at least one step of the clock holding method in the above-mentioned embodiment 1.

[0111] It can be seen that those skilled in the art should understand that all or some of the steps, systems, and functional modules / units in the above disclosed methods can be implemented as software (which can be implemented with computer program code executable by a computing device), firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component can have multiple functions, or a function or step can be performed by several physical components in cooperation. Some or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit.

[0112] In addition, it is well known to those skilled in the art that communication media generally contain computer readable instructions, data structures, computer program modules or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery media. Therefore, the present invention is not limited to any specific hardware and software combination.

[0113] The above contents are further detailed descriptions of the embodiments of the present invention in combination with specific implementation methods, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A clock holding method, characterized in that: include: Get the system reference clock; Generate a local reference clock with the same frequency as the system reference clock, determine the system state, and obtain the system reference second pulse signal, wherein the system state includes a normal state and a hold state; In the normal state, a target clock signal is generated according to the system reference clock and the system reference second pulse signal, and a frequency deviation between the local reference clock and the system reference clock is detected; The frequency of the local reference clock is adjusted according to the frequency deviation, so that the local reference clock tracks the system reference clock, and an adjustment parameter of the frequency adjustment and a corresponding adjustment time are recorded, wherein the recording of the adjustment parameter of the frequency adjustment and the corresponding adjustment time includes: Store the adjustment parameter of the frequency adjustment and the corresponding elapsed seconds, and update the elapsed seconds so that the elapsed seconds are the time interval from the moment of adjusting the adjustment parameter to the current moment, until entering the holding state, wherein the maximum value of the elapsed seconds corresponding to the same adjustment parameter is the time interval from the moment of adjusting the local reference clock frequency to the moment of entering the holding state; In the holding state, the local reference clock is adjusted according to the adjustment parameter and its corresponding adjustment time, the local reference clock is output, and a target clock signal is generated according to the local reference clock.

2. The clock holding method according to claim 1, characterized in that: Also includes: Acquiring a system reference second pulse signal; the detecting a frequency deviation between the local reference clock and the system reference clock comprises: Generate a local second pulse signal according to the local reference clock; Calculate the relative position of the phase between the local second pulse signal and the system reference second pulse signal according to the system reference clock, the system reference second pulse signal and the local second pulse signal; Acquire a reference relative position, and obtain a change amount of the relative position relative to the reference relative position according to the relative position and the reference relative position; The time interval between the moment when the reference relative position is selected and the moment when the relative position corresponding to the current change is selected is calculated, and the change is divided by the time interval to obtain the frequency deviation between the current local reference clock and the system reference clock.

3. The clock holding method according to claim 1, characterized in that: The adjusting the frequency of the local reference clock according to the frequency deviation so that the local reference clock tracks the system reference clock comprises: Determining whether the frequency deviation exceeds a preset deviation threshold; If yes, the frequency of the local reference clock is adjusted according to the frequency deviation so that the local reference clock tracks the system reference clock.

4. The clock holding method according to claim 1, characterized in that: The adjusting the local reference clock according to the adjustment parameter and its corresponding adjustment time comprises: Among the adjustment parameters and their corresponding adjustment times, the adjustment parameters are selected in sequence according to the order of adjustment times from near to far to adjust the local reference clock.

5. A clock holding system, characterized in that: include: A local clock generating circuit, used for generating a local reference clock having the same frequency as the system reference clock; A state control circuit, used for determining the state of the clock holding system, wherein the state of the clock holding system includes a normal state and a holding state; A frequency deviation detection circuit, used for detecting the frequency deviation between the local reference clock and the system reference clock in the normal state, and obtaining an adjustment parameter for adjusting the frequency of the local reference clock according to the frequency deviation, so that the local reference clock tracks the system reference clock; A frequency adjustment recording circuit is used to record the adjustment parameters of the frequency adjustment and the corresponding adjustment time in the normal state; in the holding state, output the adjustment parameters according to the adjustment parameters and the corresponding adjustment time, wherein the recording of the adjustment parameters of the frequency adjustment and the corresponding adjustment time includes: Store the adjustment parameter of the frequency adjustment and the corresponding elapsed seconds, and update the elapsed seconds so that the elapsed seconds are the time interval from the moment of adjusting the adjustment parameter to the current moment, until entering the holding state, wherein the maximum value of the elapsed seconds corresponding to the same adjustment parameter is the time interval from the moment of adjusting the local reference clock frequency to the moment of entering the holding state; The local clock generating circuit is further used to adjust the frequency of the local reference clock according to the adjustment parameter output by the frequency deviation detecting circuit in the normal state; and to adjust the frequency of the local reference clock according to the adjustment parameter output by the frequency adjustment recording circuit in the hold state; A clock source selection circuit, used for obtaining the system reference clock, obtaining the system reference second pulse signal and the local reference clock output by the local clock generation circuit, outputting the system reference clock and the system reference second pulse signal in the normal state, and outputting the local reference clock in the holding state; The target signal generating circuit is used to generate and output a target clock signal according to the signal output by the clock source selection circuit. In the normal state, the clock source selection circuit outputs a system reference clock and a system reference second pulse signal. In the holding state, the target signal generating circuit generates and outputs a target clock signal according to a local reference clock output by the clock source selection circuit.

6. A cross-connection device, characterized in that: include: A main clock board is provided with a main system clock source, and the main system clock source is used to output a main system clock and a main system second pulse signal; A backup clock board is provided with a backup system clock source, and the backup system clock source is used to output a backup system clock and a backup system second pulse signal; One or more service boards for processing services are provided with the clock holding system as claimed in claim 5, wherein the clock source selection circuit of the clock holding system is further used to select one of the main system clock and the backup system clock as the system reference clock, and select one of the main system second pulse signal and the backup system second pulse signal as the system reference second pulse signal; Cross-connect board, used for data cross-connection.

7. A cross-connection device, characterized in that: including a processor, a memory and a communication bus; The communication bus is used to realize the connection and communication between the processor and the memory; The processor is used to execute one or more computer programs stored in the memory to implement the steps of the clock keeping method according to any one of claims 1 to 4.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores one or more computer programs, and the one or more computer programs can be executed by one or more processors to implement the steps of the clock keeping method according to any one of claims 1 to 4.

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