A multi-core system and processing method based on on-chip network

Abstract

The present application discloses a multi-core system and processing method based on a network on chip, wherein a system based on a multi-core architecture of a network on chip includes: a routing unit and multiple computing units; wherein the routing unit includes a first router and a second router; the number of interfaces of the first router and the second router are different; each of the computing units includes at least two adjacently arranged processing sub-units, each processing sub-unit includes a stacked processor and a memory; for each of the computing units, the processing sub-units are connected through the routing unit.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a multi-core system and processing method based on a network on chip. Background Art

[0002] With the rapid development of semiconductor technology, multi-core chips are becoming mainstream with their super computing power. Especially in parallel computing, heterogeneous multi-core chips containing multiple computing cores have been widely used in the field of high-performance computing.

[0003] However, as the number of cores increases, the bit width of the NOC (Network on Chip) bus integrated on the chip and the scale of the router increase nonlinearly, thereby increasing the power consumption of the NOC bus when working, resulting in excessive power consumption of multi-core chips. The power consumption problem has gradually become a problem affecting the development of multi-core chips. Summary of the invention

[0004] The embodiments of the present application are intended to provide a multi-core system and processing method based on a network on chip.

[0005] The technical solution of this application is implemented as follows:

[0006] In a first aspect, an embodiment of the present application provides a multi-core system based on a network on chip, the multi-core system comprising: a routing unit and a plurality of computing units; wherein:

[0007] The routing unit includes a first router and a second router; the first router and the second router have different numbers of interfaces;

[0008] Each of the computing units includes at least two adjacent processing sub-units, and each processing sub-unit includes a processor and a memory that are stacked;

[0009] For each of the computing units, the processing sub-units are connected via the routing unit.

[0010] Optionally, the computing unit includes a first computing unit and a second computing unit, and the first computing unit and the second computing unit have different numbers of processing sub-units.

[0011] Optionally, the number of interfaces of the first router is greater than the number of interfaces of the second router, the first router is located in a first area, and the second router is located in a second area; wherein the second area is a peripheral area of ​​the first area.

[0012] Optionally, the routing unit further includes a third router, and the number of interfaces of the third router is different from that of the first router and the second router.

[0013] Optionally, the memory is configured to store operation data;

[0014] The processor is configured to obtain operation data from the memory of the same processing sub-unit, and based on the operation data, perform preset operation with other processors in the operation unit.

[0015] Optionally, the processor is also configured to obtain operation data from the memory of a target processing subunit other than the processing subunit to which it belongs; the number of routing units between the target processing subunit and the processor does not exceed the number of routing units between other processing subunits and the processor.

[0016] Optionally, the processor is further configured to obtain operation data from the memory of other processing sub-units of the corresponding operation unit.

[0017] Optionally, the memory includes DRAM memory or MRAM memory.

[0018] A second aspect of an embodiment of the present application provides a processing method, which is applied to a multi-core system based on a network on chip as described in the first aspect, including:

[0019] The processor obtains operation data from the memory of the same processing subunit;

[0020] Based on the operation data, the preset operation is performed together with other processors in the operation unit.

[0021] Optionally, when the processor fails to obtain operation data from the memory of the same processing sub-unit, the processor obtains operation data from the memory of a target processing sub-unit other than the processing sub-unit to which it belongs; the number of routing units between the target processing sub-unit and the processor does not exceed the number of routing units between other processing sub-units and the processor.

[0022] The present application discloses a multi-core system and processing method based on a network on chip, wherein the multi-core system based on a network on chip includes: a routing unit and multiple computing units; wherein the routing unit includes a first router and a second router; the number of interfaces of the first router and the second router is different; each of the computing units includes at least two adjacent processing sub-units, each of which includes a stacked processor and a memory; for each computing unit, the processing sub-units are connected through the routing unit. The present application divides multiple computing units, each of which includes a stacked processor and a memory, so that the processor does not need to obtain computing data from an off-chip memory, so that the computing unit can independently complete the computing operation, reducing the data interaction between processors that are far away, thereby reducing the bit width of the router and reducing the number of interfaces required for the router. In this way, the power consumption of the router is greatly reduced, and the overall power consumption of the system is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of the structure of a multi-core system provided in an embodiment of the present application;

[0024] Figure 2 A schematic diagram of the structure of another multi-core system provided in an embodiment of the present application;

[0025] Figure 3 A schematic diagram of the structure of a multi-core system based on an on-chip network provided in an embodiment of the present application;

[0026] Figure 4 A schematic diagram of the structure of a processing subunit provided in an embodiment of the present application;

[0027] Figure 5 A schematic diagram of a specific structure of a processing subunit provided in an embodiment of the present application;

[0028] Figure 6 A flowchart of a processing method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art.

[0030] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0031] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the steps. For example, some steps may be decomposed, while some steps may be combined or partially combined, so the actual execution order may change according to the actual situation.

[0032] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0033] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0034] In multi-core chips, the NOC bus is mainly used for data exchange between cores, such as AI (Artificial Intelligence) cores, GPU (Graphics Processing Unit) cores, and CPU (Central Processing Unit) cores. As the number of cores increases, the bit width of the NOC bus and the scale of the router will increase accordingly, resulting in an increase in total power consumption during data transmission. Here, the NOC bus is a data transmission route including routers.

[0035] For a data transmission route, the power consumption P is calculated as follows:

[0036] P=hops·P r +D 2D ·P h

[0037] Among them, P r is the router power consumption, hops is the number of routers that data is transmitted through, P h is the link power consumption between NOC buses, D 2D is the average Manhattan distance of data transmission. Router power consumption P r With n port log2n port Proportional to n port The number of router interfaces.

[0038] Based on the above calculation formula, it can be seen that the total power consumption on a data transmission route is not only related to the number of router interfaces, but also to the length of the data transmission route and the number of routers passed during the data transmission process. The more routers and router interfaces there are on the data transmission route, the greater the power consumption of the data transmission route.

[0039] In one embodiment, Figure 1 As shown, Figure 1 A schematic diagram of the structure of a multi-core system provided for an embodiment of the present application. The multi-core architecture includes a plurality of processors 110, each processor 110 is connected to a corresponding router 120, and adjacent routers 120 are connected to each other. Here, the processor may be an embedded neural network processor (NPU, network process units), which is a processor specifically applied to network application data packets, adopts a "data-driven parallel computing" architecture, and is good at processing massive multimedia data such as videos and images. Of course, the processor here may also be a CPU processor, a GPU processor, etc.

[0040] In this multi-core system, the processor has two data transmission routes, namely the first data transmission route and the second data transmission route. In the first data transmission route, the processor 110 obtains operation data from the static random access memory (SRAM) 130 in the chip through the router 120 and performs the preset operation. In the second data transmission route, the processor 110 obtains operation data from the dynamic random access memory (DRAM) 160 outside the chip through the router 120, the bus 140, and the double data rate physical layer (DDR PHY) 150 and performs the preset operation. Compared with obtaining operation data from the chip based on the first data transmission route, the second data transmission route needs to pass through more routers 120 and other devices to obtain operation data from outside the chip. Therefore, the power consumption of the second data transmission route is much greater than that of the first data transmission route.

[0041] In this embodiment, the processor 110 obtains the operation data from the static random access memory 130 on the chip first, and only when the operation data acquisition fails, the processor 110 will obtain the operation data from the dynamic random access memory 160 outside the chip. In other words, the multi-core system takes the first data transmission route first, and only when the first data transmission route fails, the second data transmission route will be taken.

[0042] Regarding the total route power consumption of the multi-core system in this embodiment, on the one hand, since it is difficult for a single processor 110 to complete the preset operation, it is often necessary for multiple processors 110 to cooperate to complete the preset operation, and the processors 110 are connected through one or more routers 120. The more routers 120 there are on the route, the greater the power consumption will be, so the power consumption of the additional routers 120 will be increased. On the other hand, the processor 110 needs to obtain operation data from the static random access memory 130, and an additional router 120 interface needs to be added to establish a connection with the static random access memory 130 on the chip, which brings additional power consumption. Even when the processor 110 cannot obtain operation data from the static random access memory 130 on the chip, it needs to obtain operation data from the dynamic random access memory 160 outside the chip, and the processor 110 needs to pass through more routers 120 to obtain operation data from the dynamic random access memory 160 outside the chip, thereby causing greater power consumption.

[0043] In another embodiment, Figure 2 As shown, Figure 2A schematic diagram of the structure of another multi-core system provided for an embodiment of the present application. The multi-core system includes a plurality of processors 210, each processor 210 is provided with a corresponding static random access memory 220, adjacent processors 210 are connected via a router 230, and adjacent routers 230 are connected to each other. Here, the processor 210 may be an embedded neural network processor (NPU), which is a processor specifically applied to network application data packets, adopts a "data-driven parallel computing" architecture, and is good at processing massive multimedia data such as videos and images. Of course, the processor here may also be a CPU processor, a GPU processor, and the like. Figure 2 In the multi-core system provided Figure 1 The static random access memory in the multi-core system provided is distributed to each processor. However, due to the limited memory of the static random access memory, in most cases the processor still needs to obtain operation data from the dynamic random access memory outside the chip.

[0044] In the multi-core system, the processor 210 has three data transmission routes, namely, the first data transmission route, the second data transmission route and the third data transmission route. In the first data transmission route, the processor 210 can directly obtain the operation data from the corresponding static random access memory 220 and perform the preset operation. In the second data transmission route, the processor 210 obtains the operation data from the static random access memory 220 corresponding to the adjacent processor 210 through the router 230 and performs the preset operation. In the third data transmission route, the processor 210 obtains the operation data from the dynamic random access memory 260 outside the chip through the router 230, the bus 240 and the double rate physical layer 250 and performs the preset operation. Compared with obtaining the operation data from the chip based on the first data transmission route and the second data transmission route, the third data transmission route needs to pass through more routers 120 and other devices to obtain the operation data from the outside of the chip. Therefore, the power consumption of the third data transmission route is much greater than the power consumption of the first data transmission route and the second data transmission route.

[0045] It should be noted that, in this embodiment, the processor 210 also preferentially obtains operation data from the corresponding static random access memory 220. When the operation data acquisition fails, the processor 210 starts to obtain operation data from the static random access memory 220 corresponding to other processors in the chip, and this requires a complex judgment mechanism to achieve. Only when the operation data acquisition fails again, the processor 210 will obtain operation data from the dynamic random access memory 260 outside the chip. In other words, the first data transmission route is preferentially adopted in the multi-core system. When the first data transmission route fails to execute, the second data transmission route will be adopted. Further, when the second data transmission route fails to execute, the third data transmission route will be adopted.

[0046] In this embodiment, under normal circumstances, it is difficult for a single processor 210 to complete the preset operation, and multiple processors 210 need to cooperate to complete the preset operation. The processors 210 are connected through one or more routers 230. The more routers 230 there are on the route, the greater the power consumption. Therefore, the power consumption of the additional routers 230 and the link power consumption between the routers 230 will be increased. Even when the processor 210 cannot obtain operation data from the corresponding static random access memory 220, it is necessary to obtain operation data from the static random access memory 220 corresponding to other processors in the chip through a complex judgment mechanism, and even from the dynamic random access memory 260 outside the chip. The processor 210 needs to pass through more routers 230 to obtain operation data from the dynamic random access memory 260 outside the chip, and requires more router interfaces, thereby causing greater power consumption.

[0047] In one embodiment, Figure 3 A schematic diagram of the structure of a multi-core system based on an on-chip network provided in an embodiment of the present application, Figure 4 A schematic diagram of the structure of a processing subunit provided in an embodiment of the present application. Figure 3 and Figure 4 As shown, the system based on the on-chip network multi-core architecture includes: a routing unit 310 and multiple computing units 320; wherein,

[0048] The routing unit 310 includes a first router 311 and a second router 312; the first router 311 and the second router 312 have different numbers of interfaces;

[0049] Each of the computing units 320 includes at least two processing sub-units 321, and each processing sub-unit 321 includes a processor 3211 and a memory 3212 that are stacked;

[0050] For each of the computing units 320 , the processing sub-units 321 are connected via the routing unit 310 .

[0051] It should be noted that Figure 3 It is described by taking an example that each of the computing units 320 includes four processing sub-units 321 .

[0052] In this embodiment, the memory 3212 is configured to store computing data. The memory 3212 may be a dynamic random access memory, or may be a flash memory (FLASH), a phase change memory (PCM), or a magnetic random access memory (MRAM). Taking the memory 3212 as a dynamic random access memory as an example, compared with a static random access memory, a dynamic random access memory of the same size has a larger memory and can store more computing data. The memory 3212 is used to store the computing data required for the processor 3211 to perform preset computing operations. The preset computing operations may be multiple computing operations based on a preset algorithm program. The data stored in different memories 3212 may be partially the same or completely the same, and there is no limitation here. Compared to Figure 1 and Figure 2 In the multi-core system provided, in this embodiment, the off-chip dynamic random access memory is set in each processor 3211, and is bonded with the processor 3211 to form a processing sub-unit 321. Therefore, the processor in this embodiment does not need to obtain calculation data from outside the chip, which greatly reduces power consumption.

[0053] The processor 3211 is configured to obtain operation data from the memory 3212 of the same processing subunit 321, and based on the operation data, perform preset operation operations together with other processors 3211 in the operation unit 320. Here, the processor 3211 can be an embedded neural network processor (NPU), which is a processor specially applied to network application data packets, adopts the architecture of "data-driven parallel computing", and is good at processing massive multimedia data such as video and images. Of course, the processor 3211 here can also be a CPU processor, a GPU processor, etc.

[0054] In this embodiment, the processing subunit 321 is formed by stacking a processor 3211 and a memory 3212. Here, the memory 3212 can be bonded to the processor 3211 by wafer on wafer or die on wafer technology. Among them, in the die on wafer technology, the memory 3212 can be formed by cutting the initial storage wafer into multiple storage dies, and then bonding the multiple storage dies to the logic wafer corresponding to the processor 3211, and then cutting the wafer to form the memory. By stacking the processor 3211 and the memory 3212, the lateral expansion of the processor in the lateral direction is avoided, which is conducive to the miniaturization of the processor. It should be understood that the relative position of the stacked processor 3211 and the memory 3212 is not restricted.

[0055] In an example, see Figure 5, Figure 5 A specific structural diagram of a processing subunit provided in an embodiment of the present application, wherein the top layer is a memory die 400, the middle layer is a logic die 401, the dotted line represents the bonding surface between the memory die 400 and the logic die 401, and the bottom layer is a substrate and a processor. The memory die can be, for example, a DRAM memory die or an MRAM memory die. Specifically, from top to bottom, there are chip substrate 410 (ChipSubstrate), memory device layer 420 (memory device Layer), metal layer 430 (Metal Layer), hybrid bonding layer 440 (Hybrid Bonding Layer), metal layer (not marked in the figure), logic device layer 450 (Logic deviceLayer), chip substrate (not marked in the figure), flip chip micro bumps 460 (Fipchip bumps), substrate 470 (Substrate), bonding bumps 480 (Bonding bumps), processor 490, wherein there are through silicon vias (Through Silicon Via, TSV) in the logic device layer and its chip substrate to complete the interlayer interconnection. Through bonding and packaging processes, the bonding packaging of memory 3212 and processor 3211 can be realized, thereby obtaining the processing subunit 321.

[0056] In this embodiment, each processor has a bonded memory. Adjacent computing units are connected through a router, and each processing sub-unit inside the computing unit is also connected through a router. Here, the processor has two data transmission routes, namely a first data transmission route and a second data transmission route. In the first data transmission route, the processor can directly obtain computing data from the bonded memory and perform a preset computing operation. In the second data transmission route, the processor obtains computing data from the memory corresponding to another processor that is closer in the same computing unit through a router and performs a preset computing operation, thereby avoiding the processor from obtaining data from the memory in the processing sub-unit of other computing units at a long distance, and reducing the power consumption of the router on the transmission link. Here, the distance between the processor and the memory is related to the number of routers between the two. The more routers there are, the greater the distance between the two. Since it is not necessary to obtain computing data from a long distance, nor is it necessary to obtain computing data from an off-chip memory, the number of interfaces required for the router and the number of routers required are greatly reduced, thereby reducing the power consumption of the router.

[0057] In this embodiment, the number of interfaces of the first router is twice the number of interfaces of the second router.

[0058] In one example, the number of interfaces of the first router 311 may be 256, and the number of interfaces of the second router 312 may be 128. Here, the first router 311 is located in the first area, and the second router 312 is located in the second area. The first area may be the central area of ​​the system, and the second area is the peripheral area of ​​the first area. In the embodiment of the present application, a router with a large number of interfaces is set in the central area so that it can meet the needs of the transmission link, and a router with a small number of interfaces is set in the peripheral area because the number of interfaces required is small. In contrast, in the aforementioned multi-core architecture, since it needs to obtain computing data from outside the chip, the number of interfaces required is often more, usually 512. This embodiment reduces the power consumption of the router during data transmission by reducing the number of interfaces of the router.

[0059] The present application divides the device into multiple computing units, each of which includes a stacked processor and memory, so that the computing unit can independently complete computing operations, reducing data interaction between processors that are far away, thereby reducing the bit width of the router and reducing the number of interfaces required for the router. In this way, the power consumption of the router is greatly reduced, and the overall power consumption of the system is reduced.

[0060] In one embodiment, the computing unit includes a first computing unit and a second computing unit, and the first computing unit and the second computing unit have different numbers of processing sub-units.

[0061] Please see here Figure 3 ,exist Figure 3 In the embodiment, each operation unit includes four processing sub-units, and the four processing sub-units can cooperate with each other to perform at least one preset operation. Of course, the number of processing sub-units included in each operation unit is not limited to four, and can also be five, six, etc., and the specific number is not limited. In addition, in the same system based on the on-chip network multi-core architecture, different operation units can include different numbers of processing sub-units, such as a first operation unit composed of four processing sub-units, a second operation unit composed of six processing sub-units, and a third operation unit and a fourth operation unit. Each operation unit includes a different number of processing sub-units, thereby performing multiple preset operations.

[0062] In one example, the composition of the operation unit is determined according to the algorithm complexity corresponding to the preset operation operation. When the algorithm complexity corresponding to the preset operation operation is high, a larger number of processing sub-units can be classified as one operation unit; conversely, when the algorithm complexity corresponding to the preset operation operation is low, a smaller number of processing sub-units can be classified as one operation unit. The specific number of processing sub-units included in one operation unit is determined according to the algorithm complexity and is not limited here.

[0063] In this embodiment, the routing unit further includes a third router (not shown in the figure), and the number of interfaces of the third router is different from that of the first router and the second router.

[0064] In this embodiment, the number of interfaces of the second router is twice the number of interfaces of the third router.

[0065] In one example, the number of interfaces of the first router 311 may be 256, the number of interfaces of the second router 312 may be 128, and the number of interfaces of the third router may be 64. Here, the first router 311 is located in the first area, the second router 312 and the third router are located in the second area, the first area may be the central area of ​​the system, and the second area is the peripheral area of ​​the first area.

[0066] In this embodiment, the routing unit may include routers with different numbers of interfaces. For example, the number of interfaces of the router located in the center area of ​​the system is greater than that of the router located in the edge area of ​​the system, and the number of interfaces of the router located in the center of the same computing unit is greater than that of the router located at the edge of the computing unit. By setting routers with different numbers of interfaces, the waste of router interfaces caused by the unified use of multiple interfaces is avoided, thereby reducing the power consumption of the routers.

[0067] In one embodiment, the processor is further configured to obtain operation data from the memory of the target processing subunit other than the corresponding processing subunit; the number of routing units between the target processing subunit and the processor does not exceed the number of routing units between other processing subunits and the processor.

[0068] In this embodiment, a data register corresponding to each processor is also included. The data register stores the distance parameter from each processor to each processing subunit. Here, the distance parameter is related to the number of routers on the transmission link. The more routers on the transmission link, the larger the distance parameter. When the processor fails to obtain operation data from the memory in the processing subunit to which it belongs, it can obtain operation parameters from the nearest other processing subunit, that is, the target processing subunit, based on the distance parameter, thereby reducing the power consumption of the routers on the data transmission route.

[0069] In one embodiment, the processor is further configured to obtain operation data from the memory of other processing sub-units of the corresponding operation unit.

[0070] Compared with obtaining operation data from other processing sub-units outside the operation unit, the data transmission route for directly obtaining operation data from the memory of other processing sub-units in the operation unit is shorter. Here, the priority of the data transmission route can be set by an algorithm. The priority is related to the number of routers on the data transmission route. The fewer the number of routers on the data transmission route, the higher the priority, that is, the processor preferentially obtains operation data from the memory of the processing sub-unit to which it belongs. When the acquisition of operation data fails, the operation data is obtained from the memory of other processing sub-units with the smallest distance parameter in the operation unit to which the processor belongs. By shortening the data transmission route for the processor to obtain data from the memory, the power consumption of the router is reduced.

[0071] The present application also provides a processing method, which is applied to the above-mentioned system based on a multi-core architecture of an on-chip network, such as Figure 6 As shown, including:

[0072] S501, the processor obtains operation data from the memory of the same processing subunit;

[0073] S502, based on the operation data, jointly executing a preset operation with other processors in the operation unit.

[0074] In this embodiment, the processor can directly obtain operation data from the memory of the same processing sub-unit and perform preset operation. Since the processor and the memory are stacked and the transmission path is short, the power consumption of data transmission can be greatly reduced.

[0075] In one embodiment, when the processor fails to obtain operation data from the memory of the same processing sub-unit, the processor obtains the operation data from the memory of the target processing sub-unit other than the processing sub-unit to which it belongs; the number of routing units between the target processing sub-unit and the processor does not exceed the number of routing units between other processing sub-units and the processor.

[0076] In this embodiment, the processor obtains operation data from the memory of the same processing subunit first. When the operation data fails to be obtained, the processor obtains the operation data from the memory of other processing subunits in the same operation unit, thereby avoiding the processor from obtaining data from the memory of a remote processing subunit outside the operation unit, and reducing the power consumption of the router on the transmission link. Here, the distance between the processor and the memory is related to the number of routers between the two. The more routers there are, the greater the distance between the two.

[0077] The embodiment of the present application divides the processor into multiple computing units, each of which includes a stacked processor and memory, so that the processor does not need to obtain computing data from an off-chip memory, so that the computing unit can independently complete computing operations, thereby reducing data interaction between processors that are far away, thereby reducing the bit width of the router and reducing the number of interfaces required for the router. In this way, the power consumption of the router is greatly reduced, and the overall power consumption of the system is reduced.

[0078] The methods disclosed in several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0079] The features disclosed in several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0080] The features disclosed in several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0081] In the several embodiments provided in the present application, it should be understood that the disclosed methods and devices can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as: multiple modules or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the device or module can be electrical, mechanical or other forms.

[0082] The modules described above as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical units, that is, they may be located in one place or distributed on multiple network modules; some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0083] In addition, all functional modules in the embodiments of the present application may be integrated into one processing module, or each module may be a separate module, or two or more modules may be integrated into one module; the above-mentioned integrated modules may be implemented in the form of hardware or in the form of hardware plus software functional modules.

[0084] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A multi-core system based on a network on chip, characterized in that: include: A routing unit, a plurality of operation units and a data register; wherein, The routing unit includes a plurality of first routers, a second router and a third router; the number of interfaces of the first router is twice the number of interfaces of the second router, and the number of interfaces of the second router is twice the number of interfaces of the third router; the number of interfaces of the router located in the center area of ​​the multi-core system is greater than the number of interfaces of the router located in the edge area of ​​the multi-core system, and the number of interfaces of the router located in the center of the same computing unit is greater than the number of interfaces of the router located at the edge of the same computing unit; Each of the computing units includes at least two adjacent processing sub-units, each of which includes a processor and a memory that are stacked; for each of the computing units, the processing sub-units are connected via the routing unit; The data register corresponds to each of the processors, and the data register is configured to store a distance parameter from each of the processors to each of the processing sub-units; The processor is configured to: obtain operation data from the memory of the same processing sub-unit, and perform preset operation with other processors in the operation unit based on the operation data; The processor is also configured to: when the operation data fails to be obtained from the memory in the processing sub-unit to which it belongs, obtain the operation data from the memory of the target processing sub-unit outside the processing sub-unit to which it belongs based on the distance parameter stored in the data register; the number of the routing units between the target processing sub-unit and the processor does not exceed the number of the routing units between other processing sub-units and the processor.

2. The multi-core system according to claim 1, characterized in that: The operation unit includes a first operation unit and a second operation unit, and the first operation unit and the second operation unit have different numbers of processing sub-units.

3. The multi-core system according to claim 1, characterized in that: The memory is configured to store the operation data.

4. The multi-core system according to claim 1, characterized in that: The processor is further configured to obtain the operation data from the memory of other processing sub-units of the operation unit to which it belongs.

5. A processing method, characterized in that: The multi-core system based on a network on chip as described in claims 1 to 4 comprises: The processor obtains operation data from the memory of the same processing subunit; Based on the operation data, the preset operation is performed together with other processors in the operation unit.

6. The method according to claim 5, characterized in that Also includes: When the processor fails to obtain operation data from the memory of the same processing sub-unit, based on the distance parameter stored in the data register, the processor obtains the operation data from the memory of the target processing sub-unit other than the processing sub-unit to which it belongs; the number of routing units between the target processing sub-unit and the processor does not exceed the number of routing units between other processing sub-units and the processor.

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