Read threshold optimization system and method using domain transformation

Abstract

The present disclosure relates to a controller that optimizes read thresholds of a memory device using domain conversion. For decoded data of each read operation, the controller determines an asymmetry ratio (AR) and a number of unsatisfied checks (USC), the AR representing a ratio of a number of first binary values to a number of second binary values in the decoded data. The controller determines a Z-axis such that AR values of a threshold set are arranged in a set order along the Z-axis. The controller determines an optimal read threshold set using coordinate values on the Z-axis that correspond to set AR values and set USC values.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a scheme for optimizing read thresholds in a memory system. Background Technology

[0002] The computing environment paradigm has shifted to ubiquitous computing systems that can be used anytime, anywhere. Consequently, the use of portable electronic devices such as mobile phones, digital cameras, and laptops has increased rapidly. These portable electronic devices typically utilize memory systems with memory devices, i.e., data storage devices. Data storage devices serve as either the main memory or auxiliary memory devices of the portable electronic devices.

[0003] Memory systems using memory devices offer superior stability, durability, high data access speeds, and low power consumption due to the absence of moving parts. Examples of memory systems with these advantages include Universal Serial Bus (USB) memory devices, memory cards with various interfaces such as Universal Flash Memory (UFS), and Solid State Drives (SSDs). Memory systems can perform read operations using a variety of read thresholds. Summary of the Invention

[0004] Aspects of the present invention include a memory system and a method for optimizing read thresholds using domain transformation.

[0005] On one hand, a memory system includes a controller and a memory device having multiple cells. The controller performs multiple read operations on the multiple cells using a set of read thresholds and at least one set of read retry thresholds, each threshold set including a first read threshold and a second read threshold. The controller decodes data associated with each of the read operations. For the decoded data in each read operation, the controller determines an asymmetric ratio (AR) and a number of unmet checks (USCs), where AR indicates the ratio of the number of first binary values ​​to the number of second binary values ​​in the decoded data. The controller determines a Z-axis such that the AR values ​​of the threshold sets are arranged along the Z-axis in a set order. The controller uses a first coordinate value and a second coordinate value on the Z-axis corresponding to the set AR values ​​and the set USC values ​​to determine an optimal set of read thresholds.

[0006] On the other hand, a method of operating a memory system includes: performing a plurality of read operations on a plurality of cells using a read threshold set and at least one read retry threshold set, each threshold set including a first read threshold and a second read threshold; decoding data associated with each of the read operations; determining, for each of the decoded data in the read operations, the number of asymmetric ratios (AR) and unmet checks (USC), the AR indicating the ratio of the number of first binary values ​​to the number of second binary values ​​in the decoded data; determining a Z-axis such that the AR values ​​of the threshold sets are arranged along the Z-axis in a set order; and determining an optimal read threshold set using coordinate values ​​on the Z-axis corresponding to the set AR values ​​and the set USC values.

[0007] Other aspects of the invention will become apparent from the following description. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating a data processing system according to an embodiment of the present invention.

[0009] Figure 2 This is a block diagram illustrating a memory system according to an embodiment of the present invention.

[0010] Figure 3 This is a circuit diagram illustrating a memory block of a memory device according to an embodiment of the present invention.

[0011] Figure 4 It is a diagram showing the state distribution of different types of cells in a memory device.

[0012] Figure 5 This is a diagram illustrating a memory system according to an embodiment of the present invention.

[0013] Figure 6 This is a diagram illustrating an example of Gray code for a three-layer cell (TLC).

[0014] Figure 7 This is a diagram showing the state distribution of pages in a three-layer cell (TLC).

[0015] Figure 8 This is a flowchart illustrating a read operation of a memory device.

[0016] Figure 9 This is a diagram illustrating the variation in the read threshold set of the least significant bit (LSB) page of a three-level cell (TLC) memory device.

[0017] Figure 10 This is a flowchart illustrating the read threshold optimization operation according to an embodiment of the present invention.

[0018] Figure 11The Z-axis is shown as follows, with the AR values ​​satisfying the threshold set according to an embodiment of the present invention arranged in ascending order along the Z-axis.

[0019] Figure 12 The embodiments of the present invention are shown, in which a first function g() is characterized according to the relation AR = g(Z) and a second function h() is characterized according to the relation USC = h(Z).

[0020] Figure 13A and Figure 13B The following is an example of estimating a first coordinate value Z_AR and a second coordinate value Z_USC according to an embodiment of the present invention.

[0021] Figure 14 An embodiment of the invention illustrates the use of a first coordinate value Z_AR and a second coordinate value Z_USC to determine the optimal read threshold set [VT2*,VT6*]. Detailed Implementation

[0022] Various embodiments are described in more detail below with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Furthermore, references to “embodiment,” “another embodiment,” etc., herein are not necessarily directed to only one embodiment, and different references to any such phrases are not necessarily directed to the same embodiment. Throughout this disclosure, the same reference numerals refer to the same parts in the drawings and embodiments of the invention.

[0023] This invention can be embodied in a variety of ways, including as a process; an apparatus; a system; a computer program product implemented on a computer-readable storage medium; and / or a processor, such as a processor adapted to execute instructions stored on and / or provided by memory linked to the processor. In this specification, these embodiments or any other form in which the invention may be adopted can be referred to as technology. Generally, the order of steps of the disclosed process can be varied within the scope of this invention. Unless otherwise stated, components such as processors or memory described as suitable for performing tasks can be implemented as general components temporarily configured to perform tasks at a given time or manufactured as specific components for performing tasks. As used herein, the term "processor," etc., refers to one or more means, circuits, and / or processing cores suitable for processing data such as computer program instructions.

[0024] The following provides a detailed description of embodiments of the invention, along with accompanying drawings illustrating aspects of the invention. The invention is described in conjunction with these embodiments, but is not limited to any particular embodiment. The scope of the invention is limited only by the claims. The invention includes many alternatives, modifications, and equivalents within the scope of the claims. Numerous specific details are set forth in the following description to provide a thorough understanding of the invention. These details are provided for illustrative purposes; the invention may be practiced according to the claims without requiring some or all of these specific details. For clarity, technical materials known in the art related to the invention have not been described in detail so as not to unnecessarily obscure the invention.

[0025] Figure 1 This is a block diagram illustrating a data processing system 2 according to an embodiment of the present invention.

[0026] Reference Figure 1 The data processing system 2 may include a host device 5 and a memory system 10. The memory system 10 may receive requests from the host device 5 and operate in response to the received requests. For example, the memory system 10 may store data to be accessed by the host device 5.

[0027] The host device 5 can be implemented using any of a variety of electronic devices. In various embodiments, the host device 5 may include electronic devices such as: a desktop computer, a workstation, a 3D television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, and / or a digital video recorder and a digital video player. In various embodiments, the host device 5 may include portable electronic devices such as: a mobile phone, a smartphone, an e-book reader, an MP3 player, a portable multimedia player (PMP), and / or a portable game player.

[0028] The memory system 10 can be implemented using any of a variety of storage devices such as solid-state drives (SSDs) and memory cards. In various embodiments, the memory system 10 can be configured as one of a variety of components among electronic devices such as: computers, ultra-mobile personal computers (PCs) (UMPCs), workstations, netbook computers, personal digital assistants (PDAs), portable computers, network tablet PCs, wireless phones, mobile phones, smartphones, e-book readers, portable multimedia players (PMPs), portable gaming devices, navigation devices, black boxes, digital cameras, digital multimedia broadcasting (DMB) players, 3D televisions, smart televisions, digital audio recorders, digital audio players, digital picture recorders, digital picture players, digital video recorders, digital video players, storage devices for data centers, devices capable of receiving and transmitting information in a wireless environment, radio frequency identification (RFID) devices, and one of a variety of electronic devices for home networks, one of a variety of electronic devices for computer networks, one of a variety of electronic devices for telematics networks, or one of a variety of components for computing systems.

[0029] The memory system 10 may include a memory controller 100 and a semiconductor memory device 200. The memory controller 100 can control all operations of the semiconductor memory device 200.

[0030] The semiconductor memory device 200 can perform one or more erase, program, and read operations under the control of the memory controller 100. The semiconductor memory device 200 can receive commands (CMD), addresses (ADDR), and data (DATA) via input / output lines. The semiconductor memory device 200 can receive power (PWR) via power lines and control signals (CTRL) via control lines. Depending on the design and configuration of the memory system 10, the control signal CTRL may include command latch enable signals, address latch enable signals, chip enable signals, write enable signals, read enable signals, and other operation signals.

[0031] The memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device, such as a solid-state drive (SSD). The SSD may include a storage device for storing data therein. When the semiconductor memory system 10 is used in an SSD, the performance of host devices coupled to the memory system 10 (e.g., Figure 1 The operating speed of the main unit 5).

[0032] The memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device, such as a memory card. For example, the memory controller 100 and the semiconductor memory device 200 can be integrated to configure PC cards, compact flash memory (CF) cards, smart media (SM) cards, memory sticks, multimedia cards (MMC), miniature multimedia cards (RS-MMC), micro-sized versions of MMC (micro MMC), secure digital cards (SD cards), mini secure digital cards (mini SD cards), micro secure digital cards (micro SD cards), secure digital mass storage (SDHC) and / or universal flash memory (UFS).

[0033] Figure 2 This is a block diagram illustrating a memory system according to an embodiment of the present invention. For example, Figure 2 The memory system can be described Figure 1 The memory system 10 shown.

[0034] Reference Figure 2 The memory system 10 may include a memory controller 100 and a semiconductor memory device 200. The memory system 10 can respond to input from a host device (e.g., Figure 1 The host device 5) operates upon request and, in particular, stores data to be accessed by the host device.

[0035] For example, semiconductor memory device 200 can store data to be accessed by host device.

[0036] The semiconductor memory device 200 can be implemented using volatile memory devices such as dynamic random access memory (DRAM) and / or static random access memory (SRAM) or non-volatile memory devices such as read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric random access memory (FRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM) and / or resistive RAM (RRAM).

[0037] The memory controller 100 can control the storage of data in the semiconductor memory device 200. For example, the memory controller 100 can control the semiconductor memory device 200 in response to a request from a host device. The memory controller 100 can provide the host device with data read from the semiconductor memory device 200, and can store data provided by the host device into the semiconductor memory device 200.

[0038] The memory controller 100 may include a storage device 110 connected via a bus 160, a control component 120 which may be implemented as a processor such as a central processing unit (CPU), an error correction code (ECC) component 130, a host interface (I / F) 140, and a memory interface (I / F) 150.

[0039] Storage device 110 can be used as working memory for memory system 10 and memory controller 100, and stores data used to drive memory system 10 and memory controller 100. When memory controller 100 controls the operation of semiconductor memory device 200, storage device 110 can store data used by memory controller 100 and semiconductor memory device 200 for operations such as read operations, write operations, programming operations and erase operations.

[0040] Storage device 110 can be implemented using volatile memory such as static random access memory (SRAM) or dynamic random access memory (DRAM). As described above, storage device 110 can store data used by the host device in semiconductor memory device 200 for read and write operations. To store data, storage device 110 may include program memory, data memory, write buffer, read buffer, mapping buffer, etc.

[0041] Control component 120 can control the general operation of memory system 10 in response to corresponding requests from the host device, particularly write and read operations for semiconductor memory device 200. Control component 120 can drive firmware called a flash translation layer (FTL) to control the general operation of memory system 10. For example, the FTL can perform operations such as logic-to-physical (L2P) mapping, wear leveling, garbage collection, and / or bad block handling. L2P mapping is referred to as logical block addressing (LBA).

[0042] ECC component 130 can detect and correct errors in data read from semiconductor memory device 200 during a read operation. When the number of error bits is greater than or equal to a threshold number of correctable error bits, ECC component 130 may not correct the error bits, but instead may output an error correction failure signal indicating that the correction of error bits has failed.

[0043] In various embodiments, the ECC component 130 may perform error correction operations based on coded modulation such as low-density parity-check (LDPC) codes, Bose-Chaudhri-Hocquenghem (BCH) codes, turbo codes, turbo product codes (TPC), Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), and block-coded modulation (BCM). However, error correction is not limited to these techniques. Thus, the ECC component 130 may include any and all circuitry, systems, or means for appropriate error correction operations.

[0044] The host interface 140 can communicate with the host device through one or more of the following interface protocols: Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Enhanced Small Disk Interface (ESDI), and / or Electronic Integrated Drive (IDE).

[0045] Memory interface 150 provides an interface between memory controller 100 and semiconductor memory device 200, allowing memory controller 100 to control semiconductor memory device 200 in response to requests from host device. Memory interface 150 can generate control signals for semiconductor memory device 200 and process data under the control of control component 120. When semiconductor memory device 200 is flash memory such as NAND flash memory, memory interface 150 can generate control signals for the memory and process data under the control of control component 120.

[0046] Semiconductor memory device 200 may include a memory cell array 210, control circuitry 220, voltage generation circuitry 230, row decoder 240, page buffer array 250 in the form of a page buffer array, column decoder 260, and input / output (I / O) circuitry 270. The memory cell array 210 may include multiple memory blocks 211 capable of storing data. The voltage generation circuitry 230, row decoder 240, page buffer array 250, column decoder 260, and I / O circuitry 270 may form peripheral circuitry for the memory cell array 210. The peripheral circuitry may perform programming, reading, or erasing operations on the memory cell array 210. The control circuitry 220 may control the peripheral circuitry.

[0047] The voltage generation circuit 230 can generate operating voltages of various levels. For example, in an erase operation, the voltage generation circuit 230 can generate operating voltages of various levels, such as erase voltage and pass voltage.

[0048] The line decoder 240 can be electrically connected to the voltage generation circuit 230 and a plurality of memory blocks 211. The line decoder 240 can select at least one memory block among the plurality of memory blocks 211 in response to a line address generated by the control circuit 220, and transmit the operating voltage supplied from the voltage generation circuit 230 to the selected memory block.

[0049] Page buffer 250 can be accessed via bit line BL ( Figure 3 (As shown) is connected to the memory cell array 210. The page buffer 250 can precharge the bit line BL with a positive voltage in response to a page buffer control signal generated by the control circuit 220, transfer data to and receive data from the selected memory block during programming and read operations, or temporarily store the transferred data.

[0050] The column decoder 260 can transmit data to and receive data from the page buffer 250, or transmit data to and receive data from the input / output circuit 270.

[0051] Input / output circuit 270 can input from external devices (e.g., Figure 1 The memory controller 100 receives commands and addresses and transmits them to the control circuit 220, which transmits data from external devices to the column decoder 260, or outputs data from the column decoder 260 to external devices via the input / output circuit 270.

[0052] The control circuit 220 can control the peripheral circuits in response to commands and addresses.

[0053] Figure 3 This is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present invention. For example, Figure 3 The storage block can be Figure 2 Any one of the storage blocks 211 in the memory cell array 210 shown.

[0054] Reference Figure 3 The exemplary storage block 211 may include multiple word lines WL0 to WLn-1, a drain select line DSL, and a source select line SSL connected to the line decoder 240. These lines may be arranged in parallel with the multiple word lines between DSL and SSL.

[0055] The exemplary memory block 211 may further include a plurality of cell strings 221 respectively connected to bit lines BL0 to BLm-1. Each column of cell strings may include one or more drain select transistors (DSTs) and one or more source select transistors (SSTs). In the illustrated embodiment, each cell string has one DST and one SST. Within the cell string, a plurality of memory cells or memory cell transistors MC0 to MCn-1 may be connected in series between the select transistors DST and SST. Each of the memory cells may be configured as a single-level cell (SLC) storing 1 bit of data, a multi-level cell (MLC) storing 2 bits of data, a three-level cell (TLC) storing 3 bits of data, or a four-level cell (QLC) storing 4 bits of data.

[0056] The source of each SST in a cell string can be connected to the common source line CSL, and the drain of each DST can be connected to the corresponding bit line. The gate of an SST in a cell string can be connected to SSL, and the gate of a DST in a cell string can be connected to DSL. The gate of a memory cell in a cell string can be connected to the corresponding word line. That is, the gate of memory cell MC0 is connected to the corresponding word line WL0, the gate of memory cell MC1 is connected to the corresponding word line WL1, and so on. A group of memory cells connected to a specific word line can be called a physical page. Therefore, the number of physical pages in memory block 211 can correspond to the number of word lines.

[0057] Page buffer array 250 may include multiple page buffers 251 connected to bit lines BL0 to BLm-1. Page buffers 251 may operate in response to page buffer control signals. For example, page buffers 251 may temporarily store data received through bit lines BL0 to BLm-1 or sense the voltage or current of the bit lines during read or verification operations.

[0058] In some embodiments, memory block 211 may include NAND flash memory cells. However, memory block 211 is not limited to this cell type, but may include NOR flash memory cells. Memory cell array 210 may be implemented as a hybrid flash memory combining two or more types of memory cells, or as a single NAND flash memory with the controller embedded within the memory chip.

[0059] Figure 4 It is a diagram showing the state or programming voltage (PV) level distribution of different types of cells in a memory device.

[0060] As mentioned above, each memory cell can be implemented using a specific type of cell, such as a single-level cell (SLC) for storing 1 bit of data, a multi-level cell (MLC) for storing 2 bits of data, a three-level cell (TLC) for storing 3 bits of data, and a four-level cell (QLC) for storing 4 bits of data. Typically, all memory cells in a particular memory device are of the same type, but this is not required. Figure 4 Show the state of each of those types of cells.

[0061] An SLC can include two states, P0 and P1. P0 indicates an erase state, and P1 indicates a programmable state. Since an SLC can be set to one of these two different states, each SLC can program or store one bit according to the set encoding method. An MLC can include four states, P0, P1, P2, and P3. Of these states, P0 indicates an erase state, and P1 through P3 indicate a programmable state. Since an MLC can be set to one of these four different states, each MLC can program or store two bits according to the set encoding method. A TLC can include eight states, P0 through P7. Of these states, P0 indicates an erase state, and P1 through P7 indicate a programmable state. Since a TLC can be set to one of these eight different states, each TLC can program or store three bits according to the set encoding method. A QLC can include 16 states, P0 through P15. Of these states, P0 indicates an erase state, and P1 through P15 indicate a programmable state. Since a QLC can be set to one of 16 different states, each QLC can program or store 4 bits according to the set encoding method.

[0062] Figure 5 This is a diagram illustrating a memory system 10 according to an embodiment of the present invention.

[0063] Reference Figure 5 The memory system 10 may include a controller 100 and a memory device 200. The memory device 200 may include multiple memory cells (e.g., NAND flash memory cells). Figure 3As shown, memory cells are arranged in an array of rows and columns. Cells in each row are connected to word lines (e.g., WL0), while cells in each column are connected to bit lines (e.g., BL0). These word lines and bit lines are used for read and write operations. During a write operation, when a word line is asserted, the data to be written ("1" or "0") is provided at the bit line. During a read operation, the word line is asserted again, and the threshold voltage for each cell can then be obtained from the bit line. Multiple pages can share memory cells belonging to (i.e., connected to) the same word line. When implementing memory cells using MLC, multiple pages include a most significant bit (MSB) page and a least significant bit (LSB) page. When implementing memory cells using TLC, multiple pages include an MSB page, a middle significant bit (CSB) page, and an LSB page. When implementing memory cells using QLC, multiple pages include an MSB page, a middle most significant bit (CMSB) page, a middle least significant bit (CLSB) page, and an LSB page. The memory cells can be programmed using an encoding scheme (e.g., Gray code) to increase the capacity of a memory system 10 such as an SSD.

[0064] Figure 6 This is a diagram illustrating an example of Gray code for a three-layer cell (TLC).

[0065] Reference Figure 6 Gray code can be used to program the TLC. As mentioned above, the TLC can have eight programming states, including an erase state E (or PV0) and seven programming states PV1 to PV7. Erasure state E (or PV0) can correspond to "110". The first programming state PV1 can correspond to "011". The second programming state PV2 can correspond to "001". The third programming state PV3 can correspond to "000". The fourth programming state PV4 can correspond to "010". The fifth programming state PV5 can correspond to "110". The sixth programming state PV6 can correspond to "100". The seventh programming state PV7 can correspond to "010".

[0066] In TLC, such as Figure 7As shown, there are three types of pages: LSB pages, CSB pages, and MSB pages. Two or three thresholds can be applied to retrieve data from the TLC. For MSB pages, the two thresholds are a first threshold VT0 and a second threshold VT4. The first threshold VT0 distinguishes between erase state E and first programming state PV1. The second threshold VT4 distinguishes between fourth programming state PV4 and fifth programming state PV5. For CSB pages, the three thresholds are a first threshold VT1, a second threshold VT3, and a third threshold VT5. The first threshold VT1 distinguishes between first programming state PV1 and second programming state PV2. The second threshold VT3 distinguishes between third programming state PV3 and fourth programming state PV4. The third threshold VT5 distinguishes between fifth programming state PV5 and sixth programming state PV6. For LSB pages, the two thresholds are a first threshold VT2 and a second threshold VT6. The first threshold VT2 distinguishes between second programming state PV2 and third programming state PV3. The second threshold VT6 distinguishes between sixth programming state PV6 and seventh programming state PV7.

[0067] Re-reference Figure 5 The controller 100 may include a read processor 510, a decoder 520, and an optimal read threshold determiner 530. These components can utilize... Figure 2 The control component 120 (i.e., firmware (FW)) is implemented internally. Although Figure 5 Not shown, but the controller 100 and memory device 200 may include, for example... Figure 2 The various other components shown.

[0068] The read processor 510 can respond to data from the host (e.g., Figure 1 The read processor 510 controls read operations on the memory device 200 based on read requests from the host device 5). The read processor 510 can control read operations based on various read thresholds. The decoder 520 can decode data associated with the read operation. In some embodiments, the read processor 510 can control read operations such as... Figure 8 The read operation shown.

[0069] Refer to the description of read operation 800 Figure 8 In step 810, the read processor 510 can use a selected read threshold set to control read operations on memory cells. In some embodiments, the selected read threshold set may be the read threshold set used in the last successful decoding. When performing a read operation on the MSB page of the TLC, the selected read threshold set may include, for example... Figure 7The diagram shows a pair of first and second read thresholds [VT0, VT4]. The first read threshold VT0 distinguishes between the erase state (i.e., E) and the first programming state (i.e., PV1), and the second read threshold VT4 distinguishes between the fourth programming state (i.e., PV4) and the fifth programming state (i.e., PV5). When performing a read operation on an LSB page of a TLC, the selection of the read threshold set may include, for example... Figure 7 The first read threshold and the second read threshold [VT2, VT6] are shown. The first read threshold VT2 is used to distinguish between the second programming state (i.e., PV2) and the third programming state (i.e., PV3), and the second read threshold VT6 is used to distinguish between the sixth programming state (i.e., PV6) and the seventh programming state (i.e., PV7).

[0070] Based on the decoding result of decoder 520, it can be determined whether the read operation using the selected read threshold set was successful or failed. When the read operation using the selected read threshold set fails, at step 820, read processor 510 can use the read retry threshold set to control one or more read retry operations for the memory cell. In some embodiments, read retries involve performing five different read attempts with different but static read threshold sets.

[0071] Based on the decoding results of decoder 520, it can be determined whether all read retry operations using the read retry threshold set were successful or failed. When all read retry operations using the read retry threshold set failed, read processor 510 can control optimal read threshold determiner 530 to perform optimal read threshold search in step 830, and then perform soft decoding. Typically, optimal read threshold search can be referred to as eBoost. Soft decoding requires multiple read retry operations in the eBoost stage to find the optimal intermediate read threshold. The number of read retry operations can be as high as 20, sometimes even more. The read latency for each read of a TLC memory device may be around 50µs, and the read latency for each read of a QLC memory device may be around 125µs. The number of read retry operations significantly increases read latency and reduces the quality of service (QoS) of the associated memory device. Therefore, various embodiments provide a read threshold optimization scheme that can reduce read latency and improve QoS. This read threshold optimization scheme can replace eBoost, thereby significantly reducing latency.

[0072] As mentioned above, when the initial read operation and all read retry operations using the read retry threshold set fail, Figure 5 The controller 100 should search for the optimal read threshold. In other words, the initial read threshold should be changed to, for example... Figure 9 The optimal read threshold is shown.

[0073] Figure 9 This is a diagram illustrating the variation in the read threshold set of LSB pages in a three-level cell (TLC) memory device. Note that LSB pages are accessed via... Figure 6 and Figure 7 The Gray code shown is used for programming.

[0074] exist Figure 9 In order to read the LSB page, the controller 100 should read the TLC according to an initial read threshold set [VT2, VT6] including a first read threshold VT2 and a second read threshold VT6. For example... Figure 9 As shown, the initial reading threshold set [VT2, VT6] can be an ideal reading threshold set with respect to the voltage distribution.

[0075] Based on the relative positions between the read threshold set [VT2, VT6] and the optimal read threshold set [VT2*, VT6*], there are four possible cases: RL, RR, LR, and LL. RL indicates that VT2 is to the left of VT2* and VT6 is to the right of VT6*, i.e., VT2* is to the right of VT2 and VT6* is to the left of VT6. RR indicates that VT2* is to the right of VT2 and VT6* is to the right of VT6. LR indicates that VT2* is to the left of VT2 and VT6* is to the right of VT6. LL indicates that VT2* is to the left of VT2 and VT6* is to the left of VT6.

[0076] Re-reference Figure 5 The optimal read threshold determiner 530 can perform an optimal read threshold search using the asymmetric ratio (AR) value associated with the decoding of multiple read attempts (i.e., read retry operations). In other words, the optimal read threshold determiner 530 can perform an AR domain transformation to search for the optimal read threshold. In some embodiments, the optimal read threshold determiner 530 can perform, as... Figure 10 The read threshold optimization operation is shown.

[0077] Figure 10 This is a flowchart illustrating a read threshold optimization operation 1000 according to an embodiment of the present invention. The read threshold optimization operation 1000 can be provided by firmware (e.g., Figure 5 The components of controller 100 (namely, read processor 510, decoder 520, and optimal read threshold determiner 530) are executed. This is an example and has no limitations. Figure 10 The read threshold optimization operation 1000 for LSB pages of TLC is illustrated. However, the read threshold optimization operation 1000 can be applied to other pages of TLC (i.e., MSB pages and CSB pages), other pages of QLC (i.e., MSB pages, LSB pages, CMSB pages, and CLSB pages), or pages of other types of NAND consistent with the teachings herein.

[0078] Reference Figure 10 At step 1010, the read processor 510 can perform read operations on multiple units using a selected read threshold set, which can be a previously used, i.e., a historical read threshold set. The selected threshold set can include a first read threshold and a second read threshold used in the last successful decoding. For example, the selected read threshold set can include a pair of read thresholds [VT2, VT6], i.e., a first read threshold VT2 and a second read threshold VT6. Further, the controller 100 can decode the data associated with the read operation.

[0079] Step 1020 can be executed when the decoding result of decoder 520 indicates that a read operation using the selected read threshold set has failed. At step 1020, read processor 510 can perform multiple read retry operations on multiple units using multiple read retry threshold sets. In some embodiments, each of the multiple read retry threshold sets may be different from the selected read threshold set. For example, the read retry threshold set may include a first read retry threshold and a second read retry threshold, each of which differs from its corresponding portion of the selected read threshold set (i.e., increases or decreases relative to its corresponding portion of the selected read threshold set). Further, controller 100 can decode the data associated with each of the read retry operations.

[0080] When the decoding result of decoder 520 indicates that all read retry operations using the read retry threshold set have failed, step 1030 can be performed to analyze the data from each of the read retry threshold operations. At step 1030, for each decoded data, the optimal read threshold determiner 530 can determine the asymmetric ratio (AR) and the number of unmet checks (USCs). In some embodiments, AR can indicate the ratio of the number of first binary values ​​(i.e., the number of 1s) to the number of second binary values ​​(i.e., the number of 0s) in the decoded data. For example, AR could be a value representing the number of 1s divided by the number of 0s in the decoded original data. In embodiments using reverse logic conventions, AR could be the number of 0s divided by the number of 1s.

[0081] At step 1040, the optimal reading threshold determiner 530 can determine the Z-axis such that the AR values ​​of the threshold set are arranged along the Z-axis in a set order. In some embodiments, such as Figure 11 As shown, the Z-axis is determined such that the AR values ​​of the threshold set are arranged in ascending order along the Z-axis.

[0082] exist Figure 11In the diagram, each symbol "●" represents a specific threshold set for the corresponding read attempt, such as [VT2, VT6], and the middle symbol "◇" represents the optimal threshold set [VT2*, VT6*]. For the threshold set [VT2, VT6] corresponding to read retries RR7, the AR is 0.8 and the number of USCs is 350. For the threshold set [VT2, VT6] corresponding to read retries RR49, the AR is 0.98 and the number of USCs is 250. For the threshold set [VT2, VT6] corresponding to read retries RR25, the AR is 1.05 and the number of USCs is 220. For the threshold set [VT2, VT6] corresponding to read retries RR10, the AR is 1.2 and the number of USCs is 350. In the example shown, the controller 100 can determine the Z-axis such that the AR values ​​of the threshold sets are arranged in ascending order along the Z-axis (i.e., ascending AR = 0.8 → AR = 0.98 → AR = 1.05 → AR = 1.2). In some embodiments, the Z-axis corresponds to a line with a slope of -1 that passes through the average of the set of a first reading threshold and a second reading threshold [VT2, VT6].

[0083] At step 1050, as Figure 12 As shown, the optimal reading threshold determiner 530 can characterize the properties of the first function g() according to the relationship AR = g(Z), and characterize the second function h() according to the relationship USC = h(Z). The first function g() simulates how the AR value changes along the Z-axis. The second function h() simulates how the USC value changes along the Z-axis.

[0084] At step 1060, the optimal read threshold determiner 530 can project each of the read thresholds in the set onto the Z-axis to obtain coordinate values ​​on the Z-axis. For example, the coordinates of all four previous read attempts [VT2, VT6] (e.g., Figure 11 The coordinates RR7, RR10, RR25, and RR49 in the model are projected onto the Z-axis to obtain the corresponding coordinate values ​​Z1, Z2, Z3, and Z4.

[0085] At step 1070, the optimal reading threshold determiner 530 can use the first function g() and coordinate values ​​Z1 to Z4 to estimate the first coordinate value on the Z-axis corresponding to the set AR value. In some embodiments, such as Figure 13A As shown, the optimal reading threshold determiner 530 can use the first function g() and coordinate values ​​Z1 to Z4 to estimate the first coordinate value Z_AR on the Z-axis corresponding to the set AR value "1".

[0086] Furthermore, the optimal read threshold determiner 530 can estimate a second coordinate value on the Z-axis corresponding to the lowest USC value, which lies on the curves fitted to Z1, Z2, Z3, and Z4. In some embodiments, such as Figure 13BAs shown, the optimal read threshold determiner 530 can estimate the second coordinate value Z_USC on the Z-axis corresponding to the lowest USC value. Various curve fitting or gradient descent algorithms can be used for this operation.

[0087] At step 1080, as Figure 14 As shown, the optimal read threshold determiner 530 can use the first coordinate value Z_AR and the second coordinate value Z_USC to determine the optimal read threshold set [VT2*, VT6*]. In some embodiments, the optimal read threshold determiner 530 can use the average of the first coordinate value Z_AR and the second coordinate value Z_USC to estimate the optimal read threshold set [VT2*, VT6*], as shown in the following equation [VT2*, VT6*] = f -1 ((Z_AR+Z_USC) / 2).

[0088] As described above, the embodiments provide a scheme for estimating the optimal read threshold using USC and AR values ​​associated with all previous read attempts obtained through AR domain transformation. This scheme requires a relatively low number of reads before soft decoding and does not require additional reads to search for the optimal intermediate read threshold for soft decoding.

[0089] Although the foregoing embodiments have been shown and described in detail for clarity and understanding, the invention is not limited to the details provided. Those skilled in the art will understand from the foregoing disclosure that many alternative ways of carrying out the invention exist. Therefore, the disclosed embodiments are illustrative and not restrictive. The invention is intended to cover all modifications and alternatives falling within the scope of the claims.

Claims

1. A memory system comprising: a memory device comprising a plurality of cells; and a controller coupled to the memory device, the controller: performs a plurality of read operations on the plurality of cells using a set of read thresholds and at least one set of read retry thresholds, each set of thresholds comprising a first read threshold and a second read threshold; decodes data associated with each of the plurality of read operations; determines, for decoded data of each of the plurality of read operations, an asymmetric ratio (AR) and a number of unsatisfied checks (USC), the AR representing a ratio of a number of first binary values to a number of second binary values in the decoded data; determines a Z-axis such that AR values of sets of thresholds are arranged in a set order along the Z-axis, the Z-axis extending diagonally along a set of the first read threshold and the second read threshold; and determines a best set of read thresholds using coordinate values on the Z-axis corresponding to set AR values and set USC values.

2. The memory system of claim 1, wherein the controller: characterizes a first function g() according to a relationship AR = g(Z) and a second function h() according to a relationship USC = h(Z); projects each of the set of read thresholds onto the Z-axis to obtain coordinate values on the Z-axis; and estimates, using the first function g() and the coordinate values, a first coordinate value on the Z-axis corresponding to a set AR value and estimates a second coordinate value on the Z-axis corresponding to a lowest USC value, and wherein the best set of read thresholds is determined using the first coordinate value and the second coordinate value.

3. The memory system of claim 2, wherein the plurality of cells are coupled to a word line and comprise a plurality of pages.

4. The memory system of claim 3, wherein the plurality of pages comprise a most significant bit (MSB) page, a center significant bit (CSB) page, and a least significant bit (LSB) page.

5. The memory system of claim 4, wherein the plurality of cells are programmed using a Gray code.

6. The memory system of claim 2, wherein the plurality of read operations comprise a read operation and one or more read retry operations, and wherein the controller performs the read operation using the set of read thresholds corresponding to a historical set of read thresholds and performs the read retry operations using two or more sets of read retry thresholds when the read operation fails.

7. The memory system of claim 2, wherein determining the Z-axis such that AR values of sets of thresholds are arranged in an ascending order along the Z-axis.

8. The memory system of claim 2, wherein the Z-axis corresponds to a line having a slope of -1 passing through an average of the first read threshold and the second read threshold.

9. The memory system of claim 2, wherein set AR values include an AR value of 1.

10. The memory system of claim 2, wherein the controller estimates the optimal read threshold set using an average of the first coordinate value and the second coordinate value.

11. A method of operating a memory system, the memory system comprising a memory device and a controller coupled to the memory device, the memory device comprising a plurality of cells, the method comprising: performing a plurality of read operations on the plurality of cells using a read threshold set and at least one read retry threshold set, each threshold set comprising a first read threshold and a second read threshold; decoding data associated with each of the plurality of read operations; determining, for decoded data of each of the plurality of read operations, an asymmetry ratio (AR) and a number of unsatisfied checks (USC), the AR representing a ratio of a number of first binary values to a number of second binary values in the decoded data; determining a Z-axis such that AR values of threshold sets are arranged in a set order along the Z-axis, the Z-axis extending diagonally along a set of the first read threshold and the second read threshold; and determining an optimal read threshold set using coordinate values on the Z-axis, the coordinate values on the Z-axis corresponding to set AR values and set USC values.

12. The method of claim 11, further comprising: characterizing a first function g() according to an AR = g(Z) relationship and a second function h() according to a USC = h(Z) relationship; projecting each of the read threshold sets onto the Z-axis to obtain coordinate values on the Z-axis; estimating, using the first function g() and the coordinate values, a first coordinate value on the Z-axis corresponding to a set AR value and estimating a second coordinate value on the Z-axis corresponding to a lowest USC value; and determining the optimal read threshold set using the first coordinate value and the second coordinate value.

13. The method of claim 12, wherein the plurality of cells are coupled to a word line and comprise a plurality of pages.

14. The method of claim 13, wherein the plurality of pages comprise a most significant bit (MSB) page, a center significant bit (CSB) page, and a least significant bit (LSB) page.

15. The method of claim 14, wherein the plurality of cells are programmed using Gray codes.

16. The method of claim 12, wherein the plurality of read operations comprise a read operation and one or more read retry operations, and wherein performing the plurality of read operations comprises: performing the read operation using a read threshold set corresponding to a historical read threshold set; and performing the read retry operations using two or more read retry threshold sets when the read operation fails.

17. The method of claim 12, wherein determining the Z-axis such that AR values of threshold sets are arranged in an ascending order along the Z-axis.

18. The method of claim 12, wherein the Z-axis corresponds to a line having a slope of -1 passing through an average of the first read threshold and the second read threshold.

19. The method of claim 12, wherein the set AR value includes an AR value of 1.

20. The method of claim 12, wherein determining the optimal read threshold set comprises: estimating the optimal read threshold set using an average of the first coordinate value and the second coordinate value.

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