Non-volatile memory device supporting high efficiency I / O interface

Abstract

Non-volatile memory devices are provided that support a high efficiency I / O interface. The non-volatile memory devices include a first pin to receive a first signal, a second pin to receive a second signal, a third pin to receive a third signal, a fourth pin to receive a write enable signal, an array of memory cells, and a memory interface circuit to obtain commands, addresses, and data from the third signal in a first mode and to obtain commands and addresses from the first and second signals and data from the third signal in a second mode. In the first mode, the memory interface circuit obtains commands from the third signal and obtains addresses from the third signal. In the second mode, the memory interface circuit obtains commands from the first and second signals and obtains addresses from the first and second signals.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0086227, filed on July 13, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The embodiments of this disclosure described herein relate to a semiconductor device, and more specifically, to a non-volatile memory device that supports a high-efficiency input / output (I / O) interface. Background Technology

[0003] Today, storage devices (such as solid-state drives (SSDs)) are widely used. A storage device can correspond to a memory system that includes non-volatile memory devices (such as flash memory) and a memory controller that controls the non-volatile memory devices. The non-volatile memory devices can exchange input / output signals with the memory controller via predetermined pins according to a protocol. For example, a non-volatile memory device can receive commands and addresses from the memory controller through specific input / output pins, and can exchange data with the memory controller through the same input / output pins. According to the above input / output interface, data may not be exchanged while commands or addresses are being transmitted, resulting in a reduction in the efficiency of the input / output interface. Therefore, there is a need for an input / output interface that can efficiently transfer data between the non-volatile memory device and the memory controller. Summary of the Invention

[0004] Embodiments of this disclosure provide a non-volatile memory device that supports high-efficiency input / output interfaces for efficient transmission of commands, addresses, and data.

[0005] According to an exemplary embodiment, a non-volatile memory device includes: a first pin for receiving a first signal from a memory controller; a second pin for receiving a second signal from the memory controller; a third pin for receiving a third signal from the memory controller; a fourth pin for receiving a write enable signal from the memory controller; a memory cell array; and memory interface circuitry, which obtains a command, an address, and data from the third signal in a first mode, and obtains a command and an address from the first and second signals and obtains data from the third signal in a second mode. In the first mode, the memory interface circuitry obtains a command from the third signal received during the enable period of the first signal based on the switching timing of the write enable signal, and obtains an address from the third signal received during the enable period of the second signal based on the switching timing of the write enable signal. In the second mode, based on the first signal with an enabled state received in the first cycle of the first time period, the memory interface circuit obtains a command from the first signal and the second signal received during the first time period based on the switching timing of the write enable signal, and based on the second signal with an enabled state received in the second cycle of the second time period, the memory interface circuit obtains an address from the first signal and the second signal received during the second time period based on the switching timing of the write enable signal, wherein the first time period includes a predetermined number of cycle periods and the second time period includes a predetermined number of cycle periods.

[0006] According to an exemplary embodiment, a non-volatile memory device includes: a first pin for receiving a control signal from a memory controller; a second pin for receiving a write enable signal from the memory controller; a third pin for receiving a data signal from the memory controller; a memory cell array; and memory interface circuitry. Based on the control signal received during a first cycle and a second cycle, which are time periods comprising a predetermined number of cycle periods, the memory interface circuitry obtains a command or address from control signals received during the remaining cycle periods of the time period. When the control signal received during the first cycle period is enabled, the memory interface circuitry obtains a command from the control signals received during the remaining cycle periods based on the switching timing of the write enable signal. When the control signal received during the second cycle period is enabled, the memory interface circuitry obtains an address from the control signals received during the remaining cycle periods based on the switching timing of the write enable signal.

[0007] According to an exemplary embodiment, a non-volatile memory device includes: a first pin for receiving a plurality of control signals, including a first control signal and a second control signal, from a memory controller; a second pin for receiving a write enable signal from the memory controller; a third pin for receiving a data signal from the memory controller; and memory interface circuitry. Based on a first control signal having an enabled state received in a first cycle of a first time period, the memory interface circuitry obtains a command from the plurality of control signals received during the first time period based on a switching timing of the write enable signal; and based on a second control signal having an enabled state received in a second cycle of a second time period, the memory interface circuitry obtains an address from the plurality of control signals received during the second time period based on a switching timing of the write enable signal. The first time period includes a predetermined number of cycle periods, and the second time period includes a predetermined number of cycle periods.

[0008] According to an exemplary embodiment, a memory controller may include: a first pin for sending a first control signal to a memory device; a second pin for sending a second control signal to the memory device; a third pin for sending a write enable signal to the memory device; a plurality of fourth pins for sending a plurality of data signals to the memory device; and a controller. When the first control signal in an enabled state is generated during a first cycle of a first time period including a predetermined number of cycle periods, the controller generates a first control signal and a second control signal including a command during the remaining cycle periods of the first time period, each cycle corresponding to one or more time periods of the write enable signal. When the second control signal in an enabled state is generated during a second cycle of a second time period including the predetermined number of cycle periods, the controller generates a first control signal and a second control signal including an address during the remaining cycle periods of the second time period. Attached Figure Description

[0009] The above and other objects and features of this disclosure will become clear from the detailed description of exemplary embodiments of this disclosure with reference to the accompanying drawings.

[0010] Figure 1 This is a block diagram illustrating a memory system according to an embodiment of the present disclosure.

[0011] Figure 2 It is shown Figure 1 A flowchart of the operation of the memory device.

[0012] Figure 3 This is a block diagram illustrating a memory system according to an embodiment of the present disclosure.

[0013] Figure 4 It shows the basis Figure 3 A conceptual diagram illustrating the signal patterns of a memory device.

[0014] Figure 5A It is shown that Figure 3 A timing diagram illustrating an example of a memory device receiving commands and addresses in the first mode.

[0015] Figure 5B It is shown that Figure 3 A timing diagram illustrating an example of a memory device receiving commands and addresses in the second mode.

[0016] Figure 6 It is shown Figure 3 A block diagram of an example memory interface circuit.

[0017] Figure 7 It is shown Figure 6 A block diagram of an example converter.

[0018] Figure 8 It is shown in the first mode in Figure 6 A timing diagram showing an example of signals generated at the memory interface circuit.

[0019] Figure 9 It is shown in the second mode in Figure 6 A timing diagram showing an example of signals generated at the memory interface circuit.

[0020] Figure 10 It is shown Figure 3 A flowchart illustrating an exemplary operation of a memory system.

[0021] Figure 11 It is shown Figure 3 A block diagram illustrating an example of an extended memory system.

[0022] Figure 12A It is shown that Figure 11 A timing diagram of an example of a memory device outputting data in the first mode.

[0023] Figure 12B It is shown that Figure 11 A timing diagram of an example of a memory device outputting data in the second mode.

[0024] Figure 12C It is shown that Figure 11 Timing diagrams of an example of a memory device operating in a first mode and a second mode during data output operations.

[0025] Figure 13 It is shown Figure 3 A block diagram of a memory device.

[0026] Figure 14 This is a circuit diagram illustrating a memory block according to an embodiment of the present disclosure.

[0027] Figure 15A An example of interleaved operation of a memory device in a first mode according to an embodiment of the present disclosure is shown.

[0028] Figure 15B An example of interleaved operation of a memory device in a second mode according to an embodiment of the present disclosure is shown.

[0029] Figure 16 This is a block diagram illustrating a memory system supporting a second mode according to an embodiment of the present disclosure.

[0030] Figure 17 It is shown that Figure 16 A timing diagram illustrating an example of a memory device receiving commands and addresses.

[0031] Figure 18 This is a block diagram illustrating a memory system supporting a second mode according to an embodiment of the present disclosure.

[0032] Figure 19 It is shown that Figure 18 A timing diagram illustrating an example of a memory device receiving commands and addresses.

[0033] Figure 20 This is a block diagram illustrating a memory system supporting a second mode according to an embodiment of the present disclosure.

[0034] Figure 21 It is shown that Figure 20 A timing diagram illustrating an example of a memory device receiving commands and addresses.

[0035] Figure 22 This is an exemplary cross-sectional view of a memory device according to an embodiment of the present disclosure.

[0036] Figure 23 This is a block diagram illustrating an SSD system using a memory device according to an embodiment of the present disclosure.

[0037] Figure 24 This is a block diagram illustrating a network system incorporating a memory system according to an embodiment of the present disclosure. Detailed Implementation

[0038] Hereinafter, embodiments of the present disclosure will be described in such detail and clarity that those skilled in the art can readily implement the present disclosure.

[0039] Figure 1 This is a block diagram illustrating a memory system according to an embodiment of the present disclosure. (Refer to...) Figure 1The memory system 10 may include a memory device 100 and a memory controller 200. The memory system 10 may support multiple channels CH1 to CHm, and the memory device 100 and the memory controller 200 may be connected through multiple channels CH1 to CHm, where m is a positive integer. For example, the memory system 10 may be implemented using a storage device such as a solid-state drive (SSD).

[0040] Memory device 100 may include a plurality of non-volatile memory devices NVM11 to NVMmn, where n is a positive integer. Each of the non-volatile memory devices NVM11 to NVMmn may be connected to one of a plurality of channels CH1 to CHm via a corresponding path. For example, non-volatile memory devices NVM11 to NVM1n may be connected to a first channel CH1 via paths W11 to W1n, and non-volatile memory devices NVM21 to NVM2n may be connected to a second channel CH2 via paths W21 to W2n. The “path” described herein may be, for example, a wire electrically connecting each non-volatile memory device to a channel. In an exemplary embodiment, each of the non-volatile memory devices NVM11 to NVMmn may be implemented using any memory cell capable of operating according to independent control signals from memory controller 200. For example, each of the non-volatile memory devices NVM11 to NVMmn may be implemented using a semiconductor chip or a semiconductor die, but this disclosure is not limited thereto. Each of the non-volatile memory devices NVM11 to NVMmn can be, for example, a semiconductor package comprising one or more semiconductor chips or semiconductor dies. For example, a semiconductor package may include one or more semiconductor chips or semiconductor dies mounted on a package substrate and encapsulated with a molding layer. As described herein, the term "semiconductor device" refers to a semiconductor chip or semiconductor die, or a semiconductor package.

[0041] The memory controller 200 can exchange signals with the memory device 100 through multiple channels CH1 to CHm. For example, the memory controller 200 can send commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the memory device 100 through channels CH1 to CHm, and can also receive data DATAa to DATAm from the memory device 100.

[0042] Through each channel, the memory controller 200 can select a non-volatile memory device connected to the corresponding channel and exchange data with the selected non-volatile memory device. For example, the memory controller 200 can select non-volatile memory device NVM11 from NVM11 to NVM1n connected to the first channel CH1. Through the first channel CH1, the memory controller 200 can send command CMDa, address ADDRa, and data DATAa to the selected non-volatile memory device NVM11 and can receive data DATAa from the selected non-volatile memory device NVM11.

[0043] The memory controller 200 can exchange signals with the memory device 100 in parallel through different channels. For example, while the memory controller 200 sends command CMDa to the memory device 100 through the first channel CH1, the memory controller 200 can also send command CMDb to the memory device 100 through the second channel CH2. Similarly, while the memory controller 200 receives data DATAa from the memory device 100 through the first channel CH1, the memory controller 200 can also receive data DATAb from the memory device 100 through the second channel CH2.

[0044] The memory controller 200 can control the overall operation of the memory device 100. The memory controller 200 can send signals to channels CH1 to CHm and can control the non-volatile memory devices NVM11 to NVM1n respectively connected to channels CH1 to CHm. For example, the memory controller 200 can send the command CMDa and the address ADDRa to the first channel CH1 and can control the non-volatile memory device selected from NVM11 to NVM1n.

[0045] Each of the non-volatile memory devices NVM11 to NVMmn can operate under the control of the memory controller 200. For example, non-volatile memory device NVM11 can receive a command CMDa, an address ADDRa, and data DATAa provided to the first channel CH1, and can program the data DATAa based on the command CMDa and the address ADDRa. For example, non-volatile memory device NVM21 can read data DATAb based on a command CMDb and an address ADDRb provided to the second channel CH2, and can send the read data DATAb to the memory controller 200.

[0046] exist Figure 1In the example shown, memory device 100 communicates with memory controller 200 through m channels and memory device 100 includes n non-volatile memory devices for each channel, but the number of channels and the number of non-volatile memory devices connected to a channel can be modified differently.

[0047] Figure 2 It is shown Figure 1 A flowchart illustrating the operation of the memory device. (Refer to...) Figure 1 and Figure 2 In operation S101, the mode of memory device 100 can be selected. One of a first mode and a second mode can be selected as the mode of memory device 100. For example, based on a command or control signal from memory controller 200 (e.g., a mode selection signal transmitted via a separate pin), memory device 100 can be set to either the first mode or the second mode. As another example, memory device 100 can be set to either the first mode or the second mode during the packaging process of memory device 100.

[0048] When the memory device 100 is set to the first mode, in operation S102, the memory device 100 can receive commands CMD and / or addresses ADDR (hereinafter referred to as "commands / addresses CMD / ADDR") via the pins through which data "DATA" is sent / received. For example, when data DATAa is sent / received via a specific pin of the first channel CH1, the memory device 100 can receive commands / addresses CMD / ADDRa from the memory controller 200 via the same specific pin. When the memory device 100 is set to the first mode, the memory controller 200 can send commands / addresses CMD / ADDR via the pins through which data "DATA" is sent / received.

[0049] When the memory device 100 is configured in the second mode, in operation S103, the memory device 100 can receive the command / address CMD / ADDR through a pin different from the pin through which the data "DATA" is sent / received. For example, when the data DATAa is sent / received through the first pin of the first channel CH1, the memory device 100 can receive the command / address CMD / ADDRa from the memory controller 200 through the second pin. When the memory device 100 is configured in the second mode, the memory controller 200 can send the command / address CMD / ADDR through a pin different from the pin through which the data "DATA" is sent / received. For example, when the memory device 100 is configured in the second mode, a set of pins can be used to send both the command / address CMD / ADDR and the data "DATA", wherein each pin in the set is configured to send only one of the command / address CMD / ADDR and the data "DATA". Therefore, in the second mode, the first set of pins can be used to send commands / addresses CMD / ADDR without sending data "DATA", and the second set of pins can be used to send data "DATA" without sending commands / addresses CMD / ADDR.

[0050] According to embodiments of this disclosure, in a second mode, the memory device 100 and the memory controller 200 can exchange command / address CMD / ADDR and data "DATA" in parallel via the same channel. For example, while the memory device 100 receives data DATAa from the memory controller 200 through a first pin of the first channel CH1, the memory device 100 can also receive command / address CMD / ADDRa from the memory controller 200 through a second pin of the first channel CH1. In contrast, in the first mode, the memory device 100 and the memory controller 200 may not be able to exchange command / address CMD / ADDR and data "DATA" in parallel via the same channel. For example, after the memory device 100 receives data DATAa from the memory controller 200 through a specific pin of the first channel CH1, the memory device 100 can receive command / address CMD / ADDRa from the memory controller 200 through the same specific pin of the first channel CH1.

[0051] As described above, the memory device 100 can operate according to one selected from a first mode and a second mode, and the memory controller 200 can send a command / address CMD / ADDR to the memory device 100 via pins predetermined according to the mode of the memory device 100. In an exemplary embodiment, the pins through which the command / address CMD / ADDR and data "DATA" are sent according to the mode can be predetermined according to a standard.

[0052] The following will refer to Figures 3 to 15B An example of a memory system operating in a first or second mode selected as memory device 100 is described more fully.

[0053] Figure 3 This is a block diagram illustrating a memory system according to an embodiment of the present disclosure. (Refer to...) Figure 3 The memory system 20 may include a memory device 300 and a memory controller 400. The memory device 300 may correspond to... Figure 1 The non-volatile memory devices NVM11 to NVMmn are based on one of multiple channels CH1 to CHm and communicate with the memory controller 400. The memory controller 400 may correspond to Figure 1 The memory controller 200.

[0054] The memory device 300 may include a first pin P11, a second pin P12, a third pin P13, a fourth pin P14, a memory interface circuit (or memory I / F) 310, a control logic circuit (or control logic) 320, and a memory cell array 330. The number of pins included is given only as an example, and in different embodiments, the memory device 300 may include a larger number of pins. The memory interface circuit 310 may receive a first signal SIG1, a second signal SIG2, a third signal SIG3, and a write enable signal nWE via the first pin P11 to the fourth pin P14. The memory interface circuit 310 may receive the third signal SIG3 via the third pin P13 and may also send the third signal SIG3 to the memory controller 400. Each of the first pin P11, the second pin P12, the third pin P13, and the fourth pin P14 may be an external connection terminal of the memory device formed of a conductive material. Each pin can be, for example, a pad (or "solder pad"), a bump, or a conductive lead, and each pin can transmit signals to and from the memory device 300.

[0055] The write enable signal nWE can remain static (e.g., high or low) and can subsequently toggle between high and low for a specific period of time. For example, the write enable signal nWE can toggle during the period when the command CMD or address ADDR is sent from the memory controller 400 or received by the memory device 300. In this case, the memory interface circuitry 310 can obtain the command CMD or address ADDR based on the write enable signal nWE.

[0056] In the first mode, the memory interface circuit 310 can obtain the command / address CMD / ADDR from the third signal SIG3. Based on the switching timing of the write enable signal nWE, the memory interface circuit 310 can obtain the command CMD from the third signal SIG3 received during the enable period of the first signal SIG1 (e.g., when the first signal SIG1 is high). Based on the switching timing of the write enable signal nWE, the memory interface circuit 310 can obtain the address ADDR from the third signal SIG3 received during the enable period of the second signal SIG2 (e.g., when the second signal SIG2 is high). In this case, the first signal SIG1 can be referred to as the "command latch enable signal CLE", and the second signal SIG2 can be referred to as the "address latch enable signal ALE".

[0057] In the second mode, based on the switching timing of the write enable signal nWE, the memory interface circuit 310 can obtain the command / address CMD / ADDR from the first signal SIG1 and the second signal SIG2. In an exemplary embodiment, when the first signal SIG1 is enabled at a specific timing (e.g., during a specific time period), the memory interface circuit 310 can obtain the command CMD from the first signal SIG1 and the second signal SIG2. When the second signal SIG2 is enabled at a specific timing, the memory interface circuit 310 can obtain the address ADDR from the first signal SIG1 and the second signal SIG2.

[0058] The memory interface circuit 310 can obtain the data "DATA" from the third signal SIG3 or can generate the third signal SIG3 containing the data "DATA", regardless of the mode. Although in Figure 3 Not shown, but the memory interface circuit 310 can obtain the data "DATA" from the third signal SIG3 based on the data strobe signal DQS received from the memory controller 400 via a separate pin. The memory interface circuit 310 can generate the data strobe signal DQS and can send the third signal SIG3, including the data "DATA", to the memory controller 400 based on the thus generated data strobe signal DQS. In the above manner, the memory interface circuit 310 is configured to access the memory cell array 330, for example, based on the control of the control logic 320 described further below, using the aforementioned first signal SIG1, second signal SIG2, and third signal SIG3, the write enable signal nWE, and the commands, addresses, and data obtained from those signals.

[0059] The control logic circuit 320 can control various types of operations of the memory device 300. The control logic circuit 320 can receive commands / addresses (CMD / ADDR) obtained from the memory interface circuit 310. The control logic circuit 320 can generate control signals for controlling any other components of the memory device 300 based on the received commands / addresses (CMD / ADDR). For example, the control logic circuit 320 can generate various types of control signals for programming data "DATA" into or reading data "DATA" from the memory cell array 330.

[0060] Under the control of the control logic circuit 320, the memory cell array 330 can store the data "DATA" obtained from the memory interface circuit 310. Under the control of the memory interface circuit 310, the memory cell array 330 can output the stored data "DATA" to the memory interface circuit 310.

[0061] The memory cell array 330 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, this disclosure is not limited thereto. For example, the memory cells may include resistive random access memory (RRAM) cells, ferroelectric random access memory (FRAM) cells, phase-change random access memory (PRAM) cells, thyristor random access memory (TRAM) cells, or magnetic random access memory (MRAM) cells. Hereinafter, embodiments of the present disclosure will be described based on embodiments in which the memory cells are NAND flash memory cells.

[0062] The memory controller 400 may include a first pin P21, a second pin P22, a third pin P23, a fourth pin P24, and a controller interface circuit (or controller I / F) 410. The first pin P21 to the fourth pin P24 may correspond to the first pin P11 to the fourth pin P14 of the memory device 300. Thus, the controller interface circuit 410 can send a first signal SIG1 to a third signal SIG3 and a write enable signal nWE through the first pin P21 to the fourth pin P24.

[0063] When the memory device 300 is in the first mode, the controller interface circuit 410 can send the command / address CMD / ADDR to the memory device 300 via the third signal SIG3 and the third pin P23. When the memory device 300 is in the second mode, the controller interface circuit 410 can send the command / address CMD / ADDR to the memory device 300 via the first signal SIG1 and the second signal SIG2, as well as the first pin P21 and the second pin P22. The controller interface circuit 410 can send or receive the data "DATA" from the memory device 300 via the third signal SIG3 and the third pin P23, regardless of the mode.

[0064] For ease of description, the operation of the memory device 300 in the first and second modes will be described below. However, this can also be applied to the memory controller 400. For example, signals SIG1 to SIG3 and nWE received through the first pin P11 to the fourth pin P14 of the memory device 300 can be transmitted through the first pin P21 to the fourth pin P24 of the memory controller 400.

[0065] Figure 4 It shows the basis Figure 3 A conceptual diagram illustrating the signal patterns of a memory device. (Refer to...) Figure 3 and Figure 4In the first mode, during a first time t1 (e.g., a first time period), the memory device 300 can obtain a first command CMD1 from the third signal SIG3. During a second time t2 (e.g., a second time period), the memory device 300 can obtain data "DATA" from the third signal SIG3, or can send the third signal SIG3 including the data "DATA" to the memory controller 400. For example, if the first command CMD1 is a programming command, the memory device 300 can receive the data "DATA" from the memory controller 400 according to the first command CMD1. If the first command CMD1 is a read command, the memory device 300 can send the data "DATA" to the memory controller 400 according to the first command CMD1. During a third time t3 (e.g., a third time period), the memory device 300 can obtain a second command CMD2 from the third signal SIG3. Therefore, in the first mode, the first command CMD1, the data "DATA", and the second command CMD2 can be sent from the memory controller 400 to the memory device 300 via the third signal SIG3 during the period from the first time t1 to the third time t3. On the other hand, in the first mode, the first command CMD1 and the second command CMD2 can be sent from the memory controller 400 to the memory device 300 via the third signal SIG3 during the period from the first time t1 to the third time t3, and the data “DATA” can be sent from the memory device 300 to the memory controller 400 via the third signal SIG3 during the period from the first time t1 to the third time t3.

[0066] In the second mode, the memory device 300 may receive a first command CMD1 from a first signal SIG1 and a second signal SIG2 during a first time t1 (e.g., a first time period). The memory device 300 may receive data “DATA” from a third signal SIG3 during a second time t2 (e.g., a second time period), or may send a third signal SIG3 including data “DATA” to the memory controller 400 during the second time t2 (e.g., a second time period). The memory device 300 may receive a second command CMD2 from the first signal SIG1 and the second signal SIG2 simultaneously with the data “DATA” being received or transmitted via the third signal SIG3. That is, in the second mode, the first command CMD1, the data “DATA”, and the second command CMD2 may be sent to the memory device 300 via the first signal SIG1, the second signal SIG2, and the third signal SIG3 during the period from the first time t1 to the second time t2. On the other hand, the first command CMD1 and the second command CMD2 can be sent to the memory device 300 via the first signal SIG1 and the second signal SIG2 during the period from the first time t1 to the second time t2, and the data "DATA" can be sent to the memory controller 400 via the third signal SIG3 during the period from the first time t1 to the second time t2. That is, the time period for sending the first command CMD1, the data "DATA", and the second command CMD2 in the second mode can be shorter than the time period for sending the first command CMD1, the data "DATA", and the second command CMD2 in the first mode.

[0067] Figure 5A It is shown that Figure 3 A timing diagram illustrating an example of a memory device receiving commands and addresses in the first mode. Figure 5B It is shown that Figure 3 A timing diagram illustrating an example of a memory device receiving commands and addresses in second mode. In detail, Figure 5A and Figure 5B An example is shown in which the memory device 300 receives the command CMD and addresses ADDR0 to ADDR4. For example, addresses ADDR0 and ADDR1 can constitute a column address, and addresses ADDR2 to ADDR4 can constitute a row address. However, this disclosure is not limited thereto. The following, as... Figure 5A and Figure 5B The embodiments of this disclosure are described in the example shown, which is based on the third signal SIG3[7:0] being received through eight third pins P13 (i.e., eight signal lines), but this disclosure is not limited thereto.

[0068] Reference Figure 3 and Figure 5AIn the first mode, the memory device 300 can receive a third signal SIG3[7:0] including command CMD and addresses ADDR0 to ADDR4. Simultaneously with receiving the third signal SIG3[7:0] including command CMD and addresses ADDR0 to ADDR4, the memory device 300 can receive a switched write enable signal nWE. For example, before receiving command CMD and addresses ADDR0 to ADDR4 from the third signal SIG3[7:0] (i.e., before the first time t1), the memory device 300 can receive a write enable signal nWE that switches from a static state (e.g., a high level).

[0069] The memory device 300 can obtain the command CMD from the third signal SIG3[7:0] during the enable period of the first signal SIG1, and can obtain addresses ADDR0 to ADDR4 from the third signal SIG3[7:0] during the enable period of the second signal SIG2. For example, the memory device 300 can sample (or latch) the third signal SIG3[7:0] at the rising edge of the write enable signal nWE to obtain the command CMD and addresses ADDR0 to ADDR4. In this case, each of the command CMD and addresses ADDR0 to ADDR4 can include 8 signal values ​​(i.e., 8 bits) received through 8 third pins P13 at the rising edge of the write enable signal nWE. For example, the command CMD can include the signal value received through the third signal SIG3[7:0] at the first time t1, and each of addresses ADDR0 to ADDR4 can include the signal value received through the third signal SIG3[7:0] at each of the second time t2 to the sixth time t6.

[0070] Reference Figure 3 and Figure 5B In the second mode, the memory device 300 can receive a first signal SIG1 and a second signal SIG2, which include the command CMD and addresses ADDR0 to ADDR4. Simultaneously with receiving the first signal SIG1 and the second signal SIG2, the memory device 300 can receive a switched write enable signal nWE from the memory controller 400. For example, the switching frequency of the write enable signal nWE received in the second mode can be greater than the switching frequency of the write enable signal nWE received in the first mode.

[0071] The period during which the command CMD and addresses ADDR0 to ADDR4 are received can be divided into multiple time periods based on the write enable signal nWE. Each time period may include a predetermined number of cycles (hereinafter, a time period including a predetermined number of cycles is referred to as a "predetermined time period" and may also be referred to as a "control signal time period"), and one cycle may correspond to one or more time periods (or cycles) of the write enable signal nWE. For example, as Figure 5B As shown, the time periods during which commands CMD and addresses ADDR0 to ADDR4 are received can be divided into six time periods, each of which may include five cycles. In this case, one cycle may correspond to one time period for writing the enable signal nWE. However, this is only an example, and in cases where other numbers of signals are used for commands and addresses, each control signal time period may have more than five cycles or less than five cycles.

[0072] The memory device 300 can obtain a command CMD or an address ADDR from a first signal SIG1 and a second signal SIG2 received during a predetermined time period (e.g., one of a first time period to a sixth time period). If the first signal SIG1 received during a specific cycle of the predetermined time period is in an enabled state (e.g., at a high level "H"), the memory device 300 can obtain the command CMD from the first signal SIG1 and the second signal SIG2 received during the predetermined time period. If the second signal SIG2 received during a specific cycle of the predetermined time period is in an enabled state, the memory device 300 can obtain the address ADDR from the first signal SIG1 and the second signal SIG2 received during the predetermined time period.

[0073] For example, if the first signal SIG1 received during the first cycle C1 of the first time period is enabled (e.g., at a high level "H"), the memory device 300 can obtain the command CMD from the first signal SIG1 and the second signal SIG2 received during the remaining cycle C1 of the first time period. In this case, the second signal SIG2 received during the first cycle C1 can be disabled (e.g., at a low level "L"). The memory device 300 can obtain the command CMD from the eight signal values ​​C[0] to C[7] of the first signal SIG1 and the second signal SIG2 sampled at the rising edge of the write enable signal nWE during the remaining cycle C1. The signal values ​​C[0] to C[7] of the first signal SIG1 and the second signal SIG2 can correspond to Figure 5A The signal value of the third signal SIG3[7:0] sampled at the first time t1.

[0074] For example, when the write enable signal nWE changes from a static state to a switching state, the first cycle C1 may correspond to the first rising edge of the write enable signal nWE. However, this disclosure is not limited thereto. For example, the rising edge of the write enable signal nWE corresponding to the first cycle C1 may vary according to a protocol.

[0075] For example, if the second signal SIG2 received during the second cycle C2 of the second time period is enabled (e.g., at a high level "H"), the memory device 300 can obtain address ADDR0 from the first signal SIG1 and the second signal SIG2 received during the remaining cycle CS2 of the second time period. In this case, the first signal SIG1 received during the second cycle C2 can be disabled (e.g., at a low level "L"). The memory device 300 can obtain address ADDR0 from the eight signal values ​​A0[0] to A0[7] of the first signal SIG1 and the second signal SIG2 sampled at the rising edge of the write enable signal nWE during the remaining cycle CS2. The signal values ​​A0[0] to A0[7] of the first signal SIG1 and the second signal SIG2 can correspond to Figure 5A The signal value of the third signal SIG3[7:0] sampled at the second time t2. Similarly, the memory device 300 can obtain addresses ADDR1 to ADDR4 from the first signal SIG1 and the second signal SIG2 received during the third to sixth time periods.

[0076] When the first signal SIG1 and the second signal SIG2 are received, each of the third signals SIG3[7:0] can be in a "dot't care" state. For example, each of the third signals SIG3[7:0] can be in one of a low level, a high level, or a high impedance (high z) state. When each of the third signals SIG3[7:0] is at a low level or a high level, the value of each of the third signals SIG3[7:0] can be a valid value or an invalid value. For example, when the command CMD or the addresses ADDR0 to ADDR4 are received via the first signal SIG1 and the second signal SIG2, and when the memory device 300 receives the data "DATA" via the third signals SIG3[7:0], each of the third signals SIG3[7:0] can include a valid data value.

[0077] Reference Figure 5BExamples of obtaining command CMD or address ADDR from first signal SIG1 and second signal SIG2 received during a specific cycle of a predetermined time period are described, but this disclosure is not limited thereto. In one exemplary embodiment, when first signal SIG1 received during the first cycle of the predetermined time period is enabled, the memory device 300 can obtain command CMD from first signal SIG1 and second signal SIG2 received during the predetermined time period; when second signal SIG2 received during the second cycle of the predetermined time period is enabled, the memory device 300 can obtain address ADDR from first signal SIG1 and second signal SIG2 received during the predetermined time period. In another exemplary embodiment, when first signal SIG1 received during the first cycle of the predetermined time period is enabled, the memory device 300 can obtain command CMD from first signal SIG1 and second signal SIG2 received during the predetermined time period; when first signal SIG1 received during the second cycle of the predetermined time period is enabled, the memory device 300 can obtain address ADDR from first signal SIG1 and second signal SIG2 received during the predetermined time period. That is, this disclosure may include various embodiments capable of identifying (or determining) command CMD or address ADDR received during a predetermined time period.

[0078] Figure 6 It is shown Figure 3 A block diagram of an example memory interface circuit. In detail, Figure 6 An example of a memory interface circuit 310 for receiving commands CMD and addresses ADDR according to the selected mode is shown. (Refer to...) Figure 6 The memory interface circuit 310 may include buffers 311a to 311h, first flip-flops (F / F) 312a to third flip-flops (F / F) 312c, converter 313, first multiplexer (MUX) 314a to fourth multiplexer (MUX) 314d, command loop generator 315 and address loop generator 316.

[0079] The first signal SIG1 to the third signal SIG3 received through pins P11 to P13 can be provided to the first flip-flop 312a to the third flip-flop 313c via buffers 311a, 311c, and 311e, respectively. The write enable signal nWE received through pin P14 can be provided to the first flip-flop 312a to the third flip-flop 312c and the converter 313. The first flip-flop 312a to the third flip-flop 312c can sample the first signal SIG1 to the third signal SIG3 at the rising edge of the write enable signal nWE, and can output the first sample signal S_S1 to the third sample signal S_S3. The first sample signal S_S1 and the second sample signal S_S2 can be provided to the converter 313 and the first multiplexer 314a and the second multiplexer 314b, and the third sample signal S_S3 can be provided to the third multiplexer 314c. The write enable signal nWE can be provided to the converter 313 and the fourth multiplexer 314d.

[0080] In the first mode, the first sampling signal S_S1 may include information indicating whether the third sampling signal S_S3 includes the command CMD, and the second sampling signal S_S2 may include information indicating whether the third sampling signal S_S3 includes the address ADDR. The third sampling signal S_S3 may include either the command CMD or the address ADDR.

[0081] In the second mode, the first sampling signal S_S1 may include information indicating whether the first sampling signal S_S1 and the second sampling signal S_S2 include the command CMD, and the second sampling signal S_S2 may include information indicating whether the first sampling signal S_S1 and the second sampling signal S_S2 include the address ADDR. The first sampling signal S_S1 and the second sampling signal S_S2 may include either the command CMD or the address ADDR.

[0082] Converter 313 can generate a restored command latch enable signal R_CLE, a restored address latch enable signal R_ALE, a restored command / address signal R_CA, and a restored write enable signal R_nWE using a first sampling signal S_S1, a second sampling signal S_S2, and a write enable signal nWE. The restored command latch enable signal R_CLE may include information indicating whether the restored command / address signal R_CA includes the command CMD, and the restored address latch enable signal R_ALE may include information indicating whether the restored command / address signal R_CA includes the address ADDR. In the first mode, because the first sampling signal S_S1 and the second sampling signal S_S2 do not include the command CMD or the address ADDR, the restored command / address signal R_CA output from converter 313 in the first mode may not include the command CMD or the address ADDR. In the second mode, because the first sampling signal S_S1 and the second sampling signal S_S2 include either command CMD or address ADDR, the recovered command / address signal R_CA output from converter 313 in the second mode can include either command CMD or address ADDR. For example, in the second mode, the recovered command / address signal R_CA output from converter 313 can include a valid command value or a valid address value.

[0083] In the second mode, each of the first sampled signal S_S1 and the second sampled signal S_S2 provided to converter 313 during a predetermined time period may include, as referenced Figure 5B The serialized value of the command / address CMD / ADDR is described. Converter 313 can output the serialized command / address (CMD / ADDR) values ​​received during a predetermined time period in parallel via the recovered command / address signal R_CA. For example, converter 313 can convert the serialized command / address (CMD / ADDR) value into a deserialized command / address (CMD / ADDR) value. To output the command / address (CMD / ADDR) value in parallel, the number of signal lines through which the recovered command / address signal R_CA is transmitted can be equal to the number of signal lines through which the third signal SIG3 is transmitted. (Refer to...) Figure 7 The operation of converter 313 will be described more fully.

[0084] The first multiplexer 314a to the fourth multiplexer 314d can receive signals R_CLE, R_ALE, R_CA, and R_nWE output from converter 313 and / or bypass signals S_S1, S_S2, S_S3, and nWE from converter 313. Based on the mode selection signal PM, the first multiplexer 314a to the fourth multiplexer 314d can output signals R_CLE, R_ALE, R_CA, and R_nWE received from converter 313, or can output bypassed signals S_S1, S_S2, S_S3, and nWE. For example, the mode selection signal PM can be received from... Figure 3 A memory controller 400 is provided, or it may be generated in the memory device 300 according to the pattern.

[0085] For example, the first multiplexer 314a to the fourth multiplexer 314d can output bypassed signals S_S1, S_S2, S_S3, and nWE based on the mode selection signal PM indicating the first mode. For example, the first multiplexer 314a to the fourth multiplexer 314d can output signals R_CLE, R_ALE, R_CA, and R_nWE received from the converter 313 based on the mode selection signal PM indicating the second mode. In this case, the information of the signals R_CLE, R_ALE, R_CA, and R_nWE output in the second mode can correspond to the information of the signals S_S1, S_S2, S_S3, and nWE output in the first mode, respectively.

[0086] The command loop generator 315 can generate a command loop signal CMD_C based on the signal output from the first multiplexer 314a and the signal output from the fourth multiplexer 314d. Here, the command loop signal CMD_C can be a signal used to extract the command CMD from the command / address signal CA output from the self-buffer 311h. For example, in a first mode, the command loop generator 315 can generate the command loop signal CMD_C based on the first sampled signal S_S1 output from the first multiplexer 314a and the write enable signal nWE output from the fourth multiplexer 314d. For example, in a second mode, the command loop generator 315 can generate the command loop signal CMD_C based on the recovered command latch enable signal R_CLE output from the first multiplexer 314a and the recovered write enable signal R_nWE output from the fourth multiplexer 314d.

[0087] Address loop generator 316 can generate address loop signal ADDR_C based on signals output from second multiplexer 314b and fourth multiplexer 314d. Here, address loop signal ADDR_C can be a signal used to extract address ADDR from command / address signal CA output from self-buffer 311h. For example, in a first mode, address loop generator 316 can generate address loop signal ADDR_C based on second sampling signal S_S2 output from second multiplexer 314b and write enable signal nWE output from fourth multiplexer 314d. For example, in a second mode, address loop generator 316 can generate address loop signal ADDR_C based on recovered address latch enable signal R_ALE output from second multiplexer 314b and recovered write enable signal R_nWE output from fourth multiplexer 314d.

[0088] In the first mode, the third sampled signal S_S3 output from the third multiplexer 314c can be output as the command / address signal CA through the buffer 311h. In the second mode, the recovered command / address signal R_CA output from the third multiplexer 314c can be output as the command / address signal CA through the buffer 311h.

[0089] In one exemplary embodiment, the command loop signal CMD_C and the command / address signal CA can be transmitted to... Figure 3 The control logic circuit 320 (e.g., the command decoder in the control logic circuit 320) can receive the command CMD from the command / address signal CA based on the command loop signal CMD_C. The address loop signal ADDR_C and the command / address signal CA can be transmitted to... Figure 3 The control logic circuit 320 (e.g., the address decoder in the control logic circuit 320) can receive the address ADDR from the command / address signal CA based on the address loop signal ADDR_C.

[0090] In one exemplary embodiment, in response to a status read command from the memory controller 400, the memory interface circuit 310 can send the status information SR of the memory device 300 to the memory controller 400 via at least one of the first pin P11 and the second pin P12. For example, as Figure 6As shown, buffers 311b and 311d can send a first signal SIG1, including status information SR, and a second signal SIG2 to the memory controller 400. The memory interface circuit 310 can send a third signal SIG3, including data "DATA", to the memory controller 400 via buffer 311f connected to the third pin P13. Thus, when the status information SR and the data "DATA" are transmitted through different pins, when the data "DATA" is transmitted from the first memory device (e.g., ...), ... Figure 1 The non-volatile memory device (NVM11) is transferred to the memory controller 200 (refer to...). Figure 1 When, the second memory device (e.g., Figure 1 The status information of the non-volatile memory device (NVM12) can be provided from the second memory device to the memory controller 200. Thus, when data "DATA" is received from the first memory device, the memory controller 200 can provide the command / address CMD / ADDR to the second memory device based on the status information of the second memory device.

[0091] Figure 7 It is shown Figure 6 A block diagram of an example converter. See reference. Figure 6 As described, since the output signals R_CLE, R_ALE, R_CA, and R_nWE of converter 313 have valid values ​​in the second mode, the operation of converter 313 in the second mode will be described below. (Refer to...) Figure 7 The converter 313 may include a divider 317, a spreader 318, and first flip-flops 319a to third flip-flops 319c.

[0092] Frequency divider 317 can receive a write enable signal nWE and divide the write enable signal nWE to generate internal clock signals ICK with different phases. For example, the number of internal clock signals ICK can be equal to the number of cycles (or cycle periods) included in a predetermined time period. The time period of each internal clock signal ICK can correspond to the predetermined time period. The internal clock signals ICK can be provided to spread spectrum 318. Frequency divider 317 can also generate a recovered write enable signal R_nWE with the same phase as one of the internal clock signals ICK. In this case, the time period of the recovered write enable signal R_nWE can correspond to the predetermined time period.

[0093] The spreader 318 can sample the first sampling signal S_S1 and the second sampling signal S_S2 based on the internal clock signal ICK, and can generate a sampling command latch enable signal S_CLE, a sampling address latch enable signal S_ALE, and a sampling command / address signal S_CA. For example, the spreader 318 can generate the sampling command latch enable signal S_CLE from the first sampling signal S_S1, and can generate the sampling address latch enable signal S_ALE from the second sampling signal S_S2. The spreader 318 can generate the sampling command / address signal S_CA from the first sampling signal S_S1 and the second sampling signal S_S2.

[0094] For example, the spreader 318 can sample the first sample signal S_S1 and the second sample signal S_S2, including the serialized command / address (CMD / ADDR) value, at different edges of the internal clock signal ICK (e.g., at the times corresponding to different edges). Thus, the command / address (CMD / ADDR) value can be sampled from the first sample signal S_S1 and the second sample signal S_S2. The spreader 318 can be connected via signal lines (the number of which is equal to...) Figure 6 The number of signal lines used to transmit the third signal SIG3) outputs a sampled command / address (CMD / ADDR) signal S_CA containing the sampled command / address (CMD / ADDR) value. In this case, because the command / address (CMD / ADDR) values ​​are output through the corresponding signal lines according to the edge timing of the internal clock signal ICK, the command / address (CMD / ADDR) value of the sampled command / address signal S_CA may be misaligned at a certain timing (e.g., at the time corresponding to an edge).

[0095] The first flip-flop 319a to the third flip-flop 319c can sample the sampled signals S_CLE, S_ALE, and S_CA at the rising (or falling) edge of the recovered write enable signal R_nWE to output the recovered signals R_CLE, R_ALE, and R_CA. The third flip-flop 319c can receive a sampled command / address signal S_CA, including the command / address (CMD / ADDR) value, during a predetermined time period, and can sample the received command / address (CMD / ADDR) value at the edge of the recovered write enable signal R_nWE. The third flip-flop 319c can output the recovered command / address signal R_CA, including the sampled command / address (CMD / ADDR) value, in a single timing sequence. Thus, the third flip-flop 319c can output the sampled command / address (CMD / ADDR) value in parallel via the recovered command / address signal R_CA.

[0096] Figure 8 It is shown in the first mode in Figure 6A timing diagram illustrating an example of signals generated at the memory interface circuit. (Refer to...) Figure 5A , Figure 6 and Figure 8 The first flip-flop 312a to the third flip-flop 312c can sample the first signal SIG1 to the third signal SIG3 at the rising edge of the write enable signal nWE, and can generate the first sampled signal S_S1, the second sampled signal S_S2, and the third sampled signal S_S3[7:0]. In the first mode, the third sampled signal S_S3[7:0] can be output as the command / address signal CA[7:0].

[0097] Based on the rising edge of the write enable signal nWE, the command loop generator 315 can generate a switching command loop signal CMD_C during the enable period (e.g., logic high) of the first sample signal S_S1. For example, as Figure 8 As shown, the command loop generator 315 can generate a command loop signal CMD_C with a rising edge (marked as ①) corresponding to the first rising edge (marked as ①) of the write enable signal nWE.

[0098] Based on the rising edge of the write enable signal nWE, the address loop generator 316 can generate a switched address loop signal ADDR_C during the enable period (e.g., logic high) of the second sampling signal S_S2. For example, as Figure 8 As shown, the address loop generator 316 can generate an address loop signal ADDR_C with five rising edges (numbered ② to ⑥) corresponding to the second to sixth rising edges (numbered ② to ⑥) of the write enable signal nWE.

[0099] As described above, in the first mode, the memory interface circuit 310 can generate a command loop signal CMD_C, an address loop signal ADDR_C, and command / address signals CA[7:0] corresponding to the eight signal lines. In this case, the command CMD can be extracted from the command / address signals CA[7:0] based on the command loop signal CMD_C, and the addresses ADDR0 to ADDR4 can be extracted from the command / address signals CA[7:0] based on the address loop signal ADDR_C.

[0100] Figure 9 It is shown in the second mode in Figure 6 A timing diagram illustrating an example of signals generated at the memory interface circuit. (Refer to...) Figure 5B , Figure 6 , Figure 7 and Figure 9The frequency divider 317 can divide the write enable signal nWE to generate five internal clock signals ICK[0] to ICK[4] with different phases. In this case, the frequency divider 317 can also generate a recovered write enable signal R_nWE, which has the same phase as the internal clock signal ICK[0] and is delayed by one time period relative to the internal clock signal ICK[0]. The time period of each of the internal clock signals ICK[0] to ICK[4] and the recovered write enable signal R_nWE can correspond to five cycles of the write enable signal nWE (i.e., a predetermined time period).

[0101] The first sampled signal S_S1 and the second sampled signal S_S2 provided to the spreader 318 can each correspond to a delay of about half a time period. Figure 5B The first signal SIG1 and the second signal SIG2. Hereinafter, for ease of description, it is assumed that the internal clock signals ICK[0] to ICK[4] are delayed by half a time period relative to the write enable signal nWE according to the first sampling signal S_S1 and the second sampling signal S_S2.

[0102] Based on the rising edge of the internal clock signal ICK[0], the spreader 318 can generate a sampled command latch enable signal S_CLE from the first sampling signal S_S1. Based on the rising edge of the internal clock signal ICK[0], the spreader 318 can generate a sampled address latch enable signal S_ALE from the second sampling signal S_S2. Based on the rising edges of the internal clock signals ICK[1] to ICK[4], the spreader 318 can generate sampled command / address signals S_CA[7:0] from the first sampling signal S_S1 and the second sampling signal S_S2. In this case, according to the timing of the edges of the internal clock signals ICK[1] to ICK[4], the command / address (CMD / ADDR) values ​​of the sampled command / address signals S_CA[7:0] can be in a timing misalignment.

[0103] The first flip-flop 319a to the third flip-flop 319c can sample the sampled signals S_CLE, S_ALE, and S_CA[7:0] at the rising edge of the recovered write enable signal R_nWE, and can output the recovered signals R_CLE, R_ALE, and R_CA[7:0] respectively. The third flip-flop 319c can sample the command / address (CMD / ADDR) value from the sampled command / address signal S_CA[7:0] received during a time period (i.e., during a predetermined time period) based on a rising edge of the recovered write enable signal R_nWE. Thus, the sampled command / address (CMD / ADDR) value can be output in a timing sequence (i.e., in parallel) through the recovered command / address signal R_CA[7:0]. For example, in the second mode, the recovered command / address signal R_CA[7:0] can be output as the command / address signal CA[7:0].

[0104] Based on the rising edge of the recovery write enable signal R_nWE, the command cycle generator 315 can generate a switched command cycle signal CMD_C during the enable period (e.g., logic high) of the recovery command latch enable signal R_CLE. For example, as Figure 9 As shown, the command loop generator 315 can generate a command loop signal CMD_C, which has a rising edge corresponding to the first rising edge of the recovery write enable signal R_nWE. For example, the switching frequency of the command loop signal CMD_C can be the same as the switching frequency of the recovery write enable signal R_nWE.

[0105] Based on the rising edge of the recovered write enable signal R_nWE, the address cycle generator 316 can generate the switching address cycle signal ADDR_C during the enable period of the recovered address latch enable signal R_ALE. For example, as Figure 9 As shown, the address loop generator 316 can generate an address loop signal ADDR_C, which has five rising edges corresponding to the second to sixth rising edges of the recovered write enable signal R_nWE. For example, the switching frequency of the address loop signal ADDR_C can be the same as the switching frequency of the recovered write enable signal R_nWE.

[0106] As described above, in the second mode, the memory interface circuit 310 can generate a command loop signal CMD_C, an address loop signal ADDR_C, and command / address signals CA[7:0] corresponding to the eight signal lines. In this case, the command CMD can be extracted from the command / address signals CA[7:0] based on the command loop signal CMD_C, and the addresses ADDR0 to ADDR4 can be extracted from the command / address signals CA[7:0] based on the address loop signal ADDR_C.

[0107] like Figure 8 and Figure 9 As shown, the memory interface circuit 310 can generate the command loop signal CMD_C, the address loop signal ADDR_C, and the command / address signal CA that can be output through the signal lines based on the first signal SIG1 to the third signal SIG3, regardless of the mode. Thus, the internal interface circuit or peripheral circuit of the memory device 300 that receives the command loop signal CMD_C, the address loop signal ADDR_C, and the command / address signal CA (e.g., Figure 3 The control logic circuit 320 can be implemented and operated in a mode-independent manner. As a result, the memory interface circuit 310 can provide compatibility, enabling the memory device 300 to operate in both a first and a second mode without requiring changes to the design of the internal interface circuitry or the peripheral circuitry.

[0108] Figure 10 It is shown Figure 3 A flowchart illustrating exemplary operation of a memory system. (Refer to...) Figure 10 In operation S21, the memory controller 400 sends a mode selection signal to the memory device 300. For example, the memory controller 400 can send the mode selection signal to the memory device 300 via a command (e.g., a "Set Feature" command) or a separate control signal for mode selection.

[0109] In operation S22, the memory device 300 is set to the selected mode in response to the mode selection signal. For example, the memory device 300 can store a mode setting value indicating the selected mode in a register. In this way, the memory device 300 can operate according to the set mode.

[0110] In operation S23, the memory controller 400 sends a command / address CMD / ADDR to the memory device 300 according to the selected mode. For example, when the memory device 300 is set to the first mode, the memory controller 400 can send the command / address CMD / ADDR to the memory device 300 via the third pin P23. For example, when the memory device 300 is set to the second mode, the memory controller 400 can send the command / address CMD / ADDR to the memory device 300 via the first pin P21 and the second pin P22. Therefore, for the same two command / address CMD / ADDR received in different situations, different pins can be used according to the selected mode.

[0111] In operation S24, the memory device 300 can receive command / address CMD / ADDR from the memory controller 400 according to the set mode. For example, when the memory device 300 is set to the first mode, the memory device 300 can obtain the command / address CMD / ADDR from the third signal SIG3. For example, when the memory device 300 is set to the second mode, the memory device 300 can obtain the command / address CMD / ADDR from the first signal SIG1 and the second signal SIG2.

[0112] Figure 11 It is shown Figure 3 A block diagram illustrating an example of an expanded memory system. (See also...) Figure 11 The memory device 300 may further include a fifth pin P15, a sixth pin P16, a seventh pin P17, and an eighth pin P18. The memory interface circuit 310 can receive a read enable signal nRE from the memory controller 400 via the fifth pin P15. For example, the read enable signal nRE can be a differential signal. The memory interface circuit 310 can receive a data strobe signal DQS from the memory controller 400 via the sixth pin P16, or can send the data strobe signal DQS to the memory controller 400. For example, the data strobe signal DQS can be a differential signal. The memory interface circuit 310 can send a ready / busy output signal nR / B to the memory controller 400 via the seventh pin P17. The memory interface circuit 310 can receive a chip enable signal nCE from the memory controller 400 via the eighth pin P18.

[0113] According to the chip enable signal nCE, the memory interface circuit 310 can exchange signals with the memory controller 400 through pins P11 to P17. For example, when the chip enable signal nCE is enabled (e.g., at a low level), the memory interface circuit 310 can exchange signals with the memory controller 400 through pins P11 to P17.

[0114] In the data output operation of the memory device 300, the memory interface circuit 310 can receive a switched read enable signal nRE via pin 5 P15 before outputting the data "DATA". The memory interface circuit 310 can generate a switched data strobe signal DQS based on the switching of the read enable signal nRE. For example, the memory interface circuit 310 can generate the data strobe signal DQS, which switches after a predetermined delay from the start time of the switching of the read enable signal nRE. The memory interface circuit 310 can output a third signal SIG3 including the data "DATA" based on the switching timing of the data strobe signal DQS. Thus, the data "DATA" can be aligned with the switching timing of the data strobe signal DQS and can be sent to the memory controller 400.

[0115] During data input operations of the memory device 300, when a third signal SIG3 including the data "DATA" is received from the memory controller 400, the memory interface circuit 310 can receive the switched data strobe signal DQS and the data "DATA" together from the memory controller 400. The memory interface circuit 310 can obtain the data "DATA" from the third signal SIG3 based on the switching timing of the data strobe signal DQS. For example, the memory interface circuit 310 can obtain the data "DATA" by sampling the third signal SIG3 at the rising and falling edges of the data strobe signal DQS.

[0116] The memory interface circuit 310 can send the operation status information of the memory device 300 to the memory controller 400 via the ready / busy output signal nR / B. When the memory device 300 is in a busy state (i.e., when internal operations of the memory device 300 are being performed), the memory interface circuit 310 can send the ready / busy output signal nR / B indicating the busy state to the memory controller 400. When the memory device 300 is in a ready state (i.e., when internal operations of the memory device 300 have been completed or not performed), the memory interface circuit 310 can send the ready / busy output signal nR / B indicating the ready state to the memory controller 400. For example, when the memory device 300 reads data "DATA" from the memory cell array 330 in response to a page read command, the memory interface circuit 310 can send the ready / busy output signal nR / B indicating a busy state (e.g., low level) to the memory controller 400. For example, when the memory device 300 programs the data “DATA” into the memory cell array 330 in response to a programming command, the memory interface circuit 310 can send a ready / busy output signal nR / B indicating a busy state to the memory controller 400.

[0117] The memory controller 400 may further include a fifth pin P25, a sixth pin P26, a seventh pin P27, and an eighth pin P28. The controller interface circuit 410 can send a read enable signal nRE to the memory device 300 via the fifth pin P25. Through the sixth pin P26, the controller interface circuit 410 can receive a data strobe signal DQS from the memory device 300, or can send the data strobe signal DQS to the memory device 300. The controller interface circuit 410 can receive a ready / busy output signal nR / B from the memory device 300 via the seventh pin P27. The controller interface circuit 410 can send a chip enable signal nCE to the memory device 300 via the eighth pin P28.

[0118] In the data output operation of the memory device 300, the controller interface circuit 410 can generate a switching read enable signal nRE and send the read enable signal nRE to the memory device 300. For example, the read enable signal nRE can remain static (e.g., high or low level) and the switching can begin before the data "DATA" is output. Thus, the memory device 300 can generate a switching data strobe signal DQS based on the read enable signal nRE. The controller interface circuit 410 can receive a third signal SIG3 including the data "DATA" and the switching data strobe signal DQS from the memory device 300. The controller interface circuit 410 can obtain the data "DATA" from the third signal SIG3 based on the switching timing of the data strobe signal DQS.

[0119] In the data input operation of memory device 300, controller interface circuit 410 can generate a switching data strobe signal DQS. For example, the data strobe signal DQS can remain static (e.g., high or low level) and can begin switching before the data "DATA" is transmitted. Controller interface circuit 410 can send a third signal SIG3, including the data "DATA", to memory device 300 based on the switching timing of the data strobe signal DQS. For example, the data "DATA" can be transmitted in a state aligned with the timing of the data strobe signal DQS.

[0120] Figure 12A It is shown that Figure 11 A timing diagram of an example of a memory device outputting data in the first mode. Figure 12B It is shown that Figure 11 A timing diagram of an example of a memory device outputting data in the second mode. Figure 12C It is shown that Figure 11 Timing diagrams illustrating examples of a memory device operating in a first and second mode during data output operations. In detail, Figures 12A to 12CAn example is shown in which the memory device 300 outputs data “DATA” according to a first command CMD1 and a first address ADDR1 and receives a second command CMD2 and a second address ADDR2. For example, the first command CMD1 may be a data output command, and the second command CMD2 may be a command that is the same as or different from the first command CMD1 in type.

[0121] Reference Figure 12A In the first mode, the memory device 300 can receive a third signal SIG3 including a first command CMD1 and a first address ADDR1. The memory device 300 can obtain the first command CMD1 from the third signal SIG3 based on a switched write enable signal nWE during the enable period of the first signal SIG1 (e.g., logic high), and can obtain the first address ADDR1 from the third signal SIG3 based on the switched write enable signal nWE during the enable period of the second signal SIG2 (e.g., logic high). For example, during the periods when the first command CMD1 and the first address ADDR1 are received, the read enable signal nRE can be high, and the data strobe signal DQS can be in an "irrelevant" state (e.g., high z state).

[0122] The memory device 300 can receive a switched read enable signal nRE from the memory controller 400 according to a first command CMD1. In response to the first command CMD1, the memory device 300 can generate a switched data strobe signal DQS according to the switching of the read enable signal nRE. In this case, the data strobe signal DQS can begin switching after a predetermined time tDQSRE from the time when the read enable signal nRE begins switching. The memory device 300 can send a third signal SIG3, including the data "DATA", along with the data strobe signal DQS to the memory controller 400. For example, during the period when the data "DATA" is sent, the first signal SIG1 and the second signal SIG2 can be low, and the write enable signal nWE can be high.

[0123] After the data "DATA" is sent, the memory device 300 can receive a third signal SIG3 including the second command CMD2 and the second address ADDR2. The memory device 300 can obtain the second command CMD2 from the third signal SIG3 based on a switched write enable signal nWE during the enable period of the first signal SIG1 (e.g., logic high), and can obtain the second address ADDR2 from the third signal SIG3 based on the switched write enable signal nWE during the enable period of the second signal SIG2 (e.g., logic high). For example, during the period when the second command CMD2 and the second address ADDR2 are received, the read enable signal nRE can be high, and the data strobe signal DQS can be in an "irrelevant" state (e.g., high z state).

[0124] Reference Figure 12B , as reference Figure 5B In the second mode, the memory device 300 can receive a first signal SIG1 and a second signal SIG2, which include a first command CMD1 and a first address ADDR1. The memory device 300 can obtain the first command CMD1 and the first address ADDR1 from the first signal SIG1 and the second signal SIG2 based on a switched write enable signal nWE. For example, during the period when the first command CMD1 and the first address ADDR1 are received, the read enable signal nRE can be at a high level, and the data strobe signal DQS and the third signal SIG3 can be in an "irrelevant" state (e.g., a high z state).

[0125] The memory device 300 can receive a switched read enable signal nRE from the memory controller 400 according to a first command CMD1. In response to the first command CMD1, the memory device 300 can generate a switched data strobe signal DQS according to the switching of the read enable signal nRE. In this case, the data strobe signal DQS can begin switching after a predetermined time tDQSRE from the time when the read enable signal nRE begins switching. The memory device 300 can send a third signal SIG3, including the data "DATA", together with the data strobe signal DQS to the memory controller 400. For example, the frequency of the write enable signal nWE can be greater than the frequencies of the read enable signal nRE and the data strobe signal DQS.

[0126] While sending data "DATA" to the memory controller 400, the memory device 300 can receive a first signal SIG1 and a second signal SIG2 from the memory controller 400, including a second command CMD2 and a second address ADDR2. The memory device 300 can obtain the second command CMD2 and the second address ADDR2 from the first signal SIG1 and the second signal SIG2 based on the switched write enable signal nWE. Therefore, the transmission of data "DATA" and the reception of the second command CMD2 and the second address ADDR2 can be performed in parallel. Thus, the period during which the write enable signal nWE, the read enable signal nRE, and the data strobe signal DQS switch simultaneously can exist in the second mode.

[0127] Reference Figure 12C The memory device 300 can operate in a first mode to obtain a first command CMD1 and a first address ADDR1, and can operate in a second mode to obtain a second command CMD2 and a second address ADDR2. In this case, the mode of the memory device 300 can be changed during operation and can be without being pre-selected.

[0128] In one exemplary embodiment, the memory device 300 may determine a mode based on a combination of a write enable signal nWE, a read enable signal nRE, and a data strobe signal DQS. The memory device 300 may generate a reference based on the determined mode. Figure 6 The described mode selection signal PM. When the switched write enable signal nWE is received while the read enable signal nRE and the data strobe signal DQS are received and remain static (e.g., high level), the memory device 300 can operate in a first mode. When the switched write enable signal nWE is received while either the switched data strobe signal DQS or the switched read enable signal nRE is received, the memory device 300 can operate in a second mode. Thus, the memory device 300 can operate in the first mode from a first time t1 to a second time t2, and can operate in the second mode from a third time t3 to a fourth time t4. In this case, the frequency of the write enable signal nWE received in the first mode can be lower than the frequency of the write enable signal nWE received in the second mode.

[0129] Because memory device 300 is as referenced Figure 12A The description of operation from the first time point t1 to the second time point t2 in the first mode indicates that the memory device 300 can obtain the first command CMD1 and the first address ADDR1 from the third signal SIG3. Because the memory device 300, as referred to... Figure 12BThe description describes the operation in the second mode from the third time t3 to the fourth time t4, so the memory device 300 can obtain the second command CMD2 and the second address ADDR2 from the first signal SIG1 and the second signal SIG2.

[0130] Figure 13 This illustrates an example embodiment. Figure 3 A block diagram of the memory device. (Refer to...) Figure 13 The memory device 300 may include control logic circuitry 320, a memory cell array 330, a page buffer unit 340, a voltage generator 350, and a line decoder 360. Although in Figure 13 Not shown, but the memory device 300 may also include Figure 3 The memory interface circuit 310 shown may also include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, etc.

[0131] The control logic circuit 320 can control various types of operations of the memory device 300. In response to the command CMD and / or address ADDR from the memory interface circuit 310, the control logic circuit 320 can output various types of control signals. For example, the control logic circuit 320 can output voltage control signal CTRL_vol, row address X-ADDR, and column address Y-ADDR.

[0132] In one exemplary embodiment, as referenced Figures 6 to 9 As described, the control logic circuit 320 can receive the command CMD and address ADDR via the command loop signal CMD_C, the address loop signal ADDR_C, and the command / address signal CA in both a first mode and a second mode. For example, the control logic circuit 320 can receive the command CMD and address ADDR using the same interface, regardless of the mode.

[0133] The memory cell array 330 may include multiple memory blocks BLK1 to BLKz (z is a positive integer), each memory block including multiple memory cells. The memory cell array 330 can be connected to the page buffer unit 340 via multiple bit lines BL, and can be connected to the line decoder 360 via multiple word lines WL, multiple serial select lines SSL, and multiple ground select lines GSL.

[0134] In one exemplary embodiment, the memory cell array 330 may include a three-dimensional memory cell array comprising a plurality of NAND strings. Each NAND string may include memory cells vertically stacked on a substrate and connected to a plurality of word lines respectively. Memory cell arrays such as those described in U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and 2011 / 0233648, which describe three-dimensional memory cell arrays, may be used. These patents and patent disclosures are incorporated herein by reference in their entirety. In one exemplary embodiment, the memory cell array 330 may include a two-dimensional memory cell array comprising a plurality of NAND strings arranged along row and column directions.

[0135] Page buffer unit 340 may include multiple page buffers PB1 to PBn (n being an integer of 3 or greater), which can be connected to multiple memory cells via multiple bit lines BL. Page buffer unit 340 can select at least one of the bit lines BL based on the column address Y-ADDR. Page buffer unit 340 can operate as a write driver or a sense amplifier depending on the operating mode. For example, in a programming operation, page buffer unit 340 can apply a bit line voltage corresponding to the data to be programmed to the selected bit line. In a read operation, page buffer unit 340 can sense the current or voltage of the selected bit line to sense the data stored in the memory cell.

[0136] Voltage generator 350 can generate various types of voltages for performing programming, reading, and erasing operations based on the voltage control signal CTRL_vol. For example, voltage generator 350 can generate programming voltage, reading voltage, programming verification voltage, erasing voltage, etc., as word line voltage VWL.

[0137] In response to the row address X-ADDR, the row decoder 360 can select one of multiple word lines WL and one of multiple string select lines SSL. For example, in a programming operation, the row decoder 360 can apply a programming voltage and a programming verification voltage to the selected word line; in a reading operation, the row decoder 360 can apply a reading voltage to the selected word line.

[0138] Figure 14 This is a circuit diagram illustrating a memory block according to an embodiment of the present disclosure. (Refer to...) Figure 14 The memory block BLK can be Figure 13One of the memory blocks BLK1 to BLKz. The memory block BLK may include NAND strings NS11 to NS33, each of which (e.g., NS11) includes a series-connected string select transistor SST, a plurality of memory cells MC, and a ground select transistor GST.

[0139] NAND strings NS11, NS21, and NS31 can be positioned between the first bit line BL1 and the common-source line CSL; NAND strings NS12, NS22, and NS32 can be positioned between the second bit line BL2 and the common-source line CSL; and NAND strings NS13, NS23, and NS33 can be positioned between the third bit line BL3 and the common-source line CSL. In each NAND string, the string select transistor SST can be connected to one of the string select lines SSL1, SSL2, and SSL3. Memory cells MC can each be connected to their corresponding word lines WL1 to WL8. The ground select transistor GST can be connected to one of the ground select lines GSL1, GSL2, and GSL3. In each NAND string, the string select transistor SST can be connected to one of the bit lines BL1, BL2, and BL3, and the ground select transistor GST can be connected to the common-source line CSL. Here, the number of NAND strings, word lines, bit lines, ground select lines, and string select lines can be modified differently depending on the embodiment.

[0140] Figure 15A An example of interlevel operation of a memory device in a first mode according to an embodiment of the present disclosure is shown. Figure 15B An example of interleaved operation of a memory device in a second mode according to an embodiment of the present disclosure is shown. Figure 15A and Figure 15B In, as referenced Figure 1 The interleaving operation will be described with reference to multiple non-volatile memory devices NVM1 to NVM4 connected to a channel, but the number of non-volatile memory devices may be modified differently.

[0141] Reference Figure 15A and Figure 15B Each of the non-volatile memory devices NVM1 to NVM4 can be accessed from the memory controller 200 (see reference tCMD) during the command transmission time tCMD. Figure 1 ) receives a page read command CMD (e.g., page read CMD), and can, in response to the page read command CMD, retrieve data from the memory cell array 330 (refer to) during the data read time tR. Figure 3The command sending time tCMD and the data reading time tR can also be referred to as the time period or duration. The first non-volatile memory device NVM1 can receive the page read command CMD from the first time t1, and can read the data "DATA" from the second time t2 in response to the page read command CMD.

[0142] Because the operation of reading data "DATA" from memory cell array 330 is performed in each of the non-volatile memory devices NVM1 to NVM4, while one non-volatile memory device performs a read operation, another non-volatile memory device can receive page read commands CMD through a common channel. For example, while the first non-volatile memory device NVM1 performs a read operation, the second non-volatile memory device NVM2 can receive page read commands CMD from a second time t2. In this way, the four page read commands CMD for non-volatile memory devices NVM1 to NVM4 can be provided continuously without a time interval of waiting for the data to be read.

[0143] After the data read operation is completed, each of the non-volatile memory devices NVM1 to NVM4 can receive a random data output command CMD (e.g., random data output CMD) from the memory controller 200 during the command transmission time tCMD, and can output the read data "DATA" during the data output time tDMA in response to the random data output command CMD. For example, the first non-volatile memory device NVM1 can receive the random data output command CMD from the third time t3, and can output the read data "DATA" from the fourth time t4 in response to the random data output command CMD. In this way, the data "DATA" can be output sequentially from the non-volatile memory devices NVM1 to NVM4.

[0144] Reference Figure 15A In the first mode, as referenced Figure 3As described, each of the non-volatile memory devices NVM1 to NVM4 can receive a random data output command CMD via pin 3 P13 and can output data "DATA" via pin 3 P13. Because the non-volatile memory devices NVM1 to NVM4 share a single channel (i.e., share pin 3 P13), the random data output command CMD cannot be sent to another non-volatile memory device while data "DATA" is being output from one non-volatile memory device. Thus, after data "DATA" is output from one non-volatile memory device, the random data output command CMD can be sent to another non-volatile memory device. For example, after data "DATA" is output from the first non-volatile memory device NVM1 from time 4 to time 5 t5, the random data output command CMD can be sent to the second non-volatile memory device NVM2 from time 5 t5. Similarly, the third non-volatile memory device NVM3 can receive the random data output command CMD after the data output operation of the second non-volatile memory device NVM2 is completed, and the fourth non-volatile memory device NVM4 can receive the random data output command CMD after the data output operation of the third non-volatile memory device NVM3 is completed. Therefore, the total time tDout1 when the data "DATA" is output from the first non-volatile memory device NVM1 to the fourth non-volatile memory device NVM4 through the above interleaving operation can be the sum of the four command transmission times tCMD and the four data output times tDMA.

[0145] Reference Figure 15B In the second mode, as referenced Figure 3As described, each of the non-volatile memory devices NVM1 to NVM4 can receive a random data output command CMD via a first pin P11 and a second pin P12, and can output data "DATA" via a third pin P13. In this case, the operation of outputting data "DATA" from one non-volatile memory device and the operation of receiving the random data output command CMD from another non-volatile memory device can be performed in parallel. Thus, while data "DATA" is being output from one non-volatile memory device, the random data output command CMD can be sent to another non-volatile memory device. For example, the random data output command CMD can be sent to the second non-volatile memory device NVM2 simultaneously with the output of data "DATA" from the first non-volatile memory device NVM1 (e.g., during the time interval from the fourth time t4 to the fifth time t5). Similarly, the third non-volatile memory device NVM3 can receive the random data output command CMD simultaneously with the data output operation of the second non-volatile memory device NVM2, and the fourth non-volatile memory device NVM4 can receive the random data output command CMD simultaneously with the data output operation of the third non-volatile memory device NVM3. Therefore, the total time tDout2 for the data "DATA" to be output from the first non-volatile memory device NVM1 to the fourth non-volatile memory device NVM4 through the above interleaving operation can be the sum of a command transmission time tCMD and four data output times tDMA.

[0146] In order to provide the random data output command CMD to each of the non-volatile memory devices NVM1 to NVM4 in the second mode, each of the non-volatile memory devices NVM1 to NVM4 may provide status information to the memory controller indicating whether an internal read operation has been completed. (See reference...) Figure 11 As described, each of the non-volatile memory devices NVM1 to NVM4 can provide status information via a ready / busy output signal nR / B. Alternatively, as referenced... Figure 6 As described, in response to a status read command from the memory controller, each of the non-volatile memory devices NVM1 to NVM4 can provide status information via any pin other than the pin that transmits data "DATA" (e.g., the first pin P11 or the second pin P12 in Figure 5). Thus, while data "DATA" is being output from one non-volatile memory device, the status information of the other non-volatile memory device can be checked.

[0147] As described above, the total time tDout2 when data "DATA" is output from multiple non-volatile memory devices NVM1 to NVM4 connected to one channel via interleaving operation in the second mode can be less than the total time tDout1 when data "DATA" is output from multiple non-volatile memory devices NVM1 to NVM4 connected to the same channel via interleaving operation in the first mode. Similarly, according to embodiments of this disclosure, the total time required for the memory controller to receive data "DATA" from multiple non-volatile memory devices connected to one channel via interleaving operation in the second mode can be less than the total time required for the memory controller to receive data "DATA" from multiple non-volatile memory devices connected to the same channel via interleaving operation in the first mode. Therefore, the speed of inputting / outputting data "DATA" can be improved in the second mode.

[0148] The following will refer to Figures 16 to 21 Describe various examples of memory systems that support the second mode.

[0149] Figure 16 This is a block diagram illustrating a memory system supporting a second mode according to an embodiment of the present disclosure. (Refer to...) Figure 16 The memory system 20a may include a memory device 300a and a memory controller 400a. The memory device 300a may include a first pin P31, a second pin P32, a third pin P33, a memory interface circuit 310a, a control logic circuit 320a, and a memory cell array 330a. The memory controller 400a may include a first pin P41, a second pin P42, a third pin P43, and a controller interface circuit 410a. The memory interface circuit 310a, the control logic circuit 320a, and the memory cell array 330a may respectively correspond to… Figure 3 The memory interface circuit 310, control logic circuit 320, and memory cell array 330, and the controller interface circuit 410a can correspond to Figure 3 The controller interface circuit 410.

[0150] The memory interface circuit 310a can receive the control signal CTRL, including command / address CMD / ADDR, from the memory controller 400a via the first pin P31. The memory interface circuit 310a can receive the write enable signal nWE from the memory controller 400a via the second pin P32. Through the third pin P33, the memory interface circuit 310a can receive the data signal DQ, including data "DATA", from the memory controller 400a, or can send the data signal DQ to the memory controller 400a. For example, the first pin P31 could be a pin used to receive the command latch enable signal CLE or the address latch enable signal ALE in a first mode (e.g., ...). Figure 3 The first pin P11 or the second pin P12), but this disclosure is not limited thereto.

[0151] The memory interface circuit 310a can obtain the command / address CMD / ADDR from the control signal CTRL based on the switching timing of the write enable signal nWE. In an exemplary embodiment, the memory interface circuit 310a can obtain the command CMD via the control signal CTRL based on the state of the control signal CTRL in a first switching timing, and can obtain the address ADDR via the control signal CTRL based on the state of the control signal CTRL in a second switching timing.

[0152] The controller interface circuit 410a can send the control signal CTRL, including the command / address (CMD / ADDR), to the memory device 300a via the first pin P41. The controller interface circuit 410a can send the write enable signal nWE to the memory device 300a via the second pin P42. Through the third pin P43, the controller interface circuit 410a can send the data signal DQ, including the data "DATA", to the memory device 300a, or receive the data signal DQ from the memory device 300a.

[0153] Figure 17 It is shown that Figure 16 A timing diagram illustrating an example of a memory device receiving commands and addresses. (Refer to...) Figure 16 and Figure 17 The memory device 300a can receive a control signal CTRL, including a command CMD and an address ADDR, from the memory controller 400a. While the control signal CTRL, including the command CMD and the address ADDR, is being received, the write enable signal nWE can be in a switching state, and the data signals DQ[7:0] can be irrelevant signals. The memory device 300a can receive the command CMD during a first time period and can receive the address ADDR during a second time period. Each of the first and second time periods can include a cycle corresponding to 10 cycles of the write enable signal nWE.

[0154] If the control signal CTRL received during the first cycle C1 of the first time period is enabled (e.g., high level), the memory device 300a can obtain the command CMD from the control signal CTRL received during the remaining cycle C1 of the first time period (after the second cycle C2). In this case, the control signal CTRL received during the second cycle C2 of the first time period can be disabled (e.g., low level). The memory device 300a can obtain the command CMD from the signal values ​​C[0] to C[7] of the control signal CTRL sampled at the rising edge of the write enable signal nWE during the remaining cycle C1.

[0155] When the control signal CTRL received during the second cycle C4 of the second time period is enabled (e.g., high level), the memory device 300a can obtain the address ADDR from the control signal CTRL received during the remaining cycle CS2 of the second time period. In this case, the control signal CTRL received during the first cycle C3 of the second time period can be disabled (e.g., low level). The memory device 300a can obtain the address ADDR from the signal values ​​A[0] to A[7] of the control signal CTRL sampled at the rising edge of the write enable signal nWE during the remaining cycle CS2. Ordinal numbers such as "first", "second", "third" etc. can be used only as markers for specific elements, steps, etc., to distinguish such elements, steps, etc. from each other. Terms not described using "first", "second", etc. in the specification may still be referred to as "first" or "second" in the claims. Furthermore, terms referred to with a specific number (e.g., "first" in a specific claim) may be described elsewhere with a different number (e.g., "second" in the specification or another claim). In some cases and contexts, such as when describing the nth cycle of a time period, "n" can indicate the order / position of the nth cycle relative to other cycles of the time period. Specific examples are further described below.

[0156] Figure 18 This is a block diagram illustrating a memory system supporting a second mode according to an embodiment of the present disclosure. (Refer to...) Figure 18The memory system 20b may include a memory device 300b and a memory controller 400b. The memory device 300b may include a first pin P51, a second pin P52, a third pin P53, a fourth pin P54, a memory interface circuit 310b, a control logic circuit 320b, and a memory cell array 330b. The memory controller 400b may include a first pin P61, a second pin P62, a third pin P63, a fourth pin P64, and a controller interface circuit 410b. The memory interface circuit 310b, the control logic circuit 320b, and the memory cell array 330b may respectively correspond to... Figure 3 The memory interface circuit 310, control logic circuit 320, and memory cell array 330, and the controller interface circuit 410b can correspond to Figure 3 The controller interface circuit 410.

[0157] The memory interface circuit 310b can receive a first control signal CTRL1 and a second control signal CTRL2, including command / address CMD / ADDR, from the memory controller 400b via first pin P51 and second pin P52. The memory interface circuit 310b can receive a write enable signal nWE from the memory controller 400b via third pin P53. Through fourth pin P54, the memory interface circuit 310b can receive a data signal DQ, including data “DATA”, from the memory controller 400b, or can send the data signal DQ to the memory controller 400b. For example, first pin P51 could be a pin used to receive a command latch enable signal CLE in a first mode (e.g., ...). Figure 3 The first pin P11), and the second pin P52 can be pins used to receive the address latch enable signal ALE in the first mode (e.g., Figure 3 (P12, the second pin). However, this disclosure is not limited thereto.

[0158] The memory interface circuit 310b can obtain command / address CMD / ADDR from the first control signal CTRL1 and the second control signal CTRL2 based on the switching timing of the write enable signal nWE. In an exemplary embodiment, the memory interface circuit 310b can obtain command CMD through control signals CTRL1 and CTRL2 based on the state of the first control signal CTRL1 at a specific switching timing, and can obtain address ADDR through control signals CTRL1 and CTRL2 based on the state of the second control signal CTRL2 at a specific switching timing.

[0159] The controller interface circuit 410b can send a first control signal CTRL1, including a command / address CMD / ADDR, and a second control signal CTRL2 to the memory device 300b via the first pin P61 and the second pin P62. The controller interface circuit 410b can send a write enable signal nWE to the memory device 300a via the third pin P63. Through the fourth pin P64, the controller interface circuit 410b can send a data signal DQ, including the data "DATA", to the memory device 300b, or receive a data signal DQ from the memory device 300b.

[0160] Figure 19 It is shown that Figure 18 A timing diagram illustrating an example of a memory device receiving commands and addresses. (Refer to...) Figure 18 and Figure 19 The memory device 300b can receive a first control signal CTRL1 and a second control signal CTRL2, including a command CMD and an address ADDR, from the memory controller 400b. While the first control signal CTRL1 and the second control signal CTRL2, including the command CMD and the address ADDR, are being received, the write enable signal nWE can be in a switching state, and the data signals DQ[7:0] can be irrelevant. The memory device 300b can receive the command CMD during a first time period and can receive the address ADDR during a second time period. Each of the first and second time periods can include a cycle corresponding to five cycles of the write enable signal nWE.

[0161] If the first control signal CTRL1 received during the first cycle C1 of the first time period is enabled (e.g., at a high level), the memory device 300b can obtain the command CMD from the control signals CTRL1 and CTRL2 received during the remaining cycle C1 of the first time period. In this case, the second control signal CTRL2 received during the first cycle C1 can be disabled (e.g., at a low level "L"). The memory device 300b can obtain the command CMD from the signal values ​​C[0] to C[7] of the control signals CTRL1 and CTRL2 sampled at the rising edge of the write enable signal nWE during the remaining cycle C1.

[0162] If the second control signal CTRL2 received during the second cycle C2 of the second time period is enabled (e.g., high level), the memory device 300b can obtain the address ADDR from the control signals CTRL1 and CTRL2 received during the remaining cycle C2 of the second time period. In this case, the first control signal CTRL1 received during the second cycle C2 of the second time period can be disabled (e.g., low level). The memory device 300b can obtain the address ADDR from the signal values ​​A[0] to A[7] of the control signals CTRL1 and CTRL2 sampled at the rising edge of the write enable signal nWE during the remaining cycle C2.

[0163] Figure 20 This is a block diagram illustrating a memory system supporting a second mode according to an embodiment of the present disclosure. (Refer to...) Figure 20 The memory system 20c may include a memory device 300c and a memory controller 400c. The memory device 300c may include a first pin P71, a second pin P72, a third pin P73, a fourth pin P74, a fifth pin P75, a memory interface circuit 310c, a control logic circuit 320c, and a memory cell array 330c. The memory controller 400c may include a first pin P81, a second pin P82, a third pin P83, a fourth pin P84, a fifth pin P85, and a controller interface circuit 410c. The memory interface circuit 310c, the control logic circuit 320c, and the memory cell array 330c may respectively correspond to... Figure 3 The memory interface circuit 310, control logic circuit 320, and memory cell array 330, and the controller interface circuit 410c can correspond to Figure 3 The controller interface circuit 410.

[0164] The memory interface circuit 310c can receive a first control signal CTRL1, a second control signal CTRL2, and a third control signal CTRL3, including command / address CMD / ADDR, from the memory controller 400c via pins P71 to P73. The memory interface circuit 310c can receive a write enable signal nWE from the memory controller 400c via pin P74. Through pin P75, the memory interface circuit 310c can receive a data signal DQ, including data “DATA,” from the memory controller 400c, or can send the data signal DQ to the memory controller 400c. For example, pin P71 could be a pin used to receive a command latch enable signal CLE in a first mode (e.g., ...). Figure 3 The first pin P11), and the second pin P72 can be pins used to receive the address latch enable signal ALE in the first mode (e.g., Figure 3(P12, the second pin). However, this disclosure is not limited thereto.

[0165] The memory interface circuit 310c can obtain command / address CMD / ADDR from the first control signal CTRL1 to the third control signal CTRL3 based on the switching timing of the write enable signal nWE. In an exemplary embodiment, the memory interface circuit 310c can obtain command CMD through control signals CTRL1 to CTRL3 based on the state of the first control signal CTRL1 at a specific switching timing, and can obtain address ADDR through control signals CTRL1 to CTRL3 based on the state of the second control signal CTRL2 at a specific switching timing. In this case, at a specific switching timing, at least one bit value of command CMD or address ADDR can be sent through the third control signal CTRL3, or an invalid value can be sent through the third control signal CTRL3.

[0166] The controller interface circuit 410c can send the first control signal CTRL1 to the third control signal CTRL3, including the command / address CMD / ADDR, to the memory device 300c via the first pin P81, the second pin P82, and the third pin P83. The controller interface circuit 410c can send the write enable signal nWE to the memory device 300c via the fourth pin P84. Through the fifth pin P85, the controller interface circuit 410c can send the data signal DQ, including the data "DATA", to the memory device 300c, or receive the data signal DQ from the memory device 300c.

[0167] Figure 21 It is shown that Figure 20 A timing diagram illustrating an example of a memory device receiving commands and addresses. (Refer to...) Figure 20 and Figure 21 The memory device 300c can receive first control signals CTRL1 to third control signals CTRL3, including command CMD and address ADDR, from the memory controller 400c. While the first control signals CTRL1 to third control signals CTRL3, including command CMD and address ADDR, are received, the write enable signal nWE can be in a switching state, and the data signals DQ[7:0] can be irrelevant signals. The memory device 300c can receive command CMD during a first time period and address ADDR during a second time period. Each of the first and second time periods can include a cycle corresponding to four cycles of the write enable signal nWE.

[0168] When the first control signal CTRL1 received during the first cycle C1 of the first time period is enabled (e.g., at a high level), the memory device 300c can obtain the command CMD from the control signals CTRL1 to CTRL3 received during the first time period. In this case, the second control signal CTRL2 received during the first cycle C1 can be disabled (e.g., at a low level "L"), and the third control signal CTRL3 received during the first cycle C1 can include one of the bit values ​​C[0] to C[7] of the command CMD, namely C[0]. The memory device 300c can obtain the command CMD from the signal values ​​C[0] to C[7] of the control signals CTRL1 to CTRL3 sampled at the rising edge of the write enable signal nWE during the first time period.

[0169] When the bit values ​​C[0] to C[7] of command CMD are received via control signals CTRL1 to CTRL3 during the first time period, at least one of the control signals CTRL1 to CTRL3 may include an invalid value during the first time period. An invalid value may be one of a low level, a high level, or a high z state. For example, such as... Figure 21 As shown, the second control signal CTRL2 and the third control signal CTRL3 may include invalid values ​​in the second cycle C2 of the first time period.

[0170] When the second control signal CTRL2 received during the first cycle C3 of the second time period is enabled (e.g., at a high level), the memory device 300c can obtain the address ADDR from the control signals CTRL1 to CTRL3 received during the second time period. In this case, the first control signal CTRL1 received during the first cycle C3 can be disabled (e.g., at a low level "L"), and the third control signal CTRL3 received during the first cycle C3 can include one of the bit values ​​A[0] to A[7] of the address ADDR. The memory device 300c can obtain the address ADDR from the signal values ​​A[0] to A[7] of the control signals CTRL1 to CTRL3 sampled at the rising edge of the write enable signal nWE during the second time period.

[0171] When the bit values ​​A[0] to A[7] of address ADDR are received via control signals CTRL1 to CTRL3 during the second time period, at least one of the control signals CTRL1 to CTRL3 may include an invalid value during the second time period. For example, such as Figure 21 As shown, the second control signal CTRL2 and the third control signal CTRL3 may include invalid values ​​in the second cycle C4 of the second time period.

[0172] The cycle time used to determine the command CMD or address ADDR is in Figure 17 , Figure 19 and Figure 21 The first or second cycle is shown as one of all cycles within a predetermined time period, but this disclosure is not limited thereto. For example, the cycle used to determine command CMD or address ADDR can be selected differently from all cycles within the predetermined time period. For example, a cycle can be described as a "specific cycle" during which the determination of whether command CMD or address ADDR is selected is made. A specific cycle can be any cycle within the predetermined time period without further confirmation. Two specific cycles can be described as a first specific cycle and a second specific cycle, and the designation "first" or "second" does not necessarily indicate the time position of said specific cycle within the predetermined time period. Phrases such as "first occurrence cycle" or "second occurrence cycle" can be used to indicate the time position. Furthermore, to indicate two cycles within different predetermined time periods (the two cycles having the same relative time position in the two predetermined time periods), the two cycles can be described as having the same relative time position in the two predetermined time periods. Alternatively, for two cycles within different predetermined time periods (the two cycles having different relative time positions in each predetermined time period), they can be described as having different relative time positions in each predetermined time period.

[0173] exist Figure 19 and Figure 21 In the example shown, the command CMD and address ADDR are determined by different control signals CTRL1 and CTRL2. However, this disclosure is not limited to this. For example, the command CMD and address ADDR can be determined by one of multiple control signals. In this case, as shown in the reference... Figure 17 The description states that a control value for determining the command CMD can be received during the first cycle of all cycles within a predetermined time period via a control signal, and a control value for determining the address ADDR can be received during its second cycle.

[0174] As described above, according to embodiments of this disclosure, each of the memory devices 300a, 300b, and 300c supporting the second mode may include one or more pins for the purpose of receiving one or more control signals including command / address CMD / ADDR. In this case, as referred to Figures 16 to 21 The number of cycles within the predetermined time period can vary depending on the number of pins used to receive commands / addresses (CMD / ADDR). For example, the interface protocol used to receive commands / addresses (CMD / ADDR) can be changed.

[0175] Figure 22 This is an exemplary cross-sectional view of a memory device according to an embodiment of the present disclosure. (Refer to...) Figure 22 The memory device 500 may include a peripheral circuit region PERI and a cell region CELL disposed on the peripheral circuit region PERI. Each of the peripheral circuit region PERI and the cell region CELL may include a first unbound region NBA1, a bound region BA, and a second unbound region NBA2.

[0176] The Peripheral Circuit Region (PERI) may include a first substrate 610, an interlayer insulating layer 615, a plurality of circuit elements 620a, 620b, and 620c formed on the first substrate 610, first metal layers 630a, 630b, and 630c respectively connected to the plurality of circuit elements 620a, 620b, and 620c, and second metal layers 640a, 640b, and 640c formed on the first metal layers 630a, 630b, and 630c. In one example embodiment, the first metal layers 630a, 630b, and 630c may be formed of tungsten, which has relatively high resistance, and the second metal layers 640a, 640b, and 640c may be formed of copper, which has relatively low resistance.

[0177] The specification only describes the first metal layers 630a, 630b, and 630c and the second metal layers 640a, 640b, and 640c, but this disclosure is not limited thereto. For example, at least one or more metal layers may also be formed on the second metal layers 640a, 640b, and 640c. At least a portion of the one or more metal layers formed on the second metal layers 640a, 640b, and 640c may be formed of aluminum or the like, which has a lower resistance than the copper (Cu) used to form the second metal layers 640a, 640b, and 640c.

[0178] Interlayer insulating layer 615 may be disposed on first substrate 610 to cover multiple circuit elements 620a, 620b and 620c, first metal layers 630a, 630b and 630c and second metal layers 640a, 640b and 640c, and may include insulating material (such as silicon oxide or silicon nitride).

[0179] Lower bonding metals 671b and 672b can be formed on the second metal layer 640b of the bonding region BA. In the bonding region BA, the lower bonding metals 671b and 672b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 571b and 572b of the cell region CELL via Cu-Cu bonding.

[0180] A cell region (CELL) can provide at least one memory block. The cell region (CELL) may include a second substrate 510 and a common-source line 520. On the second substrate 510, multiple word lines 531 to 538 (i.e., 530) may be stacked in a direction perpendicular to the upper surface of the second substrate 510 (Z-axis direction). Serial select lines and ground select lines may be arranged above and below the multiple word lines 530, respectively, and the multiple word lines 530 may be inserted between the serial select lines and the ground select lines.

[0181] In the second unbonded region NBA2, the channel structure CH can extend in a direction perpendicular to the upper surface of the second substrate 510 and can penetrate the word line 530, the serial select line, and the ground select line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer can be electrically connected to the first metal layer 550c and the second metal layer 560c. For example, the first metal layer 550c can be a bit line contact, and the second metal layer 560c can be a bit line. In an exemplary embodiment, the second metal layer 560c can extend in a first direction (i.e., the Y-axis direction) parallel to the upper surface of the second substrate 510.

[0182] exist Figure 22 In the embodiment shown, the region having the channel structure CH, the second metal layer 560c, etc., can be defined as the second unbonded region NBA2. In the second unbonded region NBA2, the second metal layer 560c can be electrically connected to the circuit element 620c providing the page buffer 593 in the peripheral circuit region PERI. For example, the second metal layer 560c can be connected to the upper bonding metals 571c and 572c in the peripheral circuit region PERI, and the upper bonding metals 571c and 572c can be connected to the lower bonding metals 671c and 672c connected to the circuit element 620c of the same page buffer 593.

[0183] In the bonding region BA, word lines 530 may extend along a second direction (i.e., the X-axis direction) parallel to the upper surface of the second substrate 510 and may be connected to a plurality of cell contact plugs 541 to 547 (e.g., 540). Word lines 530 and cell contact plugs 540 may be connected to each other at a pad provided by at least a portion of word lines 530 extending along the second direction and having different lengths. A first metal layer 550b and a second metal layer 560b may be sequentially connected on the cell contact plugs 540 connected to the word lines 530. In the bonding region BA, cell contact plugs 540 may be connected to the peripheral circuit region PERI via upper bonding metals 571b and 572b of the cell region CELL and lower bonding metals 671b and 672b of the peripheral circuit region PERI.

[0184] The cell contact plug 540 can be electrically connected in the peripheral circuitry region PERI to the circuit element 620b providing the line decoder 594. In one exemplary embodiment, the operating voltage of the circuit element 620b providing the line decoder 594 can be different from the operating voltage of the circuit element 620c providing the page buffer 593. For example, the operating voltage of the circuit element 620c providing the page buffer 593 can be greater than the operating voltage of the circuit element 620b providing the line decoder 594.

[0185] A common-source contact plug 580 may be disposed in the first unbonded region NBA1. The common-source contact plug 580 may be formed of a conductive material (such as a metal, metal compound, polysilicon, etc.) and may be electrically connected to the common-source wire 520. A first metal layer 550a and a second metal layer 560a may be sequentially stacked on the common-source contact plug 580. For example, the region where the common-source contact plug 580, the first metal layer 550a, and the second metal layer 560a are disposed may be defined as the first unbonded region NBA1.

[0186] Input / output pads 505 and 605 can be set in the first non-bonding zone NBA1. (See reference...) Figure 22 A lower insulating layer 601 covering the lower surface of the first substrate 610 may be formed on the lower surface of the first substrate 610, and a first input / output pad 605 may be formed on the lower insulating layer 601. The first input / output pad 605 may be connected to at least one of a plurality of circuit elements 620a, 620b, and 620c arranged in the peripheral circuit region PERI via a first input / output contact plug 603, and may be separated from the first substrate 610 via the lower insulating layer 601. Furthermore, a side insulating layer may be inserted between the first input / output contact plug 603 and the first substrate 610 to electrically disconnect the first input / output contact plug 603 and the first substrate 610.

[0187] Reference Figure 22 An upper insulating layer 501 covering the upper surface of the second substrate 510 may be formed on the upper surface of the second substrate 510, and a second input / output pad 505 may be formed on the upper insulating layer 501. The second input / output pad 505 may be connected to at least one of a plurality of circuit elements 620a, 620b and 620c arranged in the peripheral circuit region PERI via a second input / output contact plug 503.

[0188] According to an embodiment, the second substrate 510, common source electrode 520, etc., may not be arranged in the area where the second input / output contact plug 503 is provided. Furthermore, the second input / output pad 505 may not overlap with the word line 530 in a third direction (i.e., the Z-axis direction). See reference... Figure 22The second input / output contact plug 503 can be separated from the second base 510 in a direction parallel to the upper surface of the second base 510, and can be connected to the second input / output pad 505 through the upper insulating layer 501 of the cell region CELL.

[0189] According to embodiments, the first input / output pad 605 and the second input / output pad 505 can be selectively formed. For example, the memory device 500 may include only the first input / output pad 605 disposed on the lower surface of the first substrate 610, or it may include only the second input / output pad 505 disposed on the upper surface of the second substrate 510. Optionally, the memory device 500 may include both the first input / output pad 605 and the second input / output pad 505.

[0190] As a dummy pattern, the metal pattern of the top metal layer can exist in each of the first unbonded area NBA1 and the second unbonded area NBA2 in each of the cell area CELL and the peripheral circuit area PERI, or the top metal layer may not exist.

[0191] In the first unbonded region NBA1, the memory device 500 may include a lower metal pattern 673a in the uppermost metal layer of the peripheral circuit region PERI. The lower metal pattern 673a corresponds to the upper metal pattern 572a formed in the uppermost metal layer of the cell region CELL and has the same shape as the upper metal pattern 572a of the cell region CELL. In the peripheral circuit region PERI, the lower metal pattern 673a formed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to a separate contact. As described above, in the first unbonded region NBA1, an upper metal pattern 571a, corresponding to the lower metal pattern 672a formed in the uppermost metal layer of the peripheral circuit region PERI and having the same shape as the lower metal pattern 672a of the peripheral circuit region PERI, may be formed in the uppermost metal layer of the cell region CELL.

[0192] In the second non-bonding region NBA2, the upper metal pattern 592 can be formed in the uppermost metal layer of the cell region CELL. The upper metal pattern 592 corresponds to the lower metal pattern 652 formed in the uppermost metal layer of the peripheral circuit region PERI and has the same shape as the lower metal pattern 652 of the peripheral circuit region PERI. The contact may not be formed on the upper metal pattern 592 formed in the uppermost metal layer of the cell region CELL.

[0193] According to embodiments of this disclosure, a reinforcing metal pattern corresponding to and having the same shape as the metal pattern formed in the uppermost metal layer of one of the cell region CELL and the peripheral circuit region PERI can be formed in the uppermost metal layer of the other of the cell region CELL and the peripheral circuit region PERI, and the contact may not be formed on the reinforcing metal pattern.

[0194] In one exemplary embodiment, the first input / output pad 605 or the second input / output pad 505 may be referenced. Figures 1 to 21 The description describes a connection in one of the pins used for receiving data signals. Thus, data signals can be received through either the first input / output pad 605 or the second input / output pad 505. In this case, in the first mode, command / address CMD / ADDR can also be received through either the first input / output pad 605 or the second input / output pad 505. Although not shown, multiple first input / output pads 605 or multiple second input / output pads 505 may be present for the data signals and command / address CMD / ADDR to be received. In the second mode, command / address CMD / ADDR can be received through at least another pad.

[0195] In another embodiment, the first input / output pad 605 or the second input / output pad 505 may be referenced. Figures 1 to 21 The description describes a connection in one of the pins for receiving control signals, including command / address CMD / ADDR, in the second mode. In this case, in the second mode, the command / address CMD / ADDR can be received via either the first input / output pad 605 or the second input / output pad 505.

[0196] Figure 23 This is a block diagram illustrating an SSD system employing a memory device according to an embodiment of the present disclosure. (Refer to...) Figure 23 The SSD system 1000 includes the host 1100 and the SSD 1200.

[0197] The SSD 1200 can exchange signals SIG with the host 1100 via signal connector 1201 and can be powered by PWR via power connector 1202. The SSD 1200 may include an SSD controller 1210, multiple flash memory modules 1221 to 122m, an auxiliary power supply 1230, and a cache memory 1240, where m is a positive integer. The multiple flash memory modules 1221 to 122m can be connected to the SSD controller 1210 via multiple channels.

[0198] In response to the SIG signal from host 1100, SSD controller 1210 can control multiple flash memory modules 1221 to 122m. SSD controller 1210 can store internally generated signals or signals transmitted from external sources (e.g., the SIG signal received from host 1100) in buffer memory 1240. SSD controller 1210 can be used with reference to... Figures 1 to 21 The described memory controller is implemented. For example, when multiple flash memory modules 1221 to 122m are operating in a first mode, the SSD controller 1210 can send command / address CMD / ADDR in one channel through the same pin as the pin used to send data "DATA". When multiple flash memory modules 1221 to 122m are operating in a second mode, the SSD controller 1210 can send command / address CMD / ADDR in one channel through a pin different from the pin used to send data "DATA".

[0199] Multiple flash memory modules 1221 to 122m can operate under the control of SSD controller 1210. Auxiliary power supply 1230 is connected to host 1100 via power connector 1202. Each of the multiple flash memory modules 1221 to 122m can be referenced. Figures 1 to 21 The described memory device is implemented. For example, each of the plurality of flash memory 1221 to 122m can receive command / address CMD / ADDR in a first mode via the same pin as the pin used to receive data "DATA", and can receive command / address CMD / ADDR in a second mode via a different pin than the pin used to receive data "DATA".

[0200] The auxiliary power supply 1230 can be connected to the host 1100 via power connector 1202. The auxiliary power supply 1230 can be charged by the power PWR supplied from the host 1100. When the power PWR is not smoothly supplied from the host 1100, the auxiliary power supply 1230 can power the SSD 1200.

[0201] Figure 24 This is a block diagram illustrating a network system employing a memory system according to an embodiment of the present disclosure. (Refer to...) Figure 24The network system 2000, which serves as a device for storing various types of data and providing services, can be referred to as a "data center" or "data storage center." The network system 2000 may include application servers 2100 to 2100n and storage servers 2200 to 2200m, which can be referred to as "computing nodes," where n and m are positive integers. The number of application servers 2100 to 2100n and the number of storage servers 2200 to 2200m can be selected differently depending on the embodiment, and the number of application servers 2100 to 2100n and the number of storage servers 2200 to 2200m can be different.

[0202] Application servers 2100 to 2100n and storage servers 2200 to 2200m can communicate with each other via network 2300. Network 2300 can be implemented using, for example, Fibre Channel (FC) or Ethernet. In this case, FC can be a medium for high-speed data transmission and can use optical switches that provide high performance / high availability. Storage servers 2200 to 2200m can be configured as file storage, block storage, or object storage depending on the access method of network 2300.

[0203] In one exemplary embodiment, network 2300 may be a storage-specific network (such as a storage area network (SAN)). For example, the SAN may be an FC-SAN implemented using an FC network and in accordance with the FC protocol (FCP). In one exemplary embodiment, the SAN may be an IP-SAN implemented using the TCP / IP protocol and in accordance with the iSCSI (SCSI over TCP / IP) or Internet SCSI) protocol. In one exemplary embodiment, network 2300 may be a general-purpose network (such as a TCP / IP network). For example, network 2300 may be implemented in accordance with protocols such as FCoE (FC over Ethernet), NAS (Network Attached Storage), or NVMe-oF (NVMe over Fabrics).

[0204] The following description will primarily focus on application server 2100 (e.g., application server 1) and storage server 2200 (e.g., storage server 1). The description of application server 2100 can be applied to another application server 2100n (e.g., application server N), and the description of storage server 2200 can be applied to another storage server 2200m (e.g., storage server M).

[0205] Application server 2100 may include processor 2110 and memory 2120. Processor 2110 may control the overall operation of application server 2100 and may access memory 2120 to execute instructions and / or data loaded onto memory 2120. According to embodiments, the number of processors 2110 and the number of memories 2120 in application server 2100 may be selected differently. In one exemplary embodiment, processors 2110 and memory 2120 may consist of processor-memory pairs. In one exemplary embodiment, the number of processors 2110 and the number of memories 2120 may be selected differently.

[0206] Application server 2100 may also include storage device 2150. In this case, the number of storage devices 2150 included in application server 2100 may be selected differently depending on the embodiment. Processor 2110 may provide commands to storage device 2150, and storage device 2150 may operate in response to commands received from processor 2110. However, this disclosure is not limited thereto. For example, application server 2100 may not include storage device 2150.

[0207] Application server 2100 may also include switch 2130 and network interface card (NIC) 2140. Under the control of processor 2110, switch 2130 may selectively connect processor 2110 and storage device 2150, or may selectively connect NIC 2140 and storage device 2150. NIC 2140 may include wired interface, wireless interface, Bluetooth interface, optical interface, etc. In one exemplary embodiment, processor 2110 and NIC 2140 may be integrated into a single device. In one exemplary embodiment, storage device 2150 and NIC 2140 may be integrated into a single device.

[0208] Application server 2100 can store data requested by users or clients from one of storage servers 2200 to 2200m via network 2300. Furthermore, application server 2100 can retrieve data requested by users or clients from one of storage servers 2200 to 2200m via network 2300. For example, application server 2100 can be implemented using a web server, a database management system (DBMS), etc.

[0209] Application server 2100 can access memory 2120n or storage device 2150n included in another application server 2100n via network 2300, or access memory 2220 to 2220m or storage device 2250 to 2250m included in storage servers 2200 to 2200m via network 2300. Thus, application server 2100 can perform various operations on data stored in application servers 2100 and 2100n and / or storage servers 2200 and 2200m. For example, application server 2100 can execute instructions for moving or copying data between application servers 2100 and 2100n and / or storage servers 2200 and 2200m. In this case, for security and privacy, data can be moved via network 2300 in an encrypted state.

[0210] Storage server 2200 may include processor 2210 and memory 2220. Processor 2210 may control the overall operation of storage server 2200 and may access memory 2220 to execute instructions and / or data loaded onto memory 2220. According to embodiments, the number of processors 2210 and the number of memories 2220 in storage server 2200 may be selected differently. In one exemplary embodiment, processors 2210 and memory 2220 may consist of processor-memory pairs. In one exemplary embodiment, the number of processors 2210 and the number of memories 2220 may be selected differently.

[0211] Processor 2210 may include a single-core processor or a multi-core processor. For example, processor 2210 may include a general-purpose processor, CPU (Central Processing Unit), GPU (Graphics Processing Unit), DSP (Digital Signal Processor), MCU (Microcontroller), microprocessor, network processor, embedded processor, FPGA (Field Programmable Gate Array), ASIP (Application-Specific Instruction Set Processor), ASIC (Application-Specific Integrated Circuit) processor, etc.

[0212] Storage server 2200 may further include at least one storage device 2250. The number of storage devices 2250 included in storage server 2200 may be selected differently depending on the embodiment. Storage device 2250 may include a controller (CTRL) 2251, NAND flash memory (NAND) 2252, dynamic random access memory (DRAM) 2253, and an interface (I / F) 2254. The configuration and operation of storage device 2250 will be described more fully below. The following description of storage device 2250 can be applied to the remaining storage devices 2150, 2150n, and 2250m.

[0213] Interface 2254 can provide physical connections between processor 2210 and controller 2251, as well as between NIC 2240 and controller 2251. For example, interface 2254 can be implemented as a direct-attached storage (DAS) interface, directly connecting storage device 2250 to a dedicated cable. Furthermore, interface 2254 can be implemented as various interface types, such as ATA (Advanced Technology Attached) interface, SATA (Serial ATA) interface, e-SATA (External SATA) interface, SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), PCI (Peripheral Component Interconnect) interface, PCIe (PCI Fast) interface, NVMe (NVM Fast) interface, IEEE 1394 interface, USB (Universal Serial Bus) interface, SD (Secure Digital) card interface, MMC (Multimedia Card) interface, eMMC (Embedded Multimedia Card) interface, and CF (Compact Flash) card interface.

[0214] Controller 2251 can control the overall operation of storage device 2250. Controller 2251 can program data into NAND flash memory 2252 in response to programming commands, or can read data from NAND flash memory 2252 in response to read commands. For example, program commands and / or read commands can be provided via processor 2210 from processor 2110 in storage server 2200, processor 2210m of another storage server 2200m, or processors 2110 and 2110n in application servers 2100 and 2100n, or can be provided directly from processor 2110 in storage server 2200, processor 2210m of another storage server 2200m, or processors 2110 and 2110n in application servers 2100 and 2100n.

[0215] NAND flash memory 2252 may include multiple NAND flash memory cells. However, this disclosure is not limited thereto. For example, storage device 2250 may include any other non-volatile memory besides NAND flash memory 2252 (e.g., resistive RAM (ReRAM), phase-change RAM (PRAM), or magnetic RAM (MRAM)), or may include magnetic storage media, optical storage media, etc.

[0216] DRAM 2253 can be used as a buffer memory. For example, DRAM 2253 can be DDR SDRAM (Double Data Rate Synchronous DRAM), LPDDR (Low Power DDR) SDRAM, GDDR (Graphics DDR) SDRAM, RDRAM (Rambus DRAM), or HBM (High Bandwidth Memory). However, this disclosure is not limited thereto. For example, storage device 2250 can use any other volatile or non-volatile memory besides DRAM as buffer memory. DRAM 2253 can temporarily store (or buffer) data to be programmed into or read from NAND flash memory 2252.

[0217] Storage server 2200 may include switch 2230 and NIC 2240. Under the control of processor 2210, switch 2230 may selectively connect processor 2210 and storage device 2250, or selectively connect NIC 2240 and storage device 2250. In one exemplary embodiment, processor 2210 and NIC 2240 may be integrated into a single device. In another exemplary embodiment, storage device 2250 and NIC 2240 may be integrated into a single device.

[0218] Storage devices 2150, 2150n, 2250 and 2250m can correspond to reference Figures 1 to 21 The memory system described. For example, in response to a request provided from one of processors 2110, 2110n, 2210, and 2210m, controller 2251 can transfer command / address CMD / ADDR to NAND flash memory 2252. In this case, when NAND flash memory 2252 operates in a first mode, controller 2251 can send command / address CMD / ADDR through the same pin used to send data "DATA". When NAND flash memory 2252 operates in a second mode, controller 2251 can send command / address CMD / ADDR through a different pin than the pin used to send data "DATA".

[0219] The non-volatile memory device according to embodiments of the present disclosure can support a high-efficiency input / output interface that can send data to or receive data from the memory controller while receiving commands or addresses from the memory controller.

[0220] In addition to high-efficiency input / output interfaces, the non-volatile memory devices according to embodiments of the present disclosure may optionally support conventional input / output interfaces. Thus, interface-compatible non-volatile memory devices can be provided.

[0221] Although this disclosure has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A non-volatile memory device, comprising: The first pin is configured to receive a first signal from the memory controller; The second pin is configured to receive a second signal from the memory controller; The third pin is configured to receive a third signal from the memory controller; The fourth pin is configured to receive a write enable signal from the memory controller; Memory cell array; as well as The memory interface circuit is configured to: obtain commands, addresses, and data from a third signal in a first mode, and obtain commands and addresses from a first signal and a second signal and obtain data from the third signal in a second mode. The memory interface circuit is configured such that: In the first mode, the memory interface circuit obtains a command from the third signal received during the enable period of the first signal based on the switching timing of the write enable signal, and obtains an address from the third signal received during the enable period of the second signal based on the switching timing of the write enable signal. as well as In the second mode, based on the first signal with an enabled state received in the first cycle of the first time period, the memory interface circuit obtains a command from the first signal and the second signal received during the remaining cycle of the first time period based on the switching timing of the write enable signal, and based on the second signal with an enabled state received in the second cycle of the second time period, the memory interface circuit obtains an address from the first signal and the second signal received during the remaining cycle of the second time period based on the switching timing of the write enable signal, wherein the first time period includes a predetermined number of cycle periods and the second time period includes the predetermined number of cycle periods.

2. The non-volatile memory device according to claim 1, wherein, Each cycle corresponds to one or more time periods for writing the enable signal.

3. The non-volatile memory device according to claim 1, wherein, The memory interface circuit is configured to access the memory cell array by receiving a third signal including data at the third pin in a second mode, while simultaneously receiving a first signal and a second signal at the first and second pins respectively, wherein the first and second signals include commands or addresses.

4. The non-volatile memory device according to claim 1, wherein, The frequency of the write enable signal received in the first mode is different from the frequency of the write enable signal received in the second mode.

5. The non-volatile memory device according to claim 1, wherein, Before the first and second signals, which include commands or addresses, are received, the write enable signal changes from static to a toggled state.

6. The non-volatile memory device according to claim 1, wherein, The memory interface circuit is also configured as follows: In the second mode, in response to a status read command provided by the memory controller, the status information of the non-volatile memory device is output via at least one of the first and second pins.

7. The non-volatile memory device according to claim 1, wherein, The memory interface circuit includes: A write enable signal divider is configured to: generate a plurality of internal clock signals and a recovered write enable signal based on a write enable signal, wherein the plurality of internal clock signals have different phases from each other, and the recovered write enable signal has the same phase as one of the plurality of internal clock signals; and The spread spectrum is configured to: sample a first signal received in a first cycle based on a first internal clock signal among the plurality of internal clock signals to generate a sampled command latch enable signal; sample a second signal received in the first cycle based on the first internal clock signal to generate a sampled address latch enable signal; and sample the first and second signals received in the remaining cycle of a first time period based on the remaining internal clock signal among the plurality of internal clock signals to generate a sampled command / address signal that can be output through signal lines, the number of signal lines being equal to the number of third pins.

8. The non-volatile memory device according to claim 1, further comprising: Pin 5 is configured to receive a read enable signal from the memory controller; Pin 6 is configured to send a data strobe signal to the memory controller. The memory cell array is configured to store data obtained from the third signal; and The control logic circuit is configured to read stored data from the memory cell array. The memory interface circuit is also configured as follows: A data strobe signal is generated based on the switching of the read enable signal, and a switching signal is generated after a predetermined delay; and Generate a third signal, including the read data, aligned with the switching timing of the data strobe signal, and The third pin is configured to output a third signal, including the read data, to the memory controller.

9. The non-volatile memory device according to claim 8, further comprising: Pin 7 is configured to send a ready / busy output signal to the memory controller. The memory interface circuit is configured such that, while stored data is being read from the memory cell array, pin 7 outputs a ready / busy output signal indicating the busy state of the non-volatile memory device to the memory controller.

10. The non-volatile memory device according to claim 8, wherein, In the second mode, the frequency of the write enable signal is different from the frequency of the read enable signal.

11. The non-volatile memory device according to any one of claims 1 to 10, wherein, The memory cell array includes NAND flash memory cells arranged vertically on a substrate.

12. The non-volatile memory device according to any one of claims 1 to 10, wherein, The non-volatile memory device is configured to be set to one of a first mode and a second mode by a memory controller.

13. A non-volatile memory device, comprising: The first pin is configured to receive control signals from the memory controller; The second pin is configured to receive a write enable signal from the memory controller; The third pin is configured to receive data signals from the memory controller; Memory cell array; as well as Memory interface circuit, Specifically, based on control signals received during a first and second cycle of a time period comprising a predetermined number of cycle cycles, the memory interface circuit is configured to obtain commands or addresses from control signals received during the remaining cycle cycles of said time period. Specifically, when the control signal received during the first cycle is in an enabled state, the memory interface circuit obtains a command from the control signal received during the remaining cycle based on the switching timing of the write enable signal, and Specifically, when the control signal received during the second cycle is in an enabled state, the memory interface circuit obtains the address from the control signal received during the remaining cycle based on the switching timing of the write enable signal.

14. The non-volatile memory device according to claim 13, wherein, Each cycle corresponds to one or more time periods for writing the enable signal.

15. The non-volatile memory device according to claim 14, wherein, The predetermined number of cycles is determined based on the number of third pins.

16. The non-volatile memory device according to any one of claims 13 to 15, wherein, The memory interface circuit is configured to access the memory cell array based on a data signal including data received at the third pin and a control signal including a command or address received at the first pin.

17. A non-volatile memory device, comprising: The first pin is configured to receive a plurality of control signals from the memory controller, including a first control signal and a second control signal; The second pin is configured to receive a write enable signal from the memory controller; The third pin is configured to receive data signals from the memory controller; as well as Memory interface circuit, Specifically, based on a first control signal with an enabled state received in a first cycle of a first time period, the memory interface circuit obtains a command from the plurality of control signals received during the first time period based on the switching timing of the write enable signal; and based on a second control signal with an enabled state received in a second cycle of a second time period, the memory interface circuit obtains an address from the plurality of control signals received during the second time period based on the switching timing of the write enable signal. The first time period includes a predetermined number of cycle periods, and the second time period includes the predetermined number of cycle periods.

18. The non-volatile memory device according to claim 17, wherein, Each cycle corresponds to one or more time periods for writing the enable signal.

19. The non-volatile memory device according to claim 17, wherein, While the third pin receives a data signal including data, the first pin receives the plurality of control signals including commands or addresses.

20. The non-volatile memory device according to claim 17, wherein, At least one of the plurality of control signals has an invalid value in the third cycle of the first time period and / or the fourth cycle of the second time period.

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