Semiconductor package

Abstract

A semiconductor package includes a first semiconductor chip including a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern; a second semiconductor chip on a top surface of the first semiconductor chip; and a bump structure disposed between the first semiconductor chip and the second semiconductor chip. The bump structure is disposed in the hole and in contact with the inner sidewall of the redistribution pattern.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2020-0086234, filed on July 13, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present invention relate to semiconductor packages, and more specifically, to semiconductor packages including bump structures. Background Technology

[0004] Techniques for stacking semiconductor chips have been developed to improve the integration density and performance of semiconductor devices. For example, in multi-chip packaging (MCP) technology, multiple semiconductor chips can be mounted in a single semiconductor package. In system-in-package (SoC) technology, different types of semiconductor chips can be stacked in a single semiconductor package capable of operating as a system. To miniaturize electronic devices, it may be necessary to reduce the thickness of the semiconductor package. Additionally, it may be necessary for the semiconductor package to possess heat dissipation properties that effectively dissipate heat generated from the stacked semiconductor chips during operation. Summary of the Invention

[0005] Embodiments of the present invention can provide a miniaturized semiconductor package.

[0006] Embodiments of the present invention may also provide a semiconductor package capable of reducing the distance between stacked semiconductor chips and improving thermal properties.

[0007] In one aspect, a semiconductor package may include: a first semiconductor chip including a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having an aperture exposing an inner sidewall of the redistribution pattern; a second semiconductor chip located on the top surface of the first semiconductor chip; and a bump structure disposed between the first semiconductor chip and the second semiconductor chip. The bump structure may be disposed in the aperture and may contact the inner sidewall of the redistribution pattern.

[0008] In an aspect, a semiconductor package can include a first semiconductor chip including a semiconductor substrate and a redistribution pattern disposed on a top surface of the semiconductor substrate, the redistribution pattern having a hole; a second semiconductor chip on a top surface of the first semiconductor chip; a solder pattern disposed in the hole to be in contact with an inner sidewall of the redistribution pattern; and a pillar pattern disposed between the solder pattern and the second semiconductor chip.

[0009] In an aspect, a semiconductor package can include a first semiconductor chip including a semiconductor substrate and a redistribution pattern disposed on a top surface of the semiconductor substrate, the redistribution pattern having a hole; a second semiconductor chip on a top surface of the first semiconductor chip; a solder pattern disposed in the hole to be in contact with an inner sidewall of the redistribution pattern; and a pillar pattern disposed between the solder pattern and the second semiconductor chip. BRIEF DESCRIPTION OF DRAWINGS

[0010] The inventive concept will become more readily apparent from the following description of the embodiments, taken in conjunction with the accompanying drawings.

[0011] FIG. 1A is a cross-sectional view illustrating a semiconductor package according to an example embodiment of the inventive concept.

[0012] FIG. 1B is FIG. 1A is a cross-sectional view illustrating a semiconductor package according to an example embodiment of the inventive concept.

[0013] FIG. 1Cis a top view showing an arrangement of a bump structure, a first redistribution pattern, and a through structure according to an example embodiment of the inventive concept.

[0014] FIG. 1D is an enlarged view of a region "II" of FIG. 1A and corresponds to a cross-sectional view taken along line III-III' of FIG. 1C .

[0015] FIG. 1E is a cross-sectional view showing a process of electrically connecting a first semiconductor chip and a second semiconductor chip.

[0016] FIG. 2A is a view showing a bump structure and a first redistribution pattern according to an example embodiment of the inventive concept.

[0017] FIG. 2B is a view showing a first redistribution pattern and a first protective layer according to an example embodiment of the inventive concept.

[0018] FIG. 2C is a view showing a semiconductor package according to an example embodiment of the inventive concept.

[0019] FIG. 2D is a view showing an electrical connection of a bump structure and a first through structure according to an example embodiment of the inventive concept.

[0020] FIG. 3 is a cross-sectional view showing a semiconductor package according to an example embodiment of the inventive concept.

[0021] FIG. 4A is a cross-sectional view showing a semiconductor package according to an example embodiment of the inventive concept.

[0022] FIG. 4B is an enlarged view of a region "IV" of FIG. 4A . DETAILED DESCRIPTION

[0023] Throughout the specification, the same reference numbers or the same reference designations can represent the same elements or components.

[0024] Hereinafter, a semiconductor package according to an example embodiment of the inventive concept will be described.

[0025] FIG. 1A is a cross-sectional view showing a semiconductor package according to an example embodiment of the inventive concept. FIG. 1B is an enlarged view of a region "I" of FIG. 1A . FIG. 1C is a top view showing an arrangement of a bump structure, a first redistribution pattern, and a through structure according to an example embodiment of the inventive concept.FIG. 1D is FIG. 1A an enlarged view of the region "II" of FIG. 1C and corresponds to a cross-sectional view taken along the line III-III' of

[0026] Referring to FIG. 1A , FIG. 1B , FIG. 1C and FIG. 1D , the semiconductor package can include a first semiconductor chip 100, a second semiconductor chip 200, and a bump structure 300. The semiconductor package can further include a package substrate 900 and external terminals 950. The package substrate 900 can include an insulating base layer 910, substrate pads 920, and internal interconnection lines 930. The insulating base layer 910 can include a single layer or multiple layers. The substrate pads 920 can be exposed at a top surface of the package substrate 900. A top surface of the substrate pads 920 can be coplanar with a top surface of the package substrate 900. Otherwise, the top surface of the substrate pads 920 can be disposed at a different level from the top surface of the package substrate 900. The internal interconnection lines 930 can be disposed in the insulating base layer 910 and can be connected to the substrate pads 920. In the present specification, it will be understood that when an assembly is referred to as being "electrically connected" to another assembly, it can be directly connected to the other assembly or there can be an intermediate assembly. In the present specification, it will be understood that when an assembly is referred to as being electrically connected to the package substrate 900, it can be electrically connected to the internal interconnection lines 930. The substrate pads 920 and the internal interconnection lines 930 can include a metal such as copper, aluminum, tungsten, and / or titanium. For example, the package substrate 900 can be a printed circuit board having a circuit pattern. Alternatively, a redistribution layer can be used as the package substrate 900. When the redistribution layer is used as the package substrate 900, the insulating base layer 910 can include a photosensitive polymer or a photoimageable dielectric (PID) material. When the redistribution layer is used as the package substrate 900, the internal interconnection lines 930 can include a seed layer and a metal layer on the seed layer.

[0027] The external terminals 950 can be disposed on a bottom surface of the package substrate 900 and can be connected to the internal interconnection lines 930. For example, the external terminals 950 can be in contact with lower substrate pads 940 exposed at the bottom surface of the package substrate 900. External electrical signals can be transmitted to the internal interconnection lines 930 through the external terminals 950. The external terminals 950 can include solder balls. The external terminals 950 can include a metal such as a solder material. The solder material can include tin (Sn), silver (Ag), zinc (Zn), and / or any alloy thereof.

[0028] The term "contact" or "in contact with" as used herein, unless otherwise indicated by context, refers to direct connection (i.e., touching). Terms such as "same," "equal," "planar," or "co-planar" as used herein, when referring to direction, layout, position, shape, size, amount, or other measure, do not necessarily indicate a perfect same, equal, planar, or co-planar direction, layout, position, shape, size, amount, or other measure, but are intended to encompass a nearly same, equal, planar, or co-planar direction, layout, position, shape, size, amount, or other measure within acceptable variations that can occur, for example, due to manufacturing processes. The term "substantially" can be used herein to emphasize such a meaning, unless otherwise indicated by context or other statement. For example, items described as "substantially same," "substantially equal," or "substantially planar" can be perfectly same, equal, or planar, or can be same, equal, or planar within acceptable variations that can occur, for example, due to manufacturing processes.

[0029] The first semiconductor chip 100 can be mounted on a top surface of the package substrate 900. The first semiconductor chip 100 can include a first semiconductor substrate 110, a first circuit layer 120, first chip pads 150, first through-substrate vias 140, a first redistribution pattern 160, and a first protective layer 180. For example, the first semiconductor substrate 110 can include a semiconductor material such as silicon, germanium, or silicon germanium. The first semiconductor substrate 110 can have a top surface 110a and a bottom surface 110b opposite to each other.

[0030] The first circuit layer 120 can be disposed on the bottom surface 110b of the first semiconductor substrate 110. The first circuit layer 120 can include a first insulating layer 121, first integrated circuits 123, and first interconnection structures 125, as FIG. 1BThe first integrated circuit 123 can be provided on the bottom surface 110b of the first semiconductor substrate 110. For example, the first integrated circuit 123 can include a transistor. The first integrated circuit 123 can include a logic circuit, a memory circuit, and / or a combination thereof. The first insulating layer 121 can be provided on the bottom surface 110b of the first semiconductor substrate 110 and can cover the first integrated circuit 123. Even though not illustrated in the drawings, the first insulating layer 121 can include a plurality of stacked layers. The first insulating layer 121 can include a silicon-containing insulating material. For example, the silicon-containing insulating material can include silicon oxide, silicon nitride, silicon oxynitride, and / or tetraethyl orthosilicate. The first interconnection structure 125 can be provided in the first insulating layer 121. The first interconnection structure 125 can be electrically connected to the first integrated circuit 123. In this specification, it can be understood that when a component is referred to as being electrically connected to a semiconductor chip, it can be electrically connected to an integrated circuit of the semiconductor chip. The first interconnection structure 125 can include an interconnection pattern and a via pattern connected to the interconnection pattern. The interconnection pattern can have a long axis extending in a direction parallel to the bottom surface 110b of the first semiconductor substrate 110. The long axis of the via pattern can be parallel to a direction intersecting the bottom surface 110b of the first semiconductor substrate 110. The via pattern can be provided between a plurality of interconnection patterns and can be connected to the interconnection patterns. The width of each interconnection pattern can be greater than the width of the via pattern directly connected thereto. The first interconnection structure 125 can include a metal such as copper, aluminum, titanium, or tungsten.

[0031] The first chip pad 150 can be exposed at the bottom surface of the first semiconductor chip 100. The first chip pad 150 can be provided on the bottom surface of the first circuit layer 120. The first chip pad 150 can be electrically connected to the first integrated circuit 123 through the first interconnection structure 125. The first chip pad 150 can include a material different from that of the first interconnection structure 125. The first chip pad 150 can include a metal such as aluminum. The first chip pad 150 can be a plurality of chip pads 150.

[0032] The first semiconductor chip 100 can further include a first lower insulating pattern 130, as FIG. 1B illustrated. The first lower insulating pattern 130 can be provided on the bottom surface of the first insulating layer 121 and can cover an edge portion of the first chip pad 150. For example, the first lower insulating pattern 130 can contact a side surface of the first chip pad as well as an edge portion of the bottom surface of each first chip pad 150. The first lower insulating pattern 130 can expose at least a portion of the first chip pad 150. For example, the first lower insulating pattern 130 can expose a central portion of each first chip pad 150. The first lower insulating pattern 130 can include an insulating polymer or a silicon-based insulating material.

[0033] Semiconductor packages may also include bonding bumps 350. For example... FIG. 1A As shown, bonding bumps 350 can be disposed between the package substrate 900 and the first semiconductor chip 100, and can be electrically connected to the package substrate 900 and the first semiconductor chip 100. For example, bonding bumps 350 can be connected to substrate pads 920 and first chip pads 150. Bonding bumps 350 can contact the top surface of substrate pads 920 and the bottom surface of first chip pads 150. Bonding bumps 350 can include solder balls, bumps, or pillars. Bonding bumps 350 can include conductive material. There can be multiple bonding bumps 350.

[0034] The first through-structure 140 may be disposed in the first semiconductor substrate 110. The first through-structure 140 may penetrate the top surface 110a and the bottom surface 110b of the first semiconductor substrate 110. The first through-structure 140 may also penetrate at least a portion of the first circuit layer 120. For example, the first through-structure 140 may also penetrate the upper portion of the first insulating layer 121, such as... FIG. 1B As shown. The first through-structure 140 can also be electrically connected to at least one of the first chip pad 150 and the first integrated circuit 123 via the first interconnect structure 125. There can be a plurality of first through-structures 140, and each first through-structure 140 can be electrically connected to at least one corresponding first chip pad 150.

[0035] exist FIG. 1A and FIG. 1D In this embodiment, the first redistribution pattern 160 may be disposed on the top surface 110a of the first semiconductor substrate 110. It will be understood in this specification that when a component is referred to as being "on" another component, it may be directly on the other component, or there may be an intermediate component. For example, in some embodiments, a first upper insulating layer 170 may also be disposed between the top surface 110a of the first semiconductor substrate 110 and the first redistribution pattern 160. The first upper insulating layer 170 may comprise a silicon-containing insulating material. Even if not shown in the figures, the first upper insulating layer 170 may comprise multiple stacked layers. If the first redistribution pattern 160 is in direct contact with the top surface 110a of the first semiconductor substrate 110, the bonding strength between the first redistribution pattern 160 and the first semiconductor substrate 110 may be relatively weak. However, according to embodiments, the first redistribution pattern 160 can be stably fixed to the first semiconductor substrate 110 by the first upper insulating layer 170.

[0036] The first redistribution pattern 160 can cover the first through structure 140. For example, one end portion of the first redistribution pattern 160 can be disposed on a top surface of the first through structure 140 and can be in contact with the first through structure 140. The first redistribution pattern 160 can be electrically connected to the first through structure 140. Accordingly, the first redistribution pattern 160 can be electrically connected to the first integrated circuit 123 and the package substrate 900 through the first through structure 140.

[0037] As FIG. 1D illustrated, the first redistribution pattern 160 can have a first hole 169. The first hole 169 can penetrate a top surface of the first redistribution pattern 160 and can expose an inner side wall 160c of the first redistribution pattern 160. The first hole 169 can also penetrate a bottom surface of the first redistribution pattern 160 to expose the first upper insulating layer 170 or the first semiconductor substrate 110. The first hole 169 can not be vertically overlapped with the first through structure 140. In the present specification, the term "vertical" can mean "perpendicular to the top surface 110a of the first semiconductor substrate 110". As FIG. 1C illustrated, the first hole 169 can be spaced apart from the first through structure 140 when viewed in a top view. The first hole 169 can have a rounded quadrilateral shape when viewed in a top view. The planar shape of the first hole 169 can be variously modified. For example, the first hole 169 can have an octagonal shape or a circular shape when viewed in a top view.

[0038] The first redistribution pattern 160 can include a seed pattern 161 and a conductive pattern 162. For example, the seed pattern 161 can include at least one of titanium or copper. A bottom surface of the first redistribution pattern 160 can mean a bottom surface of the seed pattern 161. The conductive pattern 162 can be disposed on the seed pattern 161 and can be in contact with a top surface of the seed pattern 161. The conductive pattern 162 can include a metal such as copper, nickel, or any alloy thereof. The conductive pattern 162 can be formed by an electroplating process using the seed pattern 161 as an electrode. The thickness of the conductive pattern 162 can be greater than the thickness of the seed pattern 161. The thickness can mean a thickness or height measured in a direction perpendicular to the top surface 110a of the first semiconductor substrate 110. The top surface of the redistribution pattern 160 can guide the top surface of the conductive pattern 162. For the sake of simplicity and convenience of illustration, the seed pattern 161 and the conductive pattern 162 of the first redistribution pattern 160 are not separately illustrated in other drawings except FIG. 1D . However, in other drawings, the first redistribution pattern 160 can include the seed pattern 161 and the conductive pattern 162.

[0039] A first protective layer 180 can be disposed on the top surface 110a of the first semiconductor substrate 110. For example, the first protective layer 180 can cover the top surface and the outer sidewall of the first redistribution pattern 160 and the top surface of the first upper insulating layer 170. The first protective layer 180 can contact the top surface and the outer sidewall of the first redistribution pattern 160 and the top surface of the first upper insulating layer 170. The first protective layer 180 can be an organic insulating layer. For example, the first protective layer 180 can include a photosensitive polymer or a photoimageable dielectric material. For example, the photosensitive polymer or the photoimageable dielectric material can include at least one of a photosensitive polyimide, a polybenzoxazole, a phenol-based polymer, or a benzocyclobutene-based polymer. The first protective layer 180 can not extend into the first hole 169 of the first redistribution pattern 160. The first protective layer 180 can not cover the inner sidewall 160c of the first redistribution pattern 160. The first protective layer 180 can have a first opening 189. The first opening 189 can penetrate the top surface 180a and the bottom surface of the first protective layer 180. The first opening 189 can be connected to the first hole 169. The first opening 189 can expose the inner sidewall 180c of the first protective layer. The inner sidewall 180c of the first protective layer 180 can be coplanar with the inner sidewall 160c of the first redistribution pattern 160.

[0040] The second semiconductor chip 200 can be disposed on the first semiconductor chip 100. The type of the second semiconductor chip 200 can be different from the type of the first semiconductor chip 100. For example, the first semiconductor chip 100 can be a logic chip, and the second semiconductor chip 200 can be a memory chip. Alternatively, the type of the second semiconductor chip 200 can be the same as the type of the first semiconductor chip 100. For example, both the first semiconductor chip 100 and the second semiconductor chip 200 can be memory chips. As shown, the width of the second semiconductor chip 200 can be equal to the width of the first semiconductor chip 100. Alternatively, the width of the second semiconductor chip 200 can be different from the width of the first semiconductor chip 100. FIG. 1A

[0041] The second semiconductor chip 200 can include a second semiconductor substrate 210, a second circuit layer 220, and a second chip pad 250. The second semiconductor substrate 210 can include at least one of the materials described as examples of the first semiconductor substrate 110. The second circuit layer 220 can be disposed on the bottom surface 210b of the second semiconductor substrate 210. The second circuit layer 220 can include a second insulating layer 221, a second integrated circuit 223, and a second interconnection structure 225, as shown. FIG. 1D ​The second integrated circuit 223 can be provided on the bottom surface 210b of the second semiconductor substrate 210. For example, the second integrated circuit 223 can include a transistor. The second integrated circuit 223 can include a logic circuit, a memory circuit, and / or a combination thereof. The second insulating layer 221 can be provided on the bottom surface 210b of the second semiconductor substrate 210 and can cover the second integrated circuit 223. Even though not shown in the drawings, the second insulating layer 221 can include a plurality of stacked layers. The second insulating layer 221 can include a silicon-containing insulating material. The second interconnection structure 225 can be provided in the second insulating layer 221. The second interconnection structure 225 can be electrically connected to the second integrated circuit 223. The second interconnection structure 225 can include an interconnection pattern and a via pattern connected to the interconnection pattern. The interconnection pattern can have a long axis extending in a direction parallel to the bottom surface 210b of the second semiconductor substrate 210. The long axis of the via pattern can be parallel to a direction intersecting the bottom surface 210b of the second semiconductor substrate 210. The via pattern can be provided between a plurality of interconnection patterns and can be connected to the interconnection patterns. A width of each interconnection pattern can be greater than a width of the via pattern directly connected thereto. The second interconnection structure 225 can include a metal such as copper, aluminum, titanium, or tungsten.

[0042] The second chip pad 250 can be exposed at the bottom surface of the second semiconductor chip 200. The second chip pad 250 can be provided on the bottom surface of the second circuit layer 220. The second chip pad 250 can be electrically connected to the second integrated circuit 223 through the second interconnection structure 225. The second chip pad 250 can include a material different from that of the second interconnection structure 225. For example, the second chip pad 250 can include a metal such as aluminum.

[0043] The second semiconductor chip 200 can further include a second lower insulating pattern 230. The second lower insulating pattern 230 can be provided on the bottom surface of the second circuit layer 220 and can expose the second chip pad 250. The second lower insulating pattern 230 can cover an edge portion of the second chip pad 250. For example, the second lower insulating pattern 230 can contact the bottom surface of the second circuit layer 220, a side surface of the second chip pad 250, and an edge portion of the bottom surface of the second chip pad 250. The second lower insulating pattern 230 can include a silicon-based insulating material or an insulating polymer.

[0044] The bump structure 300 can be disposed between the first semiconductor chip 100 and the second semiconductor chip 200, and can be electrically connected to the first semiconductor chip 100 and the second semiconductor chip 200. The bump structure 300 can include a solder pattern 310 and a pillar pattern 320. The solder pattern 310 can be disposed in the first hole 169 of the first redistribution pattern 160, and can cover the inner side wall 160c of the first redistribution pattern 160. For example, the solder pattern 310 can be in contact with the inner side wall 160c of the first redistribution pattern 160. The solder pattern 310 can also be disposed in the first opening 189 of the first protective layer 180, and can be in contact with the inner side wall 180c of the first protective layer 180. The solder pattern 310 can include tin (Sn), silver (Ag), zinc (Zn), and / or any alloy thereof. A bottom surface 310b of the solder pattern 310 can correspond to a bottom surface of the bump structure 300. The bottom surface 310b of the solder pattern 310 can be disposed at a lower level than a top surface of the first redistribution pattern 160. In the present specification, the term "level" can mean a vertical level. A level difference between two surfaces can be measured in a direction perpendicular to a top surface 110a of the first semiconductor substrate 110. In some embodiments, the bottom surface 310b of the solder pattern 310 can be coplanar with a bottom surface of the first redistribution pattern 160. The bottom surface 310b and the side wall of the solder pattern 310 can correspond to the shape of the bottom surface 169b and the side wall of the first hole 169. As shown in FIG. 13A, a planar shape of the solder pattern 310 can correspond to a planar shape of the first hole 169. When viewed in a top view, the solder pattern 310 can have a rounded quadrilateral shape. The planar shape of the solder pattern 310 can be variously modified. For example, when viewed in a top view, the solder pattern 310 can have an octagonal shape or a circular shape. FIG. 1C

[0045] ​The pillar pattern 320 can be disposed between the solder pattern 310 and the second semiconductor chip 200. For example, the pillar pattern 320 can be disposed between the solder pattern 310 and the second chip pad 250, and can be connected to the solder pattern 310 and the second chip pad 250. A lower portion of the pillar pattern 320 can be surrounded by the solder pattern 310. For example, a bottom surface 320b of the pillar pattern 320 can be in contact with the solder pattern 310. A sidewall of the lower portion of the pillar pattern 320 can be covered by the solder pattern 310. For example, the sidewall of the lower portion of the pillar pattern 320 can be in contact with the solder pattern 310. However, embodiments of the inventive concept are not limited thereto. At least a portion of the pillar pattern 320 can be disposed in the first opening 189. For example, the bottom surface 320b of the pillar pattern 320 can be disposed at a level lower than the top surface 180a of the first protective layer 180. Accordingly, a height A1 of the bump structure 300 can be reduced. A width of the pillar pattern 320 can be substantially uniform. A top surface 320a of the pillar pattern 320 can correspond to a top surface of the bump structure 300. The pillar pattern 320 can include a conductive material such as copper. As shown in FIG. 1C FIG. 13, the pillar pattern 320 can have a rounded quadrilateral shape when viewed in a top view. Alternatively, the pillar pattern 320 can have an octagonal shape or a circular shape when viewed in a top view. Electrical connections between the first semiconductor chip 100 and the second semiconductor chip 200 and the bump structure 300 will be described below.

[0046] FIG. 1E is an enlarged view of a region "II" corresponding to FIG. 1A to illustrate a process of electrically connecting the first semiconductor chip and the second semiconductor chip. In FIG. 1E , the first integrated circuit and the first interconnection structure are omitted for simplicity and convenience of illustration.

[0047] Referring to FIG. 1EThe second semiconductor chip 200 can be prepared. As described above, the second semiconductor chip 200 can include a second semiconductor substrate 210, a second circuit layer 220, second chip pads 250, and a second lower insulating pattern 230. At this time, an initial bump structure 300P can be formed on the second chip pads 250 of the second semiconductor chip 200. The initial bump structure 300P can include a pillar pattern 320 and an initial solder pattern 310P. The initial solder pattern 310P can have a solder ball shape. For example, a lower portion of the initial solder pattern 310P can have a shape such as a hemisphere. The second semiconductor chip 200 can be disposed on the first semiconductor chip 100 in a manner that the initial solder pattern 310P is disposed in the first hole 169 of the first redistribution pattern 160. A reflow process of the initial solder pattern 310P can be performed. The reflow process can be performed at a temperature equal to or higher than a melting point of the initial solder pattern 310P. However, embodiments of the inventive concept are not limited thereto. Even though a central axis of the initial bump structure 300P can be deviated from a central axis of the first hole 169 due to a process error, since the initial solder pattern 310P is disposed in the first hole 169, the solder pattern 310 can be in good contact with the inner side wall 160c of the first redistribution pattern 160 after the reflow process is completed. As a result, the bump structure 300 described in the middle can be formed, and the first semiconductor chip 100 and the second semiconductor chip 200 can be electrically connected to each other through the bump structure 300. As shown in the middle, FIGS. 1A-1D the bump structure 300 can include a plurality of bump structures 300 laterally spaced apart from each other. The first hole 169 can include a plurality of first holes 169 separated from each other. If the first hole 169 is omitted, in the reflow process, a plurality of initial solder patterns 310P can have fluidity and thus can be in contact with each other. In this case, an electrical short can occur between the bump structures 300. However, according to an embodiment, the first hole 169 can physically isolate the initial solder patterns 310P, respectively. Since each initial solder pattern 310P is disposed in a corresponding one of the first holes 169, even though the initial solder patterns 310P have fluidity, they do not come into contact with each other. Thus, an electrical short between a plurality of solder patterns 310 can be prevented. As a result, reliability of the bump structure 300 and a semiconductor package including the same can be improved. FIG. 1A

[0048] Again referring to FIGS. 1A-1D , the bump structure 300 can be electrically connected to the first through structure 140 through the first redistribution pattern 160. Since the first redistribution pattern 160 is provided, the bump structure 300 and the first through structure 140 can not be vertically aligned with each other. Thus, an arrangement of the bump structure 300 and the first through structure 140 can be freely designed.

[0049] ​The molding layer 400 can be disposed on a top surface of the package substrate 900 to cover the first semiconductor chip 100 and the second semiconductor chip 200. Unlike FIG. 1A In some embodiments, the molding layer 400 can cover sidewalls of the first semiconductor chip 100 and the second semiconductor chip 200, but can expose a top surface of the second semiconductor chip 200. The molding layer 400 can include an insulating polymer such as an epoxy molding compound (EMC).

[0050] The first underfill layer 410 can be disposed in a first gap region between the package substrate 900 and the first semiconductor chip 100 to seal or surround the bonding bumps 350. The first underfill layer 410 can include an insulating polymer such as an epoxy molding compound (EMC). In some embodiments, the first underfill layer 410 can include a material different from a material of the molding layer 400.

[0051] The second underfill layer 420 can be disposed in a second gap region between a top surface of the first semiconductor chip 100 and a bottom surface of the second semiconductor chip 200. The second underfill layer 420 can seal or surround the bump structure 300. The second underfill layer 420 can cover sidewalls of the pillar pattern 320. The second underfill layer 420 can include an insulating polymer such as an epoxy molding compound (EMC). However, the second underfill layer 420 can include a material different from a material of the molding layer 400. For example, the insulating polymer of the second underfill layer 420 can have a chemical structure, a number average molecular weight, a substituent, or a composition ratio different from a chemical structure, a number average molecular weight, a substituent, or a composition ratio of the insulating polymer of the molding layer 400.

[0052] If the first hole 169 and the first opening 189 are omitted, the bottom surface of the bump structure 300 can be disposed at the same level as or higher than the top surface 180a of the first protective layer 180. In this case, the distance A2 between the first semiconductor chip 100 and the second semiconductor chip 200 can be equal to or greater than the height Al of the bump structure 300. However, according to an embodiment, since a portion of the bump structure 300 is disposed in the first hole 169, the distance A2 between the first semiconductor chip 100 and the second semiconductor chip 200 can be less than the height Al of the bump structure 300. Accordingly, the distance A2 between the first semiconductor chip 100 and the second semiconductor chip 200 can be reduced, and the height of the semiconductor package can be reduced. Here, the distance A2 between the first semiconductor chip 100 and the second semiconductor chip 200 can be a distance between the bottom surface of the second underfill layer 420 and the top surface 180a of the first protective layer 180 disposed on the first redistribution pattern 160. The distance A2 between the first semiconductor chip 100 and the second semiconductor chip 200 can be substantially equal to the thickness of the second underfill layer 420. The thickness of the second underfill layer 420 can correspond to the thickness of the second underfill layer 420 disposed on the top surface 180a of the first protective layer 180 disposed on the first redistribution pattern 160. In other words, the thickness of the second underfill layer 420 can be measured at a position vertically overlapped with the first redistribution pattern 160. The height Al of the bump structure 300 can be defined as a distance between the top surface 320a of the pillar pattern 320 and the bottom surface 310b of the solder pattern 310. The thickness of the second underfill layer 420 can be less than the distance between the top surface 320a of the pillar pattern 320 and the bottom surface 310b of the solder pattern 310.

[0053] If the height Al of the bump structure 300 is greater than 30 µm, the height of the semiconductor package can increase. In some embodiments, the height Al of the bump structure 300 can be in the range of about 5 µm to about 30 µm.

[0054] If the distance A2 between the first semiconductor chip 100 and the second semiconductor chip 200 is greater than 20 µm, it can be difficult to miniaturize the semiconductor package. In some embodiments, the distance A2 between the first semiconductor chip 100 and the second semiconductor chip 200 can be in the range of about 3 µm to about 20 µm. Accordingly, the semiconductor package can be further miniaturized.

[0055] The sum of the depth of the first hole 169 and the depth of the first opening 189 can substantially correspond to the difference between the height Al of the bump structure 300 and the distance A2 between the first semiconductor chip 100 and the second semiconductor chip 200. The sum of the depth of the first hole 169 and the depth of the first opening 189 can be the horizontal height difference A3 between the top surface 180a of the first protective layer 180 and the bottom surface 169b of the first hole 169. If the horizontal height difference A3 between the top surface 180a of the first protective layer 180 and the bottom surface 169b of the first hole 169 is less than 2 μm, it can be difficult to sufficiently reduce the height of the semiconductor package even though the bump structure 300 is disposed in the first hole 169. If the horizontal height difference A3 between the top surface 180a of the first protective layer 180 and the bottom surface 169b of the first hole 169 is greater than 20 μm, the sum of the thicknesses of the first redistribution pattern 160 and the first protective layer 180 can be too large. In this case, it can be difficult to reduce the height of the first semiconductor chip 100. However, according to some embodiments, the horizontal height difference A3 between the top surface 180a of the first protective layer 180 and the bottom surface 169b of the first hole 169 can be in the range of about 2 μm to about 10 μm. Accordingly, the height (or thickness) of the semiconductor package can be reduced.

[0056] The second under-fill layer 420 can have a relatively low thermal conductivity. For example, the thermal conductivity of the second under-fill layer 420 can be lower than the thermal conductivity of the bump structure 300. In particular, the thermal conductivity of the second under-fill layer 420 can be lower than the thermal conductivity of the solder pattern 310 and the thermal conductivity of the pillar pattern 320. The thermal conductivity of the second under-fill layer 420 can be lower than the thermal conductivity of the first redistribution pattern 160, the thermal conductivity of the first through-structure 140, the thermal conductivity of the second chip pad 250, and the thermal conductivity of the second interconnection structure 225. As the thickness of the second under-fill layer 420 increases, the heat dissipation properties of the semiconductor package can deteriorate. For example, if the thickness of the second under-fill layer 420 is greater than 20 μm, the heat dissipation properties of the semiconductor package can deteriorate. However, according to embodiments, since the thickness of the second under-fill layer 420 is reduced, heat generated from the first semiconductor chip 100 during operation of the semiconductor package can be rapidly released or dissipated to the outside. The thickness of the second under-fill layer 420 can be in the range of about 3 μm to about 20 μm. Accordingly, the thermal properties of the semiconductor package can be improved.

[0057] FIG. 2A FIG. 1 is a view illustrating a semiconductor package according to an example embodiment of the present inventive concept. FIG. 2A is a view illustrating a semiconductor package according to an example embodiment of the present inventive concept. FIG. 1A is a view illustrating a semiconductor package according to an example embodiment of the present inventive concept. FIG. 1CThe cross-sectional view of line III-III'. In the following text, for the sake of brevity and convenience, descriptions of the same components and / or features as in the above embodiments will be omitted.

[0058] Reference FIG. 2A The semiconductor package may include a first semiconductor chip 100, a second semiconductor chip 200, and a bump structure 300. The first semiconductor chip 100 may include a first semiconductor substrate 110, a first through-structure 140, a first upper insulating layer 170, a first redistribution pattern 160, and a first protective layer 180. The first redistribution pattern 160 may be related to a reference... FIGS. 1A-1D The description is essentially the same. However, the first aperture 169 may penetrate the top surface of the first redistribution pattern 160, but may not penetrate the bottom surface 160b of the first redistribution pattern 160. The bottom surface 169b of the first aperture 169 may be located within the first redistribution pattern 160. The bottom surface 169b of the first aperture 169 may be at a higher horizontal level than the bottom surface 160b of the first redistribution pattern 160. Therefore, the bottom surface 169b of the first aperture 169 may expose the first redistribution pattern 160. The horizontal height difference A3 between the top surface 180a of the first protective layer 180 and the bottom surface 169b of the first aperture 169 may be in the range of approximately 2 μm to approximately 10 μm.

[0059] The bump structure 300 may include a solder pattern 310 and a pillar pattern 320, and the solder pattern 310 may be disposed in a first hole 169 of the first redistribution pattern 160, thereby contacting the bottom surface 169b of the first hole 169 and the inner sidewall 160c of the first redistribution pattern 160. For example, the bottom surface 310b and the sidewall of the solder pattern 310 may contact the first redistribution pattern 160. The contact area between the solder pattern 310 and the first redistribution pattern 160 may be increased, thereby allowing the solder pattern 310 to be better electrically connected to the first redistribution pattern 160. The bottom surface 310b of the solder pattern 310 may be disposed at a horizontal height higher than the bottom surface 160b of the first redistribution pattern 160. The solder pattern 310 may be spaced apart from the first upper insulating layer 170.

[0060] FIG. 2B This is a view illustrating a first redistribution pattern and a first protective layer according to an exemplary embodiment of the concept of the present invention. FIG. 2B It corresponds to FIG. 1A An enlarged view of region "II", and corresponding to FIG. 1C The cross-sectional view of line III-III'. In the following text, for the sake of brevity and convenience, descriptions of the same components and / or features as in the above embodiments will be omitted.

[0061] Reference FIG. 2BThe semiconductor package can include a first semiconductor chip 100, a second semiconductor chip 200, and a bump structure 300.

[0062] The first protection layer 180 can have a first opening 189. A width of the first opening 189 can be greater than a width of the first hole 169. For example, the width of the first opening 189 at a bottom surface of the first protection layer 180 can be greater than the width of the first hole 169 at a top surface 160a of the first redistribution pattern 160. Accordingly, the first opening 189 can expose the top surface 160a of the first redistribution pattern 160 and an inner sidewall 180c of the first protection layer 180. The inner sidewall 180c of the first protection layer 180 can not be aligned with the inner sidewall 160c of the first redistribution pattern 160. The first hole 169 and the first opening 189 can be formed by different processes.

[0063] The solder pattern 310 can fill the first hole 169 and can be in contact with the inner sidewall 160c of the first redistribution pattern 160. The solder pattern 310 can also be disposed in the first opening 189. The solder pattern 310 can extend onto the exposed top surface 160a of the first redistribution pattern 160 and onto the inner sidewall 180c of the first protection layer 180. Accordingly, a sidewall of the solder pattern 310 can have a stepped shape.

[0064] FIG. 2C is a view showing a semiconductor package according to an example embodiment of the present inventive concept. FIG. 2C is a cross-sectional view corresponding to FIG. 1A is a magnified view of the area "II" of FIG. 1C is a cross-sectional view corresponding to the line III-III' of

[0065] Referring to FIG. 2C , the semiconductor package can include a first semiconductor chip 100, a second semiconductor chip 200, and a bump structure 300. The first semiconductor chip 100 can include a first semiconductor substrate 110, a first through structure 140, a first upper insulating layer 170, a first redistribution pattern 160, and a first protection layer 180, and can further include a first lower redistribution pattern 163 and a first lower protection layer 183. The first semiconductor substrate 110, the first through structure 140, the first upper insulating layer 170, the first redistribution pattern 160, and the first protection layer 180 can be substantially the same as described with reference to FIGS. 1A-1D However, the first redistribution pattern 160 can not be in direct contact with the first through structure 140.

[0066] A first lower redistribution pattern 163 can be disposed between the top surface 110a of the first semiconductor substrate 110 and the first redistribution pattern 160. For example, the first lower redistribution pattern 163 can be disposed between the first upper insulating layer 170 and the first redistribution pattern 160. The first lower redistribution pattern 163 can be disposed on the first through-structure 140 and can be in contact with the first through-structure 140. The first lower redistribution pattern 163 can include substantially the same material as the material of the first redistribution pattern 160.

[0067] A first lower protective layer 183 can be disposed on the first lower redistribution pattern 163 and the first upper insulating layer 170 to cover the first lower redistribution pattern 163 and the first upper insulating layer 170. The first lower protective layer 183 can be an organic insulating layer. For example, the first lower protective layer 183 can include a photosensitive polymer or a photoimageable dielectric material. The first lower protective layer 183 can include the same material as the material of the first protective layer 180, and an interface between the first protective layer 180 and the first lower protective layer 183 can not be visible or obvious. However, embodiments of the inventive concept are not limited thereto.

[0068] A conductive pattern 165 can be disposed in the first lower protective layer 183 and can penetrate the first lower protective layer 183. The conductive pattern 165 can be disposed on the first lower redistribution pattern 163 and can be connected to the first lower redistribution pattern 163. The conductive pattern 165 can include, for example, a metal.

[0069] The first redistribution pattern 160 can be disposed on the first lower protective layer 183 and the conductive pattern 165. For example, the first redistribution pattern 160 can contact top surfaces of the first lower protective layer 183 and the conductive pattern 165. The first redistribution pattern 160 can be spaced apart from the first upper insulating layer 170. The first redistribution pattern 160 can be connected to the first through-structure 140 through the conductive pattern 165 and the first lower redistribution pattern 163. The first redistribution pattern 160 can have a first hole 169. The bump structure 300 can be disposed in the first hole 169, and the solder pattern 310 can be in contact with the inner sidewall 160c of the first redistribution pattern 160. The first lower redistribution pattern 163 can not have the first hole 169. The bump structure 300 can be spaced apart from the first lower redistribution pattern 163.

[0070] In certain embodiments, the first lower redistribution pattern 163 can include a plurality of stacked first lower redistribution patterns 163, and the first lower protective layer 183 can include a plurality of stacked first lower protective layers 183. In this case, the first lower protective layer 183 can be disposed between the first lower redistribution patterns 163.

[0071] FIG. 2Dis a view showing electrical connection of a bump structure and a first through structure according to some embodiments of the inventive concept. FIG. 2D is a magnified view of a region "II" corresponding to FIG. 1A , and is a cross-sectional view of a line III-III' corresponding to FIG. 1C . Hereinafter, the description of the same components and / or features as the above embodiments will be omitted for the purpose of brief and convenient explanation.

[0072] Referring to FIG. 2D , the semiconductor package can include a first semiconductor chip 100, a second semiconductor chip 200, and a bump structure 300. The first semiconductor chip 100 can include a first semiconductor substrate 110, a first through structure 140, a first upper insulating layer 170, a first redistribution pattern 160, and a first protective layer 180, and can further include a first lower redistribution pattern 163, a first lower protective layer 183, and a conductive pattern 165. The first through structure 140, the first redistribution pattern 160, the first protective layer 180, the first lower redistribution pattern 163, the first lower protective layer 183, and the conductive pattern 165 can be substantially the same as described with reference to FIG. 2C .

[0073] However, the first lower protective layer 183 can have a lower opening 188. The lower opening 188 can penetrate a top surface and a bottom surface of the first lower protective layer 183, and can be connected to the first hole 169 of the first redistribution pattern 169. The first lower redistribution pattern 163 can have a lower hole 168. The lower hole 168 can penetrate a top surface of the first lower redistribution pattern 163. The lower hole 168 can be connected to the first hole 169 and the first opening 189 through the lower opening 188.

[0074] The bump structure 300 can be disposed in the first opening 189, the first hole 169, the lower opening 188, and the lower hole 168. The solder pattern 310 can be in contact with an inner sidewall 163c of the first lower redistribution pattern 163 and an inner sidewall 160c of the first redistribution pattern 160. The solder pattern 310 can be electrically connected to the first through structure 140 through the first redistribution pattern 160 and the first lower redistribution pattern 163. The solder pattern 310 can further cover an inner sidewall of the first lower protective layer 183 and an inner sidewall of the first protective layer 180.

[0075] In the embodiments of FIGS. 2A-2D , the semiconductor package can further include at least one of a package substrate 900, a molding layer 400, a first underfill layer 410, and a bonding bump 350 as described in the embodiments of FIGS. 1A-1D . The first semiconductor chip 100 can further include a first circuit layer 120 and a first lower insulating pattern 130. FIGS. 1A-1D the embodiments of FIG. 2A , the embodiments ofFIG. 2B Implementation examples FIG. 2C Implementation examples and FIG. 2D The embodiments can be combined with each other. For example, in FIG. 2B and FIG. 2C In this configuration, the first hole 169 penetrates both the top and bottom surfaces of the first redistribution pattern 160. Alternatively, the first hole 169 may penetrate the top surface of the first redistribution pattern 160 but may not penetrate the bottom surface. In this case, the bottom surface of the first hole 169 may be located within the first redistribution pattern 160, and the bottom surface and sidewalls of the solder pattern 310 may contact the first redistribution pattern 160.

[0076] exist FIGS. 2A-2D In the semiconductor package, the height of the bump structure 300, the distance between the first semiconductor chip 100 and the second semiconductor chip 200, the thickness of the second bottom fill layer 420, and the horizontal height difference between the top surface of the first protective layer 180 and the bottom surface of the first hole 169 can satisfy the above requirements. FIGS. 1A-1D The conditions described in the embodiments.

[0077] FIG. 3 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor package according to the present invention. (Refer to...) FIG. 3 and FIG. 1D This embodiment is described in detail, and for the purposes of brevity and convenience, descriptions of the same components and / or features as those in the above embodiments will be omitted.

[0078] Reference FIG. 3 The semiconductor package may include a package substrate 900, a first semiconductor chip 100, a plurality of second semiconductor chips 200, and a plurality of bump structures 300. The semiconductor package may also include a plurality of external terminals 950, a molding layer 400, a first underfill layer 410, and a plurality of second underfill layers 420. The semiconductor package may be a three-dimensional (3D) stacked package.

[0079] The first semiconductor chip 100 may be mounted on the packaging substrate 900. The first semiconductor chip 100 may include a first semiconductor substrate 110, a first circuit layer 120, a first lower insulating pattern 130, a first through structure 140, a first redistribution pattern 160, and a first protective layer 180.

[0080] A plurality of second semiconductor chips 200 can be mounted on a top surface of the first semiconductor chip 100. The second semiconductor chips 200 can be spaced apart from each other in a lateral direction. In the present specification, the term "lateral direction" can mean "in a direction parallel to the top surface 110a of the first semiconductor substrate 110". A kind of the second semiconductor chip 200 can be different from a kind of the first semiconductor chip 100. For example, a size, a function, and / or a number of input / output (I / O) terminals of the second semiconductor chip 200 can be different from those of the first semiconductor chip 100. The I / O terminal can be a chip pad. In some embodiments, a width of each of the second semiconductor chips 200 can be smaller than a width of the first semiconductor chip 100. Each of the second semiconductor chips 200 can perform a function different from that of the first semiconductor chip 100. For example, the first semiconductor chip 100 can be a logic chip, and the second semiconductor chip 200 can be a memory chip. The memory chip can include a volatile memory chip such as a DRAM chip or an SRAM chip. Alternatively, the memory chip can include a non-volatile memory chip such as a NAND flash memory chip. Each of the second semiconductor chips 200 can include a second semiconductor substrate 210, a second circuit layer 220, and a second chip pad 250 as described in the embodiments of FIGS. 1A to 1C. FIGS. 1A-1D The second semiconductor chip 200 can further include a second underfill layer 420.

[0081] The bump structure 300 can be disposed between the first semiconductor chip 100 and the second semiconductor chip 200. Each of the second semiconductor chips 200 can be connected to the first semiconductor chip 100 and the package substrate 900 through the bump structure 300. Each of the bump structures 300 can include a solder pattern 310 and a pillar pattern 320. The solder pattern 310 can be disposed in the first hole 169 of the first redistribution pattern 160 and can be in contact with the inner sidewall 160c of the first redistribution pattern 160. Accordingly, the semiconductor package can be miniaturized, and thermal properties of the semiconductor package can be improved. A pitch P1 of the plurality of pillar patterns 320 can be smaller than a pitch P2 of the plurality of external terminals 950.

[0082] The second underfill layer 420 can be disposed in the second gap region between the first semiconductor chip 100 and the second semiconductor chip 200, respectively, to seal or surround the bump structure 300.

[0083] The molding layer 400 can cover sidewalls of the first semiconductor chip 100 and the second semiconductor chip 200, but can expose a top surface of the second semiconductor chip 200. Alternatively, the molding layer 400 can also cover the top surface of the second semiconductor chip 200.

[0084] The semiconductor package can further include a heat dissipation structure 700. The heat dissipation structure 700 can be disposed on a top surface of the second semiconductor chip 200 and a top surface of the molding layer 400. In some embodiments, the heat dissipation structure 700 can also extend onto sidewalls of the molding layer 400. The heat dissipation structure 700 can include a heat sink, a heat slug, or a thermal interface material (TIM) layer. The heat dissipation structure 700 can include, for example, a metal.

[0085] FIG. 4A is a cross-sectional view illustrating a semiconductor package according to an example embodiment of the inventive concept. FIG. 4B is FIG. 4A an enlarged view of a region "IV" of

[0086] Referring to FIG. 4A and FIG. 4B , the semiconductor package can include a package substrate 900, external terminals 950, an interposer substrate 800, interposer bumps 850, a chip stack 1000, a third semiconductor chip 500, and a molding layer 400. The package substrate 900 can be substantially the same as described with reference to FIGS. 1A-1D . A plurality of external terminals 950 can be disposed on a bottom surface of the package substrate 900.

[0087] The interposer substrate 800 can be disposed on the package substrate 900. The interposer substrate 800 can include metal pads 820 and metal interconnection lines 830. The metal pads 820 can be exposed at a top surface of the interposer substrate 800. The metal interconnection lines 830 can be disposed in the interposer substrate 800 and can be connected to the metal pads 820. In this specification, it can be understood that when a component is referred to as being electrically connected to the interposer substrate 800, it can be electrically connected to the metal interconnection lines 830. The metal pads 820 and the metal interconnection lines 830 can include a metal such as copper, aluminum, tungsten, and / or titanium. The interposer bumps 850 can be disposed between the package substrate 900 and the interposer substrate 800 and can be connected to the package substrate 900 and the interposer substrate 800. For example, the interposer bumps 850 can be connected to the substrate pads 920 and the metal interconnection lines 830. Each of the interposer bumps 850 can include a solder ball. The interposer bumps 850 can include a metal such as a solder material.

[0088] The chip stack 1000 can be mounted on a top surface of the built-in substrate 800. The chip stack 1000 can include a first semiconductor chip 100, a second semiconductor chip 200, and a plurality of bump structures 300. The first semiconductor chip 100 can be mounted on the top surface of the built-in substrate 800. The first semiconductor chip 100 can include a first semiconductor substrate 110, a first chip pad 150, a first circuit layer 120, a first through structure 140, a first redistribution pattern 160, and a first protection layer 180. The first semiconductor chip 100 can further include a first lower insulating pattern 130, as shown in FIG. 1B The bonding bump 350 can be disposed between the built-in substrate 800 and the first semiconductor chip 100. The bonding bump 350 can be disposed between the metal pad 820 and the first chip pad 150, and can be connected to the metal pad 820 and the first chip pad 150.

[0089] The second semiconductor chip 200 can be disposed on a top surface of the first semiconductor chip 100. The bump structure 300 can be disposed between the first semiconductor chip 100 and the second semiconductor chip 200. Each bump structure 300 can be substantially the same as the bump structure described above. For example, the solder pattern 310 can be disposed in the first hole 169, and can be in direct contact with the inner sidewall 160c of the first redistribution pattern 160, as shown in FIG. 4B Accordingly, a height of the chip stack 1000 can be reduced.

[0090] The second semiconductor chip 200 can include a plurality of stacked second semiconductor chips 200. A kind of the second semiconductor chip 200 can be different from a kind of the first semiconductor chip 100. For example, the first semiconductor chip 100 can be one of a logic chip, a buffer chip, and a system on chip (SOC), and the second semiconductor chip 200 can be another one of a logic chip, a memory chip, a buffer chip, and a system on chip (SOC). In this specification, the memory chip can include a high bandwidth memory (HBM) chip. For example, the first semiconductor chip 100 can be a logic chip, and the second semiconductor chip 200 can be an HBM chip.

[0091] Hereinafter, the second semiconductor chip 200 will be described in detail. Each second semiconductor chip 200 can include a second semiconductor substrate 210, a second circuit layer 220, and a second chip pad 250, as described in the embodiment of FIGS. 1A-1D Each second semiconductor chip 200 can further include a second through structure 240, a second redistribution pattern 260, a second upper insulating layer 270, and a second protection layer 280. The second through structure 240, the second upper insulating layer 270, the second redistribution pattern 260, and the second protection layer 280 can be substantially the same as the first through structure 140, the first upper insulating layer 170, the first redistribution pattern 160, and the first protection layer 180, respectively. FIGS. 1A-1DThe first through-structure 140, the first upper insulating layer 170, the first redistribution pattern 160, and the first protective layer 180 described in the embodiments of the first semiconductor chip 100 can be substantially the same. For example, a second upper insulating layer 270 can be disposed on a top surface of a second semiconductor substrate 210. The second upper insulating layer 270 can include a silicon-based insulating material. A second through-structure 240 can be disposed in the second semiconductor substrate 210. The second through-structure 240 can penetrate the second semiconductor substrate 210 and the second upper insulating layer 270. As shown in FIG. 2B, the second through-structure 240 can also penetrate an upper portion of the second insulating layer 221 of the second circuit layer 220, and can be connected to the second interconnection structure 225 of the second circuit layer 220. The second through-structure 240 can be electrically connected to at least one of the second chip pad 250 and the second integrated circuit 223 through the second interconnection structure 225. FIG. 4B

[0092] A second redistribution pattern 260 can be disposed on the top surface of the second semiconductor substrate 210, and can be connected to the second through-structure 240. For example, the second redistribution pattern 260 can cover the second upper insulating layer 270, and can be in contact with a top surface of the second through-structure 240. Each of the second redistribution patterns 260 can have a second hole 269. The second hole 269 can expose an inner sidewall 260c of the second redistribution pattern 260.

[0093] A second protective layer 280 can be disposed on the second redistribution pattern 260. The second protective layer 280 can have a second opening 289, and each of the second openings 289 can be connected to a corresponding one of the second holes 269. Unlike the first opening 189 of the first protective layer 180, FIG. 4B a width of a bottom end of the second opening 289 can be greater than a width of a top end of the second hole 269. In this case, the second opening 289 can expose a top surface of the second redistribution pattern 260 and an inner sidewall of the second protective layer 280. In this case, the inner sidewall of the second protective layer 280 can not be coplanar with the inner sidewall 260c of the second redistribution pattern 260. A horizontal height difference between a top surface of the second protective layer 280 and a bottom surface of the second hole 269 can be in a range of about 2 μm to about 10 μm.

[0094] Even though not shown in the drawings, the second semiconductor chip 200 can further include a second lower redistribution pattern and a second lower protective layer. The second lower redistribution pattern and the second lower protective layer can be substantially the same as the first lower redistribution pattern 163 and the first lower protective layer 183, respectively, described in the embodiments of the first semiconductor chip 100. FIG. 2C FIG. 2D

[0095] ​​​The uppermost second semiconductor chip 200 can not include the second through structure 240, the second redistribution pattern 260, and the second protective layer 280. Each second semiconductor chip 200 can further include a second lower insulating pattern 230, as FIG. 4B

[0096] Hereinafter, electrical connections between the plurality of second semiconductor chips 200 through the bump structure 300 will be described. Other bump structures 300 can be disposed between the second semiconductor chips 200. The second semiconductor chips 200 can include a lower semiconductor chip and an upper semiconductor chip adjacent to each other. Here, the upper semiconductor chip can be disposed on a top surface of the lower semiconductor chip. In the bump structure 300 between the lower semiconductor chip and the upper semiconductor chip, the solder pattern 310 can be disposed in the second hole 269 of the lower semiconductor chip and can be in contact with the inner side wall 260c of the corresponding second redistribution pattern 260. Accordingly, the thickness of the chip stack 1000 and the thickness of the semiconductor package can be reduced. For example, a distance A4 between the second semiconductor chips 200 can be less than a height A1 of the corresponding bump structure 300. The corresponding bump structure 300 can correspond to the bump structure 300 between the second semiconductor chips 200 adjacent to each other. The distance A4 between the second semiconductor chips 200 can be a distance between a top surface of the second protective layer 280 on the second redistribution pattern 260 of the lower semiconductor chip and a bottom surface of the second lower insulating pattern 230 of the upper semiconductor chip. The distance A4 between the second semiconductor chips 200 can be in a range of about 3 µm to about 20 µm. The height A1 of the bump structure 300 can be in a range of about 5 µm to about 30 µm.

[0097] A bottom surface of the solder pattern 310 can be in contact with the second upper insulating layer 270. In certain embodiments, a bottom surface of the second hole 269 can be disposed in the second redistribution pattern 260. In this case, the bottom surface of the solder pattern 310 can be connected to the second redistribution pattern 260. The solder pattern 310 can be connected to the second through structure 240 through the second redistribution pattern 260 of the lower semiconductor chip. The pillar pattern 320 can be connected to the second chip pad 250 of the upper semiconductor chip. Accordingly, the upper semiconductor chip and the lower semiconductor chip can be electrically connected to each other.

[0098] As FIG. 4A illustrated, a pitch P1 of the plurality of pillar patterns 320 can be less than a pitch P2 of the external terminal 950. The pitch P1 of the pillar pattern 320 can be less than a pitch P3 of the plurality of built-in bumps 850.

[0099] ​The semiconductor package can further include a first underfill layer 410, a second underfill layer 420, a third underfill layer 430, and a fourth underfill layer 440. The first underfill layer 410 and the second underfill layer 420 can be substantially the same as described with reference to FIGS. 1A-1D

[0100] The third underfill layer 430 can be disposed in a third gap region between the second semiconductor chips 200. For example, the third underfill layer 430 can be disposed between the second semiconductor chips 200 to seal or surround the corresponding bump structures 300. A distance between the second semiconductor chips can be substantially equal to a thickness of the corresponding third underfill layer 430. The thickness of the third underfill layer 430 can be less than the height Al of the corresponding bump structure 300. For example, the thickness of the third underfill layer 430 can be in a range of about 3 pm to about 20 pm. The thickness of the third underfill layer 430 can be equal to a distance between a bottom surface of the second lower insulating pattern 230 of the upper semiconductor chip and a top surface of the second protective layer 280 on the second redistribution pattern 260 of the lower semiconductor chip. The third underfill layer 430 can include an insulating polymer. For example, the third underfill layer 430 can include an epoxy-based polymer.

[0101] The third semiconductor chip 500 can be mounted on a top surface of the built-in substrate 800. The third semiconductor chip 500 can be laterally spaced apart from the chip stack 1000. The third semiconductor chip 500 can include a central processing unit (CPU) or a graphics processing unit (GPU). The connection bumps 360 can be disposed between chip pads of the third semiconductor chip 500 and the corresponding metal pads 820. Each of the connection bumps 360 can include at least one of a solder ball or a post. The connection bumps 360 can include a metal such as a solder material. The third semiconductor chip 500 can be electrically connected to the first semiconductor chip 100, the second semiconductor chip 200, and / or the external terminals 950 through the connection bumps 360 and the metal interconnection lines 830.

[0102] The fourth underfill layer 440 can be disposed in a fourth gap region between the built-in substrate 800 and the third semiconductor chip 500. The fourth underfill layer 440 can seal or surround the connection bumps 360. The fourth underfill layer 440 can include an epoxy-based polymer.

[0103] ​The molding layer 400 can cover sidewalls of the first semiconductor chip 100 and the second semiconductor chip 200 and a sidewall of the third semiconductor chip 500. The molding layer 400 can expose a top surface of the uppermost second semiconductor chip 200 and a top surface of the first semiconductor chip 100. Alternatively, the molding layer 400 can also cover the top surface of the uppermost second semiconductor chip 200 and / or a top surface of the third semiconductor chip 500. The molding layer 400 can include an epoxy-based polymer. In some embodiments, the molding layer 400 can include a material different from materials of the first underfill layer 410, the second underfill layer 420, the third underfill layer 430, and the fourth underfill layer 440.

[0104] The semiconductor package can further include a heat dissipation structure 700. The heat dissipation structure 700 can be disposed on a top surface of the uppermost second semiconductor chip 200, a top surface of the third semiconductor chip 500, and a top surface of the molding layer 400. In some embodiments, the heat dissipation structure 700 can also extend onto a sidewall of the molding layer 400.

[0105] In the semiconductor package of FIG. 3 and the semiconductor package of FIG. 4A and FIG. 4B In the semiconductor package of FIGS. 1A-1D described in the embodiments of the semiconductor package of FIGS. 1A-1D described in the embodiments of the semiconductor package of FIG. 2A described in the embodiments of the semiconductor package of FIG. 2B described in the embodiments of the semiconductor package of FIG. 2C or FIG. 2D described in the embodiments of the semiconductor package of

[0106] According to embodiments of the inventive concept, a bump structure can be disposed between a first semiconductor chip and a second semiconductor chip. The first semiconductor chip can include a first redistribution pattern having a first hole. The bump structure can be disposed in the first hole and can be in contact with an inner sidewall of the first redistribution pattern. A bottom surface of the bump structure can be disposed at a level lower than a top surface of the first redistribution pattern. Accordingly, a distance between the first semiconductor chip and the second semiconductor chip can be reduced, and a semiconductor package can be miniaturized.

[0107] Since the bump structures are disposed in the first holes, electrical shorting between the bump structures can be inhibited or prevented. The thickness of the underfill layer between the first semiconductor chip and the second semiconductor chip can be reduced, and thus heat dissipation properties of the semiconductor package can be improved.

[0108] While the inventive concept has been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the inventive concept. It is therefore intended that the foregoing description be regarded as illustrative rather than limiting, and that it be understood that all changes and modifications are intended to be included within the scope of the inventive concept. The scope of the inventive concept is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and should not be limited or confined by the foregoing description.

Claims

1. A semiconductor package, the semiconductor package comprising: A first semiconductor chip, the first semiconductor chip including a semiconductor substrate and a redistribution pattern on the top surface of the semiconductor substrate, the redistribution pattern having holes exposing the inner sidewalls of the redistribution pattern; A second semiconductor chip, located on the top surface of the first semiconductor chip; and A bump structure is disposed between the first semiconductor chip and the second semiconductor chip. The bump structure is disposed in the hole and contacts the inner sidewall of the redistribution pattern. The first semiconductor chip further includes a protective layer located on the top surface of the redistribution pattern; The bump structure includes: a solder pattern that fills the hole and directly contacts the inner sidewall of the redistribution pattern; and a pillar pattern disposed between the solder pattern and the chip pad of the second semiconductor chip. The horizontal height of the bottom surface of the column pattern is between the horizontal height of the top surface of the protective layer and the horizontal height of the top surface of the redistribution pattern.

2. The semiconductor package according to claim 1, in, The first semiconductor chip further includes a through-structure located in the semiconductor substrate, and The redistribution pattern is electrically connected to the through structure.

3. The semiconductor package according to claim 2, wherein, When viewed from above, the bump structure is spaced apart from the through structure.

4. The semiconductor package according to claim 1, wherein, The distance between the first semiconductor chip and the second semiconductor chip is less than the height of the bump structure.

5. The semiconductor package according to claim 4, in, The distance between the first semiconductor chip and the second semiconductor chip is in the range of 3μm to 20μm, and The height of the bump structure is in the range of 5 μm to 30 μm.

6. The semiconductor package according to claim 1, further comprising: A bottom filler layer is disposed in the gap region between the first semiconductor chip and the second semiconductor chip, and covers the bump structure; The thickness of the bottom filling layer is less than the height of the bump structure.

7. The semiconductor package according to claim 6, wherein, The thermal conductivity of the bottom filling layer is lower than that of the bump structure.

8. The semiconductor package according to claim 6, wherein, The thickness of the bottom filler layer is in the range of 3 μm to 20 μm.

9. A semiconductor package, the semiconductor package comprising: A first semiconductor chip, the first semiconductor chip including a semiconductor substrate and a redistribution pattern disposed on the top surface of the semiconductor substrate, the redistribution pattern having holes; A second semiconductor chip, located on the top surface of the first semiconductor chip; Solder pattern, the solder pattern being disposed in the hole to contact the inner sidewall of the redistribution pattern; and A column pattern is disposed between the solder pattern and the second semiconductor chip. The first semiconductor chip further includes a protective layer located on the top surface of the redistribution pattern. The horizontal height of the bottom surface of the column pattern is between the horizontal height of the top surface of the protective layer and the horizontal height of the top surface of the redistribution pattern.

10. The semiconductor package according to claim 9, in, The first semiconductor chip further includes a through-structure penetrating the semiconductor substrate, and The solder pattern is electrically connected to the through-structure via the redistribution pattern.

11. The semiconductor package according to claim 9, in, The bottom surface of the hole is disposed in the redistribution pattern, and The bottom surface and sidewalls of the solder pattern are in contact with the redistribution pattern.

12. The semiconductor package of claim 9, further comprising: An upper insulating layer is disposed between the redistribution pattern and the top surface of the semiconductor substrate. The hole exposes the upper insulating layer, and The solder pattern is in contact with the upper insulating layer.

13. The semiconductor package of claim 9, further comprising: A lower redistribution pattern is disposed between the semiconductor substrate and the redistribution pattern; and A lower protective layer is disposed between the lower redistribution pattern and the redistribution pattern.

14. The semiconductor package according to claim 9, in, The protective layer has an opening. The opening is connected to the hole and exposes the inner wall of the protective layer. The solder pattern covers the inner sidewall of the protective layer.

15. The semiconductor package of claim 14, wherein, The protective layer comprises a photosensitive polymer.

16. The semiconductor package of claim 9, further comprising: A packaging substrate, on the top surface of which the first semiconductor chip is mounted. The first semiconductor chip further includes a first integrated circuit. The second semiconductor chip includes a second integrated circuit, and The column pattern includes a material different from the material of the solder pattern.

17. A semiconductor package, the semiconductor package comprising: Packaging substrate; A first semiconductor chip, wherein the first semiconductor chip is mounted on the packaging substrate; A second semiconductor chip is disposed on the top surface of the first semiconductor chip; and A bump structure is disposed between the first semiconductor chip and the second semiconductor chip. The first semiconductor chip includes: First semiconductor substrate; A first circuit layer is disposed on the bottom surface of the first semiconductor substrate and includes a first integrated circuit. A first through-hole structure is disposed in the first semiconductor substrate; A first redistribution pattern is disposed on the top surface of the first semiconductor substrate and connected to the first through structure; A first protective layer, the first protective layer being located on the top surface of the first redistribution pattern; and An upper insulating layer is located between the first semiconductor substrate and the first redistribution pattern. The second semiconductor chip includes: Second semiconductor substrate; A second circuit layer, disposed on the bottom surface of the second semiconductor substrate, and including a second integrated circuit; and Chip pads are disposed on the bottom surface of the second circuit layer and are electrically connected to the second integrated circuit; Wherein, the first redistribution pattern has a hole exposing the inner sidewall of the first redistribution pattern, and The bump structure includes: A solder pattern disposed in the hole to contact the inner sidewall of the first redistribution pattern; and A pillar pattern, wherein the pillar pattern is located between the solder pattern and the chip pads of the second semiconductor chip. The horizontal height of the bottom surface of the column pattern is between the horizontal height of the top surface of the first protective layer and the horizontal height of the top surface of the first redistribution pattern.

18. The semiconductor package of claim 17, further comprising: A bottom filler layer is disposed between the first semiconductor chip and the second semiconductor chip, and covers the sidewalls of the bump structure. Wherein, the thickness of the bottom filler layer is less than the distance between the bottom surface of the solder pattern and the top surface of the column pattern, and The thermal conductivity of the bottom filler layer is less than that of the solder pattern and the column pattern.

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