Quad Flat No-Lead Package Structure

Abstract

The present invention discloses a quad flat no-lead (QFN) package structure, comprising a lead frame, a semiconductor die, and an encapsulation material. The lead frame comprises a die pad and a plurality of contacts surrounding the die pad. The semiconductor die is positioned on the die pad and electrically connected to the plurality of contacts, wherein the shortest distance between the semiconductor die and a first side of the die pad is shorter than the shortest distance between the semiconductor die and a second side of the die pad, and the first side is opposite to the second side. The encapsulation material encapsulates the lead frame and the semiconductor die and partially exposes the plurality of contacts, wherein the aspect ratio of the QFN package is substantially equal to or greater than 3.

Description

Technical Field

[0001] The present invention relates to a package structure, and more particularly to a quad flat no-lead package structure. Background Art

[0002] The semiconductor industry is experiencing rapid growth due to the continued increase in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). Primarily, this increase in integration density comes from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. With the recent growth in demand for ever-smaller electronic devices, there has been a need for smaller and more innovative packaging technologies for semiconductor dies.

[0003] As the demand for smaller electronic products increases, the electronics industry must continue to develop higher density electronic packaging. Various technologies have been developed to meet the demand for higher quality and improved reliability, and various chip scale package (CSP) technologies have been developed for high density packaging.

[0004] Quad flat no-lead (QFN) packages are one of these CSP technologies. Based on lead frames and used for low pin count devices, the main feature of the QFN package is that it does not consist of external leads, thus shortening the transmission distance and reducing resistance to improve signal transmission.

[0005] Package warpage can occur due to mismatches in the coefficients of thermal expansion (CTE) of different package materials. Uncontrolled, this warpage can damage the QFN package and reduce semiconductor manufacturing yields. There is a need in the art for structures and manufacturing methods for QFN packages with reduced warpage. Summary of the Invention

[0006] Therefore, the present invention is directed to a quad flat no-lead package structure with reduced warpage.

[0007] The present invention provides a quad flat no-lead (QFN) package structure, comprising a lead frame, a semiconductor die, and an encapsulation material. The lead frame includes a die pad and a plurality of contacts surrounding the die pad. The semiconductor die is positioned on the die pad and electrically connected to the plurality of contacts, wherein the shortest distance between the semiconductor die and a first side of the die pad is shorter than the shortest distance between the semiconductor die and a second side of the die pad, and the first side is opposite to the second side. The encapsulation material encapsulates the lead frame and the semiconductor die and partially exposes the plurality of contacts, wherein the aspect ratio of the QFN package structure is substantially equal to or greater than 3.

[0008] According to an embodiment of the present invention, the QFN package structure further includes a plurality of conductive lines connected between the semiconductor die and the plurality of contacts.

[0009] According to an embodiment of the present invention, the multiple contacts include a plurality of first contacts closer to the first side and a plurality of second contacts closer to the second side, and the multiple conductive wires include a plurality of first conductive wires connected between the semiconductor die and the plurality of first contacts, and a plurality of second conductive wires connected between the semiconductor die and the plurality of second contacts.

[0010] According to an embodiment of the present invention, each of the plurality of first conductive lines is substantially equal to or shorter than each of the plurality of second conductive lines.

[0011] According to an embodiment of the present invention, each of the plurality of first conductive lines is substantially equal to or shorter than 1000 micrometers.

[0012] According to an embodiment of the present invention, the QFN package structure further includes a ground ring surrounding the periphery of the die pad, and a plurality of ground lines connected between the semiconductor die and the ground ring.

[0013] According to an embodiment of the present invention, the plurality of ground lines include a plurality of first ground lines connected between the semiconductor die and a portion of the ground ring on a first side, and a plurality of second ground lines connected between the semiconductor die and another portion of the ground ring on a second side.

[0014] According to an embodiment of the present invention, each of the plurality of first ground lines is shorter than each of the plurality of second ground lines.

[0015] According to an embodiment of the present invention, the QFN package structure further includes a warpage control metal layer disposed above the encapsulation material.

[0016] According to an embodiment of the present invention, a difference between a coefficient of thermal expansion (CTE) of the warpage control metal layer and a CTE of the lead frame is substantially equal to or less than 10%.

[0017] According to an embodiment of the present invention, the warpage control metal layer and the lead frame are located on two opposite sides of the encapsulation material.

[0018] According to an embodiment of the present invention, the QFN package structure further includes a solder resist layer disposed between the warpage control metal layer and the encapsulation material.

[0019] According to an embodiment of the present invention, the lead frame further includes a plurality of tie bars connected to the die pad and extending outwardly to an outer edge of the encapsulation material.

[0020] According to an embodiment of the present invention, at least one of the connecting bars is connected to the first side or the second side of the die pad.

[0021] According to an embodiment of the present invention, the die pad further includes a plurality of recesses disposed on the standoff areas in which the semiconductor die is not disposed.

[0022] According to an embodiment of the invention, a plurality of recesses are disposed along the second side.

[0023] According to an embodiment of the present invention, the thickness of the semiconductor die is substantially equal to or greater than 10 mils.

[0024] According to an embodiment of the present invention, the maximum thickness of the lead frame is substantially equal to or greater than 8 mils.

[0025] According to an embodiment of the present invention, the thickness of the encapsulation material is substantially equal to or greater than 0.6 mm.

[0026] According to an embodiment of the present invention, the QFN package structure further includes a die attach film disposed between the semiconductor die and the die pad.

[0027] The present invention provides a QFN package structure comprising a lead frame, a semiconductor die, an encapsulation material, and a warpage control metal layer. The lead frame comprises a die pad and a plurality of contacts surrounding the die pad. The semiconductor die is positioned on the die pad and electrically connected to the plurality of contacts. The encapsulation material encapsulates the lead frame and the semiconductor die and partially exposes the plurality of contacts. The QFN package structure has an aspect ratio substantially equal to or greater than 3. The warpage control metal layer is positioned above the encapsulation material.

[0028] According to an embodiment of the present invention, a difference between a CTE of the warpage control metal layer and a CTE of the lead frame is substantially equal to or less than 10%.

[0029] According to an embodiment of the present invention, the warpage control metal layer and the lead frame are located on two opposite sides of the encapsulation material.

[0030] According to an embodiment of the present invention, the QFN package structure further includes a solder resist layer disposed between the warpage control metal layer and the encapsulation material.

[0031] According to an embodiment of the present invention, a shortest distance between the semiconductor die and a first side of the die pad is shorter than a shortest distance between the semiconductor die and a second side of the die pad, and the first side is opposite to the second side.

[0032] Based on the above, the QFN package structure is designed to have a higher aspect ratio (approximately equal to or greater than 3) to achieve better space utilization. In addition, for QFN package structures with higher aspect ratios, the QFN package structure suffers from more severe warpage. Therefore, the QFN package structure may also include a warpage control metal layer disposed above the encapsulation material, and the difference between the CTE of the warpage control metal layer and the CTE of the lead frame is generally equal to or less than 10%. Therefore, the warpage control metal layer not only helps the QFN package structure dissipate heat, but also provides support and mechanical strength to the QFN package structure, and reduces warpage of the QFN package structure.

[0033] In order to better understand the foregoing, several embodiments are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0035] Figure 1 Schematic top view of a QFN package structure according to some embodiments of the present invention;

[0036] Figure 2 is a schematic cross-sectional view of a QFN package structure according to some embodiments of the present invention;

[0037] Figure 3 is a schematic top view of a QFN package structure according to another embodiment of the present invention;

[0038] Figure 4 FIG. 4 is a schematic top view of a QFN package structure according to yet another embodiment of the present invention.

[0039] Explanation of Figure Numbers

[0040] 100, 100a, 100b: quad flat no-lead package structure;

[0041] 110: lead frame;

[0042] 112: die pad;

[0043] 114: contact;

[0044] 114a: first contact;

[0045] 114b: second contact;

[0046] 116: connecting rod;

[0047] 120: semiconductor die;

[0048] 122: active surface;

[0049] 124: dorsal surface;

[0050] 126: bonding pad;

[0051] 130: encapsulating material;

[0052] 140: conductive thread;

[0053] 142: first conductive line;

[0054] 144: second conductive line;

[0055] 150: ground wire;

[0056] 152: first grounding wire;

[0057] 154: Second grounding wire;

[0058] 160: warpage control metal layer;

[0059] 162: solder mask;

[0060] 164: barrier layer;

[0061] 170: die attach film;

[0062] 1121: grounding ring;

[0063] 1122: Depression;

[0064] 1161, 1162: connecting rod;

[0065] D1, D2: shortest distance;

[0066] S1: first side;

[0067] S2: Second side. DETAILED DESCRIPTION

[0068] The present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are illustrated. As used herein, terms such as "on," "above," "below," "in front of," "behind," "to the left of," and "to the right of" are for the purpose of describing directions in the drawings only and are not intended to limit the present invention. Reference will now be made in detail to preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Furthermore, in the following embodiments, identical or similar reference numerals denote identical or similar components.

[0069] Figure 1 A schematic top view of a QFN package structure according to some embodiments of the present invention is shown. Figure 2 A schematic cross-sectional view of a QFN package structure according to some embodiments of the present invention is shown. A package configuration known as a quad flat no-lead (QFN) package is similar to a QFP, however, the corresponding contacts (leads) do not extend outside the QFN package. By hiding the leads and adhering tightly to the circuit board during bonding, the QFN package meets the demands of modern electrical components, particularly those used in mobile electronic devices such as smartphones, tablet PCs, and laptops, for a lightweight, thin, simple, and compact configuration.

[0070] refer to Figure 1 In some embodiments, a quad flat no-lead (QFN) package structure 100 may include a lead frame 110, a semiconductor die 120, and an encapsulation material 130. In some embodiments, the lead frame 110 includes a die pad 112 and a plurality of contacts 114 surrounding the die pad 112. The lead frame 110 has an upper surface and a lower surface opposite the upper surface. It should be noted that the designation of the upper surface and the lower surface is merely for convenience of description and does not represent the physical orientation of the lead frame 110. In some embodiments, the contacts 114 of the lead frame 110 may be a plurality of leads disposed around the die pad 112. Methods and manufacturing tools known in the art may be used to form the lead frame 110, and materials known in the art may be used to form the lead frame 110. In some embodiments, copper (Cu), copper alloy materials, and a wide range of metal and metal alloy materials may be used to fabricate the lead frame 110 to suit a particular application. The lead frame 110 may be made of any suitable material used in semiconductor chip packaging. Of course, specific materials may be used for certain packages for specific purposes.

[0071] In some embodiments, semiconductor die 120 has an active surface 122, a back surface 124 opposite active surface 122, and a plurality of bonding pads 126 formed on active surface 122 of semiconductor die 120. In some embodiments, semiconductor die 120 is placed on die pad 112 and electrically connected to contacts 114 of lead frame 110. In one embodiment, back surface 124 of semiconductor die 120 is adhered to an upper surface of die pad 112. QFN package structure 100 may further include a plurality of conductive wires 140 connected between semiconductor die 120 and contacts (leads) 114. More specifically, conductive wires 140 electrically connect bonding pads 126 of semiconductor die 120 to contacts 114 of lead frame 110. That is, semiconductor die 120 is placed and bonded to contacts 114 of lead frame 110 using wire bonding technology. In some embodiments, encapsulation material 130 encapsulates a portion of lead frame 110 and semiconductor die 120. In one embodiment, encapsulation material 130 encapsulates semiconductor die 120, conductive wires 140, an upper surface of die pad 112, and an upper surface 114 of contacts 114. In some embodiments, a lower surface of die pad 112 and a lower surface of contacts 114 are at least partially exposed by encapsulation material 130 for further connection.

[0072] In some embodiments, for better space (layout) utilization, the aspect ratio of the QFN package structure 100 is designed to be a rectangular package. That is, the QFN package structure 100 is designed to have a higher aspect ratio (larger length-to-width ratio). For example, the aspect ratio of the QFN package structure 100 can be approximately equal to or greater than 2.3. In an embodiment of the present invention, the aspect ratio of the QFN package structure 100 is generally equal to or greater than 3. Under the conditions of having the same number of pins (leads) and pin pitch, the package size (occupied area) of the QFN package structure 100 with a higher aspect ratio can be reduced by up to approximately 25% compared to a conventional square QFN package. In addition, by utilizing the configuration of the QFN package structure 100 with a higher aspect ratio, the number of QFN packages that can be produced from each leadframe strip is increased. Therefore, the productivity of the QFN package structure 100 can be improved, and on the other hand, the production cost of the QFN package structure 100 can be reduced.

[0073] According to some embodiments of the present invention, the die pad 112 may have a first side S1 and a second side S2 that are opposite to each other. In embodiments of the QFN package structure 100 having a rectangular shape (i.e., having a high aspect ratio), the die pad 112 is correspondingly rectangular. In embodiments of the present invention, the first side S1 and the second side S2 are the two long sides of the die pad 112. In some embodiments, the shortest distance D1 between the semiconductor die 120 and the first side S1 of the die pad 112 is shorter than the shortest distance D2 between the semiconductor die 120 and the second side S2 of the die pad 112. In other words, the semiconductor die 120 is positioned asymmetrically on the die pad 112. That is, the semiconductor die 120 is offset (deviated) from the central long axis of the die pad 112.

[0074] Thus, contacts 114 may include a plurality of first contacts 114a and a plurality of second contacts 114b. First contacts 114a are closer to first side S1, while second contacts 114b are closer to second side S2. Similarly, conductive lines 140 include a plurality of first conductive lines 142 and a plurality of second conductive lines 144, wherein first conductive lines 142 are connected between semiconductor die 120 and the plurality of first contacts 114a, and second conductive lines 144 are connected between semiconductor die 120 and the second contacts 114b. Thus, each of first conductive lines 142 is substantially equal to or shorter than each of second conductive lines 144 to reduce the impedance of first conductive lines 142. For example, each of first conductive lines 142 is substantially equal to or shorter than 1000 microns. For embodiments of the semiconductor die 120 serving as a driver IC for a display (e.g., a mini-LED or micro-LED), components with higher sensitivity to impedance (e.g., switches or MOS) may be positioned on a side of the semiconductor die 120 closer to the first side S1 so that the impedance can be reduced and the electrical performance of the semiconductor die 120 can be significantly improved.

[0075] In some embodiments, QFN package structure 100 may further include a ground ring 1121 surrounding the periphery of die pad 112, and a plurality of ground lines 150 connected between semiconductor die 120 and ground ring 1121. Thus, the ground pad of semiconductor die 120 is connected to ground ring 1121 via ground lines 150. In some embodiments, ground ring 1121 may be a silver ring plated on die pad 112. In embodiments where semiconductor die 120 is offset toward first side S1 of die pad 112, ground lines 150 include a plurality of first ground lines 152 and a plurality of second ground lines 154. First ground lines 152 connect between semiconductor die 120 and a portion of ground ring 1121 on first side S1, and second ground lines 154 connect between semiconductor die 120 and another portion of ground ring 1121 on second side S2. Therefore, each of first ground lines 152 is shorter than each of second ground lines 154 to reduce the impedance of first ground lines 152. For example, each of the first ground lines 152 is substantially equal to or shorter than 600 micrometers.

[0076] In embodiments of the QFN package structure 100 having a higher aspect ratio, the QFN package structure 100 may be subject to more severe warpage. Therefore, the QFN package structure 100 may further include a warpage control metal layer 160 disposed above the encapsulation material 130. In some embodiments, the warpage control metal layer 160 may serve as a heat sink. Thus, the warpage control metal layer 160 not only helps dissipate heat from the QFN package structure 100 but also provides support and mechanical strength to the QFN package structure 100. In some embodiments, the warpage control metal layer 160 and the leadframe 110 are located on opposite sides of the encapsulation material 130, and the difference between the coefficient of thermal expansion (CTE) of the warpage control metal layer 160 and the CTE of the leadframe 110 is substantially equal to or less than 10%. In other words, the encapsulation material 130 is disposed between the leadframe 110 and the warpage control metal layer 160, which have similar CTEs. Furthermore, since the CTE of the warpage control metal layer 160 is similar to the CTE of the lead frame 110 , the problems of thermal stress and warpage caused by the CTS mismatch between the lead frame 110 and the encapsulation material 130 can be further improved.

[0077] In some embodiments, a barrier layer 164, such as a nickel / chromium layer, may be disposed (deposited) over the warpage control metal layer 160 to prevent oxidation of the warpage control metal layer (e.g., copper layer) 160. The warpage control metal layer 160 may be bonded to the encapsulation material 130 during a molding process via thermal compression (lamination). In some embodiments, a solder resist layer 162 may be disposed between the encapsulation material 130 and the warpage control metal layer 160 to enhance the bond between the encapsulation material 130 and the warpage control metal layer 160. The configuration of the warpage control metal layer 160 reduces the thermal resistance of the QFN package structure 100 by approximately 10% or more.

[0078] In some embodiments, the lead frame 110 further includes a plurality of tie bars 116 that are connected to the die pad 112 and extend outwardly to the outer edge of the encapsulation material 130. Generally, the tie bars 116 protrude outside the encapsulation material 130 during the molding process to connect the die pad 112 to, for example, a lead frame strip. After the molding process, the protruding portions of the tie bars 116 are removed by, for example, a cutting or singulation process. In some embodiments, the tie bars 116 may have the shape of lead fingers and may be produced, for example, from a foil, or in the form of separately molded components. In some embodiments, the tie bars 116 may be positioned at the corners of the die pad 112 that extend outwardly to the outer edge of the encapsulation material 130, such as in Figure 1 shown in.

[0079] According to some embodiments of the present invention, for QFN package structures that experience more severe warpage (such as QFN package structures with higher aspect ratios), a portion of the component can be adjusted to reduce the warpage of the package. For example, the thickness T1 of the semiconductor die 120 is substantially equal to or greater than 10 mils, the maximum thickness T2 of the lead frame 110 is substantially equal to or greater than 8 mils, and the thickness T3 of the encapsulation material 130 is substantially equal to or greater than 0.6 mm. However, the reference numbers shown above are for illustrative purposes only. The present invention is not limited to this. In some embodiments, the semiconductor die 120 can be attached to the die pad 112 via a die attach film 170 rather than conventional silver paste to further reduce the warpage of the QFN package structure 100a. That is, the QFN package structure 100a may further include a die attach film 170 disposed between the semiconductor die 120 and the die pad 112.

[0080] Figure 3 FIG. 1 is a schematic top view of a QFN package structure according to another embodiment of the present invention. Figure 3 The QFN package structure 100a in the embodiment contains the same Figure 1 and Figure 2The disclosed QFN package structure 100 has many features that are the same or similar. For the purpose of clarity and simplicity, detailed descriptions of the same or similar features may be omitted, and the same or similar reference numerals represent the same or similar components. Figure 3 The QFN package structure 100a is shown in FIG. Figure 1 and Figure 2 The main differences between the QFN package structures 100 in FIG. 1 and FIG. 2 are described as follows.

[0081] refer to Figure 3 In some embodiments, for QFN package structures subject to more severe warpage (e.g., QFN package structures with a higher aspect ratio), a portion of the connecting bars 116 disposed at the corners of the die pad 112, or at least one of the connecting bars 116, may be connected to the first side S1 or the second side S2 of the die pad 112. For example, the connecting bars 116 may include a plurality of connecting bars 1161 disposed at the corners of the die pad 112, and at least one connecting bar 1162 disposed at (connected to) the first side S1 or the second side S2 of the die pad 112. In an embodiment of the present invention, the connecting bars 116 include a plurality of connecting bars 1162 disposed at both the first side S1 and the second side S2 of the die pad 112. That is, for QFN package structures with a higher aspect ratio, some of the connecting bars 116 may be disposed at the long sides S1 and S2 of the die pad 112 to provide mechanical strength and thereby reduce warpage.

[0082] Figure 4 FIG. 1 is a schematic top view of a QFN package structure according to another embodiment of the present invention. Figure 4 The QFN package structure 100b in FIG. 1 contains many features that are the same or similar to the QFN package structure 100 and the QFN package structure 100a disclosed in the previous embodiment. For the purpose of clarity and simplicity, detailed descriptions of the same or similar features may be omitted, and the same or similar reference numerals represent the same or similar components. Figure 4 The main differences between the QFN package structure 100 b and the QFN package structures 100 and 100 a disclosed in the previous embodiments are described as follows.

[0083] refer to Figure 4In some embodiments, the die pad 112 may further include a plurality of recesses 1122 disposed in the void area where the semiconductor die 120 is not disposed. For example, in an embodiment where the semiconductor die 120 is displaced (offset) toward the first side S1 of the die pad 112, the recesses 1122 may be disposed along the second side S2 of the die pad 112. The recesses 1122 are recessed portions that are recessed toward the lower surface of the die pad 112, and the encapsulation material 130 fills the recesses 1122 when encapsulating the QFN package structure 100b. As such, the configuration of the recesses 1122 increases the contact area between the encapsulation material 130 and the die pad 112, thereby improving the bonding strength between the encapsulation material 130 and the lead frame 110. Consequently, delamination between the encapsulation material 130 and the lead frame 110 is reduced, and the reliability of the QFN package structure is improved.

[0084] In summary, the QFN package structure is designed to have a higher aspect ratio (approximately equal to or greater than 3) for better space (layout) utilization. In addition, the semiconductor die is offset (shifted) toward the long side of the die pad to shorten the conductive lines on the long side, thereby reducing impedance and significantly improving the electrical performance of the semiconductor die.

[0085] Furthermore, for QFN packages with higher aspect ratios, these packages may experience more severe warpage. Therefore, the QFN package structure may further include a warpage control metal layer disposed above the encapsulation material, with the difference between the CTE of the warpage control metal layer and the CTE of the leadframe being substantially equal to or less than 10%. Thus, the warpage control metal layer not only helps dissipate heat from the QFN package structure but also provides support and mechanical strength to the QFN package structure, thereby reducing warpage of the QFN package structure.

[0086] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A quad flat no-lead (QFN) package structure, comprising: a lead frame comprising a die pad and a plurality of contacts surrounding the die pad; a semiconductor die disposed on the die pad and electrically connected to the plurality of contacts, wherein a shortest distance between the semiconductor die and a first side of the die pad is shorter than a shortest distance between the semiconductor die and a second side of the die pad, and the first side is opposite the second side; an encapsulation material encapsulating the lead frame and the semiconductor die and partially exposing the plurality of contacts, wherein an aspect ratio of the quad flat no-lead package structure is equal to or greater than 3; as well as A warpage control metal layer is disposed above the encapsulation material. 2 . The quad flat no-lead package structure of claim 1 , further comprising a plurality of conductive lines connected between the semiconductor die and the plurality of contacts.

3. The quad flat no-lead package structure according to claim 2, wherein the plurality of contacts include a plurality of first contacts closer to the first side and a plurality of second contacts closer to the second side, and the plurality of conductive lines include a plurality of first conductive lines connected between the semiconductor die and the plurality of first contacts, and a plurality of second conductive lines connected between the semiconductor die and the plurality of second contacts. 4 . The quad flat no-lead package structure according to claim 3 , wherein each of the plurality of first conductive lines is equal to or shorter than each of the plurality of second conductive lines. 5 . The quad flat no-lead package structure according to claim 3 , wherein each of the plurality of first conductive lines is equal to or shorter than 1000 μm. 6 . The quad flat no-lead package structure according to claim 1 , further comprising a ground ring surrounding a periphery of the die pad, and a plurality of ground lines connected between the semiconductor die and the ground ring.

7. The quad flat no-lead package structure according to claim 6, wherein the plurality of ground lines include a plurality of first ground lines connected between the semiconductor die and a portion of the ground ring on the first side, and a plurality of second ground lines connected between the semiconductor die and another portion of the ground ring on the second side. 8 . The quad flat no-lead package structure according to claim 7 , wherein each of the plurality of first ground lines is shorter than each of the plurality of second ground lines. 9 . The quad flat no-lead package structure of claim 1 , wherein a difference between a coefficient of thermal expansion (CTE) of the warpage control metal layer and a CTE of the lead frame is equal to or less than 10%. 10 . The quad flat no-lead package structure of claim 1 , wherein the warpage control metal layer and the lead frame are located on two opposite sides of the encapsulation material. 11 . The quad flat no-lead package structure of claim 1 , further comprising a solder resist layer disposed between the warpage control metal layer and the encapsulation material. 12 . The quad flat no-lead package structure of claim 1 , wherein the lead frame further comprises a plurality of tie bars connected to the die pad and extending outwardly to an outer edge of the encapsulation material. 13 . The quad flat no-lead package structure of claim 12 , wherein at least one of the tie bars is connected to the first side or the second side of the die pad. 14 . The quad flat no-lead package structure according to claim 1 , wherein the die pad further comprises a plurality of recesses disposed on a vacant area in which the semiconductor die is not disposed. 15 . The quad flat no-lead package structure of claim 14 , wherein the plurality of recesses are disposed along the second side. 16 . The quad flat no-lead package structure of claim 1 , wherein the semiconductor die has a thickness equal to or greater than 10 mils. 17 . The quad flat no-lead package structure of claim 1 , wherein a maximum thickness of the lead frame is equal to or greater than 8 mils. 18 . The quad flat no-lead package structure according to claim 1 , wherein a thickness of the encapsulation material is equal to or greater than 0.6 mm. 19 . The quad flat no-lead package structure of claim 1 , further comprising a die attach film disposed between the semiconductor die and the die pad.

20. A quad flat no-lead (QFN) package structure, comprising: a lead frame comprising a die pad and a plurality of contacts surrounding the die pad; a semiconductor die disposed on the die pad and electrically connected to the plurality of contacts; as well as an encapsulation material encapsulating the lead frame and the semiconductor die and partially exposing the plurality of contacts, wherein an aspect ratio of the quad flat no-lead package structure is equal to or greater than 3; as well as A warpage control metal layer is disposed above the encapsulation material. 21 . The quad flat no-lead package structure of claim 20 , wherein a difference between a thermal expansion coefficient of the warpage control metal layer and a thermal expansion coefficient of the lead frame is equal to or less than 10%. 22 . The quad flat no-lead package structure of claim 20 , wherein the warpage control metal layer and the lead frame are located on two opposite sides of the encapsulation material. 23 . The quad flat no-lead package structure of claim 20 , further comprising a solder resist layer disposed between the warpage control metal layer and the encapsulation material.

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