Method of manufacturing three-dimensional memory

Abstract

The present disclosure provides a method of manufacturing a three-dimensional memory, comprising: providing a semiconductor structure; the semiconductor structure comprising: a substrate, a stack structure, an isolation layer between the stack structure and the substrate, a gate line gap structure and a memory pillar extending through the stack structure and the isolation layer and into the substrate; removing the substrate to expose a first end portion of the gate line gap structure and a second end portion of the memory pillar; the memory pillar comprising: a channel layer, and a functional layer surrounding the channel layer; removing the first end portion to form a first recess concave from the isolation layer toward the stack structure, leaving the remaining end portion of the gate line gap structure in contact with the isolation layer; removing the exposed functional layer of the second end portion to form a second recess concave from the isolation layer toward the stack structure, leaving the remaining end portion of the memory pillar in contact with the isolation layer; covering the first recess, the second recess and the exposed isolation layer with a conductive material, and performing particle implantation on the conductive material to form a second conductive layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and particularly to a manufacturing method of a three-dimensional memory. BACKGROUND

[0002] With the continuous improvement of semiconductor manufacturing process, the process feature size is getting smaller and smaller, and the storage density of memory devices is getting higher and higher. In order to meet the demand of higher storage density, three-dimensional structure memory devices are developed. 3D NAND memory has been widely used because of its fast writing speed, simple erasing operation, and higher storage density.

[0003] The existing 3D NAND memory includes a plurality of storage units stacked along the vertical direction, which can multiply the storage density on a unit area of wafer and reduce the cost. In the related art, the storage density is usually improved by increasing the number of stacked storage unit layers. However, as the number of stacked layers of the memory chip is continuously increased, the process becomes more and more complex, and the defects caused by the mutual influence between different processes become more and more obvious. Therefore, while the number of stacked layers is continuously increasing, how to optimize the influence between processes and reduce the generation of defects becomes a problem to be solved. SUMMARY

[0004] Embodiments of the present disclosure provide a manufacturing method of a three-dimensional memory, comprising:

[0005] providing a semiconductor structure; wherein the semiconductor structure comprises: a substrate, a stack structure, an isolation layer between the stack structure and the substrate, a gate line gap structure and a storage pillar extending through the stack structure and the isolation layer and into the substrate;

[0006] removing the substrate to expose a first end portion of the gate line gap structure and a second end portion of the storage pillar; wherein, along the radial direction of the storage pillar, the storage pillar comprises: a channel layer, and a functional layer surrounding the channel layer;

[0007] removing at least part of the first end portion to form a first recess concave from the isolation layer to the stack structure, and the remaining end portion of the gate line gap structure is in contact with the isolation layer;

[0008] removing the functional layer exposed by the second end portion to form a second recess concave from the isolation layer to the stack structure, and the remaining end portion of the storage pillar is in contact with the isolation layer;

[0009] covering the first recess, the second recess, and the exposed isolation layer with a conductive material, and performing particle implantation on the conductive material to form a second conductive layer.

[0010] In some embodiments,

[0011] The gate line gap structure comprises a third conductive layer, and a second insulating layer surrounding the third conductive layer;

[0012] The removing at least part of the first end portion forms a first recess concave from the isolation layer to the stack structure, and an end portion of the remaining gate line gap structure is in contact with the isolation layer, comprising:

[0013] The second insulating layer of the first end portion is removed to form the first recess based on the isolation layer, the third conductive layer, and the remaining second insulating layer; wherein the first recess surrounds the third conductive layer, and a sidewall depth of the first recess in a first direction perpendicular to the substrate is less than a thickness of the isolation layer.

[0014] In some embodiments,

[0015] The second insulating layer comprises a first sub-layer, and a second sub-layer surrounding at least part of the first sub-layer;

[0016] The removing the second insulating layer of the first end portion forms the first recess, comprising:

[0017] The first sub-layer and the second sub-layer of the first end portion are removed by an etchant to form the first recess based on the isolation layer, the third conductive layer, the remaining first sub-layer, and the remaining second sub-layer.

[0018] In some embodiments,

[0019] In a radial direction of the storage pillar, the functional layer comprises a blocking sub-layer, a storage sub-layer, and a tunneling sub-layer, and the tunneling sub-layer is between the storage sub-layer and the channel layer;

[0020] The removing the second end portion exposes the functional layer to form a second recess concave from the isolation layer to the stack structure, and an end portion of the remaining storage pillar is in contact with the isolation layer, comprising:

[0021] The blocking sub-layer, the storage sub-layer, and the tunneling sub-layer exposed by the second end portion are removed to form the second recess based on the isolation layer, the storage pillar, the remaining blocking sub-layer, the remaining storage sub-layer, and the remaining tunneling sub-layer; wherein a sidewall depth of the second recess in a first direction perpendicular to the substrate is less than a thickness of the isolation layer.

[0022] In some embodiments,

[0023] In the first direction perpendicular to the substrate, a thickness of the second conductive layer is less than a thickness of the channel layer protruding from the isolation layer.

[0024] The method further comprises:

[0025] forming a fourth conductive layer covering the second conductive layer; wherein a thickness of the fourth conductive layer is greater than a thickness of the channel layer protruding from the isolation layer.

[0026] In some embodiments,

[0027] The second conductive layer has a thickness of 20-100 nm, and the fourth conductive layer has a thickness of 200-500 nm.

[0028] In some embodiments,

[0029] The isolation layer comprises, in a first direction perpendicular to the substrate, a first insulating sublayer, a first conductive sublayer, and a second insulating sublayer arranged in sequence, the first insulating sublayer being between the first conductive sublayer and the substrate, and the second insulating sublayer being between the first conductive sublayer and the stack structure.

[0030] The method further comprises:

[0031] After removing the substrate, the first insulating sublayer is removed to expose the first conductive sublayer.

[0032] In some embodiments, the method further comprises:

[0033] forming the isolation layer on the substrate in a first direction perpendicular to the substrate;

[0034] forming a stack structure on the isolation layer; wherein the stack structure comprises a plurality of sacrificial layers and a plurality of first insulating layers arranged in sequence and alternately stacked;

[0035] forming a channel hole extending through the stack structure, the isolation layer, and into the substrate in the first direction;

[0036] filling the sidewall of the channel hole to form the functional layer;

[0037] forming the channel layer covering the functional layer.

[0038] In some embodiments, the method further comprises:

[0039] after forming the channel layer, forming a trench extending through the stack structure, the isolation layer, and into the substrate in the first direction;

[0040] based on the trench, removing the plurality of sacrificial layers in the stack structure to form gaps between adjacent first insulating layers;

[0041] filling the gap to form a plurality of first conductive layers.

[0042] In some embodiments, the method further comprises:

[0043] Before forming the plurality of first conductive layers, forming a dielectric layer covering the first insulating layer and the functional layer exposed by the gap and the trench; wherein the dielectric layer is between the first conductive layer and the insulating layer, and between the first conductive layer and the functional layer.

[0044] In the related art, the first end of the gap structure of the gate line and the second end of the storage pillar are first subjected to particle injection, then at least part of the first end of the gap structure of the gate line and the second end of the storage pillar are etched and removed, and finally conductive material is deposited. However, after the first end and the second end are subjected to particle injection, the etching rate in the subsequent etching process is increased, resulting in over-etching of the first end and / or the second end, so that the subsequently deposited conductive material is electrically connected to the conductive layer in the stack structure, causing leakage, and causing the device to fail.

[0045] The scheme provided by the embodiments of the present disclosure reduces the influence of the particle injection process on the performance of the gap structure of the gate line and the storage pillar by optimizing the process steps, removing at least part of the first end and part of the second end first, then depositing conductive material, and finally performing particle injection to form a conductive layer. In this way, the first recess and the second recess are in contact with the isolation layer, so that the first recess and the second recess do not expose the conductive layer in the stack structure, the second conductive layer formed finally is electrically insulated from the conductive layer in the stack structure, and the probability of leakage between the second conductive layer and the conductive layer in the stack structure is reduced, which is beneficial to improve the yield of the device. BRIEF DESCRIPTION OF DRAWINGS

[0046] Figures la to le is a schematic diagram of a manufacturing method of a three-dimensional memory;

[0047] Figure 2 is a flowchart of a manufacturing method of a three-dimensional memory according to an embodiment of the present disclosure;

[0048] Figures 3a to 3f is a schematic diagram of a manufacturing method of a three-dimensional memory according to an embodiment of the present disclosure;

[0049] Figures 4a to 4g is a schematic diagram of a manufacturing method of a three-dimensional memory according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] The technical solutions of the present disclosure are described in further detail below in conjunction with the accompanying drawings and specific embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation described herein. On the contrary, these implementations are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0051] The present disclosure is described in more detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present disclosure will be more apparent from the following description and claims. It should be noted that the accompanying drawings are very simplified and use non-precise proportions, only for the purpose of facilitating, clarifying and assisting in the description of the embodiments of the present disclosure.

[0052] It can be understood that the meanings of "on", "above" and "over" of the present disclosure should be interpreted in the broadest way, so that "on" not only means "on" with no intervening features or layers between them (i.e. directly on something), but also includes the meaning of "on" with intervening features or layers between them.

[0053] In the embodiments of the present disclosure, the terms "first", "second", etc. are used to distinguish similar objects, and do not necessarily describe a specific order or sequence.

[0054] In the embodiments of the present disclosure, the term "layer" refers to a material portion including a region with a thickness. The layer can extend over the entirety of the underlying or overlying structure, or can have a scope less than that of the underlying or overlying structure. In addition, the layer can be a region of a homogeneous or inhomogeneous continuous structure with a thickness less than that of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure, or the layer can be between any horizontal pair of planes at the top surface and the bottom surface of the continuous structure. The layer can extend horizontally, vertically and / or along an inclined surface. The layer can include multiple sub-layers. For example, the isolation layer includes: a first insulating sub-layer, a first conductive sub-layer and a second insulating sub-layer arranged in the first direction in turn.

[0055] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0056] Figures la to le is a schematic diagram of a method of manufacturing a three-dimensional memory according to an exemplary embodiment, the method comprising the following steps:

[0057] Step one: refer to Figure laAs shown, a semiconductor structure is provided; the semiconductor structure comprises: a substrate 100, a stack structure 110, an isolation layer 120 between the stack structure 110 and the substrate 100, a gate line gap structure 130 and a memory pillar 140 extending through the stack structure 110 and the isolation layer 120 and into the substrate 100; along a first direction perpendicular to the substrate 100, the stack structure 110 comprises: a plurality of first conductive layers 111 and a plurality of first insulating layers 112 alternately stacked in sequence. The isolation layer 120 further comprises a first insulating sub-layer 121, a first conductive sub-layer 122 and a second insulating sub-layer 123.

[0058] Step two: refer to Figure lb As shown, the substrate 100 is removed to expose a first end portion 131 of the gate line gap structure 130 and a second end portion 141 of the memory pillar 140; along a radial direction of the memory pillar 140, the memory pillar 140 comprises: a channel layer 142, and a functional layer 143 between the channel layer 142 and the stack structure 110. The functional layer 143 can comprise a composite layer of silicon oxide / silicon nitride / silicon oxide (ONO).

[0059] Step three: refer to Figure lc As shown, the functional layer 143 exposed by the second end portion 141 is etched to form a second recess 160 concave from the isolation layer 120 to the stack structure 110, and the remaining end portion of the memory pillar 140 is in contact with the isolation layer 120; and the channel layer 142 in the second recess 160 is subjected to particle injection.

[0060] Exemplarily, the process of etching to remove the second end portion can be a wet etching, a dry etching or any combination thereof.

[0061] Step four: refer to Figure Id As shown, the first end portion 131 is etched to form a first recess 150 concave from the isolation layer 120 to the stack structure 110, and the remaining end portion of the gate line gap structure is in contact with the isolation layer 120. In this embodiment, the first insulating sub-layer 121 is also etched during the etching process.

[0062] Exemplarily, the process of etching to remove the first end portion can be a wet etching, a dry etching or any combination thereof.

[0063] Step five: refer to Figure le As shown, a conductive layer 170 is formed by covering the first recess 150, the second recess 160 and the exposed isolation layer 120 with a conductive material, which can be electrically connected to the channel layer 142 of the memory pillar 140 and used as an array common source (ACS) of 3D NAND to supply power to the memory cells. The conductive material is preferably polysilicon.

[0064] The first direction is perpendicular to the base, which can be the Z direction in the attached figure. The second direction is parallel to the base, which can be the X direction in the attached figure.

[0065] However, in the actual memory manufacturing process, the interaction between successive processes can lead to defects. Specifically, refer to... Figure lc and 1d As shown, when the particle implantation process is performed on the second recess 160, the high-energy particles implanted will damage the first end 131, causing the etching rate of the first end 131 to increase during the etching removal process in step four, resulting in over-etching.

[0066] Reference Figure Id As shown, the gate gap structure may include a second insulating layer 135 and a third conductive layer 134. In the second direction, the second insulating layer 135 includes a first sub-layer 132 and a second sub-layer 133 located between the first sub-layer 132 and the stacked structure 110. The first sub-layer 132 is a high-dielectric material, preferably alumina in this embodiment; the second sub-layer 133 is an insulating material, preferably low-temperature silicon oxide (LTO) in this embodiment; and the third conductive layer 134 is preferably polycrystalline silicon.

[0067] After particle implantation, during HF etchant etching, the etching rate of the first sublayer 132 is increased by 5 to 15 times, and the etching rate of the low-temperature silicon oxide (LTO) layer is increased by 1 to 2 times. This exposes the first conductive layer 111 in the first recess 150, resulting in the formation of the first conductive layer 111 after step five is completed. Figure le The phenomenon shown in the middle circle is that the conductive layer 170 comes into contact with the first conductive layer 111, resulting in leakage defects and affecting the electrical performance of the memory.

[0068] Based on this, the present disclosure provides a manufacturing method.

[0069] Figure 2 This is a schematic flowchart illustrating a method for manufacturing a three-dimensional memory according to an embodiment of this disclosure. (Refer to...) Figure 2 As shown, the method includes the following steps:

[0070] S100: Provides a semiconductor structure; wherein the semiconductor structure includes: a substrate, a stacked structure, an isolation layer located between the stacked structure and the substrate, a gate gap structure extending through the stacked structure and the isolation layer and into the substrate, and a memory pillar;

[0071] S200: Remove the substrate to expose the first end of the gate gap structure and the second end of the memory pillar; wherein, along the radial direction of the memory pillar, the memory pillar includes: a channel layer and a functional layer surrounding the channel layer;

[0072] S300: removing at least part of the first end portion to form a first recess concave from the isolation layer to the stack structure, and the remaining end portion of the gate line gap structure is in contact with the isolation layer;

[0073] S400: removing the functional layer exposed by the second end portion to form a second recess concave from the isolation layer to the stack structure, and the end portion of the remaining storage pillar is in contact with the isolation layer;

[0074] S500: covering the first recess, the second recess and the exposed isolation layer with a conductive material, and performing particle injection on the conductive material to form a second conductive layer.

[0075] Figures 3a to 3f is a schematic diagram of a manufacturing method of a three-dimensional memory according to an embodiment of the present disclosure. The following will be described in combination with Figures 3a to 3f The method provided by the present disclosure will be further described in detail.

[0076] First, referring to Figure 3a It is shown that step S100 is performed: providing a semiconductor structure; wherein the semiconductor structure comprises a substrate 100, a stack structure 110, an isolation layer 120 between the stack structure 110 and the substrate 100, a gate line gap structure 130 and a storage pillar 140 extending through the stack structure 110 and the isolation layer 120 and into the substrate 100; wherein, along a first direction perpendicular to the substrate 100, the stack structure 110 comprises: a plurality of first conductive layers 111 and a plurality of first insulating layers 112 arranged alternately in sequence.

[0077] Exemplarily, the constituent material of the substrate 100 can include: elemental semiconductor material (such as silicon, germanium), group III-V compound semiconductor material, group II-VI compound semiconductor material, organic semiconductor material or other semiconductor material known in the art. Figure 3a The preferred semiconductor material in the present embodiment is polysilicon.

[0078] Exemplarily, the constituent material of the plurality of first conductive layers 111 can include: monocrystalline silicon material, polysilicon material, tungsten metal material or other conductive material known in the art.

[0079] Exemplarily, the constituent material of the plurality of first insulating layers 112 can include: high-temperature silicon oxide material, low-temperature silicon oxide material, silicon nitride material, silicon oxynitride material or other insulating material known in the art. The high-temperature silicon oxide material can include silicon oxide material deposited at a chemical vapor deposition temperature in the range of 600°C to 800°C, and the low-temperature silicon oxide material can include silicon oxide material deposited at a chemical vapor deposition temperature of 350°C to 450°C.

[0080] It should be emphasized that the constituent materials of different first conductive layers 111 can not be the same, and the constituent materials of different first insulating layers 112 can also not be the same.

[0081] Referring to Figure 3a As shown, the isolation layer 120 can also be a different material layer deposited from a different material. The isolation layer 120 can include a first insulating sub-layer 121, a first conductive sub-layer 122, and a second insulating sub-layer 123 arranged in sequence along the first direction. The first insulating sub-layer 121 is located between the first conductive sub-layer 122 and the substrate 100. The second insulating sub-layer 123 is located between the first conductive sub-layer 122 and the stack structure 110.

[0082] The method of forming the material layer can be any method known to those skilled in the art, such as a low temperature chemical vapor deposition (LTCVD) process, a low pressure chemical vapor deposition (LPCVD) process, a rapid thermal chemical vapor deposition (RTCVD) process, an atomic layer deposition (ALD) process, or a plasma enhanced chemical vapor deposition (PECVD) process.

[0083] Referring to Figure 3b The method of removing the substrate 100 can include dry etching, wet etching, chemical mechanical polishing, or a combination thereof. The dry etching gas can include CF4, C2F6, NF3, Cl2, O2, NH3, or a combination thereof. The wet etchant can include HF, H3PO4, KOH, or a combination thereof.

[0084] The method of removing the substrate 100 can include dry etching, wet etching, chemical mechanical polishing, or a combination thereof. The dry etching gas can include CF4, C2F6, NF3, Cl2, O2, NH3, or a combination thereof. The wet etchant can include HF, H3PO4, KOH, or a combination thereof.

[0085] After the substrate is removed, a conductive layer can be reformed at the location of the original substrate to electrically connect the sources of the plurality of channel structures, thereby increasing the conductance of an array common source (ACS) of the channel structures. In some embodiments, the conductive layer includes a metal silicide layer in contact with the semiconductor channel of the channel structures to reduce contact resistance, and further includes a metal layer in contact with the metal silicide layer to further reduce the total resistance. As a result, the thickness of the semiconductor layer (N-type doped or P-type doped) as part of the ACS can be reduced without affecting the ACS conductance.

[0086] Referring to Figure 3c , step S300 is performed: removing the first end portion 131 to form a first recess 150 recessed downward from the isolation layer 120 to the stack structure 110, and the end portion of the remaining gate line gap structure is in contact with the isolation layer 120.

[0087] In some embodiments, the gate line gap structure includes: a third conductive layer 134, and a second insulating layer 135 surrounding the third conductive layer 134.

[0088] Step S300 can further include: removing the second insulating layer 135 of the first end portion 131 to form the first recess 150 based on the isolation layer 120, the third conductive layer 134 and the remaining second insulating layer 135; wherein the first recess 150 surrounds the third conductive layer 134, and the sidewall depth of the first recess 150 in the first direction is less than the thickness of the isolation layer 120.

[0089] Exemplarily, the composition material of the third conductive layer 134 can include any material related in the technical field, including single crystal silicon, polycrystalline silicon, metal tungsten, metal copper, metal titanium or any combination of the above materials. In the embodiments of the present disclosure, polycrystalline silicon material is preferably used.

[0090] Exemplarily, the removal process can include: dry etching, wet etching or any combination of the above processes.

[0091] It should be emphasized that the role of the conductive material here is not limited to the role of conductive connection, but also as a support. According to the needs of the process before and after, when the third conductive layer 134 only serves as a support, an insulating material such as silicon oxide material, silicon nitride material, silicon oxynitride material, etc. can be used instead, and the skilled in the art can choose flexibly.

[0092] Referring to Figure 3cIn the embodiments of the present disclosure, the depth of the sidewall of the first recess 150 in the first direction is D1, and the thickness of the isolation layer 120 in the first direction is D2, the value of D1 is less than the value of D2, and the depth D1 and D2 can be controlled by etching time, etchant ratio and etching temperature. Further, in the process of etching and removing the first end portion 131, the etchant can also etch and remove a small amount of the second end portion 141, and the removal amount is related to the selectivity of the etchant.

[0093] It can be understood that, in the embodiments of the present disclosure, the first recess is not in contact with the first conductive layer, which avoids the generation of defects such as the leakage of the first recess sidewall to the gate when the conductive layer is subsequently deposited. Figure Id The first recess sidewall shown in the defects of the leakage of the gate.

[0094] Continuing to refer to Figure 3c In some embodiments, the second insulating layer 135 includes a first sub-layer 132 and a second sub-layer 133 surrounding at least part of the first sub-layer.

[0095] The step S300 can further include: removing the first sub-layer 132 and the second sub-layer 133 of the first end portion 131 by using an etchant, to form the first recess 150 based on the isolation layer 120, the third conductive layer 134, the remaining first sub-layer 132 and the remaining second sub-layer 133.

[0096] The second direction is a direction parallel to the plane of the substrate 100, the first sub-layer 132 is a high dielectric material with a dielectric constant higher than that of silicon dioxide, and in the embodiments of the present disclosure, an aluminum oxide material is preferred. The second sub-layer 133 is an insulating material, including a silicon oxide material and a silicon nitride material. In the embodiments of the present disclosure, the above-mentioned low-temperature silicon oxide material is preferred.

[0097] In the etching process of the first end portion 131 by the etchant, the etching rate of the first sub-layer 132 and the second sub-layer 133 is equivalent, and the etching rate of the third conductive layer 134 is smaller than that of the first sub-layer 132 and the second sub-layer 133 or substantially no etching, so as to form the first recess 150 surrounding the third conductive layer 134.

[0098] Further, the first sub-layer 132 and the second sub-layer 133 are substantially on the same horizontal plane after etching, which can make the surface of the formed first recess 150 more flat, provide a better deposition interface for the formation of the subsequent second conductive layer 171, optimize the morphology of the subsequent second conductive layer 171, while maintaining the structural integrity of the third conductive layer 134, further reducing defects and improving yield.

[0099] Referring to Figure 3dAs shown, step S400 is performed: removing the functional layer 143 exposed by the second end portion 141 to form a second recess 160 concave from the isolation layer 120 to the stack structure 110, with the end portion of the remaining storage pillar 140 in contact with the isolation layer 120.

[0100] The recess direction of the second recess 160 is in a direction perpendicular to the substrate 100, away from the substrate 100 and towards the stack structure 110.

[0101] Continuing to refer to Figure 3d As shown, in some embodiments, along the radial direction of the storage pillar 140, the functional layer 143 comprises: a blocking sub-layer 144, a storage sub-layer 145 and a tunneling sub-layer 146, wherein the tunneling sub-layer 144 is between the storage sub-layer 145 and the channel layer 142.

[0102] Step S400 can further comprise: removing the blocking sub-layer 144, the storage sub-layer 145 and the tunneling sub-layer 146 exposed by the second end portion 141 to form the second recess 160 based on the isolation layer 120, the storage pillar, the remaining blocking sub-layer 144, the remaining storage sub-layer 145 and the remaining tunneling sub-layer 146; wherein along the first direction, the sidewall depth of the second recess 160 is less than the thickness of the isolation layer 120.

[0103] Illustratively, the blocking sub-layer 144 can comprise silicon oxide, silicon oxynitride, high dielectric or any combination thereof. The tunneling sub-layer 146 can comprise silicon oxide, silicon oxynitride or any combination thereof. The storage sub-layer can comprise silicon nitride, silicon oxynitride, silicon or any combination thereof. In this embodiment, the combination of the functional layer 143 is preferably a composite layer of silicon oxide / silicon nitride / silicon oxide (ONO).

[0104] The removal process can be dry etching, wet etching or any combination thereof. Referring to Figure 3d As shown, the etching removal process has a high selectivity to the functional layer 143, i.e. the stop layers of the sub-layers of the functional layer 143 after etching are substantially at the same level, and the remaining stop layers form the second recess 160 based on the isolation layer 120 with the storage pillar. The second recess 160 has a more flat surface, providing a better deposition interface for the subsequent formation of the second conductive layer 171, optimizing the morphology of the subsequently formed second conductive layer 171. At the same time, the removal etching has a low selectivity to the channel layer 142, reducing the defects of the channel layer 142 and further optimizing the conductive performance of the channel layer 142.

[0105] Referring to Figure 3dAs shown, the second recess 160 has thicknesses D3 and D4 in a first direction perpendicular to the substrate 100 and a second direction parallel to the substrate 100, respectively. Both thicknesses are less than the thickness D5 of the isolation layer 120 in the corresponding direction. In some embodiments, the size of D3 and D4 can be controlled by etching time, etchant ratio and etching temperature.

[0106] Understandably, the second recess 160 does not contact the bottom first conductive layer to avoid reference defects in subsequent processes. Figure Id The second recess 160 shown is a defect that causes leakage to the first conductive layer.

[0107] Reference Figure 3e Step S500 is executed: the first recess 150, the second recess 160 and the exposed isolation layer 120 are covered with conductive material, and the conductive material is implanted with particles to form a second conductive layer 171.

[0108] For example, the conductive material may include: monocrystalline silicon, polycrystalline silicon, or amorphous silicon. In this embodiment, polycrystalline silicon is used, and it is subjected to particle implantation to form a second conductive layer 171, thereby reducing resistance and optimizing conductivity. In some embodiments, the particle implantation element includes any one of boron, arsenic, phosphorus, germanium, gallium, and antimony.

[0109] In some embodiments, the formed second conductive layer 171 is doped (N-type doping or P-type doping) and electrically connected to the channel layer 142 of each memory pillar 140, serving as the array common source (ACS) of the three-dimensional memory to power the memory cells.

[0110] Reference Figure 3f As shown, in some embodiments, step S500 further includes:

[0111] Along the first direction, the thickness of the second conductive layer 171 is less than the thickness of the channel layer 142 protruding from the isolation layer 120; a fourth conductive layer 172 is formed covering the second conductive layer 171; wherein the thickness of the fourth conductive layer 172 is greater than the thickness of the channel layer 142 protruding from the isolation layer 120.

[0112] By controlling Figure 3e The thickness of the second conductive layer 171 is less than the thickness of the channel layer 142 protruding from the insulating layer 120, meaning the second conductive layer 171 does not completely cover the exposed insulating layer 120. (Refer to...) Figure 3f As shown, immediately following Figure 3e After the second conductive layer 171 is formed, a fourth conductive layer 172 is formed on top of the second conductive layer to cover the second conductive layer 171, thereby completely covering the portion of the channel layer 142 that protrudes from the isolation layer 120.

[0113] In some embodiments, the thickness of the fourth conductive layer 172 can be selected according to the process requirement, the deposition material can be the same as the first conductive layer 111, and then the same particle injection process as the fourth conductive layer 172 can be performed. In other words, the second conductive layer 171 shown in the formation is divided into two parts, one part of the conductive layer is manufactured first, and then the other part of the conductive layer is manufactured according to the process requirement. Figure 3e The second conductive layer 171 shown in the formation is divided into two parts, one part of the conductive layer is manufactured first, and then the other part of the conductive layer is manufactured according to the process requirement.

[0114] In some embodiments, the thickness D5 of the fourth conductive layer 172 is greater than the thickness D6 of the second conductive layer 171, wherein the thickness of the second conductive layer is 20-100 nm, and the thickness of the fourth conductive layer is 200-500 nm. The preferred D5 in the embodiment of the present disclosure is 100 nm, and the preferred D6 is 300 nm.

[0115] It can be understood that the way of forming the conductive layer in steps can thicken the conductive layer that needs to be injected with particles and optimize the conductive performance, and at the same time, the thin conductive layer deposited first can protect the bottom of the stack structure 110, avoid defects caused by excessive particle injection energy, and expand the process window of particle injection.

[0116] In some embodiments, the method for manufacturing the three-dimensional memory further comprises:

[0117] After step S100 is performed, the isolation layer of the semiconductor structure provided includes multiple sub-layers, and then in the process of removing the substrate in subsequent step S200, the isolation sub-layers that need to be removed can be flexibly selected according to the manufacturing process requirement to meet the manufacturing requirement.

[0118] Referring to Figure 3a and 3b As shown, the thickness of the isolation layer in the embodiment of the present disclosure is preferably 100 nm, and can include different material layers. The isolation layer 120 includes a first insulating sub-layer 121, a first conductive sub-layer 122, and a second insulating sub-layer 123 arranged in sequence along the first direction, the first insulating sub-layer 121 is located between the first conductive sub-layer 122 and the substrate 100, and the second insulating sub-layer 123 is located between the first conductive sub-layer 122 and the stack structure 110.

[0119] Referring to Figure 3c After the substrate 100 is removed, the first insulating sub-layer 121 is removed to expose the first conductive sub-layer 122.

[0120] Referring to Figure 3e and 3fAs shown in this embodiment, after removing the first insulator layer 121, the exposed first conductive layer 122 can contact the second conductive layer 171 formed in the subsequent step S500. The first conductive layer 122 and the second conductive layer 171 are in close contact, increasing the thickness of the conductive layer and optimizing the conductivity. The first conductive layer 122 can be made of the same material as the second conductive layer 171, which can further optimize the contact performance between the two material layers. The materials of the first insulating layer 112 and the second insulating layer 135 can be one of silicon oxide, silicon nitride, and silicon oxynitride, with silicon oxide being preferred in this embodiment. The material of the first conductive layer 122 can be one of monocrystalline silicon and polycrystalline silicon, with polycrystalline silicon being preferred in this embodiment, and is the same as the material of the second conductive layer 171.

[0121] The following is combined Figures 4a to 4g To explain in detail the manufacturing method of semiconductor structures:

[0122] Reference Figure 4a As shown, a substrate 100 is provided, and an isolation layer 120 is formed along a first direction perpendicular to the substrate 100. The isolation layer 120 may include multiple sublayers: a first insulator layer 121, a first conductive layer 122, and a second insulator layer 123. The first insulator layer 121 is located between the first conductive layer 122 and the substrate 100, and the second insulator layer 123 is located between the first conductive layer 122 and the stacked structure 110. A stacked structure is formed on the isolation layer 120; the stacked structure includes multiple sacrificial layers and multiple first insulating layers 112 alternately stacked in sequence. In this embodiment, the first insulator layer 121 and the second insulator layer 123 are preferably made of silicon oxide, and the first conductive layer 122 is preferably made of polycrystalline silicon. The sacrificial layer material may include one of silicon nitride, silicon oxynitride, monocrystalline silicon, and polycrystalline silicon, and in this embodiment, silicon nitride is preferred. The first insulating layer 112 material includes one of silicon oxide and silicon oxynitride, and in this embodiment, silicon oxide is preferred.

[0123] Reference Figure 4b As shown, a channel hole 14 is formed, which extends perpendicularly through the laminated structure and the isolation layer 120 in the first direction to the channel hole 14 in the substrate 100.

[0124] Reference Figure 4c As shown, the sidewalls of the channel hole 14 are filled to form a functional layer 143. In this embodiment, the combination of functional layer 143 is preferably a composite layer of barrier sublayer 144, storage sublayer 145, and tunneling sublayer 146, and the material is preferably silicon oxide / silicon nitride / silicon oxide (ONO).

[0125] Reference Figure 4d, forming a channel layer 142 covering the functional layer 143, the channel layer 142 is preferably made of polysilicon material. In some embodiments, the channel layer 142 can fill the channel hole 14 completely; the channel layer 142 can also be filled along the sidewall based on the topography of the functional layer 143, and then the channel hole 14 is filled with silicon oxide to form a channel core 147, which can also contain air gaps 148 to improve stress.

[0126] Referring to Figure 4e After the channel layer 142 is formed, a trench is formed through the stack structure, the isolation layer 120 and extending into the substrate 100 in the first direction; based on the trench, a plurality of sacrificial layers 113 in the stack structure are removed to form gaps between adjacent first insulating layers 112;

[0127] Referring to Figure 4f The conductive material fills the gaps to form a plurality of first conductive layers 111. The conductive material can be one of tungsten, monocrystalline silicon, and polysilicon, and the preferred embodiment is tungsten. The trench is filled with a third conductive layer 134, and a second insulating layer 135 between the third conductive layer 134 and the stack structure 110, forming a gate line gap structure. The preferred third conductive layer 134 is preferably made of polysilicon material, and the second insulating layer 135 is composed of a first sub-layer 132 and a second sub-layer 133, the first sub-layer 132 is preferably made of aluminum oxide, and the second sub-layer 133 is preferably made of low-temperature silicon oxide.

[0128] Referring to Figure 4g In some embodiments, before forming the first conductive layer 111, a dielectric layer 115 is formed in the gaps and the trench, covering the first insulating layer 112 and the functional layer 143 exposed by the gaps; the dielectric layer 115 is located between the first conductive layer 111 and the insulating layer 112, and between the first conductive layer 111 and the functional layer 143. The dielectric layer material can be one of silicon oxide, silicon oxynitride, titanium nitride, and aluminum oxide. In this embodiment, the dielectric layer material is preferably aluminum oxide, which is the same as the material of the first sub-layer 132, which can reduce the interlayer contact stress between the first sub-layer 132 and the dielectric layer 115, and save process cost.

[0129] In the embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for manufacturing a three-dimensional memory, characterized in that, include: A semiconductor structure is provided; wherein the semiconductor structure includes: a substrate, a stacked structure, an isolation layer insulating between the stacked structure and the substrate, a gate gap structure extending through the stacked structure and the isolation layer and into the substrate, and a memory pillar; The substrate is removed to expose a first end of the gate gap structure and a second end of the memory pillar; wherein, along the radial direction of the memory pillar, the memory pillar includes: a channel layer and a functional layer surrounding the channel layer; the gate gap structure includes: a third conductive layer and a second insulating layer surrounding the third conductive layer; At least a portion of the first end is removed to form a first recess that is recessed from the isolation layer into the stacked structure, with the remaining end of the gate gap structure contacting the isolation layer; the third conductive layer protrudes from the first recess; along a first direction perpendicular to the substrate, the sidewall depth of the first recess is less than the thickness of the isolation layer; The functional layer exposed at the second end is removed to form a second recess that is recessed from the isolation layer into the stacked structure, and the end of the remaining functional layer contacts the isolation layer; the channel layer protrudes from the second recess; along the first direction, the sidewall depth of the second recess is less than the thickness of the isolation layer; A conductive material is used to cover the first recess, the second recess, and the exposed isolation layer, and the conductive material is then subjected to particle implantation to form a second conductive layer.

2. The method according to claim 1, characterized in that, The removal of at least a portion of the first end, forming a first recess that extends from the isolation layer into the stacked structure, wherein the remaining end of the gate gap structure contacts the isolation layer, includes: The second insulating layer at the first end is removed to form the first recess based on the isolation layer, the third conductive layer, and the remaining second insulating layer; wherein the first recess surrounds the third conductive layer.

3. The method according to claim 2, characterized in that, The second insulating layer includes: a first sublayer, and a second sublayer that at least partially surrounds the first sublayer; The removal of the second insulating layer at the first end to form the first recess includes: The first sublayer and the second sublayer at the first end are removed using an etchant to form the first recess based on the isolation layer, the third conductive layer, the remaining first sublayer, and the remaining second sublayer.

4. The method according to claim 1, characterized in that, Along the radial direction of the storage column, the functional layer includes: a barrier sublayer, a storage sublayer, and a tunneling sublayer, wherein the tunneling sublayer is located between the storage sublayer and the channel layer; The step of removing the functional layer exposed at the second end to form a second recess extending from the isolation layer into the stacked structure, with the remaining end of the storage column contacting the isolation layer, includes: Remove the barrier sublayer, storage sublayer, and tunneling sublayer exposed at the second end to form the second recess based on the isolation layer, the storage pillar, the remaining barrier sublayer, the remaining storage sublayer, and the remaining tunneling sublayer.

5. The method according to claim 1, characterized in that, Along the first direction, the thickness of the second conductive layer is less than the thickness of the channel layer protruding from the insulating layer; The method further includes: forming a fourth conductive layer covering the second conductive layer; wherein the thickness of the fourth conductive layer is greater than the thickness of the channel layer protruding from the isolation layer.

6. The method according to claim 5, characterized in that, The thickness of the second conductive layer is 20 nm to 100 nm; the thickness of the fourth conductive layer is 200 nm to 500 nm.

7. The method according to claim 1, characterized in that, The isolation layer includes: a first insulator layer, a first conductive layer and a second insulator layer arranged sequentially along the first direction, wherein the first insulator layer is located between the first conductive layer and the substrate, and the second insulator layer is located between the first conductive layer and the stacked structure; The method further includes removing the first insulator layer after removing the substrate to expose the first conductive layer.

8. The method according to claim 1, characterized in that, The method further includes: The isolation layer is formed on the substrate along the first direction; A stacked structure is formed on the isolation layer; wherein the stacked structure includes a plurality of sacrificial layers and a plurality of first insulating layers that are alternately stacked in sequence; A channel hole is formed that penetrates the stacked structure and the isolation layer along the first direction and extends into the substrate; The sidewalls of the channel holes are filled to form the functional layer; The channel layer is formed to cover the functional layer.

9. The method according to claim 8, characterized in that, The method further includes: After the trench layer is formed, a trench is formed that penetrates the stacked structure and the isolation layer along the first direction and extends into the substrate; Based on the trench, the plurality of sacrificial layers in the stacked structure are removed to form a gap between adjacent first insulating layers; The gaps are filled to form a plurality of first conductive layers.

10. The method according to claim 9, characterized in that, The method further includes: Before forming the plurality of first conductive layers, a dielectric layer is formed within the gap and the trench, covering the first insulating layer and the functional layer exposed by the gap; wherein the dielectric layer is located between the first conductive layer and the insulating layer, and between the first conductive layer and the functional layer.

Images