Semiconductor device

Abstract

A semiconductor device capable of reducing wiring resistance caused by a stripe wiring is provided. A semiconductor device (1) includes a source pad electrode (21) formed over a second interlayer insulating layer (17), a plurality of source lead-out electrodes (22) led out from the source pad electrode (21) in a first direction (X), a drain pad electrode (31) formed over the second interlayer insulating layer (17), and a plurality of drain lead-out electrodes (32) led out from the drain pad electrode (31) in the first direction (X). The source pad electrode (21) and the plurality of source lead-out electrodes (22) are electrically connected to a plurality of source wirings (85) of a stripe wiring (100) covered with the second interlayer insulating layer (17). The drain pad electrode (31) and the plurality of drain lead-out electrodes (32) are electrically connected to a plurality of drain wirings (86) of the stripe wiring (100). The plurality of drain lead-out electrodes (32) are engaged with the plurality of source lead-out electrodes (22).

Description

Technical Field

[0001] This invention relates to a semiconductor device. Background Technology

[0002] Patent document 1 describes a semiconductor device in which a striped drain region and a source region extending in one direction are formed on a main surface of a main region.

[0003] [Background Technical Documents]

[0004] [Patent Literature]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2012-156205 Summary of the Invention

[0006] [The problem the invention aims to solve]

[0007] Consider the following scenario: a first wiring layer is disposed on a dielectric insulating layer (first insulating layer) above a main body region, and a second wiring layer is disposed on a dielectric insulating layer (second insulating layer) above the first wiring layer. The second wiring layer includes a first solder pad electrode and a second solder pad electrode. In this case, consider forming a striped pattern in the first wiring layer, where multiple first wirings (source wirings) and multiple second wirings (drain wirings) extending along the stripe direction of the drain and source regions are spaced apart. That is, consider forming striped wirings extending along the stripe direction of the drain and source regions in the first wiring layer.

[0008] In this scenario, if the first pad electrode is electrically connected to one end of the striped wiring and the second pad electrode is electrically connected to the other end of the striped wiring, there is a concern that the current path from the first pad electrode to the striped wiring (the region at the other end) becomes longer, leading to an increase in the wiring resistance of the striped wiring. Similarly, there is a concern that the current path from the second pad electrode to the striped wiring (the region at one end) becomes longer, leading to an increase in the wiring resistance caused by the striped wiring.

[0009] One embodiment of the present invention provides a semiconductor device capable of reducing wiring resistance caused by striped wiring.

[0010] [Technical means to solve the problem]

[0011] An embodiment of the present invention provides a semiconductor device comprising: a first insulating layer; a striped wiring including a plurality of first wirings and a plurality of second wirings, the plurality of first wirings and the plurality of second wirings extending along a first direction on the first insulating layer and spaced apart in a second direction intersecting the first direction, the striped wirings having a first end on one side of the first direction and a second end on the other side of the first direction; a second insulating layer covering the striped wirings on the first insulating layer; a first bonding pad electrode disposed on the second insulating layer at the first end side of the striped wirings and electrically connected to the plurality of first wirings; and a plurality of first lead electrodes on the second insulating layer. A first solder pad electrode extends in a comb-like pattern from the first solder pad electrode to the second end side of the striped wiring on the second insulating layer, and is electrically connected to a plurality of the first wirings at the second end side of the striped wiring relative to the first solder pad electrode; a second solder pad electrode is disposed on the second insulating layer on the second end side of the striped wiring and is electrically connected to a plurality of the second wirings; and a plurality of second lead electrodes extend in a comb-like pattern from the second solder pad electrode to the first end side of the striped wiring on the second insulating layer in a manner engaging with a plurality of the first lead electrodes, and are electrically connected to a plurality of the second wirings at the first end side of the striped wiring relative to the second solder pad electrode.

[0012] According to this semiconductor device, the current path from the first pad electrode to the stripe wiring can be shortened using the first lead electrode. Similarly, the current path from the second pad electrode to the stripe wiring can be shortened using the second lead electrode. This reduces wiring resistance.

[0013] An embodiment of the present invention provides a semiconductor device comprising: a first insulating layer; a striped wiring including a plurality of first wirings and a plurality of second wirings, the plurality of first wirings and the plurality of second wirings extending along a first direction on the first insulating layer and arranged at intervals in a second direction intersecting the first direction, the striped wirings having a first end on one side of the first direction and a second end on the other side of the first direction; a second insulating layer covering the striped wiring on the first insulating layer; a first pad electrode disposed on the second insulating layer at the first end side of the striped wirings and electrically connected to the plurality of first wirings; and a first lead electrode extending from the first pad electrode toward the second end side of the striped wirings in the first direction on the second insulating layer. A first solder pad electrode is electrically connected to a plurality of first wirings at the second end of the striped wiring relative to the first solder pad electrode; a second solder pad electrode is disposed on the second insulating layer at the second end of the striped wiring and electrically connected to a plurality of second wirings; and a second lead electrode is led out from the second solder pad electrode toward the first end of the striped wiring in the first direction on the second insulating layer and electrically connected to a plurality of second wirings at the first end of the striped wiring relative to the second solder pad electrode; one of the first lead electrode and the second lead electrode includes a protrusion protruding toward one side in the second direction, and the other of the first lead electrode and the second lead electrode includes a recess recessed toward the side in the second direction and engaging with the protrusion.

[0014] According to this semiconductor device, the current path from the first pad electrode to the stripe wiring can be shortened using the first lead electrode. Similarly, the current path from the second pad electrode to the stripe wiring can be shortened using the second lead electrode. By forming a protrusion in at least one of the first and second leads electrodes, the number of stripe wirings whose current paths are shortened can be increased. This reduces wiring resistance.

[0015] An embodiment of the present invention provides a semiconductor device comprising: a first insulating layer; a striped wiring including a plurality of first wirings and a plurality of second wirings, the plurality of first wirings and the plurality of second wirings extending over the first insulating layer along a first direction and arranged at intervals in a second direction intersecting the first direction, the striped wirings having a first end on one side of the first direction and a second end on the other side of the first direction; a second insulating layer covering the striped wiring over the first insulating layer; a first bonding pad electrode disposed over the second insulating layer at the first end side of the striped wirings and electrically connected to the plurality of first wirings; and a first lead electrode extending over the second insulating layer from the first bonding pad electrode toward the second end side of the striped wirings in the first direction and relative to the first bonding pad electrode. A pad electrode is electrically connected to a plurality of the first wirings at the second end side of the striped wiring; a second pad electrode is disposed on the second insulating layer at the second end side of the striped wiring and electrically connected to a plurality of the second wirings; and a second lead electrode is led out from the second pad electrode to the first end side of the striped wiring in the first direction on the second insulating layer and electrically connected to a plurality of the second wirings at the first end side of the striped wiring relative to the second pad electrode; at least one of the first lead electrode and the second lead electrode includes: a first extension extending along the first direction; a third extension extending away from the first extension towards the second end side or away from the first end side along the first direction; and a connecting portion connecting the first extension and the third extension.

[0016] According to this semiconductor device, the current path from the first pad electrode to the stripe wiring can be shortened using the first lead electrode. Similarly, the current path from the second pad electrode to the stripe wiring can be shortened using the second lead electrode. Attached Figure Description

[0017] Figure 1 This is a schematic notched perspective view of a semiconductor device according to an embodiment of the present invention.

[0018] Figure 2 This is a top view showing the internal structure of the semiconductor device, and showing the layout of the first main surface of the semiconductor chip.

[0019] Figure 3 It means Figure 2 An enlarged view of the unit cell shown.

[0020] Figure 4 It is along Figure 3 The cross-sectional view shown is along the IV-IV cut line.

[0021] Figure 5 It is along Figure 3 The cross-sectional view shown is a VV cut line.

[0022] Figure 6A It is along Figure 3 The cross-sectional view shown is the VIA-VIA cut line.

[0023] Figure 6B It is along Figure 3 The cross-sectional view shown is the VIB-VIB cut line.

[0024] Figure 7 This is a diagram showing the internal structure of the semiconductor device, mainly used to illustrate the layout of the first wiring layer.

[0025] Figure 8 Is with Figure 3 The corresponding diagram is mainly used to illustrate the layout of the first wiring layer.

[0026] Figure 9 This is a diagram showing the internal structure of the semiconductor device, mainly showing the layout of the top wiring layer.

[0027] Figure 10 yes Figure 9 An enlarged view of region X shown.

[0028] Figure 11A yes Figure 10 The enlarged perspective view of region XIA shown is used to illustrate the relationship between the first wiring layer and the top wiring layer.

[0029] Figure 11B yes Figure 10 The enlarged perspective view of region XIB shown is used to illustrate the relationship between the first wiring layer and the top wiring layer.

[0030] Figure 12 Is with Figure 9 The corresponding diagram shows the layout of the top wiring layer involved in the reference example.

[0031] Figure 13 Is with Figure 9 The corresponding figure shows the layout of the top wiring layer according to the first variation of the present invention.

[0032] Figure 14 Is with Figure 9 The corresponding figure shows the layout of the top wiring layer according to the second variation of the present invention.

[0033] Figure 15 Is with Figure 9 The corresponding figure shows the layout of the top wiring layer according to the third variation of the present invention.

[0034] Figure 16 Is with Figure 9 The corresponding figure shows the layout of the top wiring layer according to the fourth variation of the present invention.

[0035] Figure 17 Is with Figure 9 The corresponding figure shows the layout of the top wiring layer according to the fifth variation of the present invention.

[0036] Figure 18 Is with Figure 9 The corresponding figure shows the layout of the top wiring layer according to the sixth variation of the present invention.

[0037] Figure 19 Is with Figure 9 The corresponding figure shows the layout of the top wiring layer according to the seventh variation of the present invention. Detailed Implementation

[0038] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0039] Figure 1 This is a schematic notched perspective view of a semiconductor device 1 according to an embodiment of the present invention.

[0040] Semiconductor device 1 refers to small chip components based on planar dimensions, such as 1005 (1mm×0.5mm) chip, 0603 (0.6mm×0.3mm) chip, 0402 (0.4mm×0.2mm) chip, and 03015 (0.3mm×0.15mm) chip.

[0041] Semiconductor device 1 includes a cuboid-shaped chip body 2. The chip body 2 also serves as a package. That is, the chip size of semiconductor device 1 (chip body 2) is the package size. Chip body 2 includes a first chip main surface 3 on one side and a second chip main surface 4 on the other side. The first chip main surface 3 and the second chip main surface 4 are formed into a quadrilateral shape (specifically a rectangular shape) when viewed from their normal direction Z (hereinafter referred to as "top view"). The first chip main surface 3 is the connection surface (mounting surface) facing the connection object when connected to a connection object such as a mounting substrate. The second chip main surface 4 is the non-connection surface (non-mounting surface) on the opposite side of the connection surface. The second chip main surface 4 includes a polished surface or a mirror surface with polishing marks.

[0042] The chip body 2 includes four chip side surfaces 5A to 5D connecting the first chip main surface 3 and the second chip main surface 4. The four chip side surfaces 5A to 5D include a first chip side surface 5A, a second chip side surface 5B, a third chip side surface 5C, and a fourth chip side surface 5D. The first chip side surface 5A and the second chip side surface 5B extend along a first direction X and face each other in a second direction Y, which intersects the first direction X. The first chip side surface 5A and the second chip side surface 5B form the long side of the chip body 2. The third chip side surface 5C and the fourth chip side surface 5D extend in the second direction Y and face each other in the first direction X. The third chip side surface 5C and the fourth chip side surface 5D form the short side of the chip body 2. The chip side surfaces 5A to 5D include flat surfaces extending along the normal direction Z. In this configuration, the second direction Y is orthogonal to the first direction X.

[0043] In this configuration, the four corners of the chip body 2 are curved outwards from the top (R-shaped chamfer). Alternatively, the four corners of the chip body 2 can be chamfered (C-shaped chamfer). The four corners of the chip body 2 can also be left without chamfering and have sharp edges.

[0044] The designations "0603", "0402", and "03015", etc., are defined by the lengths of the long and short sides of the chip body 2. The length of the short side of the chip body 2 is not limited to the stated values ​​and can be between 0.05 mm and 1 mm. Furthermore, the length of the long side of the chip body 2 is not limited to the stated values ​​and can be between 0.1 mm and 2 mm. The ratio of the length of the long side to the length of the short side of the chip body 2 can also be between 1 and 3. The thickness of the chip body 2 can also be between 50 μm and 1000 μm.

[0045] Semiconductor device 1 (chip body 2) includes a silicon semiconductor chip 10 formed in a cuboid shape. The semiconductor chip 10 includes a first main surface 11 on one side, a second main surface 12 on the other side, and four side surfaces 13A to 13D connecting the first main surface 11 and the second main surface 12. The first main surface 11 and the second main surface 12 are formed in a quadrilateral shape (rectangular shape in this configuration) when viewed from above.

[0046] The first main surface 11 is the device surface on which the functional device is formed. The second main surface 12 forms the second chip main surface 4. The four side surfaces 13A to 13D include the first side surface 13A, the second side surface 13B, the third side surface 13C, and the fourth side surface 13D. In each intersection of adjacent side surfaces 13A to 13D on the first main surface 11, corner portions 13AC, 13AD, 13BC, and 13BD of the semiconductor chip 10 are formed.

[0047] Semiconductor chip 10 includes p-type silicon substrate 56 (reference) Figures 4 to 6B ), and n - Type epitaxial layer 57 (reference) Figures 4 to 6B Epitaxial layer 57 is formed on silicon substrate 56. The thickness of epitaxial layer 57 is, for example, 5.0 μm to 10 μm.

[0048] The semiconductor device 1 further includes a side insulating layer 15 covering the sides 13A to 13D of the semiconductor chip 10. The side insulating layer 15 collectively covers the four sides 13A to 13D.

[0049] The semiconductor device 1 further includes an interlayer insulating layer 18 covering the first main surface 11. The interlayer insulating layer 18 includes a first interlayer insulating layer (first insulating layer) 16 and a second interlayer insulating layer (second insulating layer) 17. The interlayer insulating layer 18 has a laminated structure in which the second interlayer insulating layer 17 is superimposed on the first interlayer insulating layer 16. The side insulating layer 15 is connected to the first interlayer insulating layer 16 and the second interlayer insulating layer 17. That is, the peripheral portions of the first interlayer insulating layer 16 and the peripheral portions of the second interlayer insulating layer 17 are connected to the four side surfaces 13A to 13D.

[0050] The semiconductor device 1 further includes a source terminal electrode 20, a drain terminal electrode 30, and a gate terminal electrode 40 on the first chip main surface 3. The source terminal electrode 20, the drain terminal electrode 30, and the gate terminal electrode 40 are formed on the second interlayer insulating layer 17.

[0051] The source terminal electrode 20 includes a source pad electrode (first pad electrode) 21 and a plurality of source lead-out electrodes (first lead-out electrodes) 22. The drain terminal electrode 30 includes a drain pad electrode (second pad electrode) 31 and a plurality of drain lead-out electrodes (second lead-out electrodes) 32.

[0052] Figure 2 This is a top view showing the internal structure of the semiconductor device 1, showing the layout of the first main surface 11. Figure 3 It means Figure 2 An enlarged view of unit cell 60 shown. Figure 4 It is along Figure 3 The cross-sectional view shown is along the IV-IV cut line. Figure 5 It is along Figure 3 The cross-sectional view shown is a VV cut line. Figure 6A It is along Figure 3 The cross-sectional view shown is the VIA-VIA cut line. Figure 6B It is along Figure 3 The cross-sectional view shown is the VIB-VIB cut line.

[0053] The following is for reference. Figures 2 to 6B The internal structure of semiconductor device 1 will be explained.

[0054] Semiconductor device 1 includes a first main surface 11, an active portion 53 formed on the first main surface 11, and an outer region 54 outside the active portion formed on the first main surface 11. Figure 2 As shown, the active portion 53 is generally formed in the entire first main surface 11 of the semiconductor chip 10, except for the recessed portion 52, which is recessed inward and has a quadrilateral shape in plan view, formed around a corner 13BC of the semiconductor chip 10. The outer region 54 is formed in a manner that matches the recess 52. The active portion 53 is the region in which a MOSFET structure 53A is formed, in which current flows in the thickness direction of the semiconductor chip 10 when the source-drain of the semiconductor device 1 is in a conducting state (when conducting). The outer region 54 is the region in which a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure (equivalent to MOSFET structure 53A) is not formed. The outer region 54 serves as a support for the gate terminal electrode 40 (see reference). Figure 1 The support portion functions as a support. The outer region 54 is the area where no MOSFET structure is formed (equivalent to MOSFET structure 53A). Components other than the MOSFET structure (such as protection diodes) can also be formed in the outer region 54.

[0055] The MOSFET structure 53A is a field-effect transistor composed of multiple unit cells 60 arranged in the second direction Y and extending along the first direction X. The unit cell 60 has a planar gate structure.

[0056] like Figure 3 As shown, unit cell 60 includes a DMOSFET (Double-Diffused MOSFET). Unit cell 60 includes a strip-shaped n extending along the first direction X. - Trap region 66, and the strip-shaped p extending along the first direction X - A main body region 67 is formed. A well region 66 and a main body region 67 are formed spaced apart in the second direction Y. The well regions 66 and the main body regions 67 are formed as stripes extending in the first direction X of the semiconductor chip 10. In each unit cell 60, one main body region 67 is sandwiched between two adjacent well regions 66 in the second direction Y.

[0057] like Figures 4 to 6BAs shown, the semiconductor chip 10 includes a p-type separation well 55 on its first main surface 11. The p-type separation well 55 separates a portion of the epitaxial layer 57 from other portions to define a drift region. The separation well 55 is formed in a ring shape in top view, extending from the surface portion of the epitaxial layer 57 (first main surface 11) to the silicon substrate 56. Unit cells 60 are defined on the silicon substrate 56 by surrounding a portion of the epitaxial layer 57 with the separation well 55.

[0058] like Figures 4 to 6B As shown, the separation trap 55 includes a p disposed on the upper side. + The upper region 58 and the p arranged on the lower side - The lower region 59 has a two-layer structure. The boundary between regions 58 and 59 is located at the midpoint of the thickness direction of the epitaxial layer 57.

[0059] like Figures 4 to 6B As shown, n are selectively formed in unit cell 60. + Embedded layer 63. In semiconductor chip 10, embedded layer 63 is formed in such a way that it spans the junction of silicon substrate 56 and epitaxial layer 57.

[0060] A field insulating film 64 is formed in the surface portion of the separation trap 55. The field insulating film 64 is, for example, an oxide film.

[0061] like Figures 3 to 6B As shown, in the surface portion of the well region 66, an impurity concentration of n is formed that is higher than that of the well region 66. + Type Drain Region 68. Drain Region 68 is a strip extending along the first direction X.

[0062] In addition, such as Figure 3 As shown, the surface portion of the main body region 67 includes n alternatingly arranged [number] [elements] in the first direction X. + Type source region 69A and p + Type-type contact region 69B. The source region 69A and contact region 69B together form a strip extending along the first direction X. For example... Figure 4 and Figure 6A As shown, the source region 69A includes a high-concentration region 69AA formed on the inner side and a low-concentration region 70 formed on the peripheral side. The high-concentration region 69AA is surrounded by the low-concentration region 70.

[0063] like Figure 5 and Figure 6B As shown, the outer periphery of the contact area 69B is positioned at a certain distance from the outer periphery of the main body area 67.

[0064] like Figures 4 to 6BAs shown, in the surface portion of the epitaxial layer 57, a field insulating film 71 is formed in the portion between the well region 66 and the main body region 67. The field insulating film 71 is, for example, an oxide film.

[0065] One periphery of the field insulating film 71 is disposed on the periphery of the drain region 68, and the other periphery of the field insulating film 71 is disposed on the well region 66, which is spaced inward from the outer periphery of the well region 66. The drain region 68 is formed in the region sandwiched between the periphery of the field insulating film 71 and the field insulating film 64.

[0066] Furthermore, a gate insulating film 72 is formed in the surface portion of the epitaxial layer 57, spanning between the epitaxial layer 57 and the main body region 67. A gate electrode 73 is formed on the gate insulating film 72. The gate electrode 73 is formed in a manner that selectively covers a portion of the gate insulating film 72 and a portion of the field insulating film 71.

[0067] The gate electrode 73 appears as a four-sided ring when viewed from above. For example... Figure 3 As shown, the gate electrode 73 extends along the first direction X when viewed from above. The gate electrode 73 has one end 73a and another end 73b. Furthermore, the gate electrode 73 has an outer peripheral wall 73c and an inner peripheral wall 73d. The outer peripheral wall 73c is quadrilateral in shape when viewed from above. The inner peripheral wall 73d is elliptical in shape when viewed from above. The source region 69A and the contact region 69B are exposed through an opening defined by the inner peripheral wall 73d.

[0068] like Figures 4 to 6B As shown, the gate electrode 73 may also include, for example, a lower film 74 containing Poly-Si and an upper film 75 containing WSi / Si (tungsten silicide / silicon). The gate insulating film 72 may also be an oxide film.

[0069] The gate electrode 73 is separated from the gate insulating film 72, and the region opposite to the main region 67 is the channel region 76. The formation of the channel in the channel region 76 is controlled by the gate electrode 73.

[0070] In addition, such as Figures 4 to 6B As shown, the semiconductor device 1 further includes an interlayer insulating layer 18. The interlayer insulating layer 18 includes a first interlayer insulating layer 16 and a second interlayer insulating layer 17. The first interlayer insulating layer 16 and the second interlayer insulating layer 17 are formed to cover a first main surface 11 of the semiconductor chip 10. The first interlayer insulating layer 16 and the second interlayer insulating layer 17 are formed of an insulating material, for example, silicon oxide (SiO2). The first interlayer insulating layer 16 covers a plurality of unit cells 60.

[0071] Figure 7 This is a diagram showing the internal structure of semiconductor device 1, mainly used to illustrate the layout of the first wiring layer 84. Figure 8 Is with Figure 3The corresponding diagram is mainly used to represent the layout of the first wiring layer 84.

[0072] like Figures 4-8 As shown, a first wiring layer 84 is formed on the first interlayer insulating layer 16. The first wiring layer 84 includes striped wiring 100. Striped wiring 100 includes multiple pairs of source wirings (first wirings) 85 and drain wirings (second wirings) 86. The multiple source wirings 85 and multiple drain wirings 86 are arranged at intervals in the second direction Y. The multiple source wirings 85 and multiple drain wirings 86 are formed into stripes extending along the first direction X and are arranged alternately. Striped wiring 100 has a first end 100a on the third chip side 5C side (reference). Figure 7 ) and the second end 100b on the 5D side of the fourth chip (reference) Figure 7 The striped lines 100 are formed in almost all areas except for the outer region 54 when viewed from above.

[0073] The source wiring 85 includes a main electrode formed of a metal layer. The metal layer may contain pure Cu, pure Al (purity ≥ 99%), AlSi, AlCu, AlSiCu, etc. Alternatively, a first barrier layer and a second barrier layer may be formed on the front and back sides of the main electrode, respectively. The first and second barrier layers may contain at least one of Ti and TiN. The thickness of the main electrode may also be greater than the thickness of the first and second barrier layers.

[0074] Source wiring 85 is connected to source region 69A and contact region 69B formed in body region 67 via multiple source lower contacts 89A and multiple source lower contacts 89B. Source region 69A is connected to source wiring 85 via corresponding source lower contacts 89A. In contact region 69B, it is connected to source wiring 85 via corresponding source lower contacts 89B. Figure 3 As shown, source lower contacts 89A and 89B are alternately arranged in the first direction X. A plurality of source lower contacts 89A and 89B are arranged collectively in the first direction X. Source lower contacts 89A and 89B comprise a metal layer such as tungsten. Alternatively, a barrier layer (e.g., comprising at least one of Ti and TiN) may be formed on at least one of the front, back, and side surfaces of the metal layer as needed.

[0075] The drain wiring 86 includes a main electrode formed of a metal layer. The metal layer may contain pure Cu, pure Al (purity ≥ 99%), AlSi, AlCu, AlSiCu, etc. A first barrier layer and a second barrier layer may also be formed on the front and back sides of the main electrode, respectively. The first and second barrier layers contain at least one of Ti and TiN. The thickness of the main electrode may also be greater than the thickness of the first and second barrier layers.

[0076] Drain wiring 86 is connected to drain region 68 formed in well region 66 via a plurality of drain lower contacts 92. The plurality of drain lower contacts 92 are arranged in a first direction X. The drain lower contacts 92 are opposite to source lower contacts 89A and 89B in a second direction Y. Drain lower contacts 92 comprise a metal layer such as tungsten. A barrier layer (e.g., comprising at least one of Ti and TiN) may also be formed on at least one of the front, back, and side surfaces of the metal layer as needed.

[0077] like Figure 8 As shown, the drain wiring 86 connects to the drain region 68 of the well region 66 on one side of the unit cell 60 in the Y direction, and to the drain region 68 of the well region 66 on the other side of the unit cell 60 adjacent to the unit cell 60 in the Y direction. That is, the drain wiring 86 is connected to the drain regions 68 of the two well regions 66 contained in adjacent unit cells 60. The width W86 of the drain wiring 86 in the second direction Y is equal to the width W85 of the source wiring 85 in the second direction Y. The width W86 of the drain wiring 86 in the second direction Y can also be greater than the width W85 of the source wiring 85 in the second direction Y. The width W86 of the drain wiring 86 in the second direction Y can also be less than the width W85 of the source wiring 85 in the second direction Y.

[0078] The first wiring layer 84 also includes gate wiring 87. For example... Figure 7 As shown, the gate wiring 87 extends in a strip shape around the active portion 53. The gate wiring 87 is not formed on the first side surface 13A side (i.e., the first chip side surface 5A side) of the active portion 53. Figure 8 As shown, the gate wiring 87 is connected to the gate electrode 73 via the lower gate contact 105. The lower gate contact 105 is formed at one end 73a of the gate electrode 73 extending along the first direction X (see reference). Figure 3 ) and the other end 73b (reference) Figure 3 The lower gate contact 105 is not formed in the central portion of the gate electrode 73 (excluding one end 73a and the other end 73b). The lower gate contact 105 comprises a metal layer such as tungsten. Alternatively, a barrier layer (e.g., comprising at least one of Ti and TiN) may be formed on at least one of the front, back, and side surfaces of the metal layer as needed.

[0079] like Figures 4 to 6B As shown, a top wiring layer 94 is formed on the second interlayer insulation layer 17. In this configuration, as... Figure 1 As shown, the top wiring layer 94 is formed on the first chip main surface 3 of the semiconductor device 1. That is, the second interlayer insulating layer 17 is the uppermost interlayer film. Therefore, it is called the top wiring layer 94, but when a third interlayer insulating layer or the like is further formed on the second interlayer insulating layer 17, the wiring layer of the second interlayer insulating layer 17 can also be called the second wiring layer.

[0080] Figure 9 This is a diagram showing the internal structure of semiconductor device 1, mainly showing the layout of the top wiring layer 94. Figure 10 yes Figure 9 An enlarged view of region X shown. Figure 11A yes Figure 10 The enlarged 3D view of region XIA shown is used to illustrate the relationship between the first wiring layer 84 and the top wiring layer 94. Figure 11B yes Figure 10 The enlarged 3D view of region XIB shown illustrates the relationship between the first wiring layer 84 and the top wiring layer 94. Figure 11 is... Figure 10 An enlarged 3D view of region XI shown.

[0081] As described above, the top wiring layer 94 includes a source terminal electrode 20, a drain terminal electrode 30, and a gate terminal electrode 40.

[0082] As described above, the source terminal electrode 20 includes a source pad electrode 21 and a plurality of source lead-out electrodes 22. The source terminal electrode 20 is positioned relative to the active region 53 (reference) in a top view. Figure 2 The striped wiring 100 overlaps with each other. Multiple source lead-out electrodes 22 extend towards the fourth chip side surface 5D in a comb-like pattern extending in the first direction X. (Example...) Figure 9 As shown, multiple source lead-out electrodes 22 can also be led out from the entire region of the source pad electrode 21 in the second direction Y.

[0083] The drain terminal electrode 30 includes a drain pad electrode 31 and multiple drain lead electrodes 32. The drain terminal electrode 30 is positioned relative to the active region 53 (see reference numeral). Figure 2 ) and striped wiring 100 (reference) Figure 7 They are formed in an overlapping manner. Multiple drain leads 32 extend towards the third chip side 5C in a comb-like pattern extending in the first direction X. Figure 9 As shown, multiple drain leads 32 can also be led out from the entire region of the drain pad electrode 31 in the second direction Y. The multiple drain leads 32 are spaced apart from the multiple source leads 22 and engage in the first direction X.

[0084] Gate terminal electrode 40 viewed from above and outer region 54 (reference) Figure 2 The gate terminal electrode 40 is formed by overlapping. When viewed from above, it has a quadrilateral shape.

[0085] The source terminal electrode 20, drain terminal electrode 30, and gate terminal electrode 40 comprise a main electrode formed of a metal layer. The metal layer may contain pure Cu, pure Al (purity ≥ 99%), AlSi, AlCu, AlSiCu, etc. A first barrier layer and a second barrier layer may also be formed on the front and back sides of the main electrode, respectively. The first and second barrier layers comprise at least one of Ti and TiN. The thickness of the main electrode may also be greater than the thickness of the first and second barrier layers.

[0086] The source pad electrode 21 is formed in a region closer to the third chip side surface 5C than the center in the first direction X, avoiding the formation region of the gate terminal electrode 40 in the first chip main surface 3. Specifically, the source pad electrode 21 is formed in approximately one-third of the region on the third chip side surface 5C in the first chip main surface 3. The source pad electrode 21 is approximately quadrilateral in plan view. Specifically, as... Figure 9 As shown, the source terminal electrode 20 is formed on the first chip side 5A side in the second direction Y and on the fourth chip side 5D side in the first direction X, relative to the gate terminal electrode 40.

[0087] The source pad electrode 21 includes a first source pad region 46, which is quadrilateral in shape when viewed from above, and a second source pad region 47 formed on the second chip side surface 5B side with an edge 40a relative to the first chip side surface 5A (the side in the second direction Y) of the gate terminal electrode 40. The second source pad region 47 is generally trapezoidal in shape when viewed from above. The first source pad region 46 and the second source pad region 47 are connected by a source pad connection portion 48.

[0088] like Figure 4 and Figure 5 As shown, the source pad electrode 21 is electrically connected to the plurality of source wires 85 of the striped wiring 100 via a plurality of source upper contacts (first contacts) 98. The source pad electrode 21 and the drain wiring 86 are electrically insulated from each other by a second interlayer insulating layer 17.

[0089] Multiple source contacts 98 are formed within the second interlayer insulating layer 17. The multiple source contacts 98 are disposed between the source pad electrode 21 and the source wiring 85. The multiple source contacts 98 connect the source pad electrode 21 to each source wiring 85. The multiple source contacts 98 are arranged along the source wiring 85. The source contacts 98 comprise a metal layer such as tungsten. Alternatively, a barrier layer (e.g., comprising at least one of Ti and TiN) may be formed on at least one of the front, back, and side surfaces of the metal layer, as needed.

[0090] The edge 21a of the fourth chip side 5D side of the source pad electrode 21 includes a straight portion 49 extending in a straight line in the second direction Y and an inclined portion 50. The inclined portion 50 is inclined relative to the second direction Y as it approaches the drain pad electrode 31 side towards the second chip side 5B side. Because the edge 21a has the inclined portion 50, the width W48 of the source pad connection portion 48 can be ensured to be large.

[0091] The width W22 of the comb-shaped source lead-out electrodes 22 in the second direction Y is equal to that of each other. The width W22 of the source lead-out electrodes 22 is greater than the width W85 of the source wiring 85 (reference). Figure 8 The width W22 of the source lead-out electrode 22 is greater than the width W85 of the source wiring 85 and the width W86 of the drain wiring 86 (reference). Figure 8 ) and. like Figure 10 As shown, at least one pair of the multiple source lead-out electrodes 22, viewed from above, are connected to the source wiring 85 and the drain wiring 86. Figure 10 In the example, there are 6 pairs overlapping. The edge 22a of the fourth chip side 5D of the source lead electrode 22 is aligned with the edge 31a of the third chip side 5C of the drain pad electrode 31 with a narrower width.

[0092] like Figures 10-11B As shown, multiple source leads 22 are electrically connected to multiple source wires 85 of striped wiring 100 via source contacts 98. The multiple source leads 22 are electrically insulated from the drain wires 86 by a second interlayer insulating layer 17.

[0093] Multiple source contacts 98 are configured between each source lead-out electrode 22 and each source wiring 85. These multiple source contacts 98 connect the source pad electrode 21 to each source wiring 85. The multiple source contacts 98 are arranged along the source wiring 85. Figures 10-11B As shown, the source terminal 98 is formed in the region of the source lead-out electrode 22 that overlaps with the source wiring 85 when viewed from above. Figures 10-11B As shown, no source contact 98 is formed in the region where the source lead-out electrode 22 overlaps with the drain wiring 86 when viewed from above.

[0094] The source electrode 22 extends in a serrated shape in the first direction X. The source electrode 22 is mated with the adjacent drain electrode 32 (along the adjacent drain electrode 32). The source electrode 22 includes a first source extension (first extension portion) 23, a first source bend (first bend portion, third bend portion) 24, and a second source bend (first bend portion, fourth bend portion) 25. The first source extension 23 extends from the source pad electrode 21 toward the fourth chip side surface 5D and extends along the first direction X. The first source bend 24 bends in the first source extension 23 toward the first chip side surface 5A (on the side of the second direction Y), and after bending, extends toward the fourth chip side surface 5D and extends along the first direction X. The second source bending portion 25 bends toward the second chip side surface 5B in the first source bending portion 24, and after bending, it extends toward the fourth chip side surface 5D and extends along the first direction X.

[0095] The first source bend 24 extends along the bending direction of the second drain bend 35 (described later) of the adjacent drain lead-out electrode 32. The first source bend 24 is electrically connected to the source terminal 98. The first source bend 24 is electrically insulated from the drain wiring 86 by a second interlayer insulation layer 17.

[0096] The first source bending portion 24 includes a second source extension (second extension) 26 and a first source connection portion 27. The second source extension 26 extends along the first direction X in a region further than the first source extension 23 towards the fourth chip side surface 5D, from a position offset relative to the first source extension 23 towards the first chip side surface 5A. The second source extension 26 is offset relative to the first source extension 23 towards the first chip side surface 5A by a distance equal to that of the first source extension 23. Specifically, the side edge 26b of the second source extension 26 on the second chip side surface 5B side is aligned in the second direction Y with the side edge 23a of the first source extension 23 on the first chip side surface 5A side.

[0097] The second source extension 26 faces the first drain extension 33 of the drain lead-out electrode 32 adjacent to the first chip side surface 5A in the first direction X. The second source extension 26 does not face the first source extension 23 of the source lead-out electrode 22 adjacent to the first chip side surface 5A in the first direction X. The two side edges (side edge 26a and side edge 26b) of the second source extension 26 are respectively aligned with the two side edges (side edge 33a and side edge 33b) of the first drain extension 33 of the drain lead-out electrode 32 adjacent to the first chip side surface 5A in the second direction Y.

[0098] The first source connection portion 27 connects the first source extension portion 23 and the second source extension portion 26. The first source connection portion 27 is inclined relative to the second direction Y in such a way that it moves closer to the fourth chip side surface 5D as it moves toward the first chip side surface 5A. The first source connection portion 27, when viewed from above, traverses multiple source wirings 85 and multiple drain wirings 86.

[0099] The second source bend 25 extends along the bending direction of the first drain bend 34 (described later) of the adjacent drain lead-out electrode 32. The second source bend 25 is electrically connected to the source terminal 98. The second source bend 25 is electrically insulated from the drain wiring 86 by a second interlayer insulation layer 17.

[0100] The second source bend 25 includes a third source extension (third extension) 28 and a second source connection 29. The third source extension 28 extends from the first source extension 23 toward the fourth chip side 5D in a region further from the first source bend 24 than the fourth chip side 5D, along a first direction X. The third source extension 28 faces the first source extension 23 in the first direction X. The second source connection 29 connects the second source extension 26 to the third source extension 28. The second source connection 29 is inclined relative to the second direction Y, moving closer to the fourth chip side 5D as it moves toward the second chip side 5B. The second source connection 29, when viewed from above, traverses a plurality of source wirings 85 and a plurality of drain wirings 86. A connecting portion is formed by the first source bending portion 24 and the second source connecting portion 29, which connects the first source extension portion 23 and the third source extension portion 28.

[0101] A source protrusion (protrusion) 41 is formed by the first source bending portion 24 (the second source extension portion 26 and the first source connection portion 27) and the second source connection portion 29, protruding toward the side surface 5B of the second chip (the other side of the second direction Y).

[0102] The source lead-out electrode 22 includes a source recess 42 recessed towards the first chip side surface 5A. The source recess 42 is divided by the side edge of the source protrusion 41 on the second chip side surface 5B. The source recess 42 mates with and accommodates a drain protrusion 43 adjacent to the source recess 42 on the second chip side surface 5B. In other words, the source recess 42 engages with the drain protrusion 43 adjacent to the second chip side surface 5B on the second direction Y at a distance.

[0103] Since the source recess 42 matches the drain protrusion 43 adjacent to the second chip side surface 5B, the length of the source protrusion 41 in the first direction X is longer than the length of the drain protrusion 43 adjacent to the second chip side surface 5B by the wiring width of the source lead electrode 22. Therefore, the length of the source protrusion 41 in the first direction X is longer than the length of the drain protrusion 43 adjacent to the second chip side surface 5B.

[0104] The drain pad electrode 31 is formed in the first chip main surface 3 in a region closer to the fourth chip side surface 5D than the center in the second direction Y. Specifically, the drain pad electrode 31 is formed in approximately one-third of the region on the fourth chip side surface 5D in the first chip main surface 3. The drain pad electrode 31 is quadrilateral in plan view. The end edge 31a of the drain pad electrode 31 extends linearly in the second direction Y.

[0105] like Figure 6A and Figure 6B As shown, the drain pad electrode 31 is electrically connected to the plurality of drain wires 86 of the striped wiring 100 via a plurality of drain upper contacts (second contacts) 99. The drain pad electrode 31 and the drain wires 86 are electrically insulated from each other by a second interlayer insulating layer 17.

[0106] Multiple drain contacts 99 are formed within the second interlayer insulating layer 17. The multiple drain contacts 99 are disposed between the drain pad electrode 31 and the drain wiring 88. The multiple drain contacts 99 connect the drain pad electrode 31 to each drain wiring 86. The multiple drain contacts 99 are arranged along the drain wiring 86. The drain contacts 99 comprise a metal layer such as tungsten. Alternatively, a barrier layer (e.g., comprising at least one of Ti and TiN) may be formed on at least one of the front, back, and side surfaces of the metal layer, as needed.

[0107] The width W32 of the comb-shaped drain lead-out electrodes 32 in the second direction Y is equal to that of each other. The width W32 of the drain lead-out electrodes 32 is greater than the width W86 of the drain wiring 86 (reference). Figure 8 The width W32 of the drain lead 32 is greater than the width W85 of the source wiring 85 (reference). Figure 8 The width of the drain electrode 32 is equal to the width of the source electrode 22, W22. The width of the drain electrode 32 can also be greater than the width of the source electrode 22, W22. Alternatively, the width of the drain electrode 32 can be less than the width of the source electrode 22, W22.

[0108] like Figure 10 As shown, at least one pair of multiple drain leads 32 are connected to the source wiring 85 and the drain wiring 86 in a top view. Figure 10(In the example, there are 6 pairs) overlapping. The end edge 32a of the third chip side 5C side of the drain lead electrode 32 faces the end edge 21a of the source pad electrode 21 with a narrower width. The plurality of drain lead electrodes 32 engage with the plurality of source lead electrodes 22 at least at the center of the first direction X in the first chip main surface 3.

[0109] like Figures 10-11B As shown, multiple drain leads 32 are electrically connected to multiple drain leads 86 of striped wiring 100 via drain contacts 99. The multiple drain leads 32 are electrically insulated from the source leads 85 by a second interlayer insulating layer 17.

[0110] Multiple drain contacts 99 are configured between each drain lead-out electrode 32 and each drain wiring 86. These multiple drain contacts 99 connect the drain pad electrode 31 to each drain wiring 86. The multiple drain contacts 99 are arranged along the drain wiring 86. Figures 10-11B As shown, the drain contact 99 is formed in the region of the drain lead-out electrode 32 that overlaps with the drain wiring 86 when viewed from above. Figures 10-11B As shown, no drain contact 99 is formed in the region of the drain lead electrode 32 that overlaps with the source wiring 85 when viewed from above.

[0111] The drain electrode 32 extends in a serrated shape along the first direction X. The drain electrode 32 mates with the adjacent source electrode 22 (matching the adjacent source electrode 22). The drain electrode 32 includes a first drain extension 33, a first drain bend (a second bend, a third bend) 34, and a second drain bend 35. The first drain extension 33 extends from the drain pad electrode 31 toward the third chip side surface 5C and extends along the first direction X.

[0112] The first drain bending portion 34 bends towards the first chip side surface 5A after the first drain extension portion 33, and extends towards the third chip side surface 5C after bending, and extends along the first direction X. The second drain bending portion 35 bends towards the second chip side surface 5B after the first drain bending portion 34, and extends towards the third chip side surface 5C after bending, and extends along the first direction X.

[0113] The first drain bend 34 extends along the bending direction of the second source bend 25 of the adjacent source lead-out electrode 22. The first drain bend 34 is electrically connected to the drain terminal 99. The first drain bend 34 is electrically insulated from the source wiring 85 by a second interlayer insulation layer 17.

[0114] The first drain bending portion 34 includes a second drain extension 36 and a first drain connection portion 37. The second drain extension 36 extends along a first direction X in a region further from the third chip side surface 5C than the first drain extension 33, from a position offset relative to the first drain extension 33 towards the first chip side surface 5A. The second drain extension 36 is offset relative to the first drain extension 33 towards the first chip side surface 5A by a distance equal to that of the first drain extension 33. Specifically, the side edge 36b of the second drain extension 36 on the second chip side surface 5B side is aligned in the second direction Y with the side edge 33a of the first drain extension 33 on the first chip side surface 5A side.

[0115] The second drain extension 36 faces the first source extension 23 of the source electrode 22 adjacent to the first chip side surface 5A in the first direction X. The second drain extension 36 does not face the first drain extension 33 of the drain electrode 32 adjacent to the first chip side surface 5A in the first direction. The two side edges (side edge 36a and side edge 36b) of the second drain extension 36 are respectively aligned with the two side edges (side edge 23a and side edge 23b) of the first source extension 23 of the source electrode 22 adjacent to the first chip side surface 5A in the second direction Y.

[0116] The first drain connection portion 37 connects the first drain extension portion 33 to the second drain extension portion 36. The first drain connection portion 37 is inclined relative to the second direction Y in such a way that it moves closer to the third chip side surface 5C as it moves towards the first chip side surface 5A. The first drain connection portion 37, when viewed from above, traverses a plurality of source wirings 85 and a plurality of drain wirings 86.

[0117] The second drain bend 35 extends along the bending direction of the first source bend 24 of the adjacent source lead-out electrode 22. The second drain bend 35 is electrically connected to the drain terminal 99. The second drain bend 35 is electrically insulated from the source wiring 85 by a second interlayer insulation layer 17.

[0118] The second drain bend 35 includes a third drain extension 38 and a second drain connection 39. The third drain extension 38 extends from the first drain extension 33 toward the third chip side 5C in a region closer to the third chip side 5C than the first drain bend 34, along a first direction X. The third drain extension 38 faces the first drain extension 33 in the first direction X. The second drain connection 39 connects the second drain extension 36 to the third drain extension 38. The second drain connection 39 is inclined relative to the second direction Y, moving closer to the third chip side 5C as it moves toward the second chip side 5B. The second drain connection 39, when viewed from above, traverses a plurality of source wirings 85 and a plurality of drain wirings 86. A connection is formed by the first drain bend 34 and the second drain connection 39, connecting the first drain extension 33 and the third drain extension 38.

[0119] A drain protrusion 43 protruding toward the side surface 5A of the first chip is formed by the first drain bending portion 34 (the second drain extension portion 36 and the first drain connection portion 37) and the second drain connection portion 39.

[0120] The drain lead electrode 32 includes a drain recess 44 recessed towards the first chip side surface 5A. The drain recess 44 is divided by the side edge of the drain protrusion 43 on the second chip side surface 5B. The drain recess 44 mates with and accommodates the source protrusion 41 adjacent to the drain recess 44 on the second chip side surface 5B. In other words, the drain recess 44 engages with the source protrusion 41 adjacent to the second chip side surface 5B on the second direction Y at a distance.

[0121] Since the drain recess 44 matches the source protrusion 41 adjacent to the second chip side surface 5B, the distance in the first direction X of the drain protrusion 43 is longer than the distance in the first direction X of the source protrusion 41 adjacent to the second chip side surface 5B by the amount of wiring for the drain lead electrode 32. Therefore, the distance in the first direction X of the drain protrusion 43 is longer than the distance in the first direction X of the source protrusion 41 adjacent to the second chip side surface 5B.

[0122] As described above, the distance in the first direction X of the source protrusion 41 is longer than the distance in the first direction X of the drain protrusion 43 adjacent to the second chip side surface 5B. Furthermore, the distance in the first direction X of the drain protrusion 43 is longer than the distance in the first direction X of the source protrusion 41 adjacent to the second chip side surface 5B. Therefore, the distance in the first direction X of the source protrusion 41 and the drain protrusion 43 increases towards the second chip side surface 5B.

[0123] As shown above, according to the semiconductor device 1, a plurality of source lead-out electrodes 22 extend in a comb-like shape along the first direction X from the source pad electrode 21 formed on the second interlayer insulating layer 17 toward the fourth chip side surface 5D. The plurality of source lead-out electrodes 22 are electrically connected to a plurality of source wirings 85 of the striped wiring 100 covered by the second interlayer insulating layer 17. Furthermore, a plurality of drain lead-out electrodes 32 extend in a comb-like shape along the first direction X from the drain pad electrode 31 covered by the second interlayer insulating layer 17 toward the third chip side surface 5C. The plurality of drain lead-out electrodes 32 are electrically connected to a plurality of drain wirings 86 of the striped wiring 100 covered by the second interlayer insulating layer 17. Moreover, the plurality of drain lead-out electrodes 32 and the plurality of source lead-out electrodes 22 are engaged at intervals in the first direction X. The source lead-out electrode 22 can be used to shorten the current path from the source pad electrode 21 to the stripe wiring 100. Similarly, the drain lead-out electrode 32 can be used to shorten the current path from the drain pad electrode 31 to the stripe wiring 100. As a result, the wiring resistance can be reduced.

[0124] Furthermore, according to the semiconductor device 1, by forming a first source bend 24 (a source protrusion 41 protruding in the second direction Y) in the source lead-out electrode 22, the number of source wires 85 electrically connected to the source lead-out electrode 22 can be increased. Similarly, by forming a first drain bend 34 (a drain protrusion 43 protruding in the second direction Y) in the drain lead-out electrode 32, the number of drain wires 86 electrically connected to the drain lead-out electrode 32 can be increased. This further reduces the wiring resistance.

[0125] Furthermore, according to the semiconductor device 1, the source electrode 22 engages with the drain protrusion 43 adjacent to the second chip side surface 5B at a distance in the second direction Y. Similarly, the drain electrode 32 engages with the source protrusion 41 adjacent to the second chip side surface 5B at a distance in the second direction Y. Thus, the source protrusion 41 and the drain protrusion 43 can be formed without reducing the wiring area of ​​the source electrode 22 and the wiring area of ​​the drain electrode 32.

[0126] Furthermore, according to the semiconductor device 1, by forming a third source extension 28 on the source lead-out electrode 22, the current path that can be shortened by utilizing the source lead-out electrode 22 can be increased. This allows the current path from the source pad electrode 21 to the stripe wiring 100 to be shortened using the source lead-out electrode 22. Similarly, by forming a third drain extension 38 on the drain lead-out electrode 32, the current path that can be shortened by utilizing the drain lead-out electrode 32 can be increased. This allows the current path from the drain pad electrode 31 to the stripe wiring 100 to be shortened using the drain lead-out electrode 32. This further reduces wiring resistance.

[0127] Furthermore, according to the semiconductor device 1, the edge 21a of the source pad electrode 21 has a sloped portion 50, which is sloped towards the second chip side surface 5B and close to the drain pad electrode 31. This ensures that the width W48 of the source pad connection portion 48 is large. Therefore, the resistance of the source pad connection portion 48 of the source pad electrode 21 can be reduced. Consequently, wiring resistance can be further reduced.

[0128] Figure 12 This is a diagram showing the layout of the top wiring layer 94A involved in the reference example. Figures 13-16 This is a diagram illustrating the layout of the top wiring layers 94B to 94E according to the first to fourth variations of the present invention. Figures 12-16 Corresponding to Figure 9 .exist Figures 12-16 In the middle, to and Figures 1 to 11B The configuration shown is equivalent to the configuration, with additions and Figures 1 to 11B The same reference symbols are used in the same cases, and the explanation is omitted.

[0129] like Figure 12 As shown, the top wiring layer 94A of the reference example includes a source terminal electrode 20A and a drain terminal electrode 30A. The source terminal electrode 20A includes a source pad electrode 21AA. The source pad electrode 21AA is formed in approximately two-thirds of the area on the third chip side surface 5C, bypassing the formation area of ​​the gate terminal electrode 40 on the first chip main surface 3. The source terminal electrode 20A does not include a source lead electrode (equivalent to...). Figure 9 The source electrode 22). The drain terminal electrode 30A includes the drain pad electrode 31, but does not include the drain lead electrode (equivalent to...). Figure 9 Drain electrode 32).

[0130] like Figure 13 As shown, in the first variation, the top wiring layer 94B includes a source pad electrode 21B instead of the source pad electrode 21 (see reference). Figure 9 The edge 21Ba of the source pad electrode 21B is composed only of a straight portion 49 extending linearly in the second direction Y. Therefore, a second source pad region 47B, which is strip-shaped when viewed from above, is formed instead of a second source pad region 47. The first source pad region 46 and the second source pad region 47B are electrically connected through a source pad connection portion 48B.

[0131] In the source pad electrode 21B, the end edge 21Ba does not have a tilted portion (equivalent to...). Figure 9 The inclined portion 50). Therefore, the width W48B of the source pad connection portion 48B in the source pad electrode 21B is greater than that of the source pad electrode 21 (reference). Figure 9The width W48 of the source pad connection portion 48 in the ) (refer to Figure 9 Narrow. The other components of the top wiring layer 94B are the same as those of the top wiring layer 94 (see reference). Figure 9 )same.

[0132] like Figure 14 As shown, in the top wiring layer 94C of the second variation, the distance between the first source bend 24 and the first drain bend 34 in the first direction X (i.e., the distance between the second source extension 26 and the second drain extension 36 in the first direction X) is greater than that between the top wiring layer 94 (reference). Figure 9 Shorter. Furthermore, in the top wiring layer 94C, the widths W27C and W29C of the first source connection portion 27 and the second source connection portion 29 (for example, approximately 3 μm each) are shorter than the widths W27 and W29 of the first source connection portion 27 and the second source connection portion 29 in the top wiring layer 94 (refer to...). Figure 9 For example, they are each about 9 μm shorter. Furthermore, in the top wiring layer 94C, the widths 37C and W39C of the first drain connection portion 37 and the second drain connection portion 39 (for example, each about 3 μm) are shorter than the widths W37 and W39 of the first drain connection portion 37 and the second drain connection portion 39 in the top wiring layer 94 (see reference). Figure 9 For example, each is approximately 9μm short.

[0133] like Figure 15 As shown, in the third variation, the top wiring layer 94D includes a plurality of source lead-out electrodes 22D instead of a plurality of source lead-out electrodes 22. Similarly, in the third variation, the top wiring layer 94D includes a plurality of drain lead-out electrodes 32D instead of a plurality of drain lead-out electrodes 32.

[0134] Source electrode 22D does not include the second source bend (equivalent to Figure 9 The second source bend 25). Furthermore, the drain lead-out electrode 32D does not include a second drain bend (equivalent to...). Figure 9 The second drain electrode bend 35).

[0135] like Figure 16 As shown, in the fourth variation, the top wiring layer 94E includes a plurality of source lead-out electrodes 22E instead of a plurality of source lead-out electrodes 22. Similarly, in the fourth variation, the top wiring layer 94E includes a plurality of drain lead-out electrodes 32E instead of a plurality of drain lead-out electrodes 32.

[0136] The source lead electrode 22E includes several first source bends (first bend, third bend) 24E and second source bends (first bend, fourth bend) 25E that alternately repeat in the first direction X. The first source bend 24E is inclined relative to the second direction Y such that it approaches the first chip side 5A as it moves toward the fourth chip side 5D. The second source bend 25E is inclined relative to the second direction Y such that it approaches the second chip side 5B as it moves toward the fourth chip side 5D. The first source bend 24E and the second source bend 25E are electrically connected to the source wiring 85 (reference). Figure 10 ).

[0137] The drain lead electrode 32E includes several alternating first drain bends (second bends, third bends) 34E and second drain bends 35E in the first direction X. The first drain bends 34E are inclined relative to the second direction Y, moving closer to the first chip side 5A as they move towards the third chip side 5C. The second drain bends 35E are inclined relative to the second direction Y, moving closer to the second chip side 5B as they move towards the third chip side 5C. The first drain bends 34E and the second drain bends 35E are electrically connected to drain wiring 86 (reference). Figure 10 ).

[0138] Based on the second to fourth variations, the related embodiments are implemented (see reference). Figure 9 The effects described are equivalent to those of the previous effects.

[0139] Furthermore, similar to the top wiring layer 94B in the first variation, the top wiring layers 94C to 94E in the second to fourth variations include source pad electrodes 21B instead of source pad electrodes 21 (see reference). Figure 9 The top wiring layers 94C to 94E may also include source pad electrode 21 instead of source pad electrode 21B.

[0140] Table 1 shows the embodiments (for reference). Figure 9 The table shows the wiring resistance of the top wiring layers 94 to 94E involved in the reference example and the variations 1 to 4. Table 1 shows the value when the wiring resistance of the top wiring layer 94A in the reference example is set to 1 (100%).

[0141] [Table 1]

[0142] Table 1

[0143]

[0144] As shown in Table 1, the embodiments (reference) Figure 9 The top wiring layer 94 has the lowest wiring resistance. It can be seen that the second lowest resistance is in the first variation example (see reference). Figure 13The wiring resistor of the top wiring layer 94B, followed by the second variation example (see reference). Figure 14 The top wiring layer of the 94C wiring resistor.

[0145] Figures 17-19 This is a diagram illustrating the layout of the top wiring layers 94F to 94H according to the 5th to 7th variations of the present invention. Figures 17-19 Corresponding to Figure 9 .

[0146] like Figure 17 As shown, in the fifth variation, the top wiring layer 94F includes a plurality of source lead-out electrodes 22F instead of a plurality of source lead-out electrodes 22. The source lead-out electrodes 22F include a first source extension 23, a first source bend (first bend, third bend) 24F, and a second source bend (first bend, fourth bend) 25F. The bending direction of the first source bend 24F and the second source bend 25F is in the second direction Y, which is the same as in the embodiment (reference). Figure 9 The bending directions of the first source bending portion 24F and the second source bending portion 25F are opposite.

[0147] In the fifth variation, the top wiring layer 94F includes a plurality of drain leads 32F instead of a plurality of drain leads 32. The drain leads 32F include a first drain extension 33, a first drain bend (a second bend, a third bend) 34F, and a second drain bend 35F. The bending direction of the first drain bend 34F and the second drain bend 35F is in the second direction Y, which is the same as in the embodiment (see reference). Figure 9 The bending directions of the first drain bending portion 34F and the second drain bending portion 35F are opposite.

[0148] like Figure 18 As shown, in the sixth variation, the top wiring layer 94G includes a plurality of source lead-out electrodes 22G instead of a plurality of source lead-out electrodes 22. The source lead-out electrodes 22G include a first source extension 23, a first source bend (first bend, third bend) 24G and a second source bend 25.

[0149] The first source bending portion 24G includes a second source extension portion 26G and a first source connection portion 27. The second source extension portion 26G extends along the first direction X while being offset relative to the first source extension portion 23 towards the first chip side surface 5A. The second source extension portion 26G is offset relative to the first source extension portion 23 towards the first chip side surface 5A by half the distance of the first source extension portion 23.

[0150] In the sixth variation, the top wiring layer 94G includes multiple drain lead-out electrodes 32G instead of multiple drain lead-out electrodes 32. Each drain lead-out electrode 32G includes a first drain extension 33, a first drain bend (a second bend, a third bend) 34G, and a second drain bend 35. The first drain bend 34G includes a second drain extension 36G and a first drain connection 37. The second drain extension 36G extends along the first direction X while being offset relative to the first drain extension 33 towards the first chip side surface 5A. The second drain extension 36G is offset relative to the first drain extension 33 towards the first chip side surface 5A by half the distance of the first drain extension 33.

[0151] like Figure 19 As shown, in the seventh variation, the top wiring layer 94H includes a plurality of source lead-out electrodes 22H instead of a plurality of source lead-out electrodes 22. Similarly, in the seventh variation, the top wiring layer 94H includes a plurality of drain lead-out electrodes 32H instead of a plurality of drain lead-out electrodes 32.

[0152] The plurality of drain leads 32H include a first drain extension 33H and a drain protrusion 43H. The first drain extension 33H extends from the drain pad electrode 31 toward the third chip side surface 5C and extends along the first direction X. The drain protrusion 43H protrudes from the middle portion of the first drain extension 33H toward the first chip side surface 5A.

[0153] The source lead-out electrode 22H includes a first source extension 23H and a source recess 42H. The first source extension 23H extends from the source pad electrode 21 toward the fourth chip side surface 5D and extends along the first direction X. The source recess 42H is divided by the side edge of the first source extension 23H on the second chip side surface 5B.

[0154] The source recess 42H matches the drain protrusion 43H of the drain lead-out electrode 32H adjacent to the side of the second chip 5B, and engages with the drain protrusion 43H in the second direction Y.

[0155] exist Figure 19 In this example, the drain protrusion 43H may also protrude toward the second chip side 5B side, rather than the first chip side 5A side. In this case, a source recess 42H that engages with the drain protrusion 43H in the second direction Y is formed on the side edge of the source lead electrode 22H adjacent to the drain protrusion 43H on the second chip side 5B side.

[0156] In addition, the combination of the source and drain electrodes in the protrusion and the recess can also be combined with... Figure 19The opposite is true. A protrusion (i.e., a source protrusion) may be formed in the first source extension 23H of the source electrode 22H, and a recess (i.e., a drain recess) that engages with the protrusion in the second direction Y may be formed in the first drain extension 33H of the drain electrode 32H.

[0157] Based on variations 5 to 7, the associated embodiments are implemented (see reference). Figure 9 The effects described are equivalent to those of the previous effects.

[0158] Furthermore, the drain wiring 86 may not be commonly connected to the drain regions 68 of the well regions 66 contained in adjacent unit cells 60; instead, the drain wiring 86 may only connect to one of the drain regions 68. That is, the drain wiring 86 may also be formed in a one-to-one correspondence with the drain regions 68. In this case, in the striped wiring 100, the plurality of source wirings 85 and the plurality of drain wirings 86 are arranged in the second direction Y in the order of drain wiring 86, source wiring 85, drain wiring 86, drain wiring 86, source wiring 85, drain wiring 86, drain wiring 86...

[0159] For example, the semiconductor chip 10 does not necessarily have to be rectangular when viewed from above; it can also be square or other quadrilateral shapes when viewed from above.

[0160] In each of the aforementioned configurations, a structure without the side insulating layer 15 may also be used. In this case, the sides 13A to 13D of the semiconductor chip 10 are respectively formed as a portion of the chip sides 5A to 5D of the chip body 2.

[0161] Furthermore, in the embodiments described, the components built into the semiconductor device 1 are not limited to MOSFET structures; for example, other components such as IGBTs (Insulated Gate Bipolar Transistors) and bipolar transistors may also be used.

[0162] In addition, various design changes can be implemented within the scope of the claims.

[0163] [Explanation of Symbols]

[0164] 1: Semiconductor devices

[0165] 16: First interlayer insulation layer (first insulation layer)

[0166] 17: Second interlayer insulation layer (second insulation layer)

[0167] 21: Source pad electrode (first pad electrode)

[0168] 21B: Source pad electrode (first pad electrode)

[0169] 22: Source electrode (first electrode)

[0170] 22D: Source electrode (first lead-out electrode)

[0171] 22E: Source electrode (first lead-out electrode)

[0172] 22F: Source electrode (first lead-out electrode)

[0173] 22G: Source electrode (first lead-out electrode)

[0174] 22H: Source electrode (first electrode)

[0175] 23: First source extension (first extension)

[0176] 23H: First source extension (first extension)

[0177] 24: First source electrode bending section (first bending section, third bending section)

[0178] 24E: First source electrode bending section (first bending section, third bending section)

[0179] 24F: First source electrode bend (first bend, third bend)

[0180] 24G: First source electrode bending section (first bending section, third bending section)

[0181] 24H: Source electrode protrusion (protrusion)

[0182] 25: Second source electrode bending section (first bending section, fourth bending section)

[0183] 25E: Second source electrode bend (first bend, fourth bend)

[0184] 25F: Second source electrode bend (first bend, fourth bend)

[0185] 26: Second source extension (second extension)

[0186] 28: Third source extension (third extension)

[0187] 31: Drain pad electrode (second pad electrode)

[0188] 32: Drain electrode (second lead-out electrode)

[0189] 32D: Drain electrode (second lead-out electrode)

[0190] 32E: Drain electrode (second lead-out electrode)

[0191] 32F: Drain lead-out electrode (second lead-out electrode)

[0192] 32G: Drain lead-out electrode (second lead-out electrode)

[0193] 32H: Drain electrode (second lead-out electrode)

[0194] 34: First drain bend (second bend, third bend)

[0195] 34E: First drain bend (second bend, third bend)

[0196] 34F: First drain bend (second bend, third bend)

[0197] 34G: First drain bend (second bend, third bend)

[0198] 41: Source pole protrusion (protrusion)

[0199] 41H: Source electrode protrusion (protrusion)

[0200] 42: Source electrode recess (recess)

[0201] 43: Drain protrusion (protrusion)

[0202] 44: Drain recess (recess)

[0203] 44H: Drain recess (recess)

[0204] 53A: MOSFET structure (field-effect transistor)

[0205] 60: Unit

[0206] 85: Source wiring (first wiring)

[0207] 86: Drain wiring (second wiring)

[0208] 98: Source upper contact (first contact)

[0209] 99: Drain upper contact (second contact)

[0210] 100: Striped stitching

[0211] 100a: 1st end

[0212] 100b: Second end

[0213] X: First direction

[0214] Y: 2nd direction.

Claims

1. A semiconductor device comprising: First insulating layer; The striped wiring includes a plurality of first wirings and a plurality of second wirings, the plurality of first wirings and the plurality of second wirings extending along a first direction on the first insulating layer and arranged at intervals in a second direction intersecting the first direction, the striped wirings having a first end on one side of the first direction and a second end on the other side of the first direction; A second insulating layer covers the striped wiring over the first insulating layer; The first pad electrode is disposed on the first end side of the striped wiring above the second insulating layer and is electrically connected to a plurality of the first wirings; A plurality of first lead-out electrodes extend in a comb-like manner from the first pad electrode to the second end side of the striped wiring over the second insulating layer, and are electrically connected to the plurality of the first wirings at the second end side of the striped wiring relative to the first pad electrode; A second pad electrode is disposed on the second end side of the striped wiring above the second insulating layer and is electrically connected to a plurality of the second wirings; and A plurality of second lead electrodes, on the second insulating layer, are led out in a comb-like pattern from the second pad electrode toward the first end side of the striped wiring in a manner engaging with a plurality of the first lead electrodes, and are electrically connected to a plurality of the second wirings at the first end side of the striped wiring relative to the second pad electrode; and The first lead-out electrode includes a first bent portion that bends in the second direction; The second lead-out electrode includes a second bend that extends along the bending direction of the first bend.

2. The semiconductor device according to claim 1, wherein The first lead electrode is electrically insulated from the plurality of the second wirings. The second lead electrode is electrically insulated from the plurality of the first wirings.

3. The semiconductor device according to claim 1 or 2, wherein The striped wiring includes multiple pairs of the first wiring and the second wiring. At least one of the first lead-out electrode and the second lead-out electrode overlaps with at least one pair of the first wiring and the second wiring when viewed from above.

4. The semiconductor device of claim 1, further comprising: A first contact, formed within the second insulating layer, electrically connects the first wiring to the first solder pad electrode; and The second contact, formed within the second insulating layer, electrically connects the second wiring to the second solder pad electrode. The first bend is electrically connected to the first contact and is electrically insulated from the second wiring by the second insulating layer. The second bend is electrically connected to the second contact and is electrically insulated from the first wiring by the second insulating layer.

5. The semiconductor device according to claim 1, wherein The first curved section, when viewed from above, traverses multiple first wirings and multiple second wirings. The second bend, when viewed from above, traverses multiple of the first wirings and multiple of the second wirings.

6. The semiconductor device according to claim 1, wherein The first lead-out electrode includes a plurality of the first bent portions. The second lead-out electrode includes a plurality of the second bends.

7. The semiconductor device according to claim 6, wherein The first lead-out electrode extends in a serrated shape in the first direction. The second lead-out electrode extends in a serrated shape in the first direction in a manner that matches the first lead-out electrode.

8. The semiconductor device according to claim 1, wherein The first lead electrode further includes a first extension portion extending from the first pad electrode in the first direction. The first curved portion includes a third curved portion that curves from the first extension portion toward one side in the second direction. The second lead electrode further includes a recessed portion that is recessed to one side in the second direction and engages with the third curved portion.

9. The semiconductor device according to claim 8, wherein The third bend includes a second extension that extends along the first direction from a position offset relative to the first extension toward the second direction, closer to the second end of the second extension.

10. The semiconductor device of claim 9, wherein The second extension is opposite to the second lead-out electrode in the first direction.

11. The semiconductor device of claim 10, wherein The second extension is not opposite to the first extension of the first lead electrode adjacent to the side in the second direction in the first direction.

12. The semiconductor device according to any one of claims 8 to 11, wherein The first curved portion also includes a fourth curved portion that bends toward the other side in the second direction.

13. The semiconductor device of claim 12, wherein The fourth bend includes a third extension that extends along the first direction from the first extension toward the second end, closer to the second end than the third bend.

14. The semiconductor device of claim 13, wherein The third extension faces the first extension in the first direction.

15. The semiconductor device of claim 1, further comprising: Semiconductor chips have a main surface; and A field-effect transistor is formed on the main surface and includes a plurality of unit cells extending along the first direction; The first insulating layer covers the plurality of the unit cells. The first wiring includes one of the source wiring and one of the drain wiring. The second wiring includes the source wiring and another of the drain wiring.

16. The semiconductor device of claim 15, wherein The unit cell has a planar gate structure.

17. The semiconductor device according to claim 15 or 16, wherein The first wiring includes the source wiring. The second wiring includes the drain wiring. The first pad electrode includes source pad electrodes that are electrically connected to the plurality of source wirings. The second pad electrode includes a drain pad electrode that is electrically connected to the plurality of drain wirings. The portion of the source pad electrode facing the drain pad electrode includes a straight portion extending along the second direction and an inclined portion inclined relative to the straight portion.

18. A semiconductor device comprising: First insulating layer; The striped wiring includes a plurality of first wirings and a plurality of second wirings, the plurality of first wirings and the plurality of second wirings extending along a first direction on the first insulating layer and arranged at intervals in a second direction intersecting the first direction, the striped wirings having a first end on one side of the first direction and a second end on the other side of the first direction; A second insulating layer covers the striped wiring over the first insulating layer; The first pad electrode is disposed on the first end side of the striped wiring above the second insulating layer and is electrically connected to a plurality of the first wirings; A first lead electrode extends from the first pad electrode toward the second end of the striped wiring in the first direction above the second insulating layer, and is electrically connected to a plurality of the first wirings at the second end of the striped wiring relative to the first pad electrode. A second pad electrode is disposed on the second end side of the striped wiring above the second insulating layer and is electrically connected to a plurality of the second wirings; and The second lead electrode extends from the second pad electrode toward the first end of the striped wiring in the first direction above the second insulating layer, and is electrically connected to a plurality of the second wirings relative to the second pad electrode at the first end of the striped wiring. One of the first lead-out electrodes and the second lead-out electrode includes a protrusion extending toward one side in the second direction. The first lead electrode and the second lead electrode each include a recessed portion that is recessed to one side in the second direction and engages with the protrusion.

19. A semiconductor device comprising: First insulating layer; The striped wiring includes a plurality of first wirings and a plurality of second wirings, the plurality of first wirings and the plurality of second wirings extending along a first direction on the first insulating layer and arranged at intervals in a second direction intersecting the first direction, the striped wirings having a first end on one side of the first direction and a second end on the other side of the first direction; A second insulating layer covers the striped wiring over the first insulating layer; The first pad electrode is disposed on the first end side of the striped wiring above the second insulating layer and is electrically connected to a plurality of the first wirings; A first lead electrode extends from the first pad electrode toward the second end of the striped wiring in the first direction above the second insulating layer, and is electrically connected to a plurality of the first wirings at the second end of the striped wiring relative to the first pad electrode. The second pad electrode is disposed on the second end side of the striped wiring above the second insulating layer and is electrically connected to a plurality of the second wirings; as well as The second lead electrode extends from the second pad electrode toward the first end of the striped wiring in the first direction above the second insulating layer, and is electrically connected to a plurality of the second wirings at the first end of the striped wiring relative to the second pad electrode. At least one of the first lead-out electrode and the second lead-out electrode comprises: The first extension extends along the first direction; The third extension extends along the first direction away from the first extension toward the second end side or the first end side; as well as The connecting part connects the first extension part and the third extension part.

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