A differential phase change storage unit structure, phase change memory and driving method

Abstract

The present invention relates to a differential phase-change memory cell structure, a phase-change memory and a driving method. The gate end of the first gating device, the gate end of the second gating device and the gate end of the third gating device of the differential phase-change memory cell structure are connected together as the word line of the differential phase-change memory cell structure, the source end of the first gating device and the source end of the second gating device are both grounded, the drain or source of the third gating device, the drain of the first gating device, and the first end of the first phase-change resistor are connected together, the source or drain of the third gating device, the drain of the second gating device and the first end of the second phase-change resistor are connected together; the second end of the first phase-change resistor is connected to the first bit line, and the second end of the second phase-change resistor is connected to the second bit line. The present invention can achieve high-speed drive memory performance with a smaller array area without the need for an external reference resistor.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to a differential phase change storage unit structure, a phase change memory and a driving method. Background Art

[0002] With the advent of the big data era, there is a huge amount of data that needs to be processed, and it is particularly important to improve the performance of computing systems. However, due to the separation of processors and memory in the commonly used von Neumann architecture, the technical development of the two cannot be synchronized. In the past 20 years, the performance of processors has increased by about 55% per year, while the performance of memory has increased by only about 10% per year. In the long run, the performance of memory has seriously restricted the improvement of system performance, and the high performance of processors has been difficult to play to its actual level. This is the "Memory Wall" problem proposed by scientists in 1994. Therefore, it is urgent to solve the problem of the "Memory Wall", that is, to improve the performance of memory.

[0003] Phase-Change Memory (PCM), as a new type of non-volatile memory, has become one of the strong candidates for the next generation of memory due to its high density, low power consumption, and process compatibility. Traditional phase-change memory uses 1T1R as a single storage unit (see Figure 1 ), the phase change memory under this structure needs an external reference resistor for comparison during the read operation, so the comparison interval is small, there is a certain probability of reading errors, and the reading and writing speed is slow. On this basis, the current solutions proposed include using a 2T2R structure as a single storage unit (see Figure 2 ) is used as a high-speed phase change memory. This structure can greatly improve the read operation speed because it can compare between two opposite resistances in the unit during the read operation, while increasing the comparison margin and reducing the error probability. However, its disadvantages cannot be ignored: the size of the two selection devices must be designed to be sufficient to bear the current of the RESET operation. For a memory, it has a large number of storage cells, and the 2T2R structure of the storage cell will greatly increase the area of ​​the memory. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a differential phase change memory cell structure, a phase change memory and a driving method, which can achieve high-speed driving memory performance with a smaller array area without the need for an external reference resistor.

[0005] The technical solution adopted by the present invention to solve its technical problem is: providing a differential phase change memory cell structure, including a first gating device, a second gating device, a third gating device, a first phase change resistor and a second phase change resistor; the gate end of the first gating device, the gate end of the second gating device and the gate end of the third gating device are connected together as the word line of the differential phase change memory cell structure, the source end of the first gating device and the source end of the second gating device are both grounded, the drain or source of the third gating device, the drain of the first gating device, and the first end of the first phase change resistor are connected together, the source or drain of the third gating device, the drain of the second gating device and the first end of the second phase change resistor are connected together; the second end of the first phase change resistor is connected to the first bit line, and the second end of the second phase change resistor is connected to the second bit line.

[0006] The first gating device and the second gating device have exactly the same size.

[0007] The first phase-change resistor and the second phase-change resistor are completely the same.

[0008] The first gating device, the second gating device and the third gating device are all NMOS tubes.

[0009] The technical solution adopted by the present invention to solve the technical problem is: to provide a phase change memory, which is composed of a plurality of the above-mentioned differential phase change storage unit structures.

[0010] A driving method for a phase change memory is provided, which initializes the differential phase change memory cell structure to be operated so that the resistance states of the first phase change resistor and the second phase change resistor are opposite; when performing a write operation, the first gating device, the second gating device and the third gating device are turned on through the word line; and pulse currents are respectively generated on the first bit line and the second bit line to change the resistance state of the first phase change resistor or the second phase change resistor, thereby writing data in the differential phase change memory cell structure.

[0011] When pulse currents are generated on the first bit line and the second bit line respectively, if the first bit line is added with SET current, then the second bit line is RESET current, which defines that the differential phase change memory cell structure writes 1; if the first bit line is added with RESET current, then the second bit line is SET current, which defines that the differential phase change memory cell structure writes 0.

[0012] When performing a read operation, the first selection device, the second selection device and the third selection device are turned on through the word line, the same clamping voltage is applied to the first bit line and the second bit line, and the current flowing through the first phase change resistor and the second phase change resistor is converted into a voltage through a sensitive amplifier and compared, thereby reading the data in the differential phase change storage cell structure.

[0013] The currents flowing through the first phase-change resistor and the second phase-change resistor are converted into voltages through a sensitive amplifier and compared. If the resistance of the first phase-change resistor is smaller than the resistance of the second phase-change resistor, the data in the differential phase-change storage unit structure is 1; if the resistance of the first phase-change resistor is greater than the resistance of the second phase-change resistor, the data in the differential phase-change storage unit structure is 0.

[0014] Beneficial Effects

[0015] Due to the adoption of the above technical solution, the present invention has the following advantages and positive effects compared with the prior art: the present invention connects three gate tubes and two phase change resistors to realize a unit structure of one word line and two bit lines, wherein the third gate tube is used as a transmission tube during read and write operations, so that the size of the first gate tube and the second gate tube can be reduced, and the phase change storage unit is applied to the phase change memory to achieve high-speed drive memory performance with a smaller array area without the need for an external reference resistor. In the era of big data, the present invention can effectively alleviate the "memory wall" problem and improve the computing power of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of a storage unit of a 1T1R structure in the prior art;

[0017] Figure 2 is a schematic diagram of a storage unit of a 2T2R structure in the prior art;

[0018] Figure 3 is a schematic diagram of a differential phase change memory cell structure according to a first embodiment of the present invention;

[0019] Figure 4 is a schematic diagram of the differential phase-change memory cell structure of the first embodiment of the present invention when the source and drain of the third gating device are interchanged;

[0020] Figure 5 is a flow chart of the driving method according to the third embodiment of the present invention when performing a write operation;

[0021] Figure 6 is a flow chart of the driving method according to the third embodiment of the present invention when performing a read operation;

[0022] Figure 7 It is a schematic diagram of the read and write timing in an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.

[0024] The first embodiment of the present invention relates to a differential phase change memory cell structure, such as Figure 3 As shown, it includes a gate tube M1, a gate tube M2, a gate tube M3, and a phase change resistor R1 and a phase change resistor R2; the gate tubes M1, M2 and M3 are all NMOS tubes; the phase change resistor R1 and the phase change resistor R2 are both composed of phase change materials. The gate tubes M1 and M2 have the same size, and the phase change resistors R1 and R2 are exactly the same. The gates of the gate tubes M1, M2 and M3 are connected together and connected to the word line WL, the sources of the gate tubes M1 and M2 are grounded, the drain of the gate tube M3 is connected to the drain of the gate tube M1, and is connected to one end of the phase change resistor R1, the other end of the phase change resistor R1 is connected to the first bit line BL, the source of the gate tube M3, the drain of the gate tube M2 and one end of the phase change resistor R2 are connected together, and the other end of the phase change resistor R2 is connected to the second bit line BLB.

[0025] Figure 4 The embodiment shown is that the source of the gate tube M3 is connected to the drain of the gate tube M1 and is connected to one end of the phase change resistor R1, the drain of the gate tube M3, the drain of the gate tube M2, and one end of the phase change resistor R2 are connected together, and the other parts are connected to Figure 3 same.

[0026] It can be seen that by connecting three gate tubes and two phase change resistors, a unit structure of one word line and two bit lines is realized, wherein the third gate tube is used as a transmission tube during read and write operations, so that the sizes of the first gate tube and the second gate tube can be reduced. Applying the phase change memory unit to a phase change memory can achieve high-speed driving memory performance with a smaller array area without the need for an external reference resistor.

[0027] The second embodiment of the present invention relates to a phase change memory, which is composed of a plurality of differential phase change memory cell structures of the first embodiment. The third embodiment of the present invention is a driving method of the phase change memory, which includes a read operation process and a write operation process. Figure 5 is a flowchart for performing a write operation; Figure 6 To perform a read operation, Figure 7 This is the read and write timing diagram of the driving method, combined with Figure 3 or Figure 4 Conduct analysis.

[0028] First, the differential phase-change memory cell structure needs to be initialized so that the resistance states of the first phase-change resistor R1 and the second phase-change resistor R2 are opposite.

[0029] When performing a write operation, the word line WL controls the gate to turn on the gate tubes M1, M2, and M3. At this time, the gate tube M3 acts as a transmission tube, and the two current pulses generated by the peripheral circuit are respectively added to the first bit line BL and the second bit line BLB, thereby changing the resistance state of the phase change resistor R1 and the phase change resistor R2, and successfully writing data. When the first bit line BL is SET operation and the second bit line BLB is RESET operation, data 1 is written; when the first bit line BL is RESET operation and the second bit line BLB is SET operation, data 0 is written.

[0030] For other unselected cells in the phase change memory, the gate tubes M1, M2 and M3 are turned off, and the gate tube M3 isolates the phase change resistor R1 and the phase change resistor R2, thereby avoiding the problem of write crosstalk.

[0031] When performing a read operation, the word line WL controls the gate to turn on the gate tube M1, the gate tube M2 and the gate tube M3. At this time, the gate tube M3 acts as a transmission tube, and the peripheral circuit generates two clamping voltages of the same magnitude and applies them to the first bit line BL and the second bit line BLB respectively. The current flowing through the phase change resistor R1 and the phase change resistor R2 is converted into a voltage by the sensitive amplifier and the magnitude is compared, thereby reading the data in the storage unit. When the phase change resistor R1 is in a high resistance state and the phase change resistor R2 is in a low resistance state, the voltage across the phase change resistor R1 is greater than the voltage across the phase change resistor R2, and the read data is 1; when the phase change resistor R1 is in a low resistance state and the phase change resistor R2 is in a high resistance state, the voltage across the phase change resistor R1 is less than the voltage across the phase change resistor R2, and the read data is 0.

[0032] It is not difficult to find that the present invention connects three gate tubes and two phase change resistors to realize a unit structure of one word line and two bit lines, wherein the third gate tube is used as a transmission tube during read and write operations, so that the size of the first gate tube and the second gate tube can be reduced, and the phase change storage unit is applied to the phase change memory, which can realize high-speed drive memory performance with a smaller array area without the need for an external reference resistor. In the era of big data, the present invention can effectively alleviate the "memory wall" problem and improve the computing power of the system.

Claims

1. A differential phase change memory cell structure, characterized in that: It includes a first gating device, a second gating device, a third gating device, a first phase change resistor and a second phase change resistor; the gate end of the first gating device, the gate end of the second gating device and the gate end of the third gating device are connected together as the word line of the differential phase change storage unit structure, the source end of the first gating device and the source end of the second gating device are both grounded, the drain or source of the third gating device, the drain of the first gating device, and the first end of the first phase change resistor are connected together, the source or drain of the third gating device, the drain of the second gating device and the first end of the second phase change resistor are connected together; the second end of the first phase change resistor is connected to the first bit line, and the second end of the second phase change resistor is connected to the second bit line.

2. The differential phase change memory cell structure according to claim 1, characterized in that: The first gating device and the second gating device have exactly the same size.

3. The differential phase change memory cell structure according to claim 1, characterized in that: The first phase-change resistor and the second phase-change resistor are completely the same.

4. The differential phase change memory cell structure according to claim 1, characterized in that: The first gating device, the second gating device and the third gating device are all NMOS tubes.

5. A phase change memory, characterized in that: The invention is composed of a plurality of differential phase change memory cell structures as claimed in any one of claims 1 to 4.

6. A driving method using the phase change memory according to claim 5, characterized in that: Initialize the differential phase change memory cell structure to be operated so that the resistance states of the first phase change resistor and the second phase change resistor are opposite; when performing a write operation, turn on the first gating device, the second gating device and the third gating device through the word line; generate pulse currents on the first bit line and the second bit line respectively to change the resistance state of the first phase change resistor or the second phase change resistor, thereby writing data in the differential phase change memory cell structure.

7. The driving method according to claim 6, characterized in that: When pulse currents are generated on the first bit line and the second bit line respectively, if the first bit line is added with SET current, then the second bit line is RESET current, which defines that the differential phase change memory cell structure writes 1; if the first bit line is added with RESET current, then the second bit line is SET current, which defines that the differential phase change memory cell structure writes 0.

8. The driving method according to claim 6, characterized in that: When performing a read operation, the first selection device, the second selection device and the third selection device are turned on through the word line, the same clamping voltage is applied to the first bit line and the second bit line, and the current flowing through the first phase change resistor and the second phase change resistor is converted into a voltage through a sensitive amplifier and compared, thereby reading the data in the differential phase change storage cell structure.

9. The driving method according to claim 8, characterized in that: When the current flowing through the first phase change resistor and the second phase change resistor is converted into voltage through a sensitive amplifier and compared, if the resistance value of the first phase change resistor is smaller than the resistance value of the second phase change resistor, the data in the differential phase change storage unit structure is 1; if the resistance value of the first phase change resistor is greater than the second phase change resistor, the data in the differential phase change storage unit structure is 0.

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