Plasma processing apparatus and plasma processing method

Abstract

This invention provides a plasma processing apparatus and a plasma processing method capable of appropriately controlling the tilt angle of an edge region of a substrate and suppressing discharge between the substrate and the edge ring during plasma processing. The plasma processing apparatus includes: a chamber; a stage disposed inside the chamber, having electrodes, an electrostatic chuck disposed on the electrodes, and an edge ring disposed on the electrostatic chuck to surround a substrate placed on the electrostatic chuck; a high-frequency power supply for supplying high-frequency electrical power for generating plasma from gas inside the chamber; a DC power supply for applying a negative DC voltage to the edge ring; and a control unit for controlling the high-frequency electrical power and the DC voltage. The process includes the following steps: step (a), stopping the supply of high-frequency electrical power and stopping the application of DC voltage; and step (b), starting the supply of high-frequency electrical power, and after a predetermined delay time, starting the application of DC voltage.

Description

Technical Field

[0001] This invention relates to plasma processing apparatus and plasma processing method. Background Technology

[0002] Patent Document 1 discloses a plasma processing apparatus comprising: a stage for mounting a wafer disposed within a chamber; and an edge ring disposed on the stage in a manner surrounding the wafer. The plasma processing apparatus is capable of performing plasma processing on the wafer. In this plasma processing apparatus, by applying a negative DC voltage to the edge ring consumed by the plasma, deformation of the sheath layer can be eliminated, allowing ions to be perpendicularly incident on the entire surface of the wafer.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2008-227063 Summary of the Invention

[0006] The technical problem that the invention aims to solve

[0007] The technique of the present invention is used to properly control the tilt angle of the edge region of a substrate in plasma processing and to suppress discharge between the substrate and the edge ring.

[0008] Means for solving technical problems

[0009] One aspect of the present invention is an apparatus for plasma treatment of a substrate, characterized in that it comprises: a chamber; a stage disposed inside the chamber having electrodes, an electrostatic chuck disposed on the electrodes, and an edge ring disposed on the electrostatic chuck to surround a substrate disposed on the electrostatic chuck; a high-frequency power supply for supplying high-frequency electrical power for generating plasma from gas inside the chamber; a DC power supply for applying a negative DC voltage to the edge ring; and a control unit for controlling the high-frequency electrical power and the DC voltage, the control unit controlling the apparatus to perform a process comprising the steps of: step (a), stopping the supply of the high-frequency electrical power and stopping the application of the DC voltage; and step (b), starting the supply of the high-frequency electrical power and, after a predetermined delay time, starting the application of the DC voltage.

[0010] Invention Effects

[0011] Using this invention, the tilt angle of the edge region of the substrate can be properly controlled during plasma processing, and the discharge between the substrate and the edge ring can be suppressed. Attached Figure Description

[0012] Figure 1 This is a longitudinal cross-sectional view showing the general configuration of the plasma processing apparatus of this embodiment.

[0013] Figure 2 This is an explanatory diagram of the power supply system that applies DC voltage to the edge ring in this embodiment.

[0014] Figure 3 This is an explanatory diagram showing the previous RF on / off, DC on / off, and power-off switching.

[0015] Figure 4 This is an explanatory diagram showing the RF on / off, DC on / off, and power-off switching in this embodiment.

[0016] Figure 5 This is an explanatory diagram showing the changes in high-frequency electrical power and DC voltage over time in this embodiment.

[0017] Figure 6 It means Figure 5 The table shows the states of RF on / off, DC on / off, and power off.

[0018] Figure 7 It means Figure 5 A diagram illustrating the states of the DC power supply circuit and the current removal circuit.

[0019] Figure 8 This is an illustration of a power supply system that applies a DC voltage to the edge ring in another embodiment.

[0020] Figure 9 This is an illustration of a power supply system that applies a DC voltage to the edge ring in another embodiment.

[0021] Figure 10 This is an illustration of a power supply system that applies a DC voltage to the edge ring in another embodiment.

[0022] Explanation of reference numerals in the attached figures

[0023] 1. Plasma processing device, 10. Chamber, 11. Stage, 12. Lower electrode, 13. Electrostatic chuck, 14. Edge ring, 50. First high-frequency power supply, 51. Second high-frequency power supply, 60. DC power supply, 100. Control unit, W. Wafer. Detailed Implementation

[0024] In the manufacturing process of semiconductor devices, semiconductor wafers (hereinafter referred to as "wafers") undergo plasma treatment. In plasma treatment, plasma is generated by exciting a process gas, and this plasma is used to process the wafer.

[0025] Plasma processing is performed by a plasma processing apparatus. A plasma processing apparatus generally includes a chamber, a stage, and a high-frequency (RF) power supply. In one example, the RF power supply includes a first RF power supply and a second RF power supply. The first RF power supply provides a first RF electrical power to generate plasma in the gas within the chamber. The second RF power supply provides a second RF electrical power for biasing the lower electrode, used to introduce ions into the wafer. The internal space of the chamber is configured as a processing space capable of generating plasma. The stage is disposed within the chamber. The stage has a lower electrode and an electrostatic chuck. The electrostatic chuck is disposed on the lower electrode. An edge ring can be configured on the electrostatic chuck to surround the wafer placed on it. The edge ring is provided to improve the uniformity of plasma processing of the wafer.

[0026] The edge ring is consumed over time as plasma treatment is performed. As the edge ring is consumed, its thickness decreases. As the edge ring thickness decreases, the shape of the sheath layer above the edge ring and the edge region of the wafer changes. When the shape of the sheath layer changes as described above, the incident direction of ions in the edge region of the wafer is tilted relative to the vertical direction. As a result, the opening formed in the edge region of the wafer is tilted relative to the thickness direction of the wafer.

[0027] In order to form an opening extending parallel to the thickness direction of the wafer in the edge region, it is necessary to control the shape of the edge ring and the sheath layer above the edge region of the wafer to adjust the inclination (hereinafter sometimes referred to as the "inclination angle") of the incident direction of ions into the edge region of the wafer. Therefore, in order to control the shape of the edge ring and the sheath layer above the edge region of the wafer, for example, a plasma processing apparatus capable of applying a negative DC voltage to the edge ring from a DC power supply is proposed in Patent Document 1.

[0028] However, conventional plasma processing apparatuses generate high bias, which can lead to discharges due to the potential difference between the wafer and the edge ring when high-frequency electrical power is supplied to the wafer in a pulsed manner. Therefore, plasma processing apparatuses have the function of applying a DC voltage synchronously with the pulses of the high-frequency power supply when supplying high-frequency electrical power, and de-energizing the edge ring when the high-frequency electrical power supply is stopped.

[0029] However, when high-frequency power is supplied in a pulsed manner, the bias does not rise immediately due to the reflection of the high-frequency power (reflected power). Furthermore, when the high-frequency power supply is stopped, the charge on the wafer cannot be immediately removed. Therefore, when a DC voltage is applied to the edge ring simultaneously with the high-frequency power, or when the edge ring is de-energized, a potential difference may be generated between the wafer and the edge ring, resulting in discharge. As a result, the wafer may sometimes be damaged.

[0030] The technology of the present invention enables proper control of the tilt angle of the edge region of the substrate during plasma processing and suppresses discharge between the substrate and the edge ring. Hereinafter, the plasma processing apparatus and plasma processing method of this embodiment will be described with reference to the accompanying drawings. In this specification and the drawings, elements having substantially the same functional configuration are omitted from repeated description by using the same reference numerals.

[0031] <Plasma Processing Device>

[0032] First, the plasma processing apparatus of this embodiment will be described. Figure 1 This is a longitudinal cross-sectional view showing the general configuration of the plasma processing device 1. Figure 2 This is an illustration of a power supply system that applies a DC voltage to the edge ring 14. The plasma processing apparatus 1 is a capacitively coupled type plasma processing apparatus. In the plasma processing apparatus 1, a wafer W, serving as a substrate, undergoes plasma processing. The plasma processing is not particularly limited; for example, etching, film deposition, and diffusion processes can be performed.

[0033] like Figure 1 As shown, the plasma processing apparatus 1 has a generally cylindrical chamber 10. Inside the chamber 10 is a processing space S capable of generating plasma. The chamber 10 is made of, for example, aluminum. The chamber 10 is connected to a ground potential.

[0034] The cavity 10 houses a mounting stage 11 for mounting the wafer W. The mounting stage 11 has a lower electrode 12, an electrostatic chuck 13, and an edge ring 14. In addition, an electrode plate (not shown), for example made of aluminum, may be provided on the lower surface side of the lower electrode 12.

[0035] The lower electrode 12 is made of a conductive metal such as aluminum and has a roughly circular plate shape.

[0036] A refrigerant flow path 15a is formed inside the lower electrode 12. Refrigerant can be supplied to the refrigerant flow path 15a from a refrigeration unit (not shown) located outside the chamber 10 via a refrigerant inlet pipe 15b. The refrigerant supplied to the refrigerant flow path 15a returns to the refrigeration unit via a refrigerant outlet flow path 15c. By circulating refrigerant, such as cooling water, in the refrigerant flow path 15a, the electrostatic chuck 13, the edge ring 14, and the wafer W can be cooled to the desired temperature.

[0037] An electrostatic chuck 13 is disposed on the lower electrode 12. The electrostatic chuck 13 is a component capable of holding both the wafer W and the edge ring 14 by electrostatic force. The electrostatic chuck 13 is formed such that the upper surface of the central portion is higher than the upper surface of the peripheral portion. The upper surface of the central portion of the electrostatic chuck 13 serves as a wafer mounting surface for mounting the wafer W, and the upper surface of the peripheral portion of the electrostatic chuck 13 serves as an edge ring mounting surface for mounting the edge ring 14.

[0038] Inside the electrostatic chuck 13, a first electrode 16a for adsorbing and holding the wafer W is provided at the center. Inside the electrostatic chuck 13, a second electrode 16b for adsorbing and holding the edge ring 14 is provided at the periphery. The electrostatic chuck 13 has a structure in which electrodes 16a and 16b are sandwiched between insulating members formed of insulating material.

[0039] A DC voltage from a DC power supply (not shown) can be applied to the first electrode 16a. The resulting electrostatic force allows the wafer W to be held and held on the upper surface of the central portion of the electrostatic chuck 13. Similarly, a DC voltage from a DC power supply (not shown) can be applied to the second electrode 16b. The resulting electrostatic force allows the edge ring 14 to be held and held on the upper surface of the peripheral portion of the electrostatic chuck 13.

[0040] In this embodiment, the central portion of the electrostatic chuck 13 for setting the first electrode 16a and the peripheral portion of the electrostatic chuck 13 for setting the second electrode 16b are formed as one unit; however, the central portion and the peripheral portion may also be separate units.

[0041] The edge ring 14 is an annular component that can be arranged to surround the upper surface of the wafer W placed in the center of the electrostatic chuck 13. The edge ring 14 is provided to improve the uniformity of plasma processing. Therefore, the edge ring 14 is made of a material appropriately selected according to the plasma processing, for example, it can be made of Si or SiC.

[0042] The mounting platform 11, configured as described above, is fixed to a generally cylindrical support member 17 located at the bottom of the chamber 10. The support member 17 is made of an insulator such as ceramic or quartz.

[0043] Furthermore, although not illustrated, the stage 11 may include a temperature control assembly capable of regulating at least one of the electrostatic chuck 13, edge ring 14, and wafer W to a desired temperature. The temperature control assembly may include a heater, a flow path, or a combination thereof. A temperature-regulating fluid such as a refrigerant or heat transfer gas flows in the flow path.

[0044] A spray head 20 is disposed above the mounting stage 11, opposite to the mounting stage 11. The spray head 20 has an electrode plate 21 disposed opposite to the processing space S, and an electrode support 22 disposed above the electrode plate 21. The electrode plate 21 functions as an upper electrode paired with the lower electrode 12. When the first high-frequency power supply 50 is electrically connected to the lower electrode 12 as described later, the spray head 20 is connected to the ground potential. Furthermore, the spray head 20 is supported on the upper part (top surface) of the chamber 10 via an insulating shielding member 23.

[0045] Multiple gas outlets 21a are formed on the electrode plate 21 for supplying the processing gas conveyed from the gas diffusion chamber 22a (described later) to the processing space S. The electrode plate 21 is made of, for example, a conductor or semiconductor with low resistivity that generates little Joule heat.

[0046] The electrode support 22 is a component that supports the electrode plate 21 in a detachable manner. The electrode support 22 has, for example, a structure in which a plasma-resistant film is formed on the surface of a conductive material such as aluminum. This film can be a ceramic film formed by anodizing or by yttrium oxide. A gas diffusion chamber 22a is formed inside the electrode support 22. Multiple gas flow holes 22b communicating with the gas outlet 21a are formed from the gas diffusion chamber 22a. Additionally, a gas inlet hole 22c connected to the gas supply pipe 33 described later is formed in the gas diffusion chamber 22a.

[0047] In addition, the gas supply source group 30 for supplying processing gas to the gas diffusion chamber 22a is connected to the electrode support 22 via the flow control device group 31, the valve group 32, the gas supply pipe 33, and the gas inlet hole 22c.

[0048] The gas supply source group 30 has multiple gas supply sources required for plasma processing. The flow control device group 31 includes multiple flow controllers, and the valve group 32 includes multiple valves. Each of the multiple flow controllers in the flow control device group 31 is a mass flow controller or a pressure-controlled flow controller. In the plasma processing apparatus 1, processing gas from one or more gas supply sources selected from the gas supply source group 30 is supplied to the gas diffusion chamber 22a via the flow control device group 31, the valve group 32, the gas supply pipe 33, and the gas inlet port 22c. Then, the processing gas supplied to the gas diffusion chamber 22a is dispersed into the processing space S in a spray manner via the gas flow port 22b and the gas outlet 21a.

[0049] A baffle 40 is provided at the bottom of chamber 10 and between the inner wall of chamber 10 and support member 17. The baffle 40 is constructed, for example, by coating aluminum with a ceramic such as yttrium oxide. Multiple through holes are formed in the baffle 40. The processing space S is connected to the exhaust port 41 via the baffle 40. An exhaust device 42, such as a vacuum pump, is connected to the exhaust port 41, and the exhaust device 42 can be used to reduce the pressure within the processing space S.

[0050] Additionally, a wafer W feed outlet 43 is formed on the side wall of the chamber 10, which can be opened and closed by a gate valve 44.

[0051] The plasma processing apparatus 1 also includes a first high-frequency power supply 50, a second high-frequency power supply 51, and a matching device 52. The first high-frequency power supply 50 and the second high-frequency power supply 51 are connected to the lower electrode 12 via the matching device 52. The first high-frequency power supply 50 and the second high-frequency power supply 51 constitute the high-frequency power supply in this invention.

[0052] The first high-frequency power supply 50 is a power source for generating high-frequency electrical power for plasma generation. It can supply high-frequency electrical power (HF) with a frequency ranging from 27 MHz to 100 MHz, and in one example, 40 MHz, to the lower electrode 12. The first high-frequency power supply 50 is connected to the lower electrode 12 via a first matching circuit 53 of a matching unit 52. The first matching circuit 53 is a circuit used to match the output impedance of the first high-frequency power supply 50 with the input impedance on the load side (lower electrode 12 side). Alternatively, the first high-frequency power supply 50 may not be electrically connected to the lower electrode 12, or it may be connected to the spray head 20, which serves as the upper electrode, via the first matching circuit 53.

[0053] The second high-frequency power supply 51 generates high-frequency electrical power (high-frequency bias power) LF for introducing ions into the wafer W, and supplies this high-frequency electrical power LF to the lower electrode 12. The frequency of the high-frequency electrical power LF can be in the range of 400kHz to 13.56MHz, and in one example, 400kHz. The second high-frequency power supply 51 is connected to the lower electrode 12 via a second matching circuit 54 of a matching unit 52. The second matching circuit 54 is a circuit used to match the output impedance of the second high-frequency power supply 51 with the input impedance on the load side (lower electrode 12 side).

[0054] Furthermore, in the following description, the state of supplying one or both of the high-frequency power HF from the first high-frequency power source 50 and the high-frequency power LF from the second high-frequency power source 51 to the lower electrode 12 is sometimes referred to as "RF on". Additionally, the state of not supplying high-frequency power HF and high-frequency power LF to the lower electrode 12 is sometimes referred to as "RF off". Furthermore, high-frequency power HF and high-frequency power LF are sometimes collectively referred to as "high-frequency power RF".

[0055] like Figure 1 and Figure 2 As shown, the plasma processing apparatus 1 also includes a direct current (DC) power supply 60, a switching unit 61, a first RF filter 62, and a second RF filter 63. The DC power supply 60 is electrically connected to the edge ring 14 via the switching unit 61, the second RF filter 63, and the first RF filter 62. Furthermore, in this embodiment, two RF filters 62 and 63 are provided for the DC power supply 60; however, the number of RF filters is not limited to this, and for example, it could be one.

[0056] In this embodiment, the DC power supply 60 is connected to the edge ring 14 via the switching unit 61, the first RF filter 62, and the second RF filter 63. However, the power supply system for applying DC voltage to the edge ring 14 is not limited to this. For example, the DC power supply 60 may be electrically connected to the edge ring 14 via the switching unit 61, the second RF filter 63, the first RF filter 62, and the lower electrode 12.

[0057] The DC power supply 60 is a power source used to generate a negative DC voltage (DC) applied to the edge ring 14. Furthermore, the DC power supply 60 is a variable DC power supply, capable of adjusting the level of the DC voltage (DC).

[0058] The switching unit 61 can stop the application of DC voltage DC from DC power supply 60 to edge ring 14. Specifically, the switching unit 61 can switch the connection of edge ring 14 with DC power supply circuit 64 or power elimination circuit 65.

[0059] The DC power supply circuit 64 is connected to the DC power supply 60 and is used to apply a DC voltage (DC) to the edge ring 14 from the DC power supply 60. In one example, the DC power supply circuit 64 has a switching element 64a and a damping element 64b. The switching element 64a can be, for example, a field-effect transistor (FET). However, the switching element 64a can also be an insulated-gate bipolar transistor (IGBT) or a relay in addition to an FET. When the switching element 64a is closed (on state), the edge ring 14 is connected to the DC power supply 60, and a DC voltage (DC) can be applied to the edge ring 14. On the other hand, when the switching element 64a is open (off state), no DC voltage (DC) is applied to the edge ring 14. In the following description, the state in which the switching element 64a is on is sometimes referred to as "DC on," and the state in which the switching element 64a is off is sometimes referred to as "DC off." In addition, the damping element 64b is, for example, a resistor or a coil, and its value and position can be freely determined by the designer.

[0060] The power-removing circuit 65 is used to remove charge from the edge ring 14. In one example, the power-removing circuit 65 has a switching element 65a and a damping element 65b. The switching element 65a can be, for example, a field-effect transistor (FET). However, the switching element 65a can also be an insulated-gate bipolar transistor (IGBT) or a relay in addition to an FET. When the switching element 65a is closed (conducting), the edge ring 14 and the power-removing circuit 65 are connected, and the charge in the edge ring 14 flows into the power-removing circuit 65, thus removing charge from the edge ring 14. On the other hand, when the switching element 65a is open (disconnected), the edge ring 14 is not de-charged. In the following description, the state in which the switching element 65a is on is sometimes referred to as "power-removing on," and the state in which the switching element 65a is off is sometimes referred to as "power-removing off." In addition, the damping element 65b is, for example, a resistor or a coil, and its value and position can be freely determined by the designer.

[0061] The first RF filter 62 and the second RF filter 63 are each filters used to reduce or shield high frequencies, and are provided to protect the DC power supply 60. For example, the first RF filter 62 is used to reduce or shield a 40MHz high frequency from the first high-frequency power supply 50. For example, the second RF filter 63 is used to reduce or shield a 400kHz high frequency from the second high-frequency power supply 51. The circuit configuration of the first RF filter 62 and the second RF filter 63 can be designed arbitrarily by those skilled in the art.

[0062] like Figure 1 As shown, the plasma processing apparatus 1 also includes a pulse signal source 70. The pulse signal source 70 is used to send pulse signals, i.e., signals controlling the pulse timing, to the first high-frequency power supply 50, the second high-frequency power supply 51, and the DC power supply 60. The first high-frequency power supply 50 and the second high-frequency power supply 51 each supply high-frequency electrical power HF and high-frequency electrical power LF in a pulsed manner based on the pulse signal. Additionally, the DC power supply 60 applies high-frequency electrical power HF, high-frequency electrical power LF, and DC voltage DC in a pulsed manner based on the pulse signal. Furthermore, the pulse signal source 70 can control the synchronization timing of the high-frequency electrical power HF and high-frequency electrical power LF with the DC voltage DC. Alternatively, this pulse signal source can be integrated into each of the first high-frequency power supply 50, the second high-frequency power supply 51, and the DC power supply 60.

[0063] The plasma processing apparatus 1 also includes a measuring device (not shown) for measuring the self-biasing voltage of the edge ring 14 (or the self-biasing voltage of the lower electrode 12 or the wafer W). Furthermore, the configuration of the measuring device can be designed arbitrarily by those skilled in the art.

[0064] The plasma processing apparatus 1 described above includes a control unit 100. The control unit 100 is, for example, a computer including a CPU, memory, etc., and has a program storage unit (not shown). The program storage unit stores a program for controlling the plasma processing in the plasma processing apparatus 1. Alternatively, the program may be stored in a computer-readable storage medium and installed from that storage medium into the control unit 100.

[0065] <Plasma Processing Methods>

[0066] Next, the plasma processing performed using the plasma processing apparatus 1 configured as described above will be explained.

[0067] First, the wafer W is fed into the chamber 10 and placed on the electrostatic chuck 13. Then, by applying a DC voltage DC to the first electrode 16a of the electrostatic chuck 13, the wafer W is electrostatically attracted and held on the chuck 13 using Coulomb force. Additionally, after the wafer W is fed in, the interior of the chamber 10 is depressurized to the desired vacuum level using the venting device 42.

[0068] Next, processing gas is supplied from the gas supply source group 30 to the processing space S via the spray head 20. Additionally, a first high-frequency power source 50 supplies high-frequency electrical power HF for plasma generation to the lower electrode 12, exciting the processing gas and generating plasma. At this time, a second high-frequency power source 51 supplies high-frequency electrical power LF for ion introduction. Thus, plasma processing can be performed on the wafer W using the generated plasma.

[0069] When plasma processing is completed, firstly, the supply of high-frequency electrical power HF from the first high-frequency power source 50 and the supply of processing gas from the gas supply source group 30 are stopped. Additionally, if high-frequency electrical power LF is supplied during plasma processing, the supply of that high-frequency electrical power LF is also stopped. Next, the supply of heat transfer gas to the back side of the wafer W is stopped, and the adsorption and holding of the wafer W by the electrostatic chuck 13 is stopped.

[0070] Afterwards, the wafer W is sent out of the chamber 10, and the series of plasma treatments on the wafer W are completed.

[0071] Furthermore, in plasma processing, there are also cases where plasma is generated using only the high-frequency power LF from the second high-frequency power supply 51, without using the high-frequency power HF from the first high-frequency power supply 50.

[0072] <Tilt Angle Control Method>

[0073] Next, the method for controlling the tilt angle in the plasma processing described above will be explained. The tilt angle refers to the degree of inclination (angle) of the incident direction of ions into the edge region of the wafer W relative to the vertical direction.

[0074] In one example, with the edge ring 14 in an unconsumed state, the shape of the sheath remains horizontal above the wafer W and the edge ring 14. Therefore, ions are incident on the entire surface of the wafer W in a substantially vertical direction (vertical direction). That is, the tilt angle is 0 (zero).

[0075] As the edge ring 14 is consumed and its thickness decreases, the thickness of the sheath layer in the edge region of the wafer W and above the edge ring 14 decreases, and the shape of the sheath layer changes to a downward convex shape. As a result, the incident direction of ions into the edge region of the wafer W is tilted relative to the vertical direction. Thus, an opening tilted relative to its thickness direction is formed in the edge region of the wafer W.

[0076] In addition, there is also the following situation: relative to the central region of wafer W, the thickness of the sheath increases in the edge region of wafer W and above the edge ring 14, and the shape of the sheath becomes an upward convex shape.

[0077] In the plasma processing apparatus 1 of this embodiment, the tilt angle is controlled by adjusting the DC voltage DC from the DC power supply 60.

[0078] like Figure 2 As shown, in the DC power supply 60, the DC voltage DC applied to the edge ring 14 is set to a voltage with the absolute value of the sum of the absolute value of the self-bias voltage Vdc and the set value ΔV as its negative polarity, i.e., -(|Vdc|+ΔV). Figure 2 In the diagram, the dashed lines above the wafer W and edge ring 14 represent the potentials of the wafer W and edge ring 14, respectively. The self-bias voltage Vdc is the self-bias voltage of the wafer W, which is the self-bias voltage of the lower electrode 12 when one or both of the high-frequency electrical power RF are supplied, and no DC voltage DC from the DC power supply 60 is applied to the lower electrode 12. The set value ΔV is provided by the control unit 100.

[0079] The control unit 100 uses a predetermined function or table to determine a setpoint ΔV based on the consumption of the edge ring 14 (the reduction in the thickness of the edge ring 14 relative to its initial value) and the consumption of the edge ring 14 calculated from the plasma processing conditions (e.g., processing time). That is, the control unit 100 inputs the consumption of the edge ring 14 and the self-bias voltage into the aforementioned function, or uses the consumption of the edge ring 14 and the self-bias voltage as referenced in the aforementioned table to determine the setpoint ΔV.

[0080] When determining the setpoint ΔV, the control unit 100 may use the difference between the initial thickness of the edge ring 14 and the actual thickness of the edge ring 14 measured using a measuring instrument such as a laser measuring instrument or a camera as the consumption amount of the edge ring 14. Alternatively, the control unit 100 may use other functions or tables predetermined for determining the setpoint ΔV to determine the consumption amount of the edge ring 14 based on specific parameters. These specific parameters may be any of the following: self-bias voltage Vdc, wave height Vpp of high-frequency power HF or LF, load impedance, or electrical characteristics of the edge ring 14 or its surrounding area. The electrical characteristics of the edge ring 14 or its surrounding area may be any of the following: voltage, current, or resistance value of any part of the edge ring 14 or its surrounding area. The other functions or tables are predetermined to determine the relationship between the specific parameters and the consumption amount of the edge ring 14. To determine the consumption of the edge ring 14, before performing actual plasma processing or during maintenance of the plasma processing apparatus 1, the plasma processing apparatus 1 is operated under the set measurement conditions for determining the consumption, namely, the high-frequency electrical power HF, the high-frequency electrical power LF, the pressure within the processing space S, and the flow rate of the processing gas supplied to the processing space S. Thus, the aforementioned specific parameters can be obtained, and by inputting these specific parameters into the other functions mentioned above, or by referring to the aforementioned table using these specific parameters, the consumption of the edge ring 14 can be determined.

[0081] In the plasma processing apparatus 1, during plasma processing, i.e., during the supply of high-frequency electrical power, either or both of high-frequency electrical power HF and high-frequency electrical power LF, a DC voltage DC is applied to the edge ring 14 from the DC power supply 60. This allows control over the shape of the sheath layer above the edge ring 14 and the edge region of the wafer W, reducing the tilt angle of the incident direction of ions into the edge region of the wafer W. As a result, an opening substantially parallel to the thickness direction of the wafer W can be formed throughout the entire region of the wafer W.

[0082] More specifically, in plasma processing, the self-bias voltage Vdc is measured using a measuring instrument (not shown). Additionally, a DC voltage DC is applied to the edge ring 14 from the DC power supply 60. The value of the DC voltage DC applied to the edge ring 14 is, as described above, -(|Vdc|+ΔV). |Vdc| is the absolute value of the measured self-bias voltage Vdc previously obtained by the measuring instrument, and ΔV is a set value determined by the control unit 100. As described above, the DC voltage DC applied to the edge ring 14 can be determined based on the self-bias voltage Vdc measured in plasma processing. In this way, even if the self-bias voltage Vdc changes, the DC voltage DC generated by the DC power supply 60 can be corrected, and the tilt angle can be appropriately corrected.

[0083] <Control Methods for High-Frequency Electric Power and DC Voltage>

[0084] Next, the timing of the supply of high-frequency power RF, the timing of the application of DC voltage, and the timing of the de-energization of the edge ring 14 in the plasma processing described above will be explained. The supply of high-frequency power RF refers to the supply of one or both of high-frequency power HF from the first high-frequency power source 50 and high-frequency power LF from the second high-frequency power source 51 to the lower electrode 12. The timing of the supply of high-frequency power RF is the same as the timing of RF being turned on and off as described above. The application of DC voltage is the state where the edge ring 14 is connected to the DC power source 60 (DC power supply circuit 64), and the timing of the application of DC voltage is the same as the timing of DC being turned on and off as described above. The de-energization of the edge ring 14 is the state where the edge ring 14 is connected to the de-energization circuit 65, and the timing of the de-energization of the edge ring 14 is the same as the timing of de-energization being turned on and off as described above.

[0085] [The principle of delay time Dt]

[0086] Here, as described above, in order to control the tilt angle, the DC voltage DC applied from the DC power supply 60 to the edge ring 14 is adjusted, and a set value ΔV is set as a potential difference between the wafer W and the edge ring 14. At this time, for example, if the aforementioned potential difference becomes too large, or if the timing of applying the DC voltage DC is off, resulting in an unwanted potential difference, discharge may occur between the wafer W and the edge ring 14. As a result, the wafer W may sometimes be damaged.

[0087] Therefore, in this embodiment, by utilizing the DeadTime function of the pulse moment on the DC power supply 60 side, a floating potential state is formed at the output terminal of the DC power supply 60, so that the edge ring 14 has the ability to follow the potential changes of the wafer W.

[0088] The delay time function typically present in the switching unit 61 refers to the function of delaying the switching to one circuit when switching between the DC power supply circuit 64 and the power removal circuit 65, so that the two circuits do not conduct simultaneously. A short circuit would occur if both circuits were conducted simultaneously; therefore, this delay time function is provided. When high-frequency electrical power RF is supplied in a pulsed manner, the pulse signal is sent from the pulse signal source 70 and used as a synchronization signal in the first high-frequency power supply 50, the second high-frequency power supply 51, and the DC power supply 60. The aforementioned delay time function sets a delay time for this pulse signal. During this delay time, the DC power supply 60 is neither in an on nor off state, but rather in an indeterminate state. In the following description, the usual delay time is sometimes referred to as "delay time D0," and the delay time in this embodiment is sometimes referred to as "delay time Dt."

[0089] In this embodiment, the timing of RF on / off, DC on / off, and power-off switching is controlled. Figure 3 This is an explanatory diagram illustrating conventional RF on / off, DC on / off, and power-off switching, as a comparative example of this embodiment. Figure 3 In the above-mentioned switching unit 61, there is a delay time D0, but the delay time Dt of this embodiment is not set. On the other hand, Figure 4 This is an explanatory diagram illustrating the RF on / off, DC on / off, and power-off switching in this embodiment. Figure 3 and Figure 4 In the diagram above the wafer W and edge ring 14, the dashed lines schematically represent the time-dependent changes in the potential of the wafer W and edge ring 14, respectively. That is, the vertical axis of the dashed line diagram represents potential, and the horizontal axis represents time. Furthermore, in... Figure 3 and Figure 4 To make the technology easier to understand, the illustrations of the first RF filter 62 and the second RF filter 63 are omitted.

[0090] In the past, such as Figure 3 As shown in (a), when high-frequency power RF is supplied to the lower electrode 12 (RF on), a DC voltage DC is applied to the edge ring 14 (DC on, de-energized off). In this case, when RF is on, a reflection of the high-frequency power RF occurs, causing the high-frequency power RF supplied to the lower electrode 12 to rise slowly. Therefore, the potential generated in the wafer W due to the high-frequency power RF also rises slowly relative to the moment RF is on. However, the DC power supply 60 typically rises rapidly; therefore, the potential of the edge ring 14 rises rapidly, becoming the same as the potential of the DC power supply 60. Consequently, a potential difference larger than desired is generated between the wafer W and the edge ring 14, potentially causing a discharge between the wafer W and the edge ring 14.

[0091] In addition, in the past, such as Figure 3 As shown in (b), when the high-frequency electrical power RF supplied to the lower electrode 12 is stopped (RF off), the DC voltage DC applied to the edge ring 14 is stopped (DC off), and the edge ring 14 is de-energized (de-energization on). In this case, when RF is off, de-energization is performed slowly with respect to the time constant of the hardware (device) and plasma, thus the potential of the wafer W decreases slowly. Meanwhile, the potential of the edge ring 14 decreases rapidly, becoming approximately 0 (zero) V. Therefore, a potential difference larger than desired is generated between the wafer W and the edge ring 14, potentially causing a discharge between the wafer W and the edge ring 14.

[0092] In this embodiment, when high-frequency electrical power RF is supplied to the lower electrode 12 (RF on) and a DC voltage DC is applied to the edge ring 14 (DC on), after RF is on, DC is on after a first delay time Dt1. Here, in the case of the delay time Do of a typical switching unit 61, the DC power supply 60 is in an uncertain state, neither on nor off; therefore, it is preferable that the delay time Do be as short as possible. In the first delay time Dt1 of this embodiment, as... Figure 4 As shown in (a), by turning on the switching element 64a of the DC power supply circuit 64 and turning on the switching element 65a of the power stripping circuit 65, the output terminal of the DC power supply 60 is made to float at an uncertain state. That is, by setting an idle state where neither the DC power supply circuit 64 nor the power stripping circuit 65 is used, the output terminal of the DC power supply 60 becomes a floating potential during the first delay time Dt1. In this floating potential state, the edge ring 14 changes the same potential as the wafer W, so the potential difference between the wafer W and the edge ring 14 is small after the first delay time Dt1. Moreover, after the first delay time Dt1, DC is turned on. In this case, the potential of the edge ring 14 is equal to the potential of the wafer W (the potential of the plasma and the sheath), that is, it can become a self-biased voltage Vdc corresponding to the high-frequency power RF (except for the generated reflections). Moreover, the potential of the edge ring 14 rises slowly following the potential of the wafer W. Therefore, the potential difference between the wafer W and the edge ring 14 can be suppressed.

[0093] Furthermore, in this embodiment, when the high-frequency electrical power RF supplied to the lower electrode 12 is stopped (RF off), the DC voltage DC applied to the edge ring 14 is stopped (DC off), and the edge ring 14 is de-energized (de-energization on), after the DC voltage is disconnected, the de-energization is turned on after a second delay time Dt2. That is, during the second delay time Dt2, as... Figure 4 As shown in (b), by turning on the switching element 64a of the DC power supply circuit 64 and turning on the switching element 65a of the power stripping circuit 65, the output terminal of the DC power supply 60 is made to float at an uncertain state. That is, by setting an idle state where neither the DC power supply circuit 64 nor the power stripping circuit 65 is used, the output terminal of the DC power supply 60 becomes a floating potential during the second delay time Dt2. After the floating potential state in the second delay time Dt2, the power stripping is turned on. In this case, the potential of the edge ring 14 decreases slowly following the potential of the wafer W in order to become equal to the potential of the wafer W. Therefore, the potential difference between the wafer W and the edge ring 14 can be suppressed.

[0094] [Time of RF on / off, DC on / off, power-off switching]

[0095] As described above, in this embodiment, by setting delay times Dt1 and Dt2 when the RF is turned on and off, respectively, the potential difference between the wafer W and the edge ring 14 can be suppressed. The timing of RF on / off, DC on / off, and power-off switching in the plasma processing described above will be specifically explained below.

[0096] Figure 5 This is an explanatory diagram showing the changes in high-frequency electrical power RF and DC voltage over time. Figure 5 In the above figure, the vertical axis represents high-frequency electrical power RF, and the horizontal axis represents time t. Figure 5 In the figure below, the vertical axis represents DC voltage (DC), and the horizontal axis represents time (t). Figure 6 It means Figure 5 The table shows the states of RF on / off, DC on / off, and power off. Figure 7 It means Figure 5 A diagram illustrating the states of the DC power supply circuit 64 and the power removal circuit 65.

[0097] (Step S1)

[0098] Step S1 is the step of removing charge from the edge ring 14. In step S1, the switching element 64a of the DC power supply circuit 64 is turned on (DC off), and the switching element 65a of the charge removal circuit 65 is turned off (charge removal on). This connects the edge ring 14 to the charge removal circuit 65, and the charge on the edge ring 14 is removed via the charge removal circuit 65. Furthermore, in this step S1, the supply of high-frequency electrical power RF to the lower electrode 12 is stopped (RF off).

[0099] (Step S2)

[0100] Step S2 is the first delay time Dt1, which occurs between the supply of high-frequency power RF to the lower electrode 12 (RF on) and the application of DC voltage DC to the edge ring 14 (DC on). In step S2, the switching element 64a of the DC power supply circuit 64 is kept on (DC off), and the switching element 65a of the power removal circuit 65 is turned on (power removal off). That is, by making the edge ring 14 not connected to both the DC power supply circuit 64 and the power removal circuit 65, the output of the DC power supply 60 becomes a floating potential. When RF is on, the high-frequency power RF is reflected, and therefore, the potential of the wafer W rises slowly. Moreover, when the DC power supply 60 is in a floating potential state, the potential of the edge ring 14 rises slowly following the potential of the wafer W. Therefore, after the first delay time Dt1, the potential difference between the wafer W and the edge ring 14 can be reduced, thereby suppressing discharge.

[0101] (Step S3)

[0102] Step S3 involves supplying high-frequency electrical power RF to the lower electrode 12 (RF on) and applying a DC voltage DC to the edge ring 14 (DC on), thereby performing plasma treatment on the wafer W. In step S3, the switching element 65a of the power stripping circuit 65 is kept on (power stripping off), and the switching element 64a of the DC power supply circuit 64 is closed (DC on). In this way, the tilt angle of the edge region of the wafer W can be appropriately controlled using the DC voltage DC, thereby appropriately adjusting the incident direction of ions and uniformly performing plasma treatment on the wafer W.

[0103] (Step S4)

[0104] Step S4 is the second delay time Dt2, which occurs between the cessation of high-frequency power RF supply to the lower electrode 12 (RF off) and the cessation of DC voltage application to the edge ring 14 (DC off) until the edge ring 14 is de-energized (de-energization on). In step S4, the switching element 65a of the de-energizing circuit 65 is kept on (de-energization off), and the switching element 64a of the DC power supply circuit 64 is turned on (DC off). That is, by keeping the edge ring 14 disconnected from both the DC power supply circuit 64 and the de-energizing circuit 65, the output of the DC power supply 60 becomes a floating potential. When RF is off, the potential of the wafer W slowly decreases. Moreover, when the DC power supply 60 is in a floating potential state, the potential of the edge ring 14 slowly decreases following the potential of the wafer W. Therefore, after the second delay time Dt2, the potential difference between the wafer W and the edge ring 14 can be reduced, thereby suppressing discharge.

[0105] (Step S5)

[0106] Step S5 is the step of removing charge from the edge ring 14. In step S5, similar to step S1, the switching element 64a of the DC power supply circuit 64 is kept on (DC off), and the switching element 65a of the charge removal circuit 65 is closed (charge removal on). In this way, the edge ring 14 is connected to the charge removal circuit 65, and the charge on the edge ring 14 is removed via the charge removal circuit 65.

[0107] (Step S6)

[0108] Step S6 is the first delay time Dt1, which is the period from when high-frequency electrical power RF is supplied to the lower electrode 12 again (RF is turned on) until a DC voltage DC is applied to the edge ring 14 (DC is turned on). That is, it is the same as step S2.

[0109] By repeating steps S1 to S4 as described above, a series of plasma treatments are completed.

[0110] According to this embodiment, when high-frequency electrical power RF is supplied to the lower electrode 12 (RF on) and a DC voltage DC is applied to the edge ring 14 (DC on), after RF is on, DC is turned on after a first delay time Dt1. In this case, the potential of the edge ring 14 rises slowly following the potential of the wafer W. Therefore, the potential difference between the wafer W and the edge ring 14 can be suppressed.

[0111] Furthermore, when the high-frequency electrical power RF supplied to the lower electrode 12 is stopped (RF off), the DC voltage applied to the edge ring 14 is stopped (DC off), and the edge ring 14 is de-energized (de-energization on), after the DC voltage is disconnected, the de-energization is turned on after a second delay time Dt2. In this case, the potential of the edge ring 14 slowly decreases following the potential of the wafer W. Therefore, the potential difference between the wafer W and the edge ring 14 can be suppressed.

[0112] Furthermore, when using existing functions to set the functions of this embodiment, a timing signal capable of determining three states—DC on, DC off, and floating potential—is typically required, such as a timing signal with two pulses. Therefore, the device configuration becomes very complex.

[0113] In this respect, by using delay times Dt1 and Dt2, the timing at which the edge ring 14 follows the potential of the chip W can be determined regardless of the type of DC power supply. Furthermore, because a floating potential is formed on the DC power supply 60 side, the same pulse timing signal as the high-frequency power RF can be used. In other words, the existing pulse signal source 70 can be used without modifying it.

[0114] <Specific examples of delay time Dt>

[0115] Next, specific examples of the first delay time Dt1 when the RF is turned on and the second delay time Dt2 when the RF is turned off will be explained.

[0116] First, as a comparison of delay times Dt1 and Dt2, a specific example of the delay time Do of a typical switching unit 61 will be explained. The main factor determining the delay time Do is the switching speed of the FET in the switching unit 61. In detail, the delay time Do is the time obtained by adding a margin to the rise time and fall time of the FET. For example, when the time elapsed until the FET of the DC power supply circuit 64 is completely turned off (falls), and the moment when the power-off circuit 65 is indicated to be turned on, the time obtained by adding the fall time and the margin is the delay time Do. The rise time and fall time mentioned above vary depending on the type of component, for example, from 1 ns to 10 ns. The delay time Do is, for example, from 1 ns to 100 ns.

[0117] The common constraint for delay times Dt1 and Dt2 is the ratio of delay times Dt1 and Dt2 to the time when a DC voltage (DC turn-on time) is applied to the edge ring 14. Delay times Dt1 and Dt2 are the time when no DC voltage is applied; therefore, as delay times Dt1 and Dt2 become longer, they deviate from the DC voltage application state synchronized with the high-frequency electrical power RF. Therefore, delay times Dt1 and Dt2 are determined based on the DC turn-on time. Furthermore, the necessary minimum ratio of delay times Dt1 and Dt2 is determined based on the processing evaluation results of the plasma treatment.

[0118] The specific method for determining the first delay time Dt1 when the RF is turned on is as follows. That is, the reflection time after the high-frequency electrical power RF is supplied is measured in advance, and the time above this reflection time is determined as the first delay time Dt1. Alternatively, the potential of the edge ring 14 can be measured, and the first delay time Dt1 can be determined based on the high-frequency electrical power RF and the potential of the edge ring 14. The first delay time Dt1 can be determined, for example, to be 0.1μs to 1000μs, more preferably 0.1μs to 100μs or 1μs to 300μs. Furthermore, the upper limit of the first delay time Dt1 can be determined as the time required to remove the potential difference between the second DC voltage DC2 and the first DC voltage DC1 using plasma, as described later.

[0119] The specific method for determining the second delay time Dt2 when the RF is disconnected is as follows. That is, the potential of the edge ring 14 is measured, and the second delay time Dt2 is determined such that the edge ring 14 is de-energized after its potential has sufficiently decreased. Alternatively, the high-frequency power RF can be measured, and the second delay time Dt2 can be determined solely based on this high-frequency power RF. The second delay time Dt2 can be, for example, determined to be 0.1 μs to 1000 μs, more preferably 0.1 μs to 100 μs or 1 μs to 300 μs.

[0120] <Other Implementation Methods>

[0121] The plasma processing apparatus 1 of the above-described embodiment has a DC power supply 60, a DC power supply circuit 64, and a power removal circuit 65. However, the power supply system that applies a DC voltage DC to the edge ring 14 is not limited to this. Figures 8-10 This is an illustration of a power supply system that applies a DC voltage to the edge ring 14 in other embodiments. Furthermore, in... Figures 8-10 To make the technology easier to understand, the illustrations of the first RF filter 62 and the second RF filter 63 are omitted.

[0122] It can be like Figure 8 As shown, the plasma processing apparatus 1 has a DC power supply 200 and a DC power supply circuit 210, replacing the DC power supply 60, DC power supply circuit 64, and current removal circuit 65. That is, the plasma processing apparatus 1 of this embodiment may not have a current removal circuit. The DC power supply circuit 210 has a switching element 210a and a damping element 210b.

[0123] In this case, such as Figure 8 As shown in (a), immediately after supplying high-frequency electrical power RF to the lower electrode 12 (RF on), the switching element 210a is turned on, thereby not applying DC voltage DC to the edge ring 14 (DC off).

[0124] After that, as Figure 8 As shown in (b), after a delay time Dt, the switching element 210a is closed, thereby applying a DC voltage DC (DC on) to the edge ring 14. In this case, the DC voltage DC can be applied to the edge ring 14 after the potential of the edge ring 14 follows the potential of the wafer W. As a result, the potential difference between the wafer W and the edge ring 14 can be reduced, thereby suppressing discharge. Thus, plasma treatment of the wafer W is possible.

[0125] After that, as Figure 8 As shown in (c), when the high-frequency electrical power RF is stopped from being applied to the lower electrode 12 (RF is off), the switching element 210a is turned on, thereby stopping the application of DC voltage DC to the edge ring 14.

[0126] It can also be like Figure 9As shown, a first DC power supply 300, a second DC power supply 301, a first DC power supply circuit 310, a second DC power supply circuit 311, and a power elimination circuit 320 replace the DC power supply 60, DC power supply circuit 64, and power elimination circuit 65. The first DC power supply 300 applies a first DC voltage DC1 to the edge ring 14. The second DC power supply 301 applies a second DC voltage DC2, different from the first DC voltage DC1, to the edge ring 14. The first DC power supply circuit 310 has a switching element 310a and a damping element 310b. The second DC power supply circuit 311 has a switching element 311a and a damping element 311b. The power elimination circuit 320 has a switching element 320a and a damping element 320b.

[0127] For example, when high-frequency electrical power RF is supplied to the lower electrode 12 (RF on), if it is desired to switch the DC voltage DC applied to the edge ring 14 at high speed, the first DC voltage DC1 and the second DC voltage DC2 are switched by switching the first DC power supply circuit 310 and the second DC power supply circuit 311. For example, if the first DC voltage DC1 is less than the second DC voltage DC2, it is possible to... Figure 9 After applying the first DC voltage DC1 to the edge ring 14 as shown in (a), as Figure 9 A second DC voltage DC2 is applied to the edge ring 14 as shown in (b).

[0128] Furthermore, in this embodiment, as in the embodiments described above, a first delay time Dt1 is set when the RF is turned on, and a second delay time Dt2 is set when the RF is turned off. Specifically, the first delay time Dt1 is set from the time the high-frequency electrical power RF is supplied to the lower electrode 12 until the first DC voltage DC1 is applied to the edge ring 14. The second delay time Dt2 is set from the time the high-frequency electrical power RF is stopped being supplied to the lower electrode 12 and the second DC voltage DC2 is stopped being applied to the edge ring 14 until the edge ring 14 is de-energized. Alternatively, the delay time Dt may also be set during the application of the first DC voltage DC1 and the second DC voltage DC2.

[0129] Furthermore, when the first DC voltage DC1 is less than the second DC voltage DC2, the switching from the second DC voltage DC2 to the first DC voltage DC1 requires de-energizing via the edge ring 14, which is operated by the de-energizing circuit 320. That is, the switching must be performed in the following order: applying the second DC voltage DC2, de-energizing via the edge ring 14, and then applying the first DC voltage DC1.

[0130] Furthermore, when the voltage applied to the edge ring 14 is switched from the second DC voltage DC2 to the first DC voltage DC1, and when plasma is used to remove the voltage difference between the second DC voltage DC2 and the first DC voltage DC1, it is possible to achieve the following: Figure 10 The power removal circuit 320 is omitted as shown. In this case, a delay time Dt is set during the period from when the second DC voltage DC2 is applied to the edge ring 14 until the first DC voltage DC1 is applied.

[0131] The plasma processing apparatus 1 described in the above embodiment is a capacitively coupled plasma processing apparatus; however, the plasma processing apparatus using the present invention is not limited to this. For example, the plasma processing apparatus may also be an inductively coupled plasma processing apparatus.

[0132] The embodiments disclosed herein should be considered illustrative rather than restrictive in all respects. The above embodiments may be omitted, substituted, or modified in various ways without departing from the appended claims and their spirit.

Claims

1. A plasma processing apparatus for performing plasma processing on a substrate, characterized in that it comprises: Chamber; A stage disposed inside the chamber has electrodes, an electrostatic chuck disposed on the electrodes, and an edge ring disposed on the electrostatic chuck in such a way as to surround a substrate disposed on the electrostatic chuck. A high-frequency power supply is used to supply high-frequency electrical power for generating plasma from the gas inside the chamber; A DC power supply for applying a negative DC voltage to the edge ring; A DC power supply circuit for applying the DC voltage to the edge ring; A de-energizing circuit for de-energizing the edge ring; A switching unit for switching the connection between the edge ring and the DC power supply circuit or the power removal circuit; and The control unit is used to control the high-frequency electrical power and the DC voltage. The control unit controls the device to perform a process including the following steps: Step (a): Stop supplying the high-frequency electrical power and stop applying the DC voltage, thereby de-energizing the edge ring; Step (b): Start supplying the high-frequency electrical power and stop de-energizing the edge ring; after a predetermined first delay time, start applying the DC voltage. and Step (c) involves stopping the supply of the high-frequency electrical power and stopping the application of the DC voltage, and after a predetermined second delay time, starting the de-energization of the edge ring.

2. The plasma processing apparatus as described in claim 1, characterized in that: The control unit determines the first delay time based on the ratio of the first delay time to the application time of the DC voltage.

3. The plasma processing apparatus as described in claim 2, characterized in that: The control unit measures the reflection time after the high-frequency electrical power is supplied, and determines the time exceeding the reflection time as the first delay time.

4. The plasma processing apparatus as described in claim 2 or 3, characterized in that: The control unit measures the potential of the edge ring and determines the first delay time based on the potential of the edge ring.

5. The plasma processing apparatus as described in claim 2 or 3, characterized in that: The first delay time is 0.1 μs to 1000 μs.

6. The plasma processing apparatus according to any one of claims 1 to 3, characterized in that: The control unit determines the second delay time based on the ratio of the second delay time to the application time of the DC voltage.

7. The plasma processing apparatus as described in claim 6, characterized in that: The control unit measures the potential of the edge ring and determines the second delay time based on the potential of the edge ring.

8. The plasma processing apparatus as described in claim 6, characterized in that: The control unit measures the high-frequency electrical power and determines the second delay time based on the high-frequency electrical power.

9. The plasma processing apparatus as described in claim 6, characterized in that: The second delay time is 0.1μs to 1000μs.

10. The plasma processing apparatus according to any one of claims 1 to 3, characterized in that: The DC power supply includes: A first DC power supply for applying a first DC voltage; and A second DC power supply for applying a second DC voltage different from the first DC voltage. When the DC voltage is applied, either the first DC voltage or the second DC voltage is applied.

11. The plasma processing apparatus according to any one of claims 1 to 3, characterized in that: The high-frequency power supply includes: A first high-frequency power source for supplying first high-frequency electrical power, the first high-frequency electrical power being used to generate the plasma; and A second high-frequency power source is used to supply a second high-frequency electrical power, which is used to introduce ions into a substrate placed on the electrostatic chuck. When supplying the high-frequency electrical power, one or both of the first high-frequency electrical power and the second high-frequency electrical power are supplied.

12. A plasma processing method, comprising using a plasma processing apparatus to perform plasma processing on a substrate, characterized in that: The plasma processing device includes: Chamber; A stage disposed inside the chamber has electrodes, an electrostatic chuck disposed on the electrodes, and an edge ring disposed on the electrostatic chuck in such a way as to surround a substrate disposed on the electrostatic chuck. A high-frequency power supply is used to supply high-frequency electrical power for generating plasma from the gas inside the chamber; A DC power supply for applying a negative DC voltage to the edge ring; A DC power supply circuit for applying the DC voltage to the edge ring; A de-energizing circuit for de-energizing the edge ring; and A switching unit used to switch the connection between the edge ring and the DC power supply circuit or the power removal circuit. The method includes: Step (a): Stop supplying the high-frequency electrical power and stop applying the DC voltage, thereby de-energizing the edge ring; Step (b): Start supplying the high-frequency electrical power and stop the de-energizing of the edge ring; after a predetermined first delay time, begin applying the DC voltage; and Step (c) involves stopping the supply of the high-frequency electrical power and stopping the application of the DC voltage, and after a predetermined second delay time, starting the de-energization of the edge ring.

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