A method for preparing a nanogrid, a nanogrid and applications thereof

Abstract

The application provides a preparation method of a nanometer grid, and also provides a nanometer grid prepared by the method and application. The method of the application can simplify the preparation of the nanometer grid, accurately control the length size of the grid, and realize the preparation of a nanometer grid device.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor, and particularly relates to a preparation method of a nanometer grid, a nanometer grid and application. BACKGROUND

[0002] When a nanometer grid is prepared by using the existing photolithography technology, the grid length size depends not only on the resolution of the photolithography equipment, but also on the type of photoresist, baking temperature, exposure dose, developing temperature and time and other factors in the photolithography process. This leads to that the grid length size of the device is not easy to be accurately controlled, especially the preparation of nanometer scale grid is difficult. At present, the main way to prepare the nanometer grid is to use the extreme ultraviolet photolithography machine process, which needs to spend a high cost and requires a large device, and is not easy to produce.

[0003] In addition to using the extreme ultraviolet photolithography machine to prepare the micro pattern of 100 nm and below, the electron beam exposure technology (EBL) can also be used to prepare the fine structure below 10 nm. However, for EBL, the efficiency is low, and has a strong proximity effect, and the stability of the device is required to be high, and the developing and etching process for electron beam exposure also has great problems.

[0004] It is necessary to develop a new preparation method, so as to simplify the preparation of nanometer scale grid, accurately control the grid length size, and realize the preparation of nanometer grid device, and further improve the performance of electronic device. SUMMARY

[0005] The purpose of the present application is to overcome the shortcomings of the prior art, and to provide a method for preparing a nanometer grid by combining a thin film deposition technology.

[0006] Before explaining the present application in detail, the terms used in this text are defined as follows:

[0007] The term "ALD" refers to: Atomic layer deposition.

[0008] The term "CMP" refers to: Chemical mechanical polishing.

[0009] The term "RIE" refers to: Reaction ion etching.

[0010] The term "PECVD" refers to: Plasma enhanced chemical vapor deposition.

[0011] The term "ICP-CVD" refers to Inductive Coupled Plasma Chemical Vapor Deposition.

[0012] The term "LPCVD" refers to Low Pressure Chemical Vapor Deposition.

[0013] The term "DUV lithography" refers to deep ultraviolet lithography.

[0014] The term "EUV lithography" refers to extreme ultraviolet lithography.

[0015] To achieve the above object, the first aspect of the present application provides a method for preparing a nanometer grid, comprising the following steps:

[0016] (1) providing a wafer required for process preparation;

[0017] (2) depositing a first isolation layer material on the wafer;

[0018] (3) patterning the first isolation layer obtained in step (2) using a patterning technology;

[0019] (4) depositing a second isolation layer material to cover the patterned structure;

[0020] (5) depositing a third isolation layer material to fill the trench and cover the surface;

[0021] (6) planarizing the surface of the material obtained in step (5) to obtain a flat surface and expose the structure arranged between the first, second and third isolation layers;

[0022] (7) etching to remove the material at the positions of the first and third isolation layers between the adjacent second isolation layers until the wafer surface;

[0023] Preferably, the first isolation layer and the third isolation layer are of the same material.

[0024] According to the method of the first aspect of the present application, in step (1), the wafer material is selected from one or more of the following: quartz, silicon, gallium arsenide, silicon carbide, glass, sapphire and the like substrates.

[0025] Preferably, the wafer is quartz or glass.

[0026] More preferably, the wafer is a wafer with a functional layer.

[0027] According to the method of the first aspect of the present application, the thickness of the first isolation layer material in step (2) is not less than 2 times the thickness of the second isolation layer material in step (4);

[0028] Preferably, the thickness of the second isolation layer material in step (4) is not less than 1 nm.

[0029] According to the method of the first aspect of the present application, the pattern structure in step (3) is a strip pattern.

[0030] Preferably, the distance between the strip patterns is not less than 2 times the thickness of the second isolation layer material.

[0031] According to the method of the first aspect of the present application, the material of the isolation layer is selected from one or more of the following: silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride, polysilicon, photoresist, polyimide, etc.

[0032] Preferably, the etching selectivity ratio of the materials of the first and second isolation layers is greater than 2;1.

[0033] According to the method of the first aspect of the present application, the deposition method in steps (2), (4) or (5) is a thin film deposition technique, preferably selected from one or more of the following: ALD, PECVD, ICP-CVD, LPCVD, reactive ion magnetron sputtering, spin coating.

[0034] The pattern preparation technique in step (3) is selected from one or more of the following: photolithography, electron beam exposure technology, laser direct writing technology.

[0035] Preferably, the photolithography technique is selected from one or more of the following: ultraviolet lithography, DUV lithography, EUV lithography, immersion lithography.

[0036] According to the method of the first aspect of the present application, the method further comprises the following steps:

[0037] (8) treating the non-nano-grid reserved area with a conventional process to obtain the desired mesa structure;

[0038] Preferably, the conventional process is selected from one or more of the following: photolithography, wet etching, dry etching.

[0039] The second aspect of the present application provides a nano-grid prepared according to the method of the first aspect.

[0040] Preferably, the line width of the nanogrid is 100 nm or less, preferably 28 nm or less, more preferably 14 nm or less, even more preferably 7 nm or less, further preferably 5 nm or less, most preferably 3 nm or less.

[0041] The third aspect of the present application provides a grating device, which comprises the nanogrid prepared by the preparation method according to the first aspect and / or the nanogrid according to the second aspect.

[0042] The present application aims to provide a method for preparing a nanogrid by combining a thin film deposition technique, to improve the preparation process of a device and reduce the preparation cost of a device, in view of the shortcomings of the current means.

[0043] The present application provides a method for preparing a nanogrid by using a thin film deposition technique, which comprises the following steps:

[0044] Providing a wafer required by the process;

[0045] Growing a first isolation layer material on a flat surface by using a thin film deposition technique;

[0046] Preparation of a relevant pattern structure by using a photolithography technique or other pattern preparation techniques on the first isolation layer;

[0047] Growing a second isolation layer material by using a thin film deposition technique to coat the pattern structure;

[0048] Growing a third isolation layer material by using a thin film deposition technique to fill the trench and cover the surface;

[0049] Obtaining a flat surface and exposing the structure arranged between the first, second and third isolation layers by using a CMP technique;

[0050] Removing the materials at the positions of the first and third isolation layers by using an etching technique until the wafer surface;

[0051] The first isolation layer material is consistent with the third isolation layer material;

[0052] The wafer not only comprises ordinary substrate materials such as silicon, gallium arsenide, silicon carbide and the like, but also quartz, glass and the like, and further includes a wafer with a functional layer;

[0053] The thin film deposition technique for depositing the isolation layer material comprises but is not limited to ALD, PECVD, ICP-CVD, LPCVD, reactive ion magnetron sputtering and the like, spin coating and the like;

[0054] The isolation layer material is deposited on the wafer by thin film deposition technology, and the isolation layer material includes but is not limited to silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride, photoresist, polyimide and the like.

[0055] The first isolation layer is prepared into a related pattern structure by using a photoetching technology or other pattern preparation technology, wherein the photoetching technology includes controllable photoetching technologies such as ordinary ultraviolet photoetching, DUV photoetching, EUV photoetching and immersion photoetching.

[0056] The first isolation layer is prepared into a related pattern structure by using a photoetching technology or other pattern preparation technology, wherein the other pattern preparation technology includes but is not limited to controllable pattern preparation technologies such as electron beam exposure technology and laser direct writing technology.

[0057] The second isolation layer material is deposited by using thin film deposition technology to cover the pattern structure, and the thickness of the isolation layer material should be at least 1 nm.

[0058] The first isolation layer material and the second isolation layer material are grown by using thin film deposition technology, and the etching selectivity ratio should be greater than 2:1.

[0059] In the process, the non-nano-grid reserved area can be processed by using a conventional process to obtain a required mesa structure.

[0060] The thickness of the second isolation layer determines the final line width, and the thickness is not specifically limited and can cover the current 28nm, 14nm, 7nm process, and can even be widened to 5nm, 3nm and the like.

[0061] The process result is a nano-grid structure, and the subsequent process application of the nano-grid includes but is not limited to grating devices.

[0062] The method of the present application can have but is not limited to the following beneficial effects:

[0063] The method of the present application can simplify the preparation of the nano-scale grid, accurately control the grid length size, and realize the preparation of the nano-grid device. BRIEF DESCRIPTION OF DRAWINGS

[0064] Hereinafter, the embodiments of the present application will be described in detail with reference to the accompanying drawings, in which:

[0065] Figure 1 A flowchart of an embodiment of the present application is shown.

[0066] Figure 2 A schematic diagram of preparing the first isolation layer in an embodiment of the present application is shown.

[0067] Figure 3A schematic diagram showing the preparation of a patterned structure on the first isolation layer according to an embodiment of the present application is shown.

[0068] Figure 4 A schematic diagram showing the coating of the patterned structure with the second isolation layer according to an embodiment of the present application is shown.

[0069] Figure 5 A schematic diagram showing the filling of the trench with the third isolation layer according to an embodiment of the present application is shown.

[0070] Figure 6 A schematic diagram showing the surface planarization using CMP according to an embodiment of the present application is shown.

[0071] Figure 7 A schematic diagram showing the removal of the material at the positions of the first and third isolation layers using etching technology according to an embodiment of the present application is shown.

[0072] 1, wafer; 2, first isolation layer material; 3A, 3B, 3C, second isolation layer material; 4, third isolation layer material. DETAILED DESCRIPTION

[0073] The present application will be further described with reference to the following specific examples. It should be understood, however, that these examples are included in order to provide a more complete description of the application and are not intended to limit the scope of the application as encompassed by the claims.

[0074] This section describes the materials and methods used in the experiments of the present application. Although many of the materials and methods used to achieve the objectives of the present application are known in the art, the present application is described in as much detail as possible. It is clear to those skilled in the art that, in the context, the materials and methods used in the present application are known in the art if not specifically described.

[0075] Example 1

[0076] This example is used to illustrate the method for preparing a nanometer grid using thin film deposition technology according to the present application.

[0077] The specific process is shown in Figure 1 and includes the following steps:

[0078] S100: providing a wafer 1 required for the process preparation;

[0079] S200: depositing a first isolation layer material 2;

[0080] S300: preparing a strip pattern structure on the surface of the first isolation layer material 2;

[0081] S400: depositing a second isolation layer material 3A, 3B, 3C;

[0082] S500: depositing a third isolation layer material 4 to fill the trench;

[0083] S600: planarizing the material surface.

[0084] S700: etching to remove the first isolation layer material 2, the third isolation layer material 4 and the second isolation layer material 3C under the third isolation layer material 4 until the wafer surface, forming a nanometer grid.

[0085] In the embodiment, the wafer material in S100 can be selected from one or more of the following: silicon, gallium arsenide, silicon carbide, quartz, sapphire, wafer with functional layer.

[0086] In a preferred embodiment, the material of the wafer 1 is selected as a 2-inch quartz wafer.

[0087] The deposition method in S200 is a thin film deposition technique selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering.

[0088] The thickness of the first isolation layer material 3 in S200 is 5 nm or more.

[0089] The material of the isolation layer in the embodiment is selected from one or more of the following: silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride;

[0090] The etching selectivity ratio of the materials of the first and second isolation layers is at least 2:1.

[0091] In a preferred embodiment, a CVD technique is used to deposit 100 nm of the first isolation layer material 2, aluminum oxide material: the deposition temperature is 380°C, the precursor material used is trimethylaluminum and nitric oxide, and the deposition time is 3 min, as shown in Figure 2 .

[0092] The pattern preparation technique in S300 is selected from one or more of the following: photolithography, electron beam exposure, laser direct writing; the photolithography is selected from one or more of the following: ultraviolet lithography, DUV lithography, EUV lithography, immersion lithography.

[0093] In a preferred embodiment, the surface bar structure is prepared by a photolithography step, and a pattern structure with a line width of 100 nm, a pitch of 140 nm, and a period of 240 nm is obtained. Then the bar structure is transferred to the first isolation layer material 2 aluminum oxide: using photoresist as a mask, combining RIE etching technology, using BCl3 as etching gas, power of 150 W, etching time of 3 min, the pattern of photoresist is transferred to the aluminum oxide, the line width of which is 100 nm, and the groove width between two aluminum oxide structures is 140 nm, as shown in Figure 3 .

[0094] The deposition method in S400 is a thin film deposition technology selected from one or more of the following: ALD, PECVD, ICP-CVD, LPCVD, and reactive ion magnetron sputtering. The thickness of the second isolation layer material in S400 is 1 nm or more

[0095] In a preferred embodiment, the second isolation layer material 3 silicon dioxide is grown by ALD technology, with a deposition temperature of 200 °C, using amino silane and water vapor as precursor materials, and a deposition time of 1 h, to coat the surface pattern structure, as shown in Figure 4 .

[0096] The deposition method in S500 is a thin film deposition technology selected from one or more of the following: ALD, PECVD, ICP-CVD, LPCVD, and reactive ion magnetron sputtering.

[0097] In a preferred embodiment, the third isolation layer material 4 aluminum oxide material is deposited by CVD technology, with a deposition temperature of 380 °C, using trimethylaluminum and nitric oxide as precursor materials, to fill the grooves of the pattern, as shown in Figure 5 .

[0098] The planarization method in S600 is selected from one or more of the following: CMP technology, PSG technology, and ion selective bombardment.

[0099] In a preferred embodiment, the surface is planarized by CMP technology: using a polishing machine combined with an aluminum oxide polishing liquid for polishing treatment, with a polishing rate of 10 nm / min, so that the height of the remaining isolation layer is the same as the initial deposition of aluminum oxide, i.e. 100 nm, so that the surface exposes the pattern of alternating arrangement of aluminum oxide, silicon oxide, and aluminum oxide, as shown in Figure 6 .

[0100] The etching method in S700 is selected from one or more of the following: RIE and ICP.

[0101] In a preferred embodiment, the exposed first isolation layer material 2 alumina is etched using a RIE etching technique with BCl3as the etching gas, a power of 150 W, and an etching time of 3 min to obtain a nanograting structure with a width of 10 nm, as shown in Figure 7

[0102] Figure 2 A schematic diagram corresponding to the growth of silicon oxide on a silicon surface in the present embodiment; Figure 3 A schematic diagram corresponding to the preparation of a patterned structure on the silicon oxide in the present embodiment; Figure 4 A schematic diagram corresponding to the growth of silicon nitride covering the silicon oxide structure in the present embodiment; Figure 5 A schematic diagram corresponding to after the deposition of a full coverage of trench with silicon oxide material in the present embodiment; Figure 6 A schematic diagram corresponding to after the surface planarization using CMP in the present embodiment; Figure 7 A schematic diagram corresponding to after the etching removal of the exposed alumina.

[0103] While the application has been described with a certain degree of particularity, it is to be understood that the present application is capable of numerous modifications. It is capable of other embodiments and of being practiced or being carried out in various ways. Examples of specific implementations and applications are provided solely for illustrative purposes and are not intended to be limiting.​

Claims

1. A method for preparing a nanogate, characterized in that: The method comprises the following steps: (1) Provide wafers required for process preparation; (2) depositing a first isolation layer material on the wafer; (3) preparing a pattern structure using a pattern preparation technology on the first isolation layer obtained in step (2); (4) depositing a second isolation layer material to cover the graphic structure; (5) depositing a third isolation layer material to fill the trench and cover the surface; (6) planarizing the surface of the material obtained in step (5) to obtain a flat surface and expose a structure in which the first, second, and third isolation layers are arranged alternately; (7) Etching and removing the materials at the positions of the first and third isolation layers between the adjacent second isolation layers until reaching the surface of the wafer to form a nanogate.

2. The method according to claim 1, characterized in that The first isolation layer and the third isolation layer are made of the same material.

3. The method according to claim 1 or 2, characterized in that The wafer material in step (1) is selected from one or more of the following: quartz, silicon, gallium arsenide, silicon carbide, glass, and sapphire.

4. The method according to claim 3, characterized in that The wafer material in step (1) is quartz and / or glass.

5. The method according to claim 1 or 2, characterized in that The wafer material in step (1) is a wafer with a functional layer.

6. The method according to claim 1 or 2, characterized in that The thickness of the first isolation layer material in step (2) is not less than twice the thickness of the second isolation layer material in step (4); The thickness of the second isolation layer material in step (4) is not less than 1 nm.

7. The method according to claim 1 or 2, characterized in that The graphic structure in step (3) is a strip-shaped graphic.

8. The method according to claim 7, characterized in that The spacing between the strip patterns is not less than twice the thickness of the second isolation layer material.

9. The method according to claim 1 or 2, characterized in that The material of the isolation layer is selected from one or more of the following: silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride, polysilicon, photoresist, and polyimide.

10. The method according to claim 1 or 2, characterized in that The etching selectivity ratio of the materials of the first isolation layer and the second isolation layer is greater than 2:

1.

11. The method according to claim 1 or 2, characterized in that The deposition method in step (2), (4) or (5) is a thin film deposition technique.

12. The method according to claim 11, characterized in that The thin film deposition technology is selected from one or more of the following: ALD, PECVD, ICP-CVD, LPCVD, reactive ion magnetron sputtering, and spin coating.

13. The method according to claim 1 or 2, characterized in that The preparation technology of the graphic structure in step (3) is selected from one or more of the following: photolithography technology, electron beam exposure technology, and laser direct writing technology.

14. The method according to claim 13, characterized in that The photolithography technology is selected from one or more of the following: ultraviolet lithography, DUV lithography, EUV lithography, and immersion lithography.

15. The method according to claim 1 or 2, characterized in that The method further comprises the following steps: (8) The non-nanogate retained area is processed using conventional processes to obtain the desired mesa structure.

16. The method according to claim 15, characterized in that The conventional process in step (8) is selected from one or more of the following: photolithography, wet etching, and dry etching.

17. A nanogate, characterized in that: The nanograting is prepared according to the method according to any one of claims 1 to 16.

18. The nanograting according to claim 17, characterized in that The line width of the nanogate is equal to the thickness of the second isolation layer.

19. The nanograting according to claim 17, characterized in that The line width of the nanogate is less than 100 nm.

20. The nanograting according to claim 19, characterized in that The line width of the nanogate is less than 28 nm.

21. The nanograting according to claim 20, characterized in that The line width of the nanogate is less than 14 nm.

22. The nanograting according to claim 21, characterized in that The line width of the nanogate is less than 7 nm.

23. The nanograting according to claim 22, characterized in that The line width of the nanogate is less than 5 nm.

24. The nanograting according to claim 23, characterized in that The line width of the nanogate is less than 3 nm.

25. A grating device, characterized in that: The grating device comprises a nanograting manufactured according to the manufacturing method of any one of claims 1 to 16 and / or a nanograting according to any one of claims 17 to 24.

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