Semiconductor package device manufacturing method
By adjusting the arrangement of the pins in the electroplating fixture or calibrating the position of the molded wafer using guide arms and positioning structures, the problem of uneven seed layer exposure was solved, achieving good stability and electrical connection in the electroplating process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ADVANCED SEMICON ENG INC
- Filing Date
- 2021-09-28
- Publication Date
- 2026-05-22
AI Technical Summary
In the photoresist edge removal process of square substrates, the precision limitations of the machine's robotic arm lead to uneven exposure of the seed layer, resulting in uneven electroplating thickness.
The contact of the electroplating fixture's stylus pins with the seed layer can be ensured by adjusting the angle between the exposed portion of the seed layer and the edge of the photoresist layer, adjusting the edge of the molded wafer to be parallel to the stylus pin arrangement of the electroplating fixture via the guide arm, or calibrating the position by forming a positioning structure and positioning mark on the molded wafer.
This method achieves uniform exposure of the seed layer, ensuring the stability of subsequent electroplating processes and good electrical bonding, and solving the problem of uneven electroplating thickness.
Smart Images
Figure CN113948404B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor packaging technology, and more specifically to a method for manufacturing a semiconductor packaging device. Background Technology
[0002] In the edge bead removal (EBR) process for square substrates, due to the precision limitations of the robotic arm, uneven exposure of the seed layer can occur during EBR due to substrate misalignment. If only a small portion is exposed, the contact pins of the electroplating fixture may not be able to land on the exposed seed layer after EBR (the pins will contact the photoresist). Figure 1 and Figure 2 As shown, this results in uneven electroplating thickness in the product. Summary of the Invention
[0003] This disclosure provides a method for manufacturing a semiconductor packaging device.
[0004] In a first aspect, embodiments of this disclosure provide a method for manufacturing a semiconductor packaging apparatus, comprising:
[0005] Provide molded chips;
[0006] A seed layer is formed on the molded wafer;
[0007] A photoresist layer is formed on the seed layer;
[0008] Perform an EBR process to remove part of the photoresist to expose part of the seed layer;
[0009] Adjust the contact pins of the electroplating fixture according to the angle formed between the exposed portion of the seed layer and the edge of the photoresist layer, so that the contact pins of the electroplating fixture contact the seed layer.
[0010] In some alternative embodiments, the pins of the electroplating fixture are arranged substantially parallel to the edge of the photoresist layer.
[0011] In some alternative embodiments, the orientation of the stylus arrangement of the electroplating fixture forms the included angle with the edge of the seed layer.
[0012] In some alternative embodiments, the horizontal cross-sectional shape of the molded wafer is rectangular.
[0013] In a second aspect, embodiments of this disclosure provide a method for manufacturing a semiconductor packaging apparatus, comprising:
[0014] Provide molded chips;
[0015] A seed layer is formed on the molded wafer;
[0016] A photoresist layer is formed on the seed layer;
[0017] The edge of the molded wafer is adjusted by the guide arm so that the edge of the molded wafer is parallel to the arrangement direction of the pins of the electroplating fixture.
[0018] A photoresist edge-removal EBR process is performed to remove part of the photoresist, thereby exposing part of the seed layer;
[0019] The contact pin of the electroplating fixture contacts the seed layer.
[0020] In some alternative embodiments, the horizontal cross-sectional shape of the molded wafer is rectangular.
[0021] Thirdly, embodiments of this disclosure provide a method for manufacturing a semiconductor packaging apparatus, comprising:
[0022] Provide molded chips;
[0023] A positioning structure is formed on the molded wafer;
[0024] A seed layer is formed on the molded wafer, and a positioning mark is formed on the seed layer corresponding to the positioning structure;
[0025] A photoresist layer is formed on the seed layer;
[0026] The position of the molded wafer is calibrated according to the positioning mark so that the edge of the molded wafer is parallel to the arrangement direction of the pins of the electroplating fixture;
[0027] A photoresist edge-removal EBR process is performed to remove part of the photoresist, thereby exposing part of the seed layer;
[0028] The contact pin of the electroplating fixture contacts the seed layer.
[0029] In some alternative embodiments, forming a positioning structure on the molded wafer includes:
[0030] At least two physical defects are formed on the molded wafer.
[0031] In some alternative implementations, the at least two physical defects are located at the edges of the molded wafer.
[0032] In some alternative implementations, the physical defect includes: a protrusion or a depression.
[0033] In some alternative embodiments, the horizontal cross-sectional shape of the molded wafer is rectangular.
[0034] This disclosure provides a method for manufacturing a semiconductor packaging device, comprising: providing a molded wafer; forming a seed layer on the molded wafer; forming a photoresist layer on the seed layer; performing an EBR process to remove a portion of the photoresist to expose a portion of the seed layer; and adjusting the contacts of an electroplating fixture according to the angle formed between the exposed portion of the seed layer and the edge of the photoresist layer, so that the contacts of the electroplating fixture contact the seed layer to ensure the stability of subsequent electroplating processes. Attached Figure Description
[0035] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:
[0036] Figure 1 This is a top view schematic diagram of a semiconductor packaging device for contacting photoresist with the stylus of an electroplating fixture, which addresses a problem in the prior art.
[0037] Figure 2 for Figure 1 A schematic diagram of the partial longitudinal cross-sectional structure of the dashed section;
[0038] Figure 3 This is a top view of a semiconductor packaging apparatus where the contact pins of the electroplating fixture are in contact with the seed layer after being adjusted according to the method of manufacturing a semiconductor packaging apparatus according to the present disclosure.
[0039] Figure 4 for Figure 3 A schematic diagram of the partial longitudinal cross-sectional structure of the dashed section;
[0040] Figure 5 This is a schematic diagram of using a CCD device to detect the included angle.
[0041] Figure 6 This is a schematic diagram showing how to adjust the position of the electroplating fixture according to the included angle;
[0042] Figure 7 This is a schematic flowchart of an embodiment of a method for manufacturing a semiconductor packaging apparatus according to the present disclosure;
[0043] Figure 8 This is a schematic flowchart of another embodiment of a method for manufacturing a semiconductor packaging apparatus according to the present disclosure;
[0044] Figure 9 This is a schematic flowchart of another embodiment of a method for manufacturing a semiconductor packaging apparatus according to the present disclosure.
[0045] Symbol explanation:
[0046] 11-Molded wafer; 12-Seed layer; 13-Photoresist layer; 14-Electroplated fixture; 141-Stylus pin; 15-CCD device. Detailed Implementation
[0047] The specific embodiments of this disclosure will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this disclosure and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.
[0048] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.
[0049] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including intermediate components or layers existing between the two.
[0050] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.
[0051] It should also be noted that the longitudinal section corresponding to the embodiments of this disclosure can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.
[0052] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.
[0053] Figure 3This is a top view of the contact structure of the contact pins of the electroplating fixture after adjustment according to the method of manufacturing a semiconductor packaging apparatus according to the present disclosure.
[0054] Further reference Figure 7 In order to achieve Figure 3 As shown, this disclosure provides a method for manufacturing a semiconductor packaging device, illustrating a flow 700 of an embodiment of a method for manufacturing a semiconductor packaging device according to this disclosure, the method comprising the following steps:
[0055] Step 701: Provide a substrate, which may be a molded wafer 11.
[0056] Here, the molded wafer 11 may include a chip and a packaging material covering the chip.
[0057] In this embodiment of the disclosure, the horizontal cross-sectional shape of the molded wafer 11 may include a rectangle.
[0058] In some alternative embodiments, the horizontal cross-sectional shape of the molded wafer 11 may also include polygons other than rectangles, such as triangles, pentagons, etc.; the horizontal cross-sectional shape of the molded wafer 11 may also include irregular geometric shapes.
[0059] Step 702: A seed layer 12 is formed on the molded wafer 11.
[0060] Step 703: Form a photoresist layer 13 on the seed layer 12.
[0061] Step 704: Perform EBR process to remove part of the photoresist to expose part of the seed layer 12.
[0062] Step 705: Adjust the stylus 141 of the electroplating fixture 14 according to the angle formed between the exposed part of the seed layer 12 and the edge of the photoresist layer 13 so that the stylus 141 of the electroplating fixture 14 contacts the seed layer 12.
[0063] Figure 4 for Figure 3 A schematic diagram of the partial longitudinal cross-sectional structure of the dashed section, as shown below. Figure 4 As shown, the contact pin 141 of the adjusted electroplating fixture 14 contacts the seed layer 12 to form a good electrical connection with the seed layer 12 for subsequent electroplating processes.
[0064] In this embodiment of the disclosure, there are multiple electroplating fixtures 14, and each electroplating fixture 14 is provided with multiple contact pins 141.
[0065] In some alternative embodiments, the angle formed between the arrangement direction of the stylus 141 of the adjusted electroplating fixture 14 and the edge of the seed layer 12 is the same as the angle formed between the exposed portion of the seed layer 12 and the edge of the photoresist layer 13.
[0066] The arrangement direction of the stylus 141 of the adjusted electroplating fixture 14 is substantially parallel to the edge of the photoresist layer 13.
[0067] Here, "practical parallelism" can include geometrical parallelism, or the stylus 141 of the electroplated fixture 14 being approximately parallel to the photoresist layer 13 within the allowable error range.
[0068] Figure 5 This is a schematic diagram illustrating the use of a CCD (Charge-coupled Device) to detect included angles, as shown below. Figure 5 As shown in this embodiment, the angle formed between the exposed portion of the seed layer 12 and the edge of the photoresist layer 13 can be determined by the CDD device 15.
[0069] Figure 6 This is a schematic diagram showing how to adjust the position of the electroplating fixture according to the included angle, as shown. Figure 6 As shown, after determining the angle formed between the exposed part of the seed layer 12 and the edge of the photoresist layer 13, the adjustment position of the electroplating fixture 14 can be determined according to the trigonometric function.
[0070] Figure 8 This is a schematic flowchart illustrating another embodiment of a method for manufacturing a semiconductor packaging apparatus according to the present disclosure. The method includes the following steps:
[0071] Step 801, provide the molded wafer 11.
[0072] Step 802: A seed layer 12 is formed on the molded wafer 11.
[0073] Step 803: Form a photoresist layer 13 on the seed layer 12.
[0074] Step 804: Adjust the edge of the molded wafer 11 by means of the guide arm so that the edge of the molded wafer 11 is parallel to the arrangement direction of the contact pins 141 of the electroplating fixture 14.
[0075] Step 805: Perform an EBR process to remove part of the photoresist to expose part of the seed layer 12.
[0076] Step 806: Contact the seed layer 12 with the contact pin 141 of the electroplating fixture 14.
[0077] In this embodiment, the molded wafer 11 is adjusted by the guide arm, which can correct the offset of the molded wafer 11 so that the area of the seed layer 12 exposed in the subsequent EBR process is uniform. The contact pin 141 of the electroplating fixture 14 contacts the seed layer 12 to form a good electrical connection with the seed layer 12 so as to carry out the subsequent electroplating process.
[0078] Figure 9 This is a schematic flowchart illustrating another embodiment of a method for manufacturing a semiconductor packaging apparatus according to the present disclosure. The method includes the following steps:
[0079] Step 901, provide the molded wafer 11.
[0080] Step 902: Form a positioning structure on the molded wafer 11.
[0081] In some embodiments, forming a positioning structure on the molded wafer 11 may include forming at least two physical defects on the molded wafer 11.
[0082] Here, physical defects may include protrusions or dents.
[0083] In the embodiments of this disclosure, the physical defects should be located at the edge of the molded wafer 11. It is understood that the molded wafer 11 usually has a certain amount of redundant packaging material reserved at the edge. Setting physical defects at the edge of the molded wafer 11 can avoid damaging the chip in the molded wafer 11.
[0084] Step 903: A seed layer 12 is formed on the molded wafer 11, and a positioning mark is formed on the seed layer 12 corresponding to the positioning structure.
[0085] It is understood that since the seed layer 12 is formed by adhering to the upper surface of the molded wafer 11, the corresponding positioning structure on the molded wafer 11 will form a corresponding shape on the seed layer 12. In this disclosure, the shape formed on the seed layer 12 corresponding to the positioning structure is defined as the positioning mark.
[0086] Step 904: Form a photoresist layer 13 on the seed layer 12.
[0087] It is understandable that the photoresist layer 13 will also form a corresponding shape for the positioning mark, so the positioning mark can also be identified in the photoresist layer 13.
[0088] Step 905: The position of the molded wafer 11 is calibrated according to the positioning mark so that the edge of the molded wafer 11 is parallel to the arrangement direction of the pins 141 of the electroplating fixture 14.
[0089] Here, the positioning mark can be identified by the CCD device 15, and the position of the molded wafer 11 can be calibrated according to the positioning mark to correct the offset of the molded wafer 11 so that the edge of the molded wafer 11 is parallel to the arrangement direction of the stylus 141 of the electroplating fixture 14.
[0090] Step 906: Perform an EBR process to remove part of the photoresist to expose part of the seed layer 12.
[0091] Step 907: Contact the seed layer 12 with the contact pin 141 of the electroplating fixture 14.
[0092] In this embodiment, the molded wafer 11 is calibrated by a positioning mark, which can correct the offset of the molded wafer 11 so that the area of the seed layer 12 exposed in the subsequent EBR process is uniform. The contact pin 141 of the electroplating fixture 14 contacts the seed layer 12 to form a good electrical connection with the seed layer 12 so as to carry out the subsequent electroplating process.
[0093] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual equipment due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than restrictive. Modifications may be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this disclosure.
Claims
1. A method for manufacturing a semiconductor packaging device, comprising: Provide molded chips; A seed layer is formed on the molded wafer; A photoresist layer is formed on the seed layer; A photoresist edge-removal EBR process is performed to remove part of the photoresist, thereby exposing part of the seed layer; The stylus of the electroplating fixture is adjusted according to the angle formed between the exposed portion of the seed layer and the edge of the photoresist layer, so that the stylus of the electroplating fixture contacts the seed layer. The angle formed between the edge of the exposed portion of the seed layer and the edge of the photoresist layer is determined using a CDD device, and the adjustment position of the electroplating fixture is determined according to a trigonometric function so that the stylus of the electroplating fixture contacts the seed layer. The arrangement direction of the stylus of the electroplating fixture is substantially parallel to the edge of the photoresist layer.
2. The method according to claim 1, wherein, The direction of the stylus arrangement of the electroplating fixture forms an angle with the edge of the seed layer located on the same side.
3. The method according to claim 1, wherein, The horizontal cross-sectional shape of the molded wafer is rectangular.