Semiconductor structure and method for manufacturing the same

Abstract

A method for manufacturing a semiconductor structure includes the following steps: providing a first semiconductor wafer, wherein the first semiconductor wafer includes a first dielectric layer and at least one first top metallization structure embedded in the first dielectric layer, and the top surface of the first dielectric layer is higher than the first top metallization structure by a first distance; providing a second semiconductor wafer, wherein the second semiconductor wafer includes a second dielectric layer and at least one second top metallization structure embedded in the second dielectric layer, and the top surface of the second top metallization structure is higher than the top surface of the second dielectric layer by a second distance; and hybrid bonding the first semiconductor wafer and the second semiconductor wafer. This allows for accurate and tight bonding between the first top metallization structure and the second top metallization structure, without any gaps between the two structures, thereby effectively achieving high bonding strength between the first semiconductor wafer and the second semiconductor wafer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor structure and a method for manufacturing the semiconductor structure. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements thereon. The semiconductor industry continues to increase the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. These smaller electronic components also require smaller packages, which take up less area than previous packages.

[0003] Three-dimensional integrated circuits (3DICs) are the latest development in semiconductor packaging, in which multiple semiconductor dies are stacked on top of each other, such as package-on-package (POP) and system-in-package (SIP) packaging technologies. Some 3DICs are prepared by placing die on die at the semiconductor wafer level. 3DICs offer higher integration density and other advantages, such as faster speeds and higher bandwidth, due to the reduced interconnect length between the stacked dies. However, many challenges associated with 3DICs remain. Summary of the Invention

[0004] The present disclosure generally relates to a semiconductor structure and a method for manufacturing the semiconductor structure.

[0005] According to one embodiment of the present disclosure, a method for fabricating a semiconductor structure includes the following steps: providing a first semiconductor wafer, wherein the first semiconductor wafer includes a first dielectric layer and at least one first top metallization structure embedded in the first dielectric layer, and a top surface of the first dielectric layer is higher than the first top metallization structure by a first distance; providing a second semiconductor wafer, wherein the second semiconductor wafer includes a second dielectric layer and at least one second top metallization structure embedded in the second dielectric layer, and a top surface of the second top metallization structure is higher than the top surface of the second dielectric layer by a second distance; and hybrid bonding the first semiconductor wafer and the second semiconductor wafer.

[0006] In some embodiments of the present disclosure, the second distance is smaller than the first distance.

[0007] In some embodiments of the present disclosure, the difference between the first distance and the second distance depends at least in part on the conductive thermal expansion coefficients of the first top metallization structure and the second top metallization structure.

[0008] In some embodiments disclosed herein, the method of manufacturing a semiconductor structure further includes: vertically placing a first semiconductor wafer on a second semiconductor wafer such that the first dielectric layer contacts the second dielectric layer while leaving a gap between the first top metallization structure and the second top metallization structure.

[0009] In some embodiments of the present disclosure, the first distance minus the second distance equals the vertical length of the gap.

[0010] In some embodiments of the present disclosure, hybrid bonding the first semiconductor wafer and the second semiconductor wafer includes performing an annealing process to cause the first top metallization structure and the second top metallization structure to undergo thermal expansion to fill the gap.

[0011] In some embodiments of the present disclosure, providing a first semiconductor wafer includes: forming an etch stop layer in the first semiconductor wafer; and vertically forming a first dielectric layer and a first top metallization structure on the etch stop layer.

[0012] In some embodiments of the present disclosure, providing a first semiconductor wafer includes: forming at least one groove vertically penetrating the first dielectric layer to expose a portion of the etch stop layer; and filling the groove with a first top metallization structure.

[0013] In some embodiments of the present disclosure, providing a first semiconductor wafer includes recessing the first top metallization structure to below a top surface of the first dielectric layer.

[0014] In some embodiments of the present disclosure, providing a first semiconductor wafer includes forming at least one conductive plug vertically penetrating an etch stop layer.

[0015] In some embodiments of the present disclosure, providing the second semiconductor wafer includes: vertically forming an etch stop layer on the second dielectric layer, wherein a thickness of the etch stop layer is substantially equal to the second distance.

[0016] In some embodiments disclosed herein, providing a second semiconductor wafer includes: forming at least one groove vertically penetrating the etch stop layer and the second dielectric layer; and filling the groove with a second top metallization structure such that a top surface of the second top metallization structure is substantially coplanar with a top surface of the etch stop layer.

[0017] In some embodiments of the present disclosure, providing the second semiconductor wafer includes removing the etch stop layer to expose a portion of a sidewall of the second top metallization structure.

[0018] According to one embodiment of the present disclosure, a semiconductor structure includes a lower dielectric layer, at least one lower metallization structure, an upper dielectric layer, and at least one upper metallization structure. The lower metallization structure is embedded in the lower dielectric layer. The upper dielectric layer and the lower dielectric layer form a dielectric-to-dielectric bond. The upper metallization structure is embedded in the upper dielectric layer and forms a metal-to-metal bond with the lower metallization structure, with the dielectric-to-dielectric bond and the metal-to-metal bond being located at different levels.

[0019] According to one embodiment of the present disclosure, the metal-to-metal junction is laterally surrounded by an upper dielectric layer.

[0020] According to one embodiment of the present disclosure, the lower metallization structure and the upper metallization structure include the same material.

[0021] According to one embodiment of the present disclosure, the semiconductor structure further includes an etch stop layer extending laterally above the upper dielectric layer and the upper metallization structure.

[0022] According to an embodiment of the present disclosure, the semiconductor structure further includes at least one conductive plug vertically penetrating the etch stop layer and contacting the upper metallization structure.

[0023] According to an embodiment of the present disclosure, the semiconductor structure further includes at least one top metallization structure, and the conductive plug is vertically disposed between the top metallization structure and the upper metallization structure.

[0024] According to one embodiment of the present disclosure, the semiconductor structure further includes at least one bottom metallization structure and at least one conductive plug vertically disposed between the lower metallization structure and the bottom metallization structure.

[0025] According to the aforementioned embodiments of the present disclosure, since the top surface of the first top metallization structure is lower than the top surface of the first dielectric layer by a first distance, and the top surface of the second top metallization structure is higher than the top surface of the second dielectric layer by a second distance, a gap is retained between the first top metallization structure and the second top metallization structure to allow for thermal expansion during the hybrid bonding process. As a result, the first top metallization structure and the second top metallization structure can be bonded accurately and tightly without any gaps being generated therebetween, thereby effectively achieving high bonding strength between the first semiconductor wafer and the second semiconductor wafer. Furthermore, the semiconductor structure manufactured by this process may include a first interface between the first dielectric layer and the second dielectric layer, and a second interface between the first top metallization structure and the second top metallization structure, wherein the first interface and the second top metallization structure are vertically located at different levels. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The present disclosure may be more fully understood by reading the following detailed description of the embodiments and referring to the following drawings:

[0027] Figure 1 FIG. 4 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure.

[0028] Figure 2 According to some embodiments of the present disclosure Figure 1 A flow chart of a method for manufacturing a semiconductor structure is shown.

[0029] Figures 3 to 13 According to some embodiments of the present disclosure Figure 1 The diagram shows cross-sectional views of various stages of a method for manufacturing a semiconductor structure. DETAILED DESCRIPTION

[0030] Reference will now be made in detail to the present embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0031] In addition, the terms "about," "approximately," "substantially," or "substantially" used herein generally refer to a numerical value with an error or range of less than 20%, preferably within 10%, and more preferably within 5%. Unless otherwise specified, the numerical values ​​mentioned are considered approximate, that is, with an error or range as indicated by "about," "approximately," "substantially," or "substantially."

[0032] In the present disclosure, a semiconductor structure and a method for manufacturing the same are provided. Figure 1 FIG3 is a schematic cross-sectional view of a semiconductor structure 300 according to some embodiments of the present disclosure. The semiconductor structure 300 includes a first semiconductor wafer 100 and a second semiconductor wafer 200 disposed vertically on the first semiconductor wafer 100. The semiconductor structure 300 is fabricated using a hybrid bonding process. For simplicity and clarity, this article will prioritize the fabrication method of the semiconductor structure 300.

[0033] Figure 2 According to some embodiments of the present disclosure Figure 1 Flowchart of a method for manufacturing a semiconductor structure 300 shown in FIG. The method for manufacturing the semiconductor structure 300 includes the following steps. In step S10, a first semiconductor wafer is provided, wherein the first semiconductor wafer includes a first dielectric layer and at least one first top metallization structure embedded in the first dielectric layer, and the top surface of the first dielectric layer is higher than the first top metallization structure by a first distance. In step S20, a second semiconductor wafer is provided, wherein the second semiconductor wafer includes a second dielectric layer and at least one second top metallization structure embedded in the second dielectric layer, and the top surface of the second top metallization structure is higher than the top surface of the second dielectric layer by a second distance. In step S30, the first semiconductor wafer and the second semiconductor wafer are hybrid-bonded. In the following description, the first semiconductor wafer and the second semiconductor wafer are hybrid-bonded. Figures 3 to 13 Further discussing the above steps, Figures 3 to 13 According to some embodiments of the present disclosure Figure 1 Schematic cross-sectional views of various stages of a method for manufacturing a semiconductor structure 300 are shown.

[0034] refer to Figure 3 , the first substrate 110 is provided with at least one first bottom metallization structure 120 embedded therein. Next, a first insulating layer 130 is vertically formed on the first substrate 110 and covers the first bottom metallization structure 120. In some embodiments, the first insulating layer 130 may include a dielectric material such as an oxide. Next, a first etch stop layer 140 is vertically formed on the first insulating layer 130. In some embodiments, the first etch stop layer 140 may include a dielectric material such as SiCN, SiN, Si3N4, other suitable dielectric materials, or combinations thereof. Thereafter, at least one first conductive plug 150 is formed through the first etch stop layer 140 and the first insulating layer 130, such that the first conductive plug 150 contacts the first bottom metallization structure 120. In some embodiments, the first conductive plug 150 contacts the first bottom metallization structure 120. In some embodiments, the first conductive plug 150 is formed by depositing a conductive material in a through hole penetrating the first etch stop layer 140 and the first insulating layer 130 and on the first etch stop layer 140, and then performing a chemical mechanical polishing (CMP) process to remove a portion of the conductive material outside the through hole. As a result, a top surface 151 of the first conductive plug 150 can be substantially coplanar with the top surface 141 of the first etch stop layer 140.

[0035] refer to Figure 4 , then, a first dielectric layer 160 is vertically formed on the first etch stop layer 140. In some embodiments, the first dielectric layer 160 may include a dielectric material such as an oxide. Subsequently, at least one recess R is formed through the first dielectric layer 160 to expose the first conductive plug 150 and a portion of the first etch stop layer 140 through the recess R. In some embodiments, the recess R may be formed by an etching process. The first etch stop layer 140 may prevent the recess R from being over-etched into the first conductive plug 150, thereby enabling alignment of the first top metallization structure formed in the recess R in subsequent steps. In some embodiments, there are multiple first conductive plugs 150, and the recess R is formed to expose more than one first conductive plug 150. In this case, the lateral width W of the first conductive plugs 150 is designed to be the same so that the etching process can be better controlled to further enable alignment of the first top metallization structure formed in the recess R in subsequent steps.

[0036] refer to Figure 5At least one first top metallization structure 170 is filled in the recess R, such that the first top metallization structure 170 is vertically formed on the first etch stop layer 140. In some embodiments, the first top metallization structure 170 is formed by depositing a conductive material in the recess R and on the first dielectric layer 160, and then performing a CMP process to remove a portion of the conductive material outside the recess R. As a result, the top surface 171 of the first top metallization structure 170 can be substantially coplanar with the top surface 161 of the first dielectric layer 160, and the first top metallization structure 170 can be connected to the first bottom metallization structure 120 via the first conductive plug 150. In some embodiments, the first bottom metallization structure 120, the first conductive plug 150, and the first top metallization structure 170 can comprise the same material. In alternative embodiments, any two of the first bottom metallization structure 120, the first conductive plug 150, and the first top metallization structure 170 can comprise the same material. In other embodiments, the first bottom metallization structure 120 , the first conductive plug 150 , and the first top metallization structure 170 may include different materials.

[0037] refer to Figure 6 Next, the top of the first top metallization structure 170 is removed using, for example, a selective etching process that etches the metal material of the top metallization structure 170 at a faster etching rate than the dielectric material of the first dielectric layer 160, resulting in a top surface 161 of the first dielectric layer 160 being higher than a top surface 171 of the first top metallization structure 170. In some embodiments, the top surface 161 of the first dielectric layer 160 is higher than a top surface 171 of the first top metallization structure 170 by a first distance D1. The first distance D1 is designed to maintain a gap for a hybrid bonding process performed in a subsequent step (discussed later in the description). In some embodiments, the top of the first top metallization structure 170 is removed using a time-controlled selective etching process so that the height difference between the top surface 161 of the first dielectric layer 160 and the top surface 171 of the first top metallization structure 170 can be precisely controlled to be substantially equal to the first distance D1. After the top of the first top metallization structure 170 is removed, the first semiconductor wafer 100 is provided as described above in step S10.

[0038] refer to Figure 7The second substrate 210 is provided with at least one second bottom metallization structure 220 embedded therein. Next, a second insulating layer 230 is vertically formed on the second substrate 210, covering the second bottom metallization structure 220. In some embodiments, the second insulating layer 230 may include a dielectric material such as an oxide. Thereafter, at least one second conductive plug 250 is formed through the second insulating layer 230, such that the second conductive plug 250 contacts the second bottom metallization structure 220. In some embodiments, the second conductive plug 250 is formed by depositing a conductive material within and on a via through the second insulating layer 230, followed by a CMP process to remove a portion of the conductive material outside the via. As a result, the top surface 251 of the second conductive plug 250 may be substantially coplanar with the top surface 231 of the second insulating layer 230. Next, a second dielectric layer 260 is vertically formed on the second insulating layer 230, covering the second conductive plug 250. In some embodiments, the second dielectric layer 260 may include a dielectric material such as an oxide. In some embodiments, the second insulating layer 230 and the second dielectric layer 260 may comprise the same material. In alternative embodiments, the second insulating layer 230 and the second dielectric layer 260 may comprise different materials.

[0039] refer to Figure 8 , and then vertically forming a second etch stop layer 240 on the second dielectric layer 260. In some embodiments, the second etch stop layer 240 may comprise a dielectric material such as SiCN, SiN, Si3N4, other suitable dielectric materials, or combinations thereof. In some embodiments, the thickness T1 of the second etch stop layer 240 is substantially equal to the second distance D2, where the second distance D2 is less than the first distance D1. More specifically, the second distance D2 is predetermined by the first distance D1, such that the second distance D2 is less than the first distance D1. The advantages of this design will be further discussed later in the description.

[0040] Please refer to Figure 9 , then at least one recess R is formed through the second etch stop layer 240 and the second dielectric layer 260 to expose the second conductive plug 250 and a portion of the second insulating layer 230 through the recess R. In some embodiments, the recess R can be formed by an etching process. In some embodiments, there are multiple second conductive plugs 250, and the recess R is formed to expose more than one second conductive plug 250. In this case, the lateral width W of the second conductive plugs 250 is designed to be the same to better control the etching process and further facilitate alignment of the second top metallization structure formed in the recess R in subsequent steps.

[0041] refer to Figure 10At least one second top metallization structure 270 is filled in the recess R, such that the second top metallization structure 270 is vertically formed on the second insulating layer 230. In some embodiments, the second top metallization structure 270 is formed by depositing a conductive material in the recess R and on the second etch stop layer 240, and then performing a CMP process to remove a portion of the conductive material outside the recess R. As a result, a top surface 271 of the second top metallization structure 270 can be substantially coplanar with a top surface 241 of the second etch stop layer 240, and the second top metallization structure 270 can be connected to the second bottom metallization structure 220 via a second conductive plug 250. In some embodiments, the second bottom metallization structure 220, the second conductive plug 250, and the second top metallization structure 270 can comprise the same material. In alternative embodiments, any two of the second bottom metallization structure 220, the second conductive plug 250, and the second top metallization structure 270 can comprise the same material. In other embodiments, the second bottom metallization structure 220 , the second conductive plug 250 , and the second top metallization structure 270 may include different materials.

[0042] refer to Figure 11 Next, the second etch stop layer 240 is removed by using, for example, a selective etching process that etches the dielectric material of the second etch stop layer 240 at a faster etching rate than the metal of the metallization structure 270, so that the top of the sidewall of the second top metallization structure 270 is exposed. Figure 8 ) is substantially equal to the second distance D2, so the thickness T2 of the top of the exposed second top metallization structure 270 is also substantially equal to the second distance D2. In other words, the top surface 271 of the second top metallization structure 270 is higher than the top surface 261 of the second dielectric layer 260 by the second distance D2. Since the height difference between the top surface 271 of the second top metallization structure 270 and the top surface 261 of the second dielectric layer 260 is determined by the thickness T1 of the second etch stop layer 240 (see FIG. Figure 8 ) is predetermined, so by simply removing the second etch stop layer 240, a height difference substantially equal to the second distance D2 can be accurately formed without requiring a time-controlled etching process, which is more complex and may result in inaccurate height differences. After removing the second etch stop layer 240, a second semiconductor wafer 200 is provided in step S20 as described above.

[0043] refer to Figure 12Next, the first semiconductor wafer 100 is vertically placed on the second semiconductor wafer 200, such that the second dielectric layer 260 of the second semiconductor wafer 200 is vertically aligned with the first dielectric layer 160 of the first semiconductor wafer 100, and the second top metallization structure 270 of the second semiconductor wafer 200 is vertically aligned with the first top metallization structure 170 of the first semiconductor wafer 100, for the subsequent hybrid bonding process. In other words, the first semiconductor wafer 100 is placed upside down relative to the second semiconductor wafer 200. In this way, the second dielectric layer 260 contacts the first dielectric layer 160, and because the top surface 171 of the first top metallization structure 170 is lower than the top surface 161 of the first dielectric layer 160 by a first distance D1, the top surface 271 of the second top metallization structure 270 is higher than the top surface 261 of the second dielectric layer 260 by a second distance D2, and the second distance D2 is predetermined to be smaller than the first distance D1, a gap G is formed between the first top metallization structure 170 and the second top metallization structure 270, leaving the first top metallization structure 170 and the second top metallization structure 270 to experience thermal expansion during the subsequent hybrid bonding process.

[0044] In some embodiments, the first distance D1 further depends on the conductive thermal expansion coefficients of the first top metallization structure 170 and the second top metallization structure 270. More specifically, the relationship between the first distance D1 and the second distance D2 can be expressed as: D1 = D2 + ΔX, where ΔX is the expected metal thermal expansion dimension, which depends on the conductive thermal expansion coefficients of the first top metallization structure 170 and the second top metallization structure 270. In this case, the vertical length L of the gap G is substantially equal to the expected metal thermal expansion dimension ΔX. In some embodiments, the expected metal thermal expansion dimension ΔX further depends on the metal materials used in the first top metallization structure 170 and the second top metallization structure 270. Therefore, by determining the expected metal thermal expansion dimension ΔX based on the metal materials used in the first top metallization structure 170 and the second top metallization structure 270, hybrid bonding between the first semiconductor wafer 100 and the second semiconductor wafer 200 can be better achieved.

[0045] Please refer to Figure 13 In step S30, a hybrid bonding process is then performed to bond the first semiconductor wafer 100 to the second semiconductor wafer 200. More specifically, an annealing process is performed to cause the first top metallization structure 170 and the second top metallization structure 270 to undergo thermal expansion, thereby ultimately filling the gap G. As a result, the bonding between the first top metallization structure 170 and the second top metallization structure 270 can be accurate and tight, without any gaps being generated therebetween, thereby better achieving high bonding strength between the first semiconductor wafer 100 and the second semiconductor wafer 200.

[0046] exist Figure 13 After step S30, the semiconductor structure 300 of the present disclosure is formed. The semiconductor structure 300 includes a first semiconductor wafer 100 and a second semiconductor wafer 200 vertically disposed on the first semiconductor wafer 100. The first semiconductor wafer 100 includes a first dielectric layer 160 and a first top metallization structure 170 embedded within the first dielectric layer 160. The second semiconductor wafer 200 includes a second dielectric layer 260 and a second top metallization structure 270 embedded within the second dielectric layer 260. The first dielectric layer 160 is bonded to the second dielectric layer 260, and the first top metallization structure 170 is bonded to the second top metallization structure 270. In some embodiments, the first top metallization structure 170 and the second top metallization structure 270 may comprise the same conductive material. In alternative embodiments, the first top metallization structure 170 and the second top metallization structure 270 may comprise different conductive materials.

[0047] In some embodiments, a dielectric-to-dielectric bond 10 (e.g., formed by a hybrid bonding process) is located between a first dielectric layer (upper dielectric layer) 160 and a second dielectric layer (lower dielectric layer) 260, while a metal-to-metal bond 20 (e.g., formed by a hybrid bonding process) is located between a first top metallization structure 170 and a second top metallization structure 270. In some embodiments, the dielectric-to-dielectric bond 10 results in an observable dielectric-to-dielectric interface and / or a mixed region of dielectric materials (e.g., depending on the temperature and / or duration of the annealing of the hybrid bond), while the metal-to-metal bond 20 results in an observable metal-to-metal interface and / or a mixed region of metallic materials (e.g., depending on the temperature and / or duration of the annealing of the hybrid bond).

[0048] In some embodiments, the dielectric-to-dielectric bond 10 and the metal-to-metal bond 20 are vertically located at different levels. For example, the dielectric-to-dielectric bond 10 may be located between the first semiconductor wafer 100 and the second semiconductor wafer 200, while the metal-to-metal bond 20 may be laterally surrounded by the first dielectric layer 160 of the first semiconductor wafer 100. Furthermore, the distance D between the dielectric-to-dielectric bond 10 and the metal-to-metal bond 20 may be substantially equal to the first distance D1 described above.

[0049] In some embodiments, the first semiconductor wafer 100 of the semiconductor structure 300 further includes a first substrate 110 and a first bottom metallization structure (top metallization structure) 120 embedded in the first substrate 110, and the second semiconductor wafer 200 of the semiconductor structure 300 further includes a second substrate 210 and a second bottom metallization structure (bottom metallization structure) 220 embedded in the second substrate 210. In some embodiments, the first semiconductor wafer 100 of the semiconductor structure 300 further includes a first conductive plug 150 vertically disposed between the first top metallization structure (upper metallization structure) 170 and the first bottom metallization structure 120, and the second semiconductor wafer 200 of the semiconductor structure 300 further includes a second conductive plug 250 vertically disposed between the second top metallization structure (lower metallization structure) 270 and the second bottom metallization structure 220. The first conductive plug 150 contacts the first top metallization structure 170 and the first bottom metallization structure 120 to establish an electrical connection therebetween, and the second conductive plug 250 contacts the second top metallization structure 270 and the second bottom metallization structure 220 to establish an electrical connection therebetween. Thus, the electrical connection between the first semiconductor wafer 100 and the second semiconductor wafer 200 can be further achieved through the bonding between the first top metallization structure 170 and the second top metallization structure 270.

[0050] In some embodiments, because the first etch stop layer 140 is retained in the first semiconductor wafer 100 during the fabrication process of the semiconductor structure 300, the first semiconductor wafer 100 of the semiconductor structure 300 may include the first etch stop layer 140 extending laterally above the first dielectric layer (upper dielectric layer) 160 and the first top metallization structure 170. In some embodiments, the first conductive plug 150 may penetrate the first etch stop layer 140 to form an electrical connection between the first top metallization structure 170 and the first bottom metallization structure 120.

[0051] According to the aforementioned embodiments of the present disclosure, since the top surface of the first top metallization structure is lower than the top surface of the first dielectric layer by a first distance, and the top surface of the second top metallization structure is higher than the top surface of the second dielectric layer by a second distance, a gap is retained between the first top metallization structure and the second top metallization structure to allow for thermal expansion during the hybrid bonding process. As a result, the first top metallization structure and the second top metallization structure can be bonded accurately and tightly without any gaps being generated therebetween, thereby effectively achieving high bonding strength between the first semiconductor wafer and the second semiconductor wafer. Furthermore, the semiconductor structure manufactured by this process may include a first interface between the first dielectric layer and the second dielectric layer, and a second interface between the first top metallization structure and the second top metallization structure, wherein the first interface and the second top metallization structure are vertically located at different levels.

[0052] Although certain embodiments of the present disclosure have been described in considerable detail, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0053] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, the present disclosure encompasses modifications and variations of the present disclosure that fall within the scope of the appended claims.

[0054]

Explanation of symbols

[0055] 10: Dielectric to dielectric bonding

[0056] 20: Metal to Metal Bonding

[0057] 100: First semiconductor wafer

[0058] 110: first substrate

[0059] 120: first bottom metallization structure

[0060] 130: first insulating layer

[0061] 140: first etching stop layer

[0062] 141: Top

[0063] 150: first conductive plug

[0064] 151: Top

[0065] 160: first dielectric layer

[0066] 161: Top

[0067] 170: first top metallization structure

[0068] 171: Top

[0069] 200: second semiconductor wafer

[0070] 210: Second substrate

[0071] 220: Second bottom metallization structure

[0072] 230: Second insulation layer

[0073] 231: Top

[0074] 240: Second etch stop layer

[0075] 241: Top

[0076] 250: second conductive plug

[0077] 251: Top

[0078] 260: second dielectric layer

[0079] 261: Top

[0080] 270: Second top metallization structure

[0081] 271: Top

[0082] 300:Semiconductor Structure

[0083] D: Distance

[0084] D1: First distance

[0085] D2: Second distance

[0086] G: Gap

[0087] L: vertical length

[0088] R: Groove

[0089] S10, S20, S30: Steps

[0090] T1, T2: thickness

[0091] W: horizontal width

[0092] ΔX: Expected thermal expansion of the metal.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a first semiconductor wafer, wherein the first semiconductor wafer includes a first dielectric layer and at least one first top metallization structure embedded in the first dielectric layer, and a top surface of the first dielectric layer is higher than the first top metallization structure by a first distance; Providing a second semiconductor wafer, wherein the second semiconductor wafer includes a second dielectric layer and at least one second top metallization structure embedded in the second dielectric layer, and a top surface of the second top metallization structure is higher than a top surface of the second dielectric layer by a second distance, and providing the second semiconductor wafer includes: forming an etch stop layer vertically on the second dielectric layer, wherein a thickness of the etch stop layer is substantially equal to the second distance; as well as The first semiconductor wafer and the second semiconductor wafer are hybrid-bonded. 2 . The method for manufacturing a semiconductor structure according to claim 1 , wherein the second distance is smaller than the first distance. 3 . The method of fabricating a semiconductor structure according to claim 1 , wherein a difference between the first distance and the second distance depends at least in part on a conductive thermal expansion coefficient of the first top metallization structure and the second top metallization structure.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein: Also includes: The first semiconductor wafer is vertically placed on the second semiconductor wafer such that the first dielectric layer contacts the second dielectric layer and a gap is left between the first top metallization structure and the second top metallization structure. The method for manufacturing a semiconductor structure according to claim 4 , wherein the first distance minus the second distance equals a vertical length of the gap.

6. The method for manufacturing a semiconductor structure according to claim 4 , wherein hybrid bonding the first semiconductor wafer and the second semiconductor wafer comprises: An annealing process is performed to cause the first top metallization structure and the second top metallization structure to undergo thermal expansion to fill the gap.

7. The method for manufacturing a semiconductor structure according to claim 1 , wherein providing the first semiconductor wafer comprises: forming an etch stop layer in the first semiconductor wafer; as well as The first dielectric layer and the first top metallization structure are vertically formed on the etch stop layer.

8. The method for manufacturing a semiconductor structure according to claim 7, wherein providing the first semiconductor wafer comprises: forming at least one groove vertically penetrating the first dielectric layer so as to expose a portion of the etch stop layer; as well as The groove is filled with the first top metallization structure.

9. The method for manufacturing a semiconductor structure according to claim 8, wherein providing the first semiconductor wafer comprises: The first top metallization structure is recessed to below the top surface of the first dielectric layer.

10. The method for manufacturing a semiconductor structure according to claim 7, wherein providing the first semiconductor wafer comprises: At least one conductive plug is formed vertically penetrating the etching stop layer.

11. The method for manufacturing a semiconductor structure according to claim 1 , wherein providing the second semiconductor wafer comprises: forming at least one groove vertically penetrating the etch stop layer and the second dielectric layer; as well as The recess is filled with the second top metallization structure such that the top surface of the second top metallization structure is substantially coplanar with the top surface of the etch stop layer.

12. The method for manufacturing a semiconductor structure according to claim 11, wherein providing the second semiconductor wafer comprises: The etch stop layer is removed to expose a portion of a sidewall of the second top metallization structure.

13. A semiconductor structure, characterized in that: include: a lower dielectric layer; at least one lower metallization structure embedded in the lower dielectric layer; an upper dielectric layer forming a dielectric-to-dielectric junction with the lower dielectric layer; as well as at least one upper metallization structure embedded in the upper dielectric layer and forming a metal-to-metal bond with the lower metallization structure, wherein the dielectric-to-dielectric bond and the metal-to-metal bond are located at different levels; and At least one bottom metallization structure and at least one conductive plug vertically disposed between the lower metallization structure and the bottom metallization structure. The semiconductor structure of claim 13 , wherein the metal-to-metal junction is laterally surrounded by the upper dielectric layer. The semiconductor structure of claim 13 , wherein the lower metallization structure and the upper metallization structure comprise the same material.

16. The semiconductor structure according to claim 13, wherein Also included is an etch stop layer extending laterally above the upper dielectric layer and the upper metallization structure.

17. The semiconductor structure according to claim 13, wherein: The conductive plug vertically penetrates an etch stop layer and contacts the upper metallization structure.

18. The semiconductor structure according to claim 17, wherein The invention also includes at least one top metallization structure, and the conductive plug is vertically arranged between the top metallization structure and the upper metallization structure.

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