Integrated circuit device and method of forming the same

Abstract

The present disclosure relates to integrated circuit devices and methods of forming the same. One method includes forming gate structures between gate spacers; etching back the gate structures to below the top ends of the gate spacers; forming a gate dielectric cap over the etched back gate structures; performing an ion implantation process to form a doped region in the gate dielectric cap; depositing a contact etch stop layer over the gate dielectric cap and depositing an ILD layer over the contact etch stop layer; performing a first etch process to form gate contact openings extending through the ILD layer and terminating before reaching the doped region of the gate dielectric cap; performing a second etch process to deepen the gate contact openings, wherein the second etch process etches the doped region of the gate dielectric cap at a slower etch rate than etching the contact etch stop layer; and forming gate contacts in the deepened gate contact openings.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to integrated circuit devices and methods of forming the same. BACKGROUND

[0002] Technological advances in IC materials and design have produced generations of ICs, each having greater functionality and often less geometric size, than previous generations. As a result, the SUMMARY

[0003] According to one embodiment of the present disclosure, a method of forming an integrated circuit device is provided, comprising: forming gate structures between gate spacers and over a semiconductor substrate; etching back the gate structures to below a top end of the gate spacers; forming a gate dielectric cap over the etched back gate structures; performing an ion implantation process to form a doped region in the gate dielectric cap; depositing a contact etch stop layer over the gate dielectric cap and an interlayer dielectric (ILD) layer over the contact etch stop layer; performing a first etch process to form gate contact openings extending through the ILD layer and terminating before reaching the doped region of the gate dielectric cap; performing a second etch process to deepen the gate contact openings, wherein the second etch process etches the doped region of the gate dielectric cap at a slower etch rate than etching the contact etch stop layer; and forming gate contacts in the deepened gate contact openings.

[0004] According to another embodiment of the disclosure, a method of forming an integrated circuit device is provided, including: forming a first gate dielectric cap over a first gate structure and a second gate dielectric cap over a second gate structure; forming a first doped region in the first gate dielectric cap and a second doped region in the second gate dielectric cap; depositing a contact etch stop layer over the first gate dielectric cap and the second gate dielectric cap and depositing an interlayer dielectric (ILD) layer over the contact etch stop layer; performing a first etch process to form a first gate contact opening and a second gate contact opening extending through the ILD layer such that the contact etch stop layer is exposed, wherein a width of the first gate contact opening is less than a width of the second gate contact opening; performing a second etch process on the contact etch stop layer to extend the first gate contact opening and the second gate contact opening toward the first gate structure and the second gate structure, wherein after the second etch process etches through the first doped region in the first gate dielectric cap, a sidewall profile of the first gate contact opening becomes more vertical than before etching the first doped region; and after performing the second etch process, forming a first gate contact in the first gate contact opening and a second gate contact in the second gate contact opening.

[0005] According to yet another embodiment of the disclosure, an integrated circuit device is provided, including: a source / drain epitaxial structure over a substrate; source / drain contacts over the source / drain epitaxial structure, respectively; a gate structure laterally between the source / drain contacts; a gate dielectric cap over the gate structure and having opposing sidewalls that contact the source / drain contacts, respectively, wherein the gate dielectric cap has a doped region extending from a top surface of the gate dielectric cap into the gate dielectric cap; a contact etch stop layer extending over the source / drain contacts and the gate dielectric cap; an interlayer dielectric (ILD) layer over the contact etch stop layer; and a gate contact extending through the ILD layer, the contact etch stop layer, and the doped region of the gate dielectric cap to electrically connect with the gate structure. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to the standard practice in the industry, various features are not necessarily drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.

[0007] Figures 1-20BPerspective and cross-sectional views showing intermediate stages in the formation of an integrated circuit structure in accordance with some embodiments of the present disclosure are shown.

[0008] Figures 21-39B Perspective and cross-sectional views showing intermediate stages in the formation of an integrated circuit structure in accordance with some embodiments of the present disclosure are shown. DETAILED DESCRIPTION

[0009] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description of various embodiments, directional terms (e.g., above, below, upper, lower, up, down, top, bottom) are used for clarity in referring to the relative location of one component to another. Other embodiments can differ (e.g., depending on the relative orientation of the device). The application is not limited to the accurate orientation shown in the figures. For example, the features of the first feature can be formed over or on the second feature in the following description, which can include embodiments in which the first feature and the second feature are formed in direct contact, and can also include embodiments in which additional features can be formed between the first feature and the second feature, such that the first feature and the second feature can not be in direct contact. Furthermore, the present disclosure can repeat certain

[0010] Furthermore, spatially relative terms (e.g., “beneath,” “below,” “lower,” “above,” “upper,” and the like) can be used herein for ease of describing one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. As used herein, “about,” “approximately,” “near,” or “substantially” shall generally mean within twenty percent, or within ten percent, or within five percent of a given value or range. Numerical values given herein are approximate, meaning that the terms “about,” “approximately,” “near,” or “substantially” can also be inferred when not expressly stated.

[0011] The present disclosure relates generally to integrated circuit structures and methods of forming the same, and more particularly to fabricating transistors (e.g., fin field effect transistors (FinFETs), gate-all-around (GAA) transistors) and gate contacts over gate structures of the transistors. It should also be noted that the present disclosure presents embodiments in the form of multi-gate transistors. Multi-gate transistors include those with gate structures formed on at least two sides of a channel region. These multi-gate devices can include p-type metal oxide semiconductor devices or n-type metal oxide semiconductor devices. Due to the fin-like structure of the specific examples, these specific examples can be presented herein and referred to as FinFETs. FinFETs have gate structures formed on three sides of a channel region (e.g., around an upper portion of a channel region in a semiconductor fin). Embodiments of a multi-gate transistor (referred to as a GAA) device are also presented herein. GAA devices include any device with its gate structure or a portion of its gate structure formed on 4 sides of a channel region (e.g., around a portion of a channel region). The devices presented herein also include embodiments with channel regions disposed in nanosheet channel(s), nanowire channel(s), and / or other suitable channel configurations.

[0012] After completing front end of line (FEOL) processing for fabricating the transistors, gate contacts are formed over the gate structures of the transistors. Formation of the gate contacts generally includes, for example but not limited to, depositing an interlayer dielectric (ILD) layer over a gate dielectric cap that covers a high-k / metal gate (HKMG) structure, forming gate contact openings extending through the ILD layer and the gate dielectric cap by using one or more etching processes, and then depositing one or more metal layers in the gate contact openings to serve as the gate contacts.

[0013] In some embodiments, an additional etch stop layer (also referred to as a middle contact etch stop layer (MCESL)) is blanket formed over the gate dielectric cap prior to forming the ILD layer. The MCESL has a different etch selectivity than the ILD layer, and thus the MCESL can slow down an etching process that proceeds through the ILD layer. After performing a contact etch process to form gate contact openings extending through the ILD layer, another etching process (sometimes referred to as a liner removal (LRM) etch because the MCESL and the gate dielectric cap can combine to serve as a liner over a top surface of the gate structure) is performed to penetrate the MCESL and the gate dielectric cap.

[0014] According to circuit functionality and / or design rules, the contact etch process can form gate contact openings having different sizes. Alternatively, due to inaccuracy of the contact etch process, a size difference of the gate contact openings can be inadvertently formed. The size difference formed in the contact etch process can cause the wider gate contact openings to extend deeper into the MCESL than the narrower gate contact openings. This difference in opening depth is referred to as a depth loading problem. Because of the depth loading problem, the wider gate contact openings can sometimes punch through the MCESL and even the gate dielectric cap before the LRM etch process is performed. Thus, the LRM etch process can further deepen the wider gate contact openings into, for example, the gate spacers next to the gate structures, forming a tiger tooth-like recess therein, which in turn creates an increased risk of leakage current (e.g., from the gate contact to the source / drain contact). Moreover, because of the depth loading, the narrower gate contact openings can sometimes have a more tapered profile than the wider gate contact openings, which in turn creates a reduced gate contact area and thus an increased contact resistance.

[0015] Accordingly, the present disclosure provides, in various embodiments, an additional ion implantation step performed on the gate dielectric cap. The ion implantation step creates a doped region in the gate dielectric cap having a different material composition, and thus a different etch selectivity than the undoped region in the gate dielectric cap. Thus, when the gate contact openings reach the doped region, the doped region allows the LRM etch process to slow down. Slowing down the LRM etch can prevent a tiger tooth-like pattern from being formed in the larger openings, which in turn reduces the risk of leakage current. Moreover, slowing down the LRM etch allows the contact openings to be formed with a more vertical profile, which in turn creates an increased gate contact area and thus a reduced contact resistance.

[0016] Figures 1-20B Perspective and cross-sectional views showing intermediate stages in the formation of an integrated circuit structure 100 according to some embodiments of the present disclosure are shown. According to some example embodiments, the formed transistors can include p-type transistors (e.g., p-type FinFETs) and n-type transistors (e.g., n-type FinFETs). Throughout the various views and illustrative embodiments, like reference numerals are used to represent like elements. It will be understood that the various stages shown can be performed in a different order, and that additional stages can be provided before, during, and after the stages shown. Some of the stages described below can be replaced or eliminated for additional embodiments of the method. Figures 1-20B Perspective and cross-sectional views showing intermediate stages in the formation of an integrated circuit structure 100 according to some embodiments of the present disclosure are shown. According to some example embodiments, the formed transistors can include p-type transistors (e.g., p-type FinFETs) and n-type transistors (e.g., n-type FinFETs). Throughout the various views and illustrative embodiments, like reference numerals are used to represent like elements. It will be understood that the various stages shown can be performed in a different order, and that additional stages can be provided before, during, and after the stages shown. Some of the stages described below can be replaced or eliminated for additional embodiments of the method.

[0017] Figure 1A perspective view of an initial structure is shown. The initial structure includes a substrate 12. The substrate 12 can be a semiconductor substrate (also referred to as a wafer in some embodiments), which can be a silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. According to some embodiments of the present disclosure, the substrate 12 includes a bulk silicon substrate and an epitaxial silicon germanium (SiGe) layer or a germanium layer (with no silicon) on top of the bulk silicon substrate. The substrate 12 can be doped with p-type impurities or n-type impurities. Isolation regions 14, such as shallow trench isolation (STI) regions, can be formed extending into the substrate 12. Portions of the substrate 12 located between adjacent STI regions 14 are referred to as semiconductor strips 102.

[0018] The STI regions 14 can include a liner oxide (not shown). The liner oxide can be formed from a thermal oxide formed by thermal oxidation of a surface layer of the substrate 12. The liner oxide can also be a deposited silicon oxide layer formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The STI regions 14 can also include a dielectric material on top of the liner oxide, and the dielectric material can be formed using flowable chemical vapor deposition (FCVD), spin-on, etc.

[0019] Referring to Figure 2 The STI regions 14 are recessed such that a top portion of the semiconductor strips 102 protrudes above a top surface of the adjacent STI regions 14 to form protruding fins 104. The etching can be performed using a dry etching process, with NH3 and NF3 used as etching gases. A plasma can be generated during the etching process. Argon can also be included. According to alternative embodiments of the present disclosure, the recessing of the STI regions 14 is performed using a wet etching process. For example, the etching chemistry can include dilute HF.

[0020] In the above example embodiments, the fins can be patterned by any suitable method. For example, one or more photolithography processes (including a dual patterning or multi-patterning process) can be used to pattern the fins. In general, a dual patterning or multi-patterning process combines photolithography and self-alignment processes, allowing for the creation of patterns with, for example, a pitch that is less than is obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate, and the sacrificial layer is patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins.

[0021] The material of the protruding fin 104 can also be replaced with a material different from that of the substrate 12. For example, if the protruding fin 104 is for an n-type transistor, the protruding fin 104 can be formed of Si, SiP, SiC, SiPC, or a III-V compound semiconductor (e.g., InP, GaAs, AlAs, InAs, InAlAs, InGaAs), etc. On the other hand, if the protruding fin 104 is for a p-type transistor, the protruding fin 104 can be formed of Si, SiGe, SiGeB, Ge, or a III-V compound semiconductor (e.g., InSb, GaSb, InGaSb), etc.

[0022] Referring to Figure 3A and Figure 3B The dummy gate structure 106 is formed on the top surface and sidewalls of the protruding fin 104. Figure 3B A cross-sectional view taken from a vertical plane containing line B-B in Figure 3A The formation of the dummy gate structure 106 includes sequentially depositing a gate dielectric layer and a dummy gate electrode layer on the fin 104, followed by patterning the gate dielectric layer and the dummy gate electrode layer. As a result of the patterning, the dummy gate structure 106 includes a gate dielectric layer 108 and a dummy gate electrode 110 located above the gate dielectric layer 108. The gate dielectric layer 108 can be any acceptable dielectric layer (e.g., silicon oxide, silicon nitride, etc., or a combination thereof), and the gate dielectric layer 108 can be formed using any acceptable process (e.g., thermal oxidation, spin-on process, CVD, etc.). The dummy gate electrode 110 can be any acceptable electrode layer, including, for example, polysilicon, metal, etc., or a combination thereof. The gate electrode layer can be deposited by any acceptable deposition process (e.g., CVD, plasma-enhanced CVD (PECVD), etc.). Each dummy gate structure 106 spans a single or multiple protruding fins 104. The dummy gate structure 106 can have a longitudinal direction that is perpendicular to the longitudinal direction of the corresponding protruding fin 104.

[0023] A mask pattern can be formed over the dummy gate electrode layer to assist in the patterning. In some embodiments, the hard mask pattern includes a bottom mask 112 located over a blanket layer of polysilicon and a top mask 114 located over the bottom mask 112. The hard mask pattern is made of one or more layers of SiO2, SiCN, SiON, Al2O3, SiN, or other suitable material. In certain embodiments, the bottom mask 112 includes silicon nitride and the top mask 114 includes silicon oxide. The dummy electrode layer is patterned into the dummy gate electrode 110 and the blanket gate dielectric layer is patterned into the gate dielectric layer 108 by using the mask pattern as an etch mask.

[0024] Next, as Figure 4As shown, gate spacers 116 are formed on the sidewalls of dummy gate structure 106. In some embodiments of the gate spacer forming step, a spacer material layer is deposited on substrate 12. The spacer material layer can be a conformal layer that is subsequently etched back to form gate sidewall spacers 116. In some embodiments, the spacer material layer includes multiple layers, for example, a first spacer layer 118 and a second spacer layer 120 formed on first spacer layer 118. First spacer layer 118 and second spacer layer 120 are each made of a suitable material, for example, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof. First spacer layer 118 and second spacer layer 120 can be formed by, for example but not limited to, sequentially depositing two different dielectric materials over dummy gate structure 106 using a process such as a CVD process, a sub-atmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process. An anisotropic etch process is then performed on the deposited spacer layers 118 and 120 to expose portions of fins 104 that are not covered by dummy gate structure 106 (e.g., in source / drain regions of fins 104). Portions of spacer layers 118 and 120 that are directly above dummy gate structure 106 can be completely removed by the anisotropic etch process. Portions of spacer layers 118 and 120 that are on the sidewalls of dummy gate structure 106 can be left intact, thereby forming gate sidewall spacers, which are denoted as gate spacers 116 for simplicity. In some embodiments, first spacer layer 118 is formed of silicon oxide having a lower dielectric constant than silicon nitride, and second spacer layer 120 is formed of silicon nitride, which has a higher etch resistance than silicon oxide for a subsequent etch process (e.g., etching source / drain recesses in fins 104). In some embodiments, gate sidewall spacers 116 can be used to offset subsequently formed doped regions (e.g., source / drain regions). Gate spacers 116 can further be used to design or modify source / drain region profiles.

[0025] In Figure 5 some embodiments, after the formation of gate sidewall spacers 116 is completed, source / drain epitaxial structures 122 are formed on source / drain regions of fins 104 that are not covered by dummy gate structure 106 and gate sidewall spacers 116. In some embodiments, the formation of source / drain epitaxial structures 122 includes recessing source / drain regions of fins 104, and then epitaxially growing semiconductor material in the recessed source / drain regions of fins 104.

[0026] The source / drain regions of the fins 104 can be recessed using a suitable selective etching process that etches the semiconductor fins 104 but etches little to none of the top mask 114 and gate spacers 116 of the dummy gate structures 106. For example, recessing the semiconductor fins 104 can be performed by dry chemical etching with a plasma source and an etchant gas. The plasma source can be an inductively coupled plasma (ICP) etch, a transformer coupled plasma (TCP) etch, an electron cyclotron resonance (ECR) etch, a reactive ion etch (RIE), or the like, and the etchant gas can be fluorine, chlorine, bromine, combinations thereof, or the like, that etches the semiconductor fins 104 at a faster etch rate than it etches the top mask 114 and gate spacers 116 of the dummy gate structures 106. In some other embodiments, recessing the semiconductor fins 104 can be performed by wet chemical etching (e.g., ammonium peroxide mixture (APM), NH4OH, tetramethylammonium hydroxide (TMAH), combinations thereof, or the like) that etches the semiconductor fins 104 at a faster etch rate than it etches the top mask 114 and gate spacers 116 of the dummy gate structures 106. In some other embodiments, recessing the semiconductor fins 104 can be performed by a combination of dry chemical etching and wet chemical etching.

[0027] Once the recesses are created in the source / drain regions of the fins 104, source / drain epitaxial structures 122 are formed in the source / drain recesses in the fins 104 by using one or more epitaxial (epi) processes that provide one or more epitaxial materials on the semiconductor fins 104. During the epitaxial growth process, the gate spacers 116 confine the one or more epitaxial materials to the source / drain regions in the fins 104. In some embodiments, the lattice constant of the epitaxial structures 122 is different from the lattice constant of the semiconductor fins 104, such that the channel regions in the fins 104 and between the epitaxial structures 122 can be strained or stressed by the epitaxial structures 122 to improve carrier mobility of the semiconductor devices and enhance device performance. The epitaxial process includes CVD deposition techniques (e.g., PECVD, vapor phase epitaxy (VPE), and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and / or other suitable processes. The epitaxial process can use gaseous and / or liquid precursors that interact with the composition of the semiconductor fins 104.

[0028] In some embodiments, the source / drain epitaxial structure 122 can include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials. The source / drain epitaxial structure 122 can be doped in-situ during the epitaxial process by introducing dopant species including p-type dopants such as boron or BF2, n-type dopants such as phosphorus or arsenic, and / or other suitable dopants including combinations of the foregoing. If the source / drain epitaxial structure 122 is not doped in-situ, an implantation process (i.e., a junction implantation process) is performed to dope the source / drain epitaxial structure 122. In some example embodiments, the source / drain epitaxial structure 122 in n-type transistors includes SiP, while the source / drain epitaxial structure 122 in p-type transistors includes GeSnB and / or SiGeSnB. In embodiments having different device types, a mask (e.g., photoresist) can be formed over the n-type device regions while exposing the p-type device regions, and a p-type epitaxial structure can be formed on the exposed fins 104 in the p-type device regions. The mask can then be removed. Subsequently, a mask (e.g., photoresist) can be formed over the p-type device regions while exposing the n-type device regions, and an n-type epitaxial structure can be formed on the exposed fins 104 in the n-type device regions. The mask can then be removed.

[0029] Once the source / drain epitaxial structure 122 is formed, an anneal process can be performed to activate the p-type dopants or n-type dopants in the source / drain epitaxial structure 122. The anneal process can be, for example, a rapid thermal anneal (RTA), a laser anneal, a millisecond thermal anneal (MSA) process, or the like.

[0030] Next, a gate dielectric layer 124 is formed over the fins 104. The gate dielectric layer 124 can be formed by any suitable process, such as a thermal oxidation process, a chemical vapor deposition (CVD) process, a plasma-enhanced CVD (PECVD) process, an atomic layer deposition (ALD) process, or the like. The gate dielectric layer 124 can include silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or other suitable materials. Figure 6In this process, an interlayer dielectric (ILD) layer 126 is formed on substrate 12. In some embodiments, a contact etch stop layer (CESL) may be formed prior to the formation of the ILD layer 126. In some examples, the CESL comprises a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other suitable materials having a different etch selectivity than the ILD layer 126. The CESL can be formed by a plasma-enhanced chemical vapor deposition (PECVD) process and / or other suitable deposition or oxidation processes. In some embodiments, the ILD layer 126 comprises materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide (e.g., borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG)), and / or other suitable dielectric materials having a different etch selectivity than the CESL. The ILD layer 126 can be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after the formation of the ILD layer 126, the wafer may undergo a high thermal budget process to anneal the ILD layer 126.

[0031] In some examples, after forming the ILD layer 126, a planarization process can be performed to remove excess material from the ILD layer 126. For example, the planarization process includes a chemical mechanical planarization (CMP) process, which removes portions of the ILD layer 126 (and CESL, if present) covering the dummy gate structure 106. In some embodiments, the CMP process also removes hard mask layers 112, 114 (e.g., Figure 5 (as shown) and exposes the dummy gate electrode 110.

[0032] Next, as Figure 7 As shown, the remaining dummy gate structure 106 is removed, thereby forming a gate trench GT1 between the respective gate sidewall spacers 116. The dummy gate structure 106 is removed using a selective etching process (e.g., selective dry etching, selective wet etching, or a combination thereof), which etches the material in the dummy gate structure 106 at a faster etch rate than it etches other materials (e.g., gate sidewall spacers 116 and / or ILD layer 126).

[0033] After that, as Figure 8As shown, replacement gate structures 130 are formed in the gate trenches GT1, respectively. The gate structures 130 can be final gates for the FinFETs. The final gate structures can each be a high-k / metal gate (HKMG) stack, although other compositions are possible. In some embodiments, each gate structure 130 forms a gate associated with three sides of a channel region provided by the fin 104. In other words, each gate structure 130 surrounds the fin 104 on three sides. In various embodiments, the high-k / metal gate structure 130 includes a gate dielectric layer 132 lined on the gate trench GT1, a work function metal layer 134 formed on the gate dielectric layer 132, and a fill metal 136 formed on the work function metal layer 134 and filling a remaining portion of the gate trench GT1. The gate dielectric layer 132 includes an interface layer (e.g., a silicon oxide layer) and a high-k gate dielectric layer on the interface layer. As used and described herein, a high-k gate dielectric includes a dielectric material having a high dielectric constant (e.g., greater than the dielectric constant of thermal silicon oxide (~3.9)). The work function metal layer 134 and / or the fill metal layer 136 used in the high-k / metal gate structure 130 can include a metal, a metal alloy, or a metal silicide. Formation of the high-k / metal gate structure 130 can include a variety of deposition processes for forming the various gate materials, one or more liner layers, and one or more CMP processes for removing excess gate material.

[0034] In some embodiments, the interface layer of the gate dielectric layer 132 can include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interface layer can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-k dielectric layer of the gate dielectric layer 132 can include hafnium oxide (HfO2). Alternatively, the gate dielectric layer 132 can include other high-k dielectrics such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), silicon oxynitride (SiON), and combinations thereof.

[0035] The work function metal layer 134 can include a work function metal for providing a suitable work function for the high-k / metal gate structure 130. For an n-type FinFET, the work function metal layer 134 can include one or more n-type work function metals (N-metals). The n-type work function metal can illustratively include, but is not limited to, titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and / or other suitable materials. On the other hand, for a p-type FinFET, the work function metal layer 134 can include one or more p-type work function metals (P-metals). The p-type work function metal can illustratively include, but is not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and / or other suitable materials.

[0036] In some embodiments, the fill metal 136 can illustratively include, but is not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials.

[0037] Reference is then made to Figure 9 A back-etch process is performed to back-etch the replacement gate structure 130 and the gate spacers 116, thereby forming a recess Rl over the back-etched gate structure 130 and the back-etched gate spacers 116. In some embodiments, because the material of the replacement gate structure 130 has a different etch selectivity than the gate spacers 116, a first selective etch process can be performed first to back-etch the replacement gate structure 130, thereby lowering the replacement gate structure 130 to fall below the gate spacers 116. Then, a second selective etch process is performed to lower the gate spacers 116. As a result, the top surface of the replacement gate structure 130 can be at a different level than the top surface of the gate spacers 116. For example, in the illustrated embodiment as shown in Figure 9 However, in some other embodiments, the top surface of the replacement gate structure 130 can be flush with or higher than the top surface of the gate spacers 116.

[0038] A gate metal cap 138 is then optionally formed on top of the replacement gate structure 130 by an appropriate process such as CVD or ALD. In some embodiments, the metal cap 138 is formed on the replacement gate structure 130 using a bottom-up approach. For example, the metal cap 138 is selectively grown on metal surfaces such as the work function metal layer 134 and the fill metal 136, and thus the sidewalls of the gate spacers 116 are substantially free of the grown metal cap 138. In some embodiments where the FFW is formed using a chlorine-containing precursor, the metal cap 138 can be, for example but not limited to, a substantially fluorine-free tungsten (FFW) film having an amount of fluorine contaminants less than 5 atomic % and an amount of chlorine contaminants greater than 3 atomic %. For example, the FFW film or a film containing FFW can be formed by ALD or CVD using one or more non-fluorine-based tungsten precursors such as, but not limited to, tungsten pentachloride (WC15), tungsten hexachloride (WC16). In some embodiments, portions of the metal cap 138 can extend over the gate dielectric layer 132 such that the metal cap 138 can also cover the exposed surface of the gate dielectric layer 132. Since the metal cap 138 is formed in a bottom-up manner, its formation can be simplified by, for example, reducing the number of repeated etch-back processes (used to remove unwanted metal material due to conformal growth).

[0039] In some embodiments where the metal cap 138 is formed using a bottom-up approach, the metal cap 138 has a different nucleation delay on metal surfaces (i.e., metal in the gate structure 130) compared to dielectric surfaces (i.e., dielectric in the gate spacers 116 and / or the ILD layer 126). The nucleation delay on the metal surfaces is shorter than the nucleation delay on the dielectric surfaces. Thus, the difference in nucleation delay allows for selective growth on the metal surfaces. The present disclosure takes advantage of such selectivity in various embodiments to allow metal to grow from the gate structure 130 while suppressing metal growth from the spacers 116 and / or the ILD layer 126. As a result, the deposition rate of the metal cap 138 on the gate structure 130 is faster than the deposition rate of the metal cap 138 on the spacers 116 and the ILD layer 126. In some embodiments, the top surface of the resulting metal cap 138 is lower than the top surface of the etched-back gate spacers 116. However, in some other embodiments, the top surface of the metal cap 138 can be flush with or higher than the top surface of the etched-back gate spacers 116.

[0040] Next, as Figure 10As shown, a dielectric cap layer 140 is formed, which is deposited over the substrate 12 until the recesses Rl are overfilled. The dielectric cap layer 140 includes SiN, SiC, SiCN, SiON, SiCON, combinations thereof, and the like, and is formed by a suitable deposition technique such as CVD, plasma-enhanced CVD (PECVD), ALD, remote plasma ALD (RPALD), plasma-enhanced ALD (PEALD), combinations thereof, and the like. A CMP process is then performed to remove the cap layer outside the recesses Rl, leaving portions of the dielectric cap layer 140 in the recesses Rl to serve as gate dielectric caps 142. In Figure 11 The resulting structure is shown in

[0041] Referring to Figure 12 , source / drain contacts 144 are formed extending through the ILD layer 126. The formation of the source / drain contacts 144 includes, for example but not limited to, performing one or more etching processes to form contact openings extending through the ILD layer 126 (and the CESL, if present) to expose the source / drain epitaxial structures 122; depositing one or more metallic materials that overfill the contact openings; and then performing a CMP process to remove the excess metallic material outside the contact openings. In some embodiments, the one or more etching processes are selective etches that etch the ILD layer 126 at a faster etch rate than the gate dielectric caps 142 and the gate spacers 116. As a result, the selective etches are performed using the dielectric caps 142 and the gate spacers 116 as etch masks, such that the contact openings (and thus the source / drain contacts 144) are formed self-aligned to the source / drain epitaxial structures 122 without the need to use an additional photolithography process. In that case, the source / drain contacts 144 can be referred to as self-aligned contacts (SACs), and the gate dielectric caps 142 that allow the formation of the self-aligned contacts 144 can be referred to as SAC caps 142. As a result of the formation of the self-aligned contacts, the SAC caps 142 each have opposing sidewalls that are in contact with the source / drain contacts 144, respectively.

[0042] In Figure 13In some embodiments, an ion implantation process IMP1 is performed to dope one or more impurities (e.g., dopant ions) into the gate dielectric cap 142. For example, ionized dopant DP (e.g., oxygen, germanium, argon, xenon, boron, and / or other suitable species capable of producing an etch selectivity different from that of the material of the gate dielectric cap 142) can be implanted into the gate dielectric cap 142, thereby forming a doped region 1421 in the gate dielectric cap 142. In some embodiments, a patterned mask (e.g., a patterned photoresist) can be formed to cover the exposed surfaces of the source / drain contacts 144 prior to performing the ion implantation process IMP1 by using a suitable photolithography process, the implantation process IMP1 is performed using the patterned mask as an implantation mask, and then the patterned mask is removed (e.g., by ashing) after the ion implantation process IMP1 is completed. In this case, the source / drain contacts 144 are substantially free of dopant DP. Alternatively, the ion implantation process IMP1 can also implant some ionized dopant DP into the source / drain contacts 144, and thus form a doped region in the source / drain contacts 144. In this case, the doped region in the source / drain contacts 144 can then be punched through in a subsequent etching process to form source / drain vias over the source / drain contacts 144.

[0043] In some embodiments, the ion implantation process IMP1 is performed at a dose of about 1E15 ions / cm 2 to about 5E20 ions / cm 2 , an energy of about 1 keV to about 180 keV, and a temperature of about 20 °C to about 450 °C. The dopant concentration and / or dopant depth of the resulting doped region 1421 depend on the process conditions of the ion implantation process IMP1. If the process conditions of the ion implantation process IMP1 are not within the selected ranges described above, the dopant concentration and / or dopant depth in the resulting doped region 1421 can not be satisfactory, thereby slowing down the subsequent LRM etching process.

[0044] In some embodiments, the ion implantation process IMP1 implants molecular oxygen ions (O2 + ) or atomic oxygen ions (O + ) into the gate dielectric cap 142, thereby producing an oxygen-doped region 1421 in the gate dielectric cap 142 while leaving a lower region 1422 of the gate dielectric cap 142 substantially undoped. As a result, the oxygen-doped region 1421 has a higher oxygen concentration (or oxygen atom percentage) than the undoped region 1422. For example, but not limited to, the oxygen-doped region 1421 has an oxygen concentration of about 1E18 atoms / cm 3 to about 5E23 atoms / cm 3the oxygen-doped region 1421 has a too low oxygen concentration, the etch rate of the oxygen-doped region 1421 can be too fast to slow down the subsequent LRM etch process.

[0045] In some embodiments, the oxygen-doped region 1421 has an oxygen concentration gradient due to the ion implantation process IMP1. In more detail, the oxygen concentration of the oxygen-doped region 1421 varies according to the depth inside the oxygen-doped region 1421. For example, the oxygen concentration can decrease as the distance from the top surface of the oxygen-doped region 1421 increases. In some embodiments where the gate dielectric cap 142 is silicon nitride, the oxygen-to-nitrogen atomic ratio in the oxygen-doped region 1421 is also a gradient. For example, the oxygen-to-nitrogen atomic ratio in the oxygen-doped region 1421 can decrease as the distance from the top surface of the oxygen-doped region 1421 increases.

[0046] In some embodiments, the doped region 1421 has a dopant depth D1 that extends from the top surface of the gate dielectric cap 142 into the gate dielectric cap 142. In some embodiments, for a 3 nm technology node, the dopant depth D1 is in a range from about 1 angstrom to about 50 angstroms. In some other embodiments, the ratio of the dopant depth D1 to the maximum thickness T1 of the gate dielectric cap 142 is in a range from about 3% to about 60%. If the dopant depth D1 and / or the ratio of D1 / T1 is too small, the doped region 1421 can be too thin to slow down the subsequent LRM etch process. If the dopant depth D1 and / or the ratio of D1 / T1 is too large, the doped region 1421 can be too thick to be punched through in the expected duration. For other technology nodes, such as a 20 nm node, a 16 nm node, a 10 nm node, a 7 nm node, and / or a 5 nm node, the dopant depth D1 can be in a range from about 1 nm to about 20 nm.

[0047] In some embodiments, after the ion implantation process IMP1 is completed, an anneal process can be performed to repair implant damage in the gate dielectric cap 142 and / or the source / drain contacts 144. In some other embodiments, the anneal process can be skipped such that the doped region 1421 can not undergo anneal.

[0048] In Figure 14Once the doped region 1421 is formed in the gate dielectric cap 142, an intermediate contact etch stop layer (MCESL) 146 is then formed over the source / drain contacts 144 and the gate dielectric cap 142. The MCESL 146 can be formed by a PECVD process and / or other suitable deposition processes. In some embodiments, the MCESL 146 is a silicon nitride layer and / or has a layer that interacts with the subsequently formed ILD layer (e.g., ...). Figure 15 Other suitable materials with different etching selectivity (as shown). In some embodiments, both the undoped regions 1422 and MCESL 146 of the gate dielectric cap 142 are silicon nitride (SiN), and therefore the doped region 1421 (e.g., oxygen-doped region) in the gate dielectric cap 142 has different etching selectivity than both the undoped regions 1422 and MCESL 146.

[0049] refer to Figure 15 Another ILD layer 148 is formed on top of the MCESL 146. In some embodiments, the ILD layer 148 comprises materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide (e.g., borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), etc.), and / or other suitable dielectric materials having different etch selectivity than the MCESL 146 (e.g., silicon nitride). In some embodiments, the ILD layer 148 is made of silicon oxide (SiO2). X ILD layer 148 can be formed using PECVD or other suitable deposition techniques.

[0050] refer to Figure 16 The ILD layer 148 is patterned using a first etching process (also known as a contact etching process) ET1 to form gate contact openings O21 and O22 extending through the ILD layer 148. In some embodiments, the contact etching process ET1 is an anisotropic etching process, such as plasma etching. Taking plasma etching as an example, the gate contact openings O21 and O22 are patterned using a first etching process (also known as a contact etching process) ET1 to form gate contact openings O21 and O22 extending through the ILD layer 148. Figure 15The semiconductor substrate 12, shown in the structure, is loaded into a plasma tool and the semiconductor substrate 12 is exposed to a plasma environment generated by RF or microwave power in a gas mixture of a fluorine containing gas (e.g., C4F8, C5F8, C4F6, CHF3, or similar species), an inert gas (e.g., argon or helium), and optionally a weak oxidizer (e.g., O2 or CO or similar species) for a duration sufficient to etch through the ILD layer 148 and recess the exposed portions of the MCESL 146 at the bottom of the gate contact openings O21 and O22. A plasma generated in a gas mixture including C4F6, CF4, CHF3, O2, and argon can be used to etch through the ILD layer 148 and recess the exposed portions of the MCESL 146 at the bottom of the gate contact openings O21 and O22. The plasma etch environment has a pressure of about 10 to about 100 mTorr, and the plasma is generated by RF power between about 50 to about 1000 Watts.

[0051] In some embodiments, the foregoing etchant and etch conditions of the contact etch process ET1 are selected in such a manner that the MCESL 146 (e.g., SiN) exhibits a slower etch rate than the ILD layer 148 (e.g., SiO x ) more quickly than the etch rate of the nitride. As a result, according to some embodiments of the disclosure, the contact etch process ET1 is performed using a gas mixture that is free of hydrogen. In other words, the plasma in the contact etch process ET1 is generated in a gas mixture that does not include a hydrogen (H2) gas. In this manner, the etch rate of the nitride remains low in the contact etch process ET1, which in turn allows the oxide (i.e., the ILD material) to be etched at a faster etch rate than the nitride (i.e., the MCESL and the gate dielectric cap material).

[0052] In some embodiments, prior to the contact etch process ET1, a lithography process is performed to define the intended top-down pattern of the gate contact openings O21 and O22. For example, the lithography process can include: patterning a photoresist layer (not shown) over the ILD layer 148 (e.g., SiO2) to define the intended top-down pattern of the gate contact openings O21 and O22. Figure 15A photoresist layer is spin-coated onto the surface of the photoresist (as shown); a post-exposure baking process is performed; and the photoresist layer is developed to form a patterned mask having a top view pattern of gate contact openings O21 and O22. In some embodiments, patterning the photoresist to form the patterned mask may be performed using an electron beam lithography process or an extreme ultraviolet (EUV) lithography process.

[0053] In such Figure 16 In some embodiments shown, a gate contact opening O21 with a first lateral dimension (e.g., a first maximum width W21) and a gate contact opening O22 with a second lateral dimension (e.g., a second maximum width W22) are simultaneously formed in the contact etching process ET1. The second maximum width W22 may be larger than the first maximum width W21. The width difference between the gate contact openings O21 and O22 may be intentionally formed according to circuit function and / or design rules. Alternatively, due to the imprecision of the contact etching process ET1, the width difference between the gate contact openings O21 and O22 may be unintentionally formed. For example, one or more of the gate contact openings O21 and O22 may be limited by other features (e.g., a patterned mask formed on the ILD layer 148), and have different dimensions from the original design when the formed gate contact openings O21 and O22 are not aligned with the original design. Although the accompanying drawings throughout the specification show the integrated circuit structure 100 including only narrower and wider gate contact openings O21, this is merely an example. Depending on the application, the integrated circuit structure 100 can accommodate any number of gate contacts of different sizes.

[0054] It has been observed that the width difference between gate contact openings O21 and O22 affects the result of contact etching process ET1, causing the narrower gate contact opening O21 to be shallower than the wider gate contact opening O22. More specifically, once contact etching process ET1 is completed, the narrower gate contact opening O21 has a depth D21, and the wider gate contact opening O22 has a depth D22 greater than D21. This difference in depth between gate contact openings O21 and O22 is referred to as depth loading caused by the width difference of the gate contact openings.

[0055] Figure 17 A cross-sectional view of the initial stage of a second etching process (also known as an LRM etching process) ET2 according to some embodiments of the present disclosure is shown. Figure 18 A cross-sectional view of the next stage of the LRM etching process ET2 according to some embodiments of the present disclosure is shown, as well as Figure 19AA cross-sectional view of the final stage of the LRM etching process ET2 according to some embodiments of the present disclosure is shown. The etching duration of the LRM etching process ET2 is controlled to penetrate (or pass through) the MCESL 146 and the gate dielectric cap 142, thereby deepening or extending the gate contact openings O21 and O22 down to the gate metal cap 138 above the gate structure 130. As a result of the LRM etching process ET2, the gate metal cap 138 is exposed at the bottom of the deepened gate contact openings O21 and O22.

[0056] In some embodiments, the LRM etching process ET2 is an anisotropic etching process using different etchants and / or etching conditions than the contact etching process ET1, such as plasma etching (e.g., inductively coupled plasma (ICP), capacitively coupled plasma (CCP), etc.). The etchant and / or etching conditions of the LRM etching process ET2 are selected in such a way that the doped region 1421 exhibits a slower etching rate than the MCESL 146 and the undoped region 1422. In other words, in the LRM etching process ET2, the doped region 1421 has higher etch resistance than the MCESL 146 and the undoped region 1422. In this way, when the gate contact openings O21 and O22 reach the doped region 1421, the doped region 1421 can slow down the LRM etching process ET2, which in turn slows down the vertical etching rate and depth increase in the gate contact openings O21 and O22. Therefore, the depth difference between the narrower gate contact opening O21 and the wider gate contact opening O22 can be reduced by using the doped region 1421. This reduced depth loading prevents the formation of a serrated pattern in the wider gate contact opening O22, thereby reducing the risk of leakage current (e.g., leakage current from the gate contact to the source / drain contact). Furthermore, since the doped region 1421 slows down the vertical etch rate of the lower portion of the gate contact openings O21 and O22 when they reach the doped region 1421, but does not slow down the lateral etch rate, the LRM etching process ET2 can laterally extend the lower portion of the gate contact openings O21 and O22 during etching of the anti-etch layer 145. This allows for an increase in the bottom width of the gate contact openings O21 and O22, and the gate contact openings O21 and O22 can become more vertical than before the doped region 1421 is penetrated. Figures 17-18 As shown.

[0057] Taking plasma etching as an example of the LRM etching process ET2, it will have Figure 16The semiconductor substrate 12 of the structure shown is loaded into a plasma tool and the semiconductor substrate 12 is exposed to a plasma environment generated by RF or microwave power in a gas mixture of one or more of: a fluorine-containing gas (e.g., CHF3, CF4, C2F2, C4F6, C x H y F z (x, y, z = 0-9) or the like), a hydrogen-containing gas (e.g., H2), a nitrogen-containing gas (e.g., N2), and an inert gas (e.g., argon or helium). The plasma etch environment has a pressure of about 10 to about 100 mTorr, and the plasma is generated by RF power of between about 50 to about 1000 Watts.

[0058] The plasma generated from the hydrogen-containing gas mixture can etch silicon nitride at a faster etch rate than etching doped silicon nitride (e.g., oxygen-doped silicon nitride), and thus the LRM etch process ET2 using the hydrogen-containing gas mixture etches the doped region 1421 at a slower etch rate than etching the MCESL 146. In this way, the doped region 1421 can slow down the LRM etch process ET2. In some embodiments, the LRM etch process ET2 uses a gas mixture of CHF3gas with H2gas, where the flow ratio of CHF3gas to H2gas is about 1 : 1 to about 1 : 100. In some embodiments, the LRM etch process ET2 uses a gas mixture of CF4gas with H2gas, where the flow ratio of CF4gas to H2gas is about 1 : 1 to about 1 : 100. In some embodiments, the LRM etch process ET2 uses a gas mixture of CH2F2gas with H2gas, where the flow ratio of CH2F2gas to H2gas is about 1 : 1 to about 1 : 100. Too high of a flow of H2gas can cause the etch rate to be too fast when etching through the undoped region 1422 of the gate dielectric cap 142, which in turn can cause non-negligible tiger tooth-like recesses in the wider gate contact opening O22. Too low of a flow of H2gas can cause insufficient etch selectivity between the doped region 1421 and the MCESL 146. In some embodiments, the ratio of the etch rate of the doped region 1421 to the etch rate of the MCESL 146 and / or the undoped region 1422 is in the range of about 2 to about 10.

[0059] As Figure 17As shown, in the initial stage of LRM etching process ET2, the plasma etchant etches MCESL 146 at a first vertical etch rate A1. In the next stage of LRM etching process ET2, once the gate contact openings O21 and O22 penetrate MCESL 146, the doped region 1421 of the gate dielectric cap 142 is exposed, and then the plasma etchant etches the doped region 1421 at a second vertical etch rate A2, which is slower than the first vertical etch rate A1, as... Figure 18 As shown. As a result, the depth difference between the narrower gate contact opening O21 and the wider gate contact opening O22 can be reduced by using the doped region 1421. Furthermore, the LRM etching process ET2 can laterally extend the lower portions of the gate contact openings O21 and O22 during the etching of the doped region 1421, resulting in gate contact openings O21 and O22 having increased bottom width and more vertical sidewall profiles, as shown. Figure 18 As shown. Figure 19A The results of the LRM etching process ET2 shown show that the gate contact openings O21 and O22 have substantially vertical sidewalls and no tiger-tooth-shaped recesses.

[0060] In some embodiments, the sidewalls of the gate contact openings O21 and O22 extend linearly and vertically through the entire thickness of the ILD layer 148, the entire thickness of the MCESL 146, and the entire thickness of the dielectric cap 142, without any change in slope. Figure 19B In some other embodiments shown, because the LRM etching process ET2 can etch the undoped region 1422 at a faster vertical etch rate than etching the doped region 1421 of the gate dielectric cap 142, especially when the gate dielectric cap 142 is formed of the same material as MCESL 146 (e.g., silicon nitride), the lower sidewalls of the gate contact openings O21 and O22 may taper gradually. In this case, the sidewalls of the gate contact openings O21 and O22 may be more vertical (or steeper) in the upper part of the gate contact openings O21 and O22 than in the lower part, and the slope change of the sidewalls of the gate contact openings O21 and O22 may be located at the interface between the doped region 1421 and the undoped region 1422.

[0061] In such Figure 19AIn some embodiments shown, the wider gate contact opening O22 can extend into the adjacent gate spacer 116, creating a notched corner C22 in the gate spacer 116. This notched corner C22 can be unintentionally formed due to inaccuracy of the contact etch process ET1 and / or the LRM etch process ET2. However, even in this case, the gate spacer 116 will not be unintentionally over-etched to form a tiger tooth recess, because the increased depth in the wider gate contact opening O22 slows down during the punch-through doping 1421 as previously discussed. Given that the wider gate contact opening O22 has no tiger tooth recess or is negligible, the risk of leakage current (e.g., between the source / drain contact and the subsequently formed gate contact in the gate contact opening O22) can be reduced. In some embodiments where the gate spacer 116 is a double-layer structure, the notched gate spacer 116 has a stepped top surface structure, where the lower step of the stepped top surface structure is the top surface of the first spacer layer 118 that is recessed by the LRM etch process ET2, and the upper step of the stepped top surface structure is the top surface of the second spacer layer 120 that is not recessed by the LRM etch process ET2.

[0062] In some embodiments, the contact etch process ET1 and the LRM etch process ET2 discussed above are performed in-situ (e.g., using the same plasma etch tool without vacuum break). In some embodiments, the contact etch process ET1 and the LRM etch process ET2 are combined into an in-situ etch including four stages: 1) etching through the ILD layer 148 (e.g., silicon oxide), 2) etching through the MCESL 146 (e.g., silicon nitride), 3) etching through the doped region 1421 (e.g., oxygen-doped region) of the SAC cap 142, and 4) etching through the non-doped region 1422 (e.g., silicon nitride) of the SAC cap 142. In some embodiments, the contact etch process ET1 and the LRM etch process ET2 discussed above are performed non-in-situ. The contact etch process ET1 includes two stages: 1) etching through the ILD layer 148 (e.g., silicon oxide), and 2) etching through the MCESL 146 (e.g., silicon nitride). The LRM etch process ET2 includes two stages: 1) etching through the doped region 1421 (e.g., oxygen-doped region) of the SAC cap 142, and 2) etching through the non-doped region 1422 (e.g., silicon nitride) of the SAC cap 142. The gas ratios and / or power for these stages can be the same or different according to various embodiments of the present disclosure. In some embodiments, because the thickness of the doped region 1421 of the SAC cap 142 is not greater than about 50 Angstroms, it can be naturally punched through without worrying about etch stop (i.e., without worrying that the etch process can be stopped by the doped region 1421).

[0063] Referring to Figure 20A Gate contacts 151 and 152 are then formed in the gate contact openings O21 and O22 to electrically connect to the HKMG structure 130 through the gate metal cap 138. For example, but not limited to, the gate contacts 151 and 152 are formed using the following manner: depositing one or more metal materials that overfill the gate contact openings O21 and O22, followed by a CMP process to remove the excess metal material(s) that are outside of the gate contact openings O21 and O22. As a result of the CMP process, the gate contacts 151 and 152 have top surfaces that are substantially coplanar with the ILD layer 148. The gate contacts 151 and 152 can include metal materials such as copper, aluminum, tungsten, combinations thereof, etc., and can be formed using PVD, CVD, ALD, etc. In some embodiments, the gate contacts 151 and 152 can further include one or more barrier / adhesion layers (not shown) to protect the ILD layer 148, the MCESL 146, and / or the gate dielectric cap 142 from metal diffusion (e.g., copper diffusion). The one or more barrier / adhesion layers can include titanium, titanium nitride, tantalum, tantalum nitride, etc., and can be formed using PVD, CVD, ALD, etc.

[0064] In some embodiments, the gate contacts 151 and 152 inherit the geometry of the gate contact openings O21 and O22 having vertical sidewall profiles and no tiger tooth profiles, and as a result, the gate contacts 151 and 152 also have vertical sidewall profiles and no tiger tooth profiles. More specifically, the sidewalls of the gate contacts 151 and 152 extend linearly and vertically through the entire thickness of the ILD layer 148, the entire thickness of the MCESL 146, and the entire thickness of the doped region 1421 of the dielectric cap 142 and the entire thickness of the undoped region 1422 of the dielectric cap 142 without a change in slope. In some other embodiments as shown in FIG. 2B, the sidewalls of the gate contacts 151 and 152 can taper gradually at the lower portions of the gate contacts 151 and 152 because the LRM etch process ET2 can etch the undoped region 1422 at a faster vertical etch rate than the doped region 1421 of the gate dielectric cap 142, especially when the gate dielectric cap 142 is formed of the same material as the MCESL 146 (e.g., silicon nitride). In this case, the sidewalls of the gate contacts 151 and 152 can be more vertical (or steeper) within the upper portions of the gate contacts 151 and 152 than within the lower portions of the gate contacts 151 and 152, and the change in slope of the sidewalls of the gate contacts 151 and 152 can be located at the interface between the doped region 1421 and the undoped region 1422. Figure 20B In some other embodiments as shown in FIG. 2B, the sidewalls of the gate contacts 151 and 152 can taper gradually at the lower portions of the gate contacts 151 and 152 because the LRM etch process ET2 can etch the undoped region 1422 at a faster vertical etch rate than the doped region 1421 of the gate dielectric cap 142, especially when the gate dielectric cap 142 is formed of the same material as the MCESL 146 (e.g., silicon nitride). In this case, the sidewalls of the gate contacts 151 and 152 can be more vertical (or steeper) within the upper portions of the gate contacts 151 and 152 than within the lower portions of the gate contacts 151 and 152, and the change in slope of the sidewalls of the gate contacts 151 and 152 can be located at the interface between the doped region 1421 and the undoped region 1422.

[0065] Figures 21-39B Perspective and cross-sectional views showing intermediate stages in the formation of an integrated circuit structure 200 according to some embodiments of the present disclosure are shown. According to some example embodiments, the formed transistors can include p-type transistors (e.g., p-type GAA FETs) and n-type transistors (e.g., n-type FAA FETs). Throughout the various views and illustrative embodiments, like reference numerals are used to represent like elements. It will be understood that additional operations can be provided before, during, and after the procedures illustrated in the figures, and some of the operations described below can be replaced or eliminated, for other embodiments of the methods. The order of the operations / processes can be interchangeable. Figures 21-39B

[0066] Figure 21 Figure 22 Figure 23 Figure 24A Figure 25A Figure 26A Figure 27A Perspective views of some embodiments of the integrated circuit structure 200 at intermediate stages during fabrication. Figure 24B Figure 25B Figure 26B Figure 27B Figures 28-30 ,​​​​​​​​​​​Figure 31A and Figures 32-39B is a cross-sectional view of some embodiments of integrated circuit structure 200 at an intermediate stage during fabrication along a first cut (e.g., cut X-X in Figure 24A along a length direction of the channel and perpendicular to a top surface of the substrate. Figure 31B is a cross-sectional view of some embodiments of integrated circuit structure 200 at an intermediate stage during fabrication along a second cut (e.g., cut Y-Y in Figure 24A in the gate region and perpendicular to a length direction of the channel.

[0067] Referring to Figure 21 , an epitaxial stack 220 is formed over a substrate 210. In some embodiments, substrate 210 can comprise silicon (Si). Alternatively, substrate 210 can comprise germanium (Ge), silicon germanium (SiGe), a III-V material (e.g., GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb, and / or GaInAsP; or combinations thereof), or other suitable semiconductor material. In some embodiments, substrate 210 can comprise a semiconductor-on-insulator (SOI) structure, such as a buried dielectric layer. Further alternatively, substrate 210 can comprise a buried oxide (BOX) layer, such as formed by a method known as separation by implanted oxygen (SIMOX) technique, wafer bonding, SEG, or other suitable method.

[0068] Epitaxial stack 220 comprises an epitaxial layer 222 of a first composition, which is interposed with an epitaxial layer 224 of a second composition. The first and second compositions can be different. In some embodiments, epitaxial layer 222 is SiGe, and epitaxial layer 224 is silicon (Si). However, other embodiments are possible, including those that provide a first and second composition that have different oxidation rates and / or etch selectivity. In some embodiments, epitaxial layer 222 comprises SiGe, and the Si oxidation rate of epitaxial layer 224 is less than the SiGe oxidation rate of epitaxial layer 222, where epitaxial layer 224 comprises Si.

[0069] Epitaxial layer 224, or portions thereof, can form nanosheet channel(s) of a multi-gate transistor. The term nanosheet is used herein to refer to any material portion having a nanoscale or even micrometer scale dimension and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term refers to both circular and substantially circular cross-sectional elongated material portions, as well as to beam-shaped or strip-shaped material portions that include, for example, a cylindrical or substantially rectangular cross-section. The use of epitaxial layer 224 to define one or more channels of a device is discussed further below.

[0070] Note that the three layers of epitaxial layers 222 and three layers of epitaxial layers 224 are arranged in an alternating fashion, which is for purposes of illustration only and is not intended to limit what is specifically recited in the claims. It can be appreciated that any number of epitaxial layers can be formed in the epitaxial stack 220; the number of layers depends on the number of channel regions required for the transistor. In some embodiments, the number of epitaxial layers 224 is between 2 and 10. Figure 21 As described in greater detail below, the epitaxial layers 224 can serve as the channel region(s) for a subsequently formed multi-gate device, and the thickness is selected based on device performance considerations. The epitaxial layers 222 can ultimately be removed, and serve to define the vertical distance between adjacent channel region(s) for a subsequently formed multi-gate device, and the thickness is selected based on device performance considerations. Thus, the epitaxial layers 222 can also be referred to as sacrificial layers, and the epitaxial layers 224 can also be referred to as channel layers.

[0071] The epitaxial growth of the layers of the stack 220 can be performed, for example, by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layers (e.g., epitaxial layers 224) comprise the same material as the substrate 210. In some embodiments, the epitaxially grown layers 222 and 224 comprise a different material than the substrate 210. As noted above, in at least some examples, the epitaxial layers 222 comprise an epitaxially grown silicon germanium (SiGe) layer, and the epitaxial layers 224 comprise an epitaxially grown silicon (Si) layer. Alternatively, in some embodiments, either of the epitaxial layers 222 and 224 can comprise other materials, such as germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof. As discussed, the materials of the epitaxial layers 222 and 224 can be selected based on providing different oxidation and / or etching selectivity characteristics. In some embodiments, the epitaxial layers 222 and 224 are substantially free of dopants (i.e., have an external dopant concentration of between about 0 cm -3 18 cm -3 between about 1 x 1018cm-3and about 1 x 1020cm-3), where no intentional doping is performed, for example, during the epitaxial growth process.

[0072] Referring to

[0073] Figure 22 ​​A plurality of semiconductor fins 230 extending from substrate 210 are formed. In various embodiments, each fin 230 includes a substrate portion 212 formed from substrate 210 and portions of each epitaxial layer of the epitaxial stack (including epitaxial layers 222 and 224). The fins 230 can be fabricated using suitable processes including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, spacing smaller than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on the substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the fins 230 can then be patterned using the remaining spacers or mandrels by etching the initial epitaxial stack 220. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes.

[0074] In such Figure 21 and Figure 22 In the illustrated embodiment, a hard mask (HM) layer 910 is formed on the epitaxial stack 220 prior to patterning the fin 230. In some embodiments, the HM layer includes an oxide layer 912 (e.g., a pad oxide layer that may include SiO2) and a nitride layer 914 (e.g., a pad nitride layer that may include Si3N4) formed on the oxide layer. The oxide layer 912 may act as an adhesion layer between the epitaxial stack 220 and the nitride layer 914, and may also act as an etch stop layer for etching the nitride layer 914. In some examples, the HM oxide layer 912 includes thermally grown oxides, chemical vapor deposition (CVD) deposited oxides, and / or atomic layer deposition (ALD) deposited oxides. In some embodiments, the HM nitride layer 914 is deposited on the HM oxide layer 912 by CVD and / or other suitable techniques.

[0075] The fins 230 can then be fabricated using suitable processes including photolithography and etching processes. The photolithography process can include forming a photoresist layer (not shown) over the HM layer 910, exposing the photoresist to a pattern, performing a post-exposure bake process, and developing the resist to form a patterned mask including resist. In some embodiments, the patterning of the resist to form the patterned mask elements can be performed using an e-beam lithography process or an extreme ultraviolet (EUV) lithography process (which uses light having a wavelength of, for example, about 1-200 nm) in the EUV region. The patterned mask can then be used to protect regions of the substrate 210 and layers formed thereon while an etching process forms the trenches 202 through the HM layer 910, through the epitaxial stack 220, and into the substrate 210 in the unprotected regions, leaving a plurality of extended fins 230. The trenches 202 can be etched using dry etching (e.g., reactive ion etching), wet etching, and / or combinations thereof. Many other embodiments of the process of forming fins on a substrate can also be used, including, for example, defining fin regions (e.g., by a mask or isolation regions) and epitaxially growing the epitaxial stack 220 in the form of the fins 230.

[0076] Next, as shown in Figure 23 the STI regions 240 are formed interposed between the fins 230. Details of the material and processes for the STI regions 240 are similar to those previously discussed for the STI regions 14, and thus are not repeated for the sake of brevity.

[0077] Referring to Figure 24A and Figure 24B The dummy gate structure 250 is formed over the substrate 210 and disposed at least partially over the fins 230. Portions of the fins 230 that are located under the dummy gate structure 250 can be referred to as channel regions. The dummy gate structure 250 can also define source / drain (S / D) regions of the fins 230, such as regions of the fins 230 that are adjacent to and on opposite sides of the channel regions.

[0078] The dummy gate formation step first forms a dummy gate dielectric layer 252 over the fin 230. Subsequently, a dummy gate electrode layer 254 and a hard mask that can include multiple layers 256 and 258 (e.g., an oxide layer 256 and a nitride layer 258) are formed over the dummy gate dielectric layer 252. The hard mask is then patterned, and then the dummy gate electrode layer 252 is patterned by using the patterned hard mask as an etch mask. In some embodiments, after patterning the dummy gate electrode layer 254, the dummy gate dielectric layer 252 is removed from the S / D regions of the fin 230. The etching process can include wet etching, dry etching, and / or a combination thereof. The etching process is selected to selectively etch the dummy gate dielectric layer 252 without substantially etching the fin 230, the dummy gate electrode layer 254, the oxide mask layer 256, and the nitride mask layer 258. The materials of the dummy gate dielectric layer and the dummy gate electrode layer are similar to those of the dummy gate dielectric layer 108 and the dummy gate electrode layer 110 discussed previously, and thus are not repeated for the sake of brevity.

[0079] After the formation of the dummy gate structure 250 is completed, a gate spacer 260 is formed on the sidewalls of the dummy gate structure 250. For example, a spacer material layer is deposited on the substrate 210. The spacer material layer can be a conformal layer that is subsequently etched back to form gate sidewall spacers. In the illustrated embodiment, the spacer material layer 260 is conformally disposed on the top and sidewalls of the dummy gate structure 250. The spacer material layer 260 can include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, a SiCN film, silicon oxycarbide, a SiOCN film, and / or a combination thereof. In some embodiments, the spacer material layer 260 includes multiple layers, such as a first spacer layer 262 and a second spacer layer 264 formed on the first spacer layer 262 (as shown). For example, the spacer material layer 260 can be formed by depositing a dielectric material over the gate structure 250 using an appropriate deposition process. An anisotropic etching process is then performed on the deposited spacer material layer 260 to expose portions of the fin 230 that are not covered by the dummy gate structure 250 (e.g., in the source / drain regions of the fin 230). Portions of the spacer material layer that are directly above the dummy gate structure 250 can be completely removed by this anisotropic etching process. Portions of the spacer material layer that are on the sidewalls of the dummy gate structure 250 can remain, forming gate sidewall spacers, which are denoted as gate spacers 260 for the sake of simplicity. It should be noted that although the gate spacers 260 are multi-layer structures in the cross-sectional view of Figure 24B the spacer material layer 260 can be formed by depositing a dielectric material over the gate structure 250 using an appropriate deposition process. An anisotropic etching process is then performed on the deposited spacer material layer 260 to expose portions of the fin 230 that are not covered by the dummy gate structure 250 (e.g., in the source / drain regions of the fin 230). Portions of the spacer material layer that are directly above the dummy gate structure 250 can be completely removed by this anisotropic etching process. Portions of the spacer material layer that are on the sidewalls of the dummy gate structure 250 can remain, forming gate sidewall spacers, which are denoted as gate spacers 260 for the sake of simplicity. It should be noted that although the gate spacers 260 are multi-layer structures in the cross-sectional view of Figure 24B , they are shown as single-layer structures in the perspective view of Figure 24A for the sake of simplicity.

[0080] Next, as Figure 25Aand Figure 25B As shown, a recess R6 is formed in the semiconductor fin 230 and between the corresponding dummy gate structures 250 by etching the lateral extension of the semiconductor fin 230 beyond the exposed portion of the gate spacer 260 (e.g., in the source / drain regions of the fin 230) using, for example, an anisotropic etching process (which uses the dummy gate structure 250 and the gate spacer 260 as an etching mask). After the anisotropic etching, the end surfaces of the sacrificial layer 222 and the channel layer 224 are aligned with the corresponding outermost walls of the gate spacer 260 due to the anisotropic etching. In some embodiments, the anisotropic etching can be performed by dry chemical etching using a plasma source and reactive gases. The plasma source can be an inductively coupled plasma (ICR) source, a transformer coupled plasma (TCP) source, an electron cyclotron resonance (ECR) source, etc., and the reactant gas can be, for example, a fluorine-based gas (e.g., SF6, CH2F2, CH3F, CHF3, etc.), a chlorine-based gas (e.g., Cl2), hydrogen bromide gas (HBr), oxygen (O2), etc., or a combination thereof.

[0081] Next, in Figure 26A and Figure 26B In this process, sacrificial layer 222 is recessed laterally or horizontally using a suitable etching technique, thereby vertically forming lateral recesses R7 between respective channel layers 224. This step can be performed using a selective etching process. For example, but not limited to, sacrificial layer 222 is SiGe, and channel layer 224 is silicon, to allow selective etching of sacrificial layer 222. In some embodiments, selective wet etching includes APM etching (e.g., a mixture of ammonium hydroxide-hydrogen peroxide-water) of SiGe at an etch rate faster than that used to etch Si. In some embodiments, selective etching includes SiGe oxidation followed by removal of SiGeO. x For example, oxidation can be provided by O3 cleaning, and then SiGeO can be removed by an etchant such as NH4OH. x This etchant selectively etches SiGeO at a faster etch rate than it etches Si. x Furthermore, because the oxidation rate of Si is much lower than that of SiGe (sometimes 30 times lower), the channel layer 224 is not significantly etched through the process of laterally recessing the sacrificial layer 222. As a result, the channel layer 224 extends laterally beyond the opposite end face of the sacrificial layer 222.

[0082] exist Figure 27A and Figure 27B In the middle, an internal spacer material layer 270 is formed to fill the spacer material layer 270 formed by the reference above. Figure 26A and Figure 26BA recess R7 left by the lateral etching of the sacrificial layer 222. The inner spacer material layer 270 can be a low-k dielectric material, such as Si02, SiN, SiCN, or SiOCN, and can be formed by an appropriate deposition method such as ALD. After the deposition of the inner spacer material layer 270, an anisotropic etch process can be performed to trim the deposited inner spacer material 270 so that only the portion of the deposited inner spacer material 270 that fills the recess R7 left by the lateral etching of the sacrificial layer 222 is retained. After the trimming process, for simplicity, the remaining portion of the deposited inner spacer material is denoted as inner spacer 270. The inner spacer 270 serves to isolate the metal gate from the source / drain epitaxial structure formed in subsequent processing. In Figure 27A and Figure 27B In examples,

[0083] In Figure 28 a source / drain epitaxial structure 280 is formed over the source / drain regions S / D of the semiconductor fin 230. The source / drain epitaxial structure 280 can be formed by performing an epitaxial growth process that provides epitaxial material on the fin 230. During the epitaxial growth process, the gate sidewall spacer 260 and the inner spacer 270 confine the source / drain epitaxial structure 280 to the source / drain regions S / D. The material and process details for the source / drain epitaxial structure 280 for the GAA FET are similar to those previously discussed for the source / drain epitaxial structure 122 for the FinFET, and thus, for brevity, are not repeated.

[0084] In Figure 29 an interlayer dielectric (ILD) layer 310 is formed on the substrate 210. In some embodiments, a CESL is optionally formed prior to forming the ILD layer 310. In some examples, after the ILD layer 310 is deposited, a planarization process can be performed to remove excess material of the ILD layer 310. For example, the planarization process includes a chemical mechanical planarization (CMP) process that removes portions of the ILD layer 310 (and the CESL layer, if present) that cover the dummy gate structure 250 and planarizes a top surface of the integrated circuit structure 200. In some embodiments, the CMP process also removes the hard mask layers 256, 258 (as shown in Figure 28 and exposes the dummy gate electrode layer 254.

[0085] After that, the dummy gate structure 250 is first removed, and then the sacrificial layer 222 is removed. In Figure 30The resulting structure is illustrated. In some embodiments, the dummy gate structure 250 is removed using a selective etching process (e.g., selective dry etching, selective wet etching, or a combination thereof) that etches the material in the dummy gate structure 250 at a faster etch rate than it etches other materials (e.g., gate sidewall spacers 260 and / or ILD layer 310), thereby forming a gate trench GT2 between the respective gate sidewall spacers 260, with the sacrificial layer 222 exposed in the gate trench GT2. Subsequently, the sacrificial layer 222 in the gate trench GT2 is removed using another selective etching process that etches the sacrificial layer 222 at a faster etch rate than it etches the channel layer 224, thereby forming an opening O6 between adjacent channel layers 224. In this way, the channel layer 224 becomes a nanosheet suspended above the substrate 210 and between the source / drain epitaxial structures 280. This step is also referred to as a channel release process. At this intermediate processing step, the openings O6 between the nanosheets 224 can be filled with ambient conditions (e.g., air, nitrogen, etc.). In some embodiments, depending on the geometry of the nanosheets 224, the nanosheets 224 can be interchangeably referred to as nanowires, nanoplatelets, and nanorings. For example, in some other embodiments, the channel layer 224 can be shaped into a substantially circular shape (i.e., cylindrical) due to a selective etching process used to completely remove the sacrificial layer 222. In that case, the resulting channel layer 224 can be referred to as a nanowire.

[0086] In some embodiments, the sacrificial layer 222 is removed using a selective wet etching process. In some embodiments, the sacrificial layer 222 is SiGe, and the channel layer 224 is silicon, to allow for selective removal of the sacrificial layer 222. In some embodiments, the selective wet etching includes APM etching (e.g., a mixture of ammonium hydroxide-hydrogen peroxide-water). In some embodiments, selective removal includes SiGe oxidation followed by removal of SiGeO. x For example, oxidation can be provided by O3 cleaning, and then SiGeO can be removed by an etchant such as NH4OH. x This etchant selectively etches SiGeO at a faster etch rate than it etches Si. x Furthermore, because the oxidation rate of Si is much lower than that of SiGe (sometimes 30 times lower), the channel layer 224 is not significantly etched through the channel release process. It can be noted that the channel release step and the preceding steps of the lateral recess sacrificial layer (such as...) Figure 26A and Figure 26BBoth steps (shown) use a selective etching process (etching SiGe at a faster etch rate than etching Si), and therefore in some embodiments, the two steps can use the same etchant chemicals. In this case, the etching time / duration of the channel release step is longer than the etching time / duration of the previous step of the lateral recess sacrificial layer in order to completely remove the sacrificial SiGe layer.

[0087] exist Figure 31A and Figure 31B In this configuration, replacement gate structures 320 are formed in gate trenches GT2 to surround each nanosheet 224 suspended within the gate trenches GT2. The gate structure 320 can be the final gate of a GAA FET. The final gate structure can be a high-k / metal gate stack, but other compositions are also possible. In some embodiments, each gate structure 320 forms a gate associated with a multi-channel provided by multiple nanosheets 224. For example, the high-k / metal gate structure 320 is formed in an opening O6 provided by the release of the nanosheets 224 (e.g., ...). Figure 30 (As shown). In various embodiments, the high-k / metal gate structure 320 includes a gate dielectric layer 322 formed around a nanosheet 224, a work function metal layer 324 formed around the gate dielectric layer 322, and a fill metal 326 formed around the work function metal layer 324 and filling the remaining gate trench GT2. The gate dielectric layer 332 includes an interface layer (e.g., a silicon oxide layer) and a high-k gate dielectric layer above the interface layer. As used and described herein, the high-k gate dielectric includes a dielectric material having a high dielectric constant (e.g., greater than the dielectric constant of thermally heated silicon oxide (about 3.9)). The work function metal layer 324 and / or fill metal 326 used in the high-k / metal gate structure 320 may include metals, metal alloys, or metal silicides. The formation of the high-k / metal gate structure 320 may include deposition processes for forming various gate materials, one or more liner layers, and one or more CMP processes for removing excess gate material. As shown in the figure taken along the longitudinal axis of the high-k / metal gate structure 320 Figure 31B As shown in the cross-sectional view, a high-k / metal gate structure 320 surrounds each nanosheet 224, and is therefore referred to as the gate of a GAA FET. The material and process details of the GAA FET gate structure 320 are similar to those of the FinFET gate structure 130, and therefore, for the sake of brevity, will not be repeated.

[0088] exist Figure 32In this process, an etch-back process is performed to replace the gate structure 320 and the gate spacer 260, thereby forming a recess on the etched gate structure 320 and the etched gate spacer 260. In some embodiments, because the material replacing the gate structure 320 has a different etch selectivity than the gate spacer 260, the top surface of the replacing gate structure 320 can be at a different level from the top surface of the gate spacer 260. For example, in... Figure 32 In the illustrated embodiment, the top surface of the replacement gate structure 320 is lower than the top surface of the gate spacer 260. However, in some other embodiments, the top surface of the replacement gate structure 320 may be flush with or higher than the top surface of the gate spacer 260.

[0089] Then, a gate metal cap 330 is optionally formed on top of the etched-back replacement gate structure 320 using a suitable process such as CVD or ALD. For example, but not limited to, the metal cap 330 may be a substantially fluorine-free tungsten (FFW) film with less than 5 atomic% fluorine contamination and more than 3 atomic% chlorine contamination. Process details regarding the formation of the FFW have been discussed previously with respect to the gate metal cap 138, and therefore will not be repeated for the sake of brevity.

[0090] exist Figure 33 In this configuration, a gate dielectric cap 340 is formed on top of the gate metal cap 330 and the gate spacer 260. Because the top surface of the gate metal cap 330 is lower than the top surface of the gate spacer 260, each gate dielectric cap 340 has a stepped bottom surface, with the lower step contacting the top surface of the gate metal cap 330 and the upper step contacting the top surface of the gate spacer 260. The material and process details of the dielectric caps are similar to those of the previously discussed gate dielectric cap 142, and therefore will not be repeated for the sake of brevity.

[0091] exist Figure 34In this process, source / drain contacts 350 extending through the ILD layer 310 are formed. The formation of the source / drain contacts 350 includes, for example, but not limited to: performing one or more etching processes to form contact openings extending through the ILD layer 310 to expose the source / drain epitaxial structure 280; depositing one or more metal materials to overfill the contact openings; and then performing a CMP process to remove excess metal material located outside the contact openings. In some embodiments, one or more etching processes are selective etching, which etches the ILD layer 310 at a faster etch rate than etching the gate dielectric cap 340 and the gate spacer 260. As a result, selective etching is performed using the gate dielectric cap 340 and the gate spacer 260 as etch masks, such that the contact openings, and therefore the source / drain contacts 350, are formed to be self-aligned with the source / drain epitaxial structure 280 without the need for additional photolithography processes. In that case, the source / drain contact 350 can be referred to as a self-aligned contact (SAC), and the gate dielectric cap 340 that allows the self-aligned contact 350 to be formed can be referred to as an SAC cap 340.

[0092] exist Figure 35 In this process, an ion implantation process IMP2 is performed to dope one or more impurities (e.g., dopant ions) into the gate dielectric cap 340. For example, an ionized dopant DP (e.g., oxygen, germanium, argon, xenon, boron, and / or other suitable substances capable of producing etch selectivity different from that of the material of the gate dielectric cap 340) can be implanted into the gate dielectric cap 340 to form a doped region 3401 in the gate dielectric cap 340. In some embodiments, prior to performing the ion implantation process IMP2, a patterned mask (e.g., a patterned photoresist) can be formed using a suitable photolithography process to cover the exposed surfaces of the source / drain contacts 350. The ion implantation process IMP2 is performed with the patterned mask in place, and then the patterned mask is removed after the ion implantation process IMP2 is completed (e.g., by ashing). In this case, the source / drain contacts 350 are substantially free of dopant DP. Alternatively, ion implantation process IMP2 can also implant some ionized dopant DP into the source / drain contact 350, thus forming a doped region in the source / drain contact 350. In this case, the doped region in the source / drain contact 350 can then be penetrated in a subsequent etching process to form a source / drain via on the source / drain contact 350. The process details of ion implantation process IMP2 are similar to those of ion implantation process IMP1 discussed earlier, and therefore will not be repeated for the sake of brevity.

[0093] In some embodiments, the ion implantation process will implant molecular oxygen ions (O2)+ ) or atomic oxygen ions (O + ) are implanted into the gate dielectric cap 340, and thus the oxygen-doped region 3401 of the gate dielectric cap 340 has a higher oxygen concentration than the undoped region 3402. For example, but not limited to, the oxygen concentration of the oxygen-doped region 3401 ranges from about 1E18 atoms / cm 3 to about 5E23 atoms / cm 3 , and the oxygen concentration of the undoped region 3402 is substantially zero. If the oxygen-doped region 3401 has too high of an oxygen concentration, the etch rate of the oxygen-doped region 3401 can be too slow to be punched through in the expected duration of the subsequent LRM etch process. If the oxygen-doped region 3401 has too low of an oxygen concentration, the etch rate of the oxygen-doped region 3401 can be too fast to slow down the subsequent LRM etch process.

[0094] In some embodiments, the oxygen-doped region 3401 has an oxygen concentration gradient due to the ion implantation process IMP2. In more detail, the oxygen concentration of the oxygen-doped region 3401 varies according to the depth inside the oxygen-doped region 3401. For example, the oxygen concentration can decrease as the distance from the top surface of the oxygen-doped region 3401 increases. In some embodiments where the gate dielectric cap 340 is silicon nitride, the oxygen-to-nitrogen atomic ratio in the oxygen-doped region 3401 is also a gradient. For example, the oxygen-to-nitrogen atomic ratio in the oxygen-doped region 3401 can decrease as the distance from the top surface of the oxygen-doped region 3401 increases.

[0095] In some embodiments, the doped region 3401 has a dopant depth D3 that extends from the top surface of the gate dielectric cap 340 into the gate dielectric cap 340. In some embodiments, for a 3 nm technology node, the dopant depth D3 ranges from about 1 angstrom to about 50 angstroms. In some other embodiments, the ratio of the dopant depth D3 to the maximum thickness T3 of the gate dielectric cap 340 ranges from about 3% to about 60%. If the dopant depth D3 and / or the D3 / T3 ratio is too small, the doped region 3401 can be too thin to slow down the subsequent LRM etch process. If the dopant depth D3 and / or the D3 / T3 ratio is too large, the doped region 3401 can be too thick to be punched through in the expected duration. For other technology nodes, such as 20 nm node, 16 nm node, 10 nm node, 7 nm node, and / or 5 nm node, the dopant depth D3 can range from about 1 nm to about 20 nm.

[0096] In some embodiments, after the ion implantation process IMP2 is completed, an anneal process can be performed to repair implantation damage in the gate dielectric cap 340 and / or the source / drain contacts 350. In some other embodiments, the anneal process can be skipped, such that the doped region 3401 can not undergo annealing.

[0097] In Figure 36 which the doped region 3401 has been formed in the gate dielectric cap 340, then the MCESL 360 is deposited over the source / drain contacts 350 and the doped region 3401. Subsequently, another ILD layer 370 is deposited over the MCESL 360. In some embodiments, both the undoped region 3402 of the gate dielectric cap 340 and the MCESL 360 are silicon nitride, and the ILD layer 370 is silicon oxide (SiO X ), and thus the ILD layer 370 and the doped region 3401 (e.g., oxygen-doped region) in the gate dielectric cap 340 have different etch selectivity than the undoped region 3402 and the MCESL 360.

[0098] In Figure 37 which the doped region 3401 has been formed in the gate dielectric cap 340, then the MCESL 360 is deposited over the source / drain contacts 350 and the doped region 3401. Subsequently, another ILD layer 370 is deposited over the MCESL 360. In some embodiments, both the undoped region 3402 of the gate dielectric cap 340 and the MCESL 360 are silicon nitride, and the ILD layer 370 is silicon oxide (SiO X ), and thus the ILD layer 370 and the doped region 3401 (e.g., oxygen-doped region) in the gate dielectric cap 340 have different etch selectivity than the undoped region 3402 and the MCESL 360.

[0099] In some embodiments, as Figure 37 illustrated, the first lateral dimension (e.g., first maximum width W41) of the gate contact opening O41 and the second lateral dimension (e.g., second maximum width W42) of the gate contact opening O42 are formed simultaneously in the contact etch process ET3. The second maximum width W42 can be greater than the first maximum width W41. The width difference between the gate contact openings O41 and O42 can be intentionally formed according to circuit functionality and / or design rules. Alternatively, as previously discussed with respect to the gate contact openings O21 and O22, the width difference between the gate contact openings O41 and O42 can be unintentionally formed due to inaccuracy of the contact etch process ET3. The width difference of the gate contact openings O41 and O42 makes the wider gate contact opening O42 deeper than the narrower gate contact opening O41.

[0100] In Figure 38AIn some embodiments, the LRM etch process ET4 is performed to penetrate the MCESL 360 and the gate dielectric cap 340, thus deepening the gate contact openings O41 and O42 to extend downward to the gate metal cap 330 above the gate structure 320. As a result of the LRM etch process ET4, the gate metal cap 340 is exposed at the bottom of the deepened gate contact openings O41 and O42. The etchant and / or etch conditions of the LRM etch process ET4 are selected in such a way that the doped region 3401 exhibits a slower etch rate than the MCESL 360 and the undoped region 3402. Process details regarding the LRM etch process ET4 have been previously discussed with respect to the LRM etch process ET2, and thus are not repeated here for the sake of brevity.

[0101] Because of the etch selectivity between the doped region 3401 and the MCESL 360, the doped region 3401 can slow down the LRM etch process ET4 as it punches through the MCESL 360, which in turn will slow down the vertical etch rate and the depth increase in the gate contact openings O41 and O42 as they reach the doped region 3401. Thus, the depth difference between the narrower gate contact opening O41 and the wider gate contact opening O42 can be reduced by the doped region 3401. The reduced depth loading can thus prevent the formation of a tiger tooth pattern in the wider gate contact opening O42, which in turn reduces the risk of leakage current (e.g., from the gate contact to the source / drain contact). Moreover, because the doped region 3401 slows down the vertical etch rate without slowing down the lateral etch rate as the gate contact openings O41 and O42 reach the doped region 3401, the LRM etch process ET4 can laterally expand the lower portions of the gate contact openings O41 and O42 during the etching of the doped region 3401, which can increase the bottom width of the gate contact openings O41 and O42, and the gate contact openings O41 and O42 can become more vertical than before the doped region 3401 is punched through.

[0102] In some embodiments, the sidewalls of the gate contact openings O41 and O42 extend linearly and vertically through the entire thickness of the ILD layer 370, the entire thickness of the MCESL 360, the entire thickness of the doped region 3401 of the gate dielectric cap 340, and the entire thickness of the undoped region 3402 of the dielectric cap 340 without a change in slope. As such, the sidewalls of the gate contact openings O41 and O42 can be substantially vertical and linear in shape. Figure 38BIn some other embodiments shown, because the LRM etching process ET4 can etch the undoped region 3402 at a faster vertical etch rate than etching the doped region 3401 of the gate dielectric cap 340, especially when the gate dielectric cap 340 is formed of the same material as MCESL 360 (e.g., silicon nitride), the lower sidewalls of the gate contact openings O41 and O42 can taper gradually. In this case, the sidewalls of the gate contact openings O41 and O42 can be more vertical (or steeper) in the upper part of the gate contact openings O41 and O42 than in the lower part, and the slope change of the sidewalls of the gate contact openings O41 and O42 can be located at the interface between the doped region 3401 and the undoped region 3402.

[0103] In such Figure 38A In some embodiments shown, the wider gate contact opening O42 may extend into the adjacent gate spacer 260, thereby creating a notched corner C42 in the gate spacer 260. This notched corner C42 may be unintentionally formed due to the inaccuracies of the contact etching process ET3 and / or the LRM etching process ET4. However, even in this case, the gate spacer 260 is not over-etched to form a serrated recess because, as previously discussed, the increase in depth in the wider gate contact opening O42 slows down during the punch-through doped region 3401. Because the wider gate contact opening O42 has no or negligible serrated recess, the risk of leakage current (e.g., leakage current between the source / drain contacts and the gate contacts subsequently formed in the gate contact opening O42) can be reduced. In some embodiments where the gate spacer 260 is a double-layer structure, the notched gate spacer 260 has a stepped top surface structure, wherein the lower step of the stepped top surface structure is the top surface of the first spacer layer 262 recessed by the LRM etching process ET4, and the upper step of the stepped top surface structure is the top surface of the second spacer layer 264 not recessed by the LRM etching process ET4.

[0104] exist Figure 39A In the process, a narrower gate contact 381 and a wider gate contact 382 are formed in the narrower gate contact opening O41 and the wider gate contact opening O42, respectively, to be electrically connected to the HKMG structure 320 via the gate metal cap 330. The material and process details of the gate contacts 381 and 382 are similar to those of the previously discussed gate contacts 151 and 152, and therefore will not be repeated for the sake of brevity.

[0105] In some embodiments, the gate contacts 381 and 382 inherit the geometry of the gate contact openings O41 and O42 that have vertical sidewall profiles and no tiger tooth profiles, and as a result, the gate contacts 381 and 382 also have vertical sidewall profiles and no tiger tooth profiles. More specifically, the sidewalls of the gate contacts 381 and 382 extend linearly and perpendicularly through the entire thickness of the ILD layer 370, the entire thickness of the MCESL 360, and the entire thickness of the doped region 3401 of the dielectric cap 340 and the entire thickness of the undoped region 3402 of the dielectric cap 340 without a change in slope. In some other embodiments as shown in FIG. 3B, the sidewalls of the gate contacts 381 and 382 can taper gradually at the lower portions of the gate contacts 381 and 382 because the LRM etch process ET4 can etch the undoped region 3402 at a faster vertical etch rate than the doped region 3401 of the gate dielectric cap 340, especially when the gate dielectric cap 340 is formed of the same material as the MCESL 360 (e.g., silicon nitride). In this case, the sidewalls of the gate contacts 381 and 382 can be more vertical (or steeper) within the upper portions of the gate contacts 381 and 382 than within the lower portions of the gate contacts 381 and 382, and the change in slope of the sidewalls of the gate contacts 381 and 382 can be located at the interface between the doped region 3401 and the undoped region 3402. Figure 39B

[0106] Based on the above discussion, it can be seen that the present disclosure provides advantages in various embodiments. However, it should be understood that other embodiments can provide additional advantages, and not all advantages are necessarily disclosed herein, and particular advantages are not required for all embodiments. One advantage is that the depth loading problem of the gate contact openings can be mitigated. Another advantage is that the gate contact openings can have more vertical sidewall profiles. Another advantage is that the gate contact resistance can be reduced as compared to tapered gate contacts due to the increased bottom surface area of the gate contacts with vertical sidewall profiles. Another advantage is that the risk of leakage current (e.g., from the gate contact to the source / drain contact) can be reduced.

[0107] ​In some embodiments, a method includes: forming gate structures between gate spacers and over a semiconductor substrate; etching back the gate structures to be lower than top ends of the gate spacers; forming a gate dielectric cap over the etched back gate structures; performing an ion implantation process to form a doped region in the gate dielectric cap; depositing a contact etch stop layer over the gate dielectric cap, and depositing an ILD layer over the contact etch stop layer; performing a first etching process to form gate contact openings extending through the ILD layer and terminating before reaching the doped region of the gate dielectric cap; performing a second etching process to deepen the gate contact openings, wherein the second etching process etches the doped region of the gate dielectric cap at a slower etching rate than etching the contact etch stop layer; and forming gate contacts in the deepened gate contact openings. In some embodiments, the second etching process etches an undoped region of the gate dielectric cap at a faster etching rate than etching the doped region of the gate dielectric cap. In some embodiments, the gate dielectric cap is formed of a same material as the contact etch stop layer. In some embodiments, the gate dielectric cap and the contact etch stop layer are nitride-based. In some embodiments, the ion implantation process implants oxygen, germanium, argon, xenon, or boron into the gate dielectric cap. In some embodiments, the doped region in the gate dielectric cap has a higher oxygen concentration than the contact etch stop layer. In some embodiments, the doped region in the gate dielectric cap has a higher oxygen concentration than an undoped region in the gate dielectric cap.

[0108] In some embodiments, the method further includes: after performing the ion implantation process, performing an annealing process on the gate dielectric cap. In some embodiments, the first etching process is a plasma etching process using a plasma generated from a gas mixture free of hydrogen. In some embodiments, the second etching process is a plasma etching process using a plasma generated from a gas mixture containing hydrogen.

[0109] In some embodiments, the gas mixture containing hydrogen is a mixture of a fluorine-containing gas and hydrogen gas. In some embodiments, the fluorine-containing gas is a CHF3 gas, a CF4 gas, or a combination thereof.

[0110] In some embodiments, a method includes: forming a first gate dielectric cap over a first gate structure and a second gate dielectric cap over a second gate structure; forming a first doped region in the first gate dielectric cap and a second doped region in the second gate dielectric cap; depositing a contact etch stop layer over the first gate dielectric cap and the second gate dielectric cap and depositing an interlayer dielectric (ILD) layer over the contact etch stop layer; performing a first etch process to form a first gate contact opening and a second gate contact opening extending through the ILD layer such that the contact etch stop layer is exposed, wherein a width of the first gate contact opening is less than a width of the second gate contact opening; performing a second etch process on the contact etch stop layer to extend the first gate contact opening and the second gate contact opening toward the first gate structure and the second gate structure, wherein after the second etch process etches through the first doped region in the first gate dielectric cap, a sidewall profile of the first gate contact opening becomes more vertical than before the first doped region is etched; and after performing the second etch process, forming a first gate contact in the first gate contact opening and a second gate contact in the second gate contact opening. In some embodiments, the first etch process is such that a depth of the first gate contact opening is less than a depth of the second gate contact opening. In some embodiments, after the second etch process etches through the first doped region and the second doped region, a depth difference between the first gate contact opening and the second gate contact opening becomes less than a depth difference before the first doped region and the second doped region are etched. In some embodiments, the second etch process uses a gas mixture having hydrogen gas and the first etch process does not use hydrogen gas.

[0111] In some embodiments, a device includes: a source / drain epitaxial structure over a substrate; a source / drain contact over the source / drain epitaxial structure, respectively; a gate structure laterally between the source / drain contacts; a gate dielectric cap over the gate structure and having opposing sidewalls that contact the source / drain contacts, respectively, the gate dielectric cap having a doped region extending from a top surface of the gate dielectric cap into the gate dielectric cap; a contact etch stop layer extending over the source / drain contacts and the gate dielectric cap; an ILD layer over the contact etch stop layer; and a gate contact extending through the ILD layer, the contact etch stop layer, and the doped region of the gate dielectric cap to electrically connect with the gate structure. In some embodiments, the doped region of the gate dielectric cap has a higher oxygen-to-nitrogen atomic ratio than an undoped region of the gate dielectric cap. In some embodiments, the doped region of the gate dielectric cap has an oxygen concentration gradient. In some embodiments, the doped region of the gate dielectric cap is thinner than the contact etch stop layer.

[0112] The foregoing has outlined rather generally the features of several embodiments in order that the detailed description that follows can be better understood. Additional aspects and advantages will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example various embodiments of the disclosure.

[0113] Example 1 is a method of forming an integrated circuit device, comprising: forming gate structures between gate spacers and over a semiconductor substrate; etching back the gate structures to below a top end of the gate spacers; forming a gate dielectric cap over the etched back gate structures; performing an ion implantation process to form a doped region in the gate dielectric cap; depositing a contact etch stop layer over the gate dielectric cap and depositing an interlayer dielectric (ILD) layer over the contact etch stop layer; performing a first etch process to form gate contact openings extending through the ILD layer and terminating before reaching the doped region of the gate dielectric cap; performing a second etch process to deepen the gate contact openings, wherein the second etch process etches the doped region of the gate dielectric cap at a slower etch rate than the contact etch stop layer; and forming gate contacts in the deepened gate contact openings.

[0114] Example 2 is the method of Example 1, wherein the second etch process etches an undoped region of the gate dielectric cap at a faster etch rate than the doped region in the gate dielectric cap.

[0115] Example 3 is the method of Example 1, wherein the gate dielectric cap is formed of a same material as the contact etch stop layer.

[0116] Example 4 is the method of Example 1, wherein the gate dielectric cap and the contact etch stop layer are nitride-based.

[0117] Example 5 is the method of Example 1, wherein the ion implantation process implants oxygen, germanium, argon, xenon, or boron into the gate dielectric cap.

[0118] Example 6 is the method of Example 1, wherein the doped region in the gate dielectric cap has a higher oxygen concentration than the contact etch stop layer.

[0119] Example 7 is the method of Example 1, wherein the doped region in the gate dielectric cap has a higher oxygen concentration than an undoped region in the gate dielectric cap.

[0120] Example 8 is the method of example 1, further comprising: performing an anneal process on the gate dielectric cap after performing the ion implant process.

[0121] Example 9 is the method of example 1, wherein the first etch process is a plasma etch process using a plasma generated from a gas mixture that is free of hydrogen.

[0122] Example 10 is the method of example 1, wherein the second etch process is a plasma etch process using a plasma generated from a gas mixture that contains hydrogen.

[0123] Example 11 is the method of example 10, wherein the gas mixture that contains hydrogen is a mixture of a fluorine-containing gas and hydrogen gas.

[0124] Example 12 is the method of example 11, wherein the fluorine-containing gas is a CHF3gas, a CF4gas, or a combination thereof.

[0125] Example 13 is a method of forming an integrated circuit device, comprising: forming a first gate dielectric cap over a first gate structure and a second gate dielectric cap over a second gate structure; forming a first doped region in the first gate dielectric cap and a second doped region in the second gate dielectric cap; depositing a contact etch stop layer over the first gate dielectric cap and the second gate dielectric cap, and depositing an interlayer dielectric (ILD) layer over the contact etch stop layer; performing a first etch process to form a first gate contact opening and a second gate contact opening extending through the ILD layer such that the contact etch stop layer is exposed, wherein a width of the first gate contact opening is less than a width of the second gate contact opening; performing a second etch process on the contact etch stop layer to extend the first gate contact opening and the second gate contact opening toward the first gate structure and the second gate structure, wherein a sidewall profile of the first gate contact opening becomes more vertical after the second etch process etches through the first doped region in the first gate dielectric cap than before etching the first doped region; and forming a first gate contact in the first gate contact opening and a second gate contact in the second gate contact opening after performing the second etch process.

[0126] Example 14 is the method of example 13, wherein the first etch process is such that a depth of the first gate contact opening is less than a depth of the second gate contact opening.

[0127] Example 15 is the method of example 13, wherein, after the second etch process etches through the first and second doped regions, a depth difference between the first gate contact opening and the second gate contact opening becomes less than a depth difference before etching the first and second doped regions.

[0128] Example 16 is the method of example 13, wherein the second etch process uses a gas mixture with hydrogen gas, and the first etch process does not use hydrogen gas.

[0129] Example 17 is an integrated circuit device comprising: a source / drain epitaxial structure over a substrate; source / drain contacts over the source / drain epitaxial structure, respectively; a gate structure laterally between the source / drain contacts; a gate dielectric cap over the gate structure and having opposing sidewalls that contact the source / drain contacts, respectively, wherein the gate dielectric cap has a doped region extending from a top surface of the gate dielectric cap into the gate dielectric cap; a contact etch stop layer extending over the source / drain contacts and the gate dielectric cap; an interlayer dielectric (ILD) layer over the contact etch stop layer; and a gate contact extending through the ILD layer, the contact etch stop layer, and the doped region of the gate dielectric cap to electrically connect with the gate structure.

[0130] Example 18 is the device of example 17, wherein the doped region of the gate dielectric cap has a higher oxygen-to-nitrogen atomic ratio than an undoped region of the gate dielectric cap.

[0131] Example 19 is the device of example 17, wherein the doped region of the gate dielectric cap has an oxygen concentration gradient.

[0132] Example 20 is the device of example 17, wherein the doped region of the gate dielectric cap is thinner than the contact etch stop layer.

Claims

1. A method of forming an integrated circuit device, comprising: forming gate structures between gate spacers and over a semiconductor substrate; etching back the gate structures to below a top end of the gate spacers; forming a gate dielectric cap over the etched back gate structures; performing an ion implantation process to form a doped region in the gate dielectric cap; depositing a contact etch stop layer over the gate dielectric cap and depositing an interlayer dielectric (ILD) layer over the contact etch stop layer; performing a first etch process to form a gate contact opening extending through the ILD layer and exposing the contact etch stop layer; performing a second etch process to deepen the gate contact opening, wherein the second etch process etches the doped region of the gate dielectric cap at a slower etch rate than etching the contact etch stop layer, wherein the second etch process etches through the contact etch stop layer and the gate dielectric cap; and forming a gate contact in the deepened gate contact opening.

2. The method of claim 1, wherein, the second etch process etches an undoped region of the gate dielectric cap at a faster etch rate than etching the doped region in the gate dielectric cap.

3. The method of claim 1, wherein, the gate dielectric cap is formed of a same material as the contact etch stop layer.

4. The method of claim 1, wherein, the gate dielectric cap and the contact etch stop layer are nitride based.

5. The method of claim 1, wherein, the ion implantation process implants oxygen, germanium, argon, xenon, or boron into the gate dielectric cap.

6. The method of claim 1, wherein, the doped region in the gate dielectric cap has a higher oxygen concentration than the contact etch stop layer.

7. The method of claim 1, wherein, the doped region in the gate dielectric cap has a higher oxygen concentration than an undoped region in the gate dielectric cap.

8. The method of claim 1, further comprising: performing an anneal process to the gate dielectric cap after performing the ion implantation process.

9. The method of claim 1, wherein, the first etch process is a plasma etch process using a plasma generated from a gas mixture that is free of hydrogen.

10. The method of claim 1, wherein, the second etch process is a plasma etch process using a plasma generated from a gas mixture that contains hydrogen.

11. The method of claim 10, wherein, the gas mixture that contains hydrogen is a mixture of a fluorine containing gas and hydrogen gas.

12. The method of claim 11, wherein, the fluorine containing gas is a CHF3 gas, a CF4 gas, or a combination thereof.

13. A method of forming an integrated circuit device, comprising: forming a first gate dielectric cap over a first gate structure and forming a second gate dielectric cap over a second gate structure; forming a first doped region in the first gate dielectric cap and forming a second doped region in the second gate dielectric cap; depositing a contact etch stop layer over the first gate dielectric cap and the second gate dielectric cap and depositing an interlayer dielectric (ILD) layer over the contact etch stop layer; performing a first etch process to form a first gate contact opening and a second gate contact opening extending through the ILD layer such that the contact etch stop layer is exposed, wherein a width of the first gate contact opening is less than a width of the second gate contact opening; performing a second etch process on the contact etch stop layer to extend the first gate contact opening and the second gate contact opening toward the first gate structure and the second gate structure, wherein a sidewall profile of the first gate contact opening becomes more vertical after the second etch process etches through the first doped region in the first gate dielectric cap; and forming a first gate contact in the first gate contact opening and a second gate contact in the second gate contact opening after performing the second etch process.

14. The method of claim 13, wherein, the first etch process is such that a depth of the first gate contact opening is less than a depth of the second gate contact opening.

15. The method of claim 13, wherein, a depth difference between the first gate contact opening and the second gate contact opening becomes less after the second etch process etches through the first doped region and the second doped region than before etching the first doped region and the second doped region.

16. The method of claim 13, wherein, the second etch process uses a gas mixture having hydrogen gas and the first etch process does not use hydrogen gas.

17. An integrated circuit device, comprising: a source / drain epitaxial structure over a substrate; source / drain contacts over the source / drain epitaxial structure, respectively; a gate structure laterally between the source / drain contacts; a gate dielectric cap over the gate structure and having opposing sidewalls that contact the source / drain contacts, respectively, wherein the gate dielectric cap has a doped region extending from a top surface of the gate dielectric cap into the gate dielectric cap; a contact etch stop layer extending over the source / drain contacts and the gate dielectric cap; an interlayer dielectric (ILD) layer over the contact etch stop layer; and a gate contact extending through the ILD layer, the contact etch stop layer, and the doped region of the gate dielectric cap to electrically connect with the gate structure, wherein the gate contact is formed by: performing a first etch process to form a gate contact opening extending through the ILD layer and exposing the contact etch stop layer; performing a second etch process to deepen the gate contact opening, wherein the second etch process etches the doped region of the gate dielectric cap at a slower etch rate than etching the contact etch stop layer, wherein the second etch process etches through the contact etch stop layer and the gate dielectric cap; and forming the gate contact in the deepened gate contact opening.

18. The device of claim 17, wherein, the doped region of the gate dielectric cap has a higher oxygen-to-nitrogen atomic ratio than an undoped region of the gate dielectric cap.

19. The device of claim 17, wherein, the doped region of the gate dielectric cap has an oxygen concentration gradient.

20. The device of claim 17, wherein, the doped region of the gate dielectric cap is thinner than the contact etch stop layer.

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